JP2511010B2 - Method for manufacturing vertical MOS transistor - Google Patents
Method for manufacturing vertical MOS transistorInfo
- Publication number
- JP2511010B2 JP2511010B2 JP62005664A JP566487A JP2511010B2 JP 2511010 B2 JP2511010 B2 JP 2511010B2 JP 62005664 A JP62005664 A JP 62005664A JP 566487 A JP566487 A JP 566487A JP 2511010 B2 JP2511010 B2 JP 2511010B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- mos transistor
- diffusion window
- semiconductor substrate
- vertical mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 26
- 150000004767 nitrides Chemical class 0.000 description 8
- 239000008186 active pharmaceutical agent Substances 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- -1 Boron ions Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 A.産業上の利用分野 本発明は、オン電圧，オン抵抗がともに低くかつ高速
スイッチング特性を有する縦型MOSトランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a vertical MOS transistor having both low on-voltage and low on-resistance and high-speed switching characteristics.
B.従来の技術 第４図は、特開昭60−10677号に開示されている従来
の縦型MOSトランジスタを示す。B. Prior Art FIG. 4 shows a conventional vertical MOS transistor disclosed in JP-A-60-10677.
第４図の縦型MOSトランジスタは、面方位（100）のＮ
型高濃度基板1a上にＮ型低濃度エピタキシャル層1bを形
成して成るＮ型半導体基板１を備え、このＮ型半導体基
板１はMOSトランジスタのドレインに供されその裏面に
ドレイン電極配線２が形成されている。Ｎ型半導体基板
１中には、Ｐウェル領域3,N+領域4a,4b（符号４で代表
する）およびP+領域５が形成され、N+領域４はMOSトラ
ンジスタのソース領域となり、P+領域５はＰウェル領域
３をN+領域４と同電位にするために形成されている。ま
た、Ｎ型半導体基板１の表面とN+領域４の一部の表面と
にゲート酸化膜６を介してゲート電極７が配置され、こ
のゲート電極７は層間絶縁膜８によって覆われている。
ゲート酸化膜６と接するＰウェル領域３の表面領域がチ
ャネル領域９である。The vertical MOS transistor shown in FIG. 4 has an N of plane orientation (100).
An N-type semiconductor substrate 1 is formed by forming an N-type low-concentration epitaxial layer 1b on a high-concentration type substrate 1a. This N-type semiconductor substrate 1 is used as a drain of a MOS transistor and a drain electrode wiring 2 is formed on the back surface thereof. Has been done. In the N-type semiconductor substrate 1, a P well region 3, N + regions 4a and 4b (represented by reference numeral 4) and a P + region 5 are formed, and the N + region 4 becomes a source region of a MOS transistor, and P + Region 5 is formed so that P well region 3 has the same potential as N + region 4. A gate electrode 7 is arranged on the surface of the N-type semiconductor substrate 1 and a part of the surface of the N + region 4 via a gate oxide film 6, and the gate electrode 7 is covered with an interlayer insulating film 8.
The surface region of the P well region 3 in contact with the gate oxide film 6 is the channel region 9.
P+領域５およびソース領域となるN+領域４にはソース
電極配線10が接続され、ゲート電極７にはゲート電極配
線11が接続されている。またこの縦型MOSトランジスタ
にはチャネルリークを防止するためのチャネルストッパ
電極12が設けられている。A source electrode wiring 10 is connected to the P + region 5 and the N + region 4 serving as a source region, and a gate electrode wiring 11 is connected to the gate electrode 7. Further, this vertical MOS transistor is provided with a channel stopper electrode 12 for preventing channel leak.
このような構造の縦型MOSトランジスタでは、第５図
に示すように全稜角が150度以上にした多角形状の拡散
窓12をゲート電極７に形成し、同一拡散窓12から２重拡
散によってＰウェル領域３とN+領域４を形成する。これ
により、四角形や六角系の拡散窓を用いて作成した縦型
MOSトランジスタと比べて、立上りが急峻なVG−IDS特性
（VG:ゲート電圧、IDS:ドレイン，ソース間に流れる電
流）を得ている。In the vertical MOS transistor having such a structure, as shown in FIG. 5, a polygonal diffusion window 12 having a total ridge angle of 150 degrees or more is formed in the gate electrode 7, and the same diffusion window 12 is formed by double diffusion to form a P-type diffusion window. Well region 3 and N + region 4 are formed. As a result, vertical type created using a rectangular or hexagonal diffusion window
Compared to MOS transistors, it has V G -I DS characteristics with a sharp rise (V G : gate voltage, I DS : current flowing between drain and source).
C.発明が解決しようとする問題点 しかしながら上述したような従来の縦型MOSトランジ
スタでは、チャネル領域９の表面の不純物濃度が、ソー
ス領域であるN+領域４の端部からドレインであるＮ型半
導体基板１へ向かって横方向に指数関数的に減少するた
め、ゲート電圧の上昇とともにドレイン側からチャネル
領域９の表面に反転層形成が進行し、ドレイン側から空
乏層がソース領域４に接近する。オン電圧近くになる
と、この空乏層がソース空乏層と接触しパンチスルー電
流が流れるので、VG−IDS特性の立上りを横型MOSトラン
ジスタほどまでは急峻なものにすることができないとい
う問題があった。C. Problems to be Solved by the Invention However, in the conventional vertical MOS transistor as described above, the impurity concentration on the surface of the channel region 9 is from the end of the N + region 4 which is the source region to the N type which is the drain. Since it exponentially decreases in the lateral direction toward the semiconductor substrate 1, the inversion layer formation progresses from the drain side to the surface of the channel region 9 as the gate voltage rises, and the depletion layer approaches the source region 4 from the drain side. . When the voltage is close to the on-state voltage, this depletion layer contacts the source depletion layer and punch-through current flows.Therefore, there is a problem that the rise of the V G −I DS characteristics cannot be made as steep as that of a lateral MOS transistor. It was
本発明は、ソース領域端部からドレイン領域にいたる
チャネル領域表面の不純物濃度分布を一定濃度領域を経
た後に指数関数的に減少させることで、VG−IDS特性の
立上りを急峻にすることの可能な縦型MOSトランジスタ
を提供することを目的としている。The present invention reduces the impurity concentration distribution on the surface of the channel region from the end of the source region to the drain region exponentially after passing through the constant concentration region, thereby making the rise of the V G −I DS characteristic steep. The purpose is to provide a possible vertical MOS transistor.
D.問題点を解決するための手段 一実施例を示す第１図により本発明を説明すると、本
発明に係る縦型MOSトランジスタは、第１の導電型の半
導体基板１上に形成された第２の導電型のウェル領域21
の端部に半導体基板１に至るチャネル領域24が形成され
るように当該ウェル領域21内に第１の導電型のソース領
域４が形成され、チャネル領域24の表面上にゲート絶縁
膜22を介してゲート電極23が形成された縦型MOSトラン
ジスタの製造方法に適用され、第１導電型の半導体基板
１の上面に絶縁膜22を介してゲート電極23となる電極膜
23を形成する工程と、電極膜23の上面に多結晶シリコン
層32を形成する工程と、絶縁膜22、電極膜23および多結
晶シリコン層32の一部を選択的に除去して第１の拡散窓
34を形成する工程と、第１の拡散窓34の側面から横方向
所定範囲の多結晶シリコン層32を除去して第２の拡散窓
35を形成する工程と、第２の拡散窓35を通して半導体基
板１内に第２の導電型の不純物イオン36を注入して熱拡
散させることにより、ウェル領域21を形成する工程と、
第１の拡散窓34を通して不純物イオンを注入して熱拡散
させることにより、ソース領域４を形成する工程と、を
備えることにより上記目的は達成される。D. Means for Solving Problems The present invention will be described with reference to FIG. 1 showing an embodiment. A vertical MOS transistor according to the present invention is a first MOS transistor formed on a semiconductor substrate 1 of a first conductivity type. 2 conductivity type well region 21
The source region 4 of the first conductivity type is formed in the well region 21 so that the channel region 24 reaching the semiconductor substrate 1 is formed at the end of the channel region 24, and the gate insulating film 22 is formed on the surface of the channel region 24. Applied to a method of manufacturing a vertical MOS transistor in which a gate electrode 23 is formed, and an electrode film to be the gate electrode 23 via an insulating film 22 on the upper surface of the first conductivity type semiconductor substrate 1.
23, a step of forming a polycrystalline silicon layer 32 on the upper surface of the electrode film 23, and a step of selectively removing a part of the insulating film 22, the electrode film 23 and the polycrystalline silicon layer 32, Diffusion window
A step of forming the second diffusion window by removing the polycrystalline silicon layer 32 in a predetermined lateral direction from the side surface of the first diffusion window 34.
Forming the well region 21 by injecting the second conductivity type impurity ions 36 into the semiconductor substrate 1 through the second diffusion window 35 to thermally diffuse the same.
The above object is achieved by including the step of forming the source region 4 by implanting impurity ions through the first diffusion window 34 and thermally diffusing the impurity ions.
E.作用 電極膜23の上面に絶縁膜23を介して多結晶シリコン層
32を形成した後、絶縁膜22、電極膜23および多結晶シリ
コン層32の一部を選択的に除去して第１の拡散窓34を形
成する。次に、第１の拡散窓34の側面から横方向所定範
囲の多結晶シリコン層32を除去して第２の拡散窓35を形
成する。次に、第２の拡散窓35を通して半導体基板１内
に不純物イオン36を注入した後、熱拡散してウェル層21
を形成する。次に、第１の拡散窓34を通して不純物イオ
ンを注入後に熱拡散させてソース領域４を形成する。こ
れにより、ソース領域４の位置決めを精度よく行え、か
つ第２の拡散窓35を通して注入された不純物イオンのソ
ース領域周辺の濃度を略一定にできる。このように形成
した縦型MOSトランジスタのゲート電極23に電圧を印加
すると、ゲート電極23の直下のチャネル領域24にソース
領域ととは反対側の部分からソース領域に向かって反転
層が成長する。反転層がウェル層21内に形成された不純
物濃度分布の一様な領域25に達すると、この領域25の全
面にわたって反転層が瞬時にチャネル領域全面にわたっ
て反転層が形成されることになる。この結果、ソース領
域４とドレイン領域１とが電気的に接続されソース領域
４とドレイン領域１との間に電流が流れる。またチャネ
ル領域24の全面にわたって反転層が形成されるまでドレ
イン側からの空乏層はソース側の空乏層に接触すること
はないのでパンチスルーによるリーク電流は流れない。
これらのことからVG−IDS特性の立上りが従来よりも急
峻になる。E. Working Polycrystalline silicon layer on the upper surface of electrode film 23 with insulating film 23 interposed
After forming 32, the insulating film 22, the electrode film 23, and a part of the polycrystalline silicon layer 32 are selectively removed to form a first diffusion window 34. Next, the second diffusion window 35 is formed by removing the polycrystalline silicon layer 32 in a predetermined lateral direction from the side surface of the first diffusion window 34. Next, after the impurity ions 36 are implanted into the semiconductor substrate 1 through the second diffusion window 35, they are thermally diffused and the well layer 21 is formed.
To form. Next, the impurity ions are implanted through the first diffusion window 34 and then thermally diffused to form the source region 4. As a result, the source region 4 can be accurately positioned, and the concentration of the impurity ions implanted through the second diffusion window 35 around the source region can be made substantially constant. When a voltage is applied to the gate electrode 23 of the vertical MOS transistor thus formed, the inversion layer grows in the channel region 24 immediately below the gate electrode 23 from the portion opposite to the source region toward the source region. When the inversion layer reaches the region 25 formed in the well layer 21 and having a uniform impurity concentration distribution, the inversion layer is instantaneously formed over the entire surface of this region 25 over the entire channel region. As a result, the source region 4 and the drain region 1 are electrically connected and a current flows between the source region 4 and the drain region 1. Further, since the depletion layer from the drain side does not contact the depletion layer on the source side until the inversion layer is formed over the entire surface of the channel region 24, a leak current due to punch through does not flow.
For these reasons, the rise of the V G -I DS characteristics becomes steeper than in the past.
F.実施例 以下、本発明の実施例を図面に基づいて説明する。F. Examples Hereinafter, examples of the present invention will be described with reference to the drawings.
第１図は縦型MOSトランジスタの構成図、第２図は第
１図のＡ−Ａ′線に沿ったＰウェル領域の表面の不純物
濃度分布を示す図であり、第４図と同様の箇所には同一
符号を付し、その説明を省略する。FIG. 1 is a configuration diagram of a vertical MOS transistor, and FIG. 2 is a diagram showing the impurity concentration distribution on the surface of the P well region along the line AA ′ in FIG. Are denoted by the same reference numerals, and description thereof will be omitted.
Ｎ型半導体基板１にはＰウェル領域21が形成され、ま
たＮ型半導体基板１の上面にはゲート酸化膜6,ゲート電
極７と同様のゲート酸化膜22,ゲート電極23が順次に形
成されている。ゲート酸化膜22と接するＰウェル領域21
の部分、すなわちＡ−Ａ′線で示す表面領域がチャネル
領域24となる。Ｐウェル領域21内の不純物濃度分布は、
斜線で示す領域25内は一様で、領域25の端部からＮ型半
導体基板１へ横方向に向かって指数関数的に減少する。
したがって、チャネル領域24の濃度分布も、第２図に実
線で示すように領域25の大半が一様であり、領域25の端
部からＮ型半導体基板１へ横方向に向けて指数関数的に
減少する。なお、破線は第４図に示した従来の縦型MOS
トランジスタにおける同一領域の不純物濃度分布を示し
ている。A P well region 21 is formed on the N-type semiconductor substrate 1, and a gate oxide film 6, a gate oxide film 22 similar to the gate electrode 7, and a gate electrode 23 are sequentially formed on the upper surface of the N-type semiconductor substrate 1. There is. P-well region 21 in contact with gate oxide film 22
, That is, the surface region indicated by the line AA ′ is the channel region 24. The impurity concentration distribution in the P well region 21 is
The region 25 indicated by the diagonal lines is uniform and decreases exponentially from the end of the region 25 toward the N-type semiconductor substrate 1 in the lateral direction.
Therefore, the concentration distribution of the channel region 24 is uniform in most of the region 25 as shown by the solid line in FIG. 2, and exponentially extends from the end of the region 25 to the N-type semiconductor substrate 1 in the lateral direction. Decrease. The broken line indicates the conventional vertical MOS shown in FIG.
The impurity concentration distribution of the same area | region in a transistor is shown.
このような構造の縦型MOSトランジスタの製造工程を
第３図（ａ）〜（ｅ）を用いて説明する。The manufacturing process of the vertical MOS transistor having such a structure will be described with reference to FIGS.
第３図（ａ）に示す工程では、面方位（100）のシリ
コン単結晶からなるＮ型高濃度基板1a上にＮ型低濃度エ
ピタキシャル層1bを形成したＮ型半導体基板１を用意
し、このＮ型半導体基板１の表面に、厚さ500ÅのSiO2
からなるゲート酸化膜22と図示しないが厚さ7000ÅのSi
O2からなるフィールド絶縁膜を形成し、さらにその上に
厚さ2500Åで、ボロンを１×1020個/cm3以上に添加した
ポリシリコンからなるゲート電極23を形成する。In the step shown in FIG. 3A, an N-type semiconductor substrate 1 in which an N-type low-concentration epitaxial layer 1b is formed on an N-type high-concentration substrate 1a made of a silicon single crystal having a plane orientation (100) is prepared. On the surface of the N-type semiconductor substrate 1, SiO 2 with a thickness of 500Å
The gate oxide film 22 made of Si and 7000 Å thick Si (not shown)
A field insulating film made of O 2 is formed, and a gate electrode 23 made of polysilicon having a thickness of 2500 Å and doped with 1 × 10 20 boron / cm 3 or more is formed on the field insulating film.
次いで第３図（ｂ）に示す工程では、減圧CVD法によ
り厚さ1000Åの下層ナイトライド膜31,厚さ１μｍの不
純物無添加ポリシリコン32,厚さ300Åの上層ナイトライ
ド膜33をゲート電極23上に形成する。Next, in the step shown in FIG. 3 (b), the lower nitride film 31 having a thickness of 1000 Å, the undoped polysilicon 32 having a thickness of 1 μm, the upper nitride film 33 having a thickness of 300 Å are formed on the gate electrode 23 by the low pressure CVD method. Form on top.
次いで第３図（ｃ）に示す工程では、多角形状の第１
の拡散窓34を所定のマスクを用いて形成する。すなわち
上層ナイトライド膜33上に所定のホトレジストを塗布
し、これをマスクとして光露光し、しかる後にドライエ
ッチングする。これにより上層ナイトライド膜33,不純
物添加ポリシリコン32,下層ナイトライド膜31およびゲ
ート電極23は同一寸法にエッチングされて多角形状の第
１の拡散窓34が形成される。次に、強アルカリエッチン
グ液（例えばエチレンジアミンとピロカテコールと水の
混合液）で選択的に不純物無添加ポリシリコン32を横方
向にエッチングし、Ｐウェル領域21形成用の第２の拡散
窓35を形成する。Next, in the step shown in FIG. 3C, the first polygonal shape
The diffusion window 34 is formed using a predetermined mask. That is, a predetermined photoresist is applied on the upper nitride film 33, light exposure is performed using this as a mask, and then dry etching is performed. As a result, the upper nitride film 33, the impurity-doped polysilicon 32, the lower nitride film 31, and the gate electrode 23 are etched to the same size to form the polygonal first diffusion window 34. Next, the impurity-free polysilicon 32 is selectively laterally etched with a strong alkaline etching solution (for example, a mixed solution of ethylenediamine, pyrocatechol and water) to form the second diffusion window 35 for forming the P well region 21. Form.
次いで第３図（ｄ）に示す工程では、熱リン酸によっ
て上層ナイトライド膜33を選択的に除去したあと、第２
の拡散窓35からイオン注入法によってボロンイオン36を
200KeVで加速しＮ型半導体基板１の表面に選択的に添加
する。Next, in the step shown in FIG. 3D, after the upper nitride film 33 is selectively removed by hot phosphoric acid, the second nitride film 33 is removed.
Boron ions 36 from the diffusion window 35 of the
It is accelerated at 200 KeV and selectively added to the surface of the N-type semiconductor substrate 1.
次いで第３図（ｅ）に示す工程では、不純物無添加ポ
リシリコン32の全部を強アルカリ液で除去し、次いで下
層ナイトライド膜31を熱リン酸で除去する。次いで、11
00℃の温度下にてボロンイオン36を拡散しＰウェル領域
21を形成する。このときに第３図（ｄ）に示す工程によ
って添加されたボロンイオン36の濃度が一定の領域25が
Ｐウェル領域21内に形成される。Next, in the step shown in FIG. 3 (e), the entire impurity-free polysilicon 32 is removed with a strong alkaline solution, and then the lower nitride film 31 is removed with hot phosphoric acid. Then 11
Boron ions 36 are diffused at a temperature of 00 ° C to form the P well region.
Form 21. At this time, a region 25 having a constant concentration of the boron ion 36 added by the step shown in FIG. 3D is formed in the P well region 21.
しかる後、たとえば特開昭60−10677号公報に開示さ
れている工程と同様の工程によって、N+領域4,P+領域5,
層間絶縁膜8,ソース電極配線10,ゲート電極配線11,チャ
ネルストッパ電極12,ドレイン電極配線２を形成して第
１図に示すような縦型MOSトランジスタが作られる。Then, for example, by a process similar to the process disclosed in JP-A-60-10677, N + region 4, P + region 5,
An interlayer insulating film 8, a source electrode wiring 10, a gate electrode wiring 11, a channel stopper electrode 12, and a drain electrode wiring 2 are formed to form a vertical MOS transistor as shown in FIG.
このように構造の縦型MOSトランジスタでは、ゲート
電極23にソース領域であるN+領域４に対して電圧を印加
すると、チャネル領域24には位置Ａ′の側から位置Ａに
向けて徐々に反転層が形成される。反転層が不純物濃度
分布の一様な領域25に達すると、瞬時に領域25全面にお
いて反転層が形成され、ソース領域としてのN+領域４と
ドレイン領域としてのＮ型半導体基板１との間に急激に
電流が流れる。また不純物濃度分布の一様な領域25が存
在することによって、チャネル領域24の全領域に反転層
が形成されるまでドレイン側からの空乏層がソース側の
空乏層に接触することがなくなりパンチスルーによるリ
ーク電流を阻止することができる。このようなことか
ら、立上りが急峻なVG−IDS特性の縦型MOSトランジスタ
が得られる。In the vertical MOS transistor having such a structure, when a voltage is applied to the gate electrode 23 with respect to the source region N + region 4, the channel region 24 is gradually inverted from the position A ′ side toward the position A. A layer is formed. When the inversion layer reaches the region 25 having a uniform impurity concentration distribution, the inversion layer is instantaneously formed on the entire surface of the region 25, and between the N + region 4 as the source region and the N-type semiconductor substrate 1 as the drain region. The current suddenly flows. The presence of the region 25 having a uniform impurity concentration distribution prevents the depletion layer from the drain side from coming into contact with the depletion layer on the source side until the inversion layer is formed in the entire region of the channel region 24. It is possible to prevent the leakage current due to. From this, a vertical MOS transistor having a V G -I DS characteristic with a sharp rise can be obtained.
G.発明の効果 以上に説明したように本発明によれば、第２の拡散窓
と第２の拡散窓の内部に形成された第１の拡散窓を用い
てそれぞれ不純物イオンを注入し熱拡散するため、ソー
ス領域の位置決めを精度よく行えるとともに、ソース領
域周辺の不純物濃度を略一定にでき、パンチオフの発生
を抑制してＶG−ＩDS特性を急峻にすることができる。G. Effect of the Invention As described above, according to the present invention, impurity ions are implanted into each of the second diffusion window and the first diffusion window formed inside the second diffusion window to perform thermal diffusion. Therefore, the source region can be accurately positioned, the impurity concentration around the source region can be made substantially constant, punch-off can be suppressed, and the VG-IDS characteristics can be made sharp.
第１図は本発明の縦型MOSトランジスタの構成図、第２
図は第１図のＡ−Ａ′線に沿ったＰウェル領域の表面の
不純物濃度分布を示す図、第３図（ａ）〜（ｅ）は第１
図に示す縦型MOSトランジスタの製造工程を示す図、第
４図は従来の縦型MOSトランジスタの構成図、第５図は
第４図の縦型MOSトランジスタを形成する際の拡散窓を
示す図である。 1:N型半導体基板、21:Pウェル領域 22:ゲート酸化膜、23:ゲート電極 24:チャネル領域 25:不純物濃度分布一様の領域FIG. 1 is a block diagram of a vertical MOS transistor of the present invention, and FIG.
The figure shows the impurity concentration distribution on the surface of the P-well region along the line AA 'in FIG. 1, and FIGS. 3 (a) to 3 (e) show the first figure.
The figure which shows the manufacturing process of the vertical MOS transistor shown in the figure, FIG. 4 is a block diagram of the conventional vertical MOS transistor, and FIG. 5 is the figure which shows the diffusion window at the time of forming the vertical MOS transistor of FIG. Is. 1: N-type semiconductor substrate, 21: P well region 22: Gate oxide film, 23: Gate electrode 24: Channel region 25: Region with uniform impurity concentration distribution
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−80969（ＪＰ，Ａ) 特開 昭55−63876（ＪＰ，Ａ) 特開 昭61−281557（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-59-80969 (JP, A) JP-A-55-63876 (JP, A) JP-A-61-281557 (JP, A)
Claims (1)
第２の導電型のウェル領域の端部に前記半導体基板に至
るチャネル領域が形成されるように当該ウェル領域内に
第１の導電型のソース領域が形成され、前記チャネル領
域の表面上にゲート絶縁膜を介してゲート電極が形成さ
れた縦型MOSトランジスタの製造方法において、 第１導電型の半導体基板の上面に絶縁膜を介して前記ゲ
ート電極となる電極膜を形成する工程と、 前記電極膜の上面に多結晶シリコン槽を形成する工程
と、 前記絶縁膜、前記電極膜および前記多結晶シリコン槽の
一部を選択的に除去して第１の拡散窓を形成する工程
と、 前記第１の拡散窓の側面から横方向所定範囲の前記多結
晶シリコン槽を除去して第２の拡散窓を形成する工程
と、 前記第２の拡散窓を通して前記半導体基板内に第２の導
電型の不純物イオンを注入して熱拡散させることによ
り、前記ウェル層を形成する工程と、 前記第１の拡散窓を通して不純物イオンを注入して熱拡
散させることにより、前記ソース領域を形成する工程
と、を備えることを特徴とする縦型MOSトランジスタの
製造方法。1. A first well in a well region of a second conductivity type formed on a first conductivity type semiconductor substrate so that a channel region reaching the semiconductor substrate is formed at an end portion of the well region of the second conductivity type. In the method of manufacturing the vertical MOS transistor, the source region of the conductivity type is formed, and the gate electrode is formed on the surface of the channel region via the gate insulating film. Forming an electrode film to serve as the gate electrode via a step of forming a polycrystalline silicon tank on the upper surface of the electrode film, selecting the insulating film, the electrode film and a part of the polycrystalline silicon tank Removing the first diffusion window to form a first diffusion window, and removing the polycrystalline silicon tank in a laterally predetermined range from a side surface of the first diffusion window to form a second diffusion window. Through the second diffusion window A step of forming the well layer by implanting and thermally diffusing second conductivity type impurity ions into the semiconductor substrate; and implanting and thermally diffusing impurity ions through the first diffusion window, A step of forming the source region, and a method for manufacturing a vertical MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62005664A JP2511010B2 (en) | 1987-01-13 | 1987-01-13 | Method for manufacturing vertical MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62005664A JP2511010B2 (en) | 1987-01-13 | 1987-01-13 | Method for manufacturing vertical MOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63173372A JPS63173372A (en) | 1988-07-16 |
| JP2511010B2 true JP2511010B2 (en) | 1996-06-26 |
Family
ID=11617370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62005664A Expired - Fee Related JP2511010B2 (en) | 1987-01-13 | 1987-01-13 | Method for manufacturing vertical MOS transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2511010B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0254969A (en) * | 1988-08-19 | 1990-02-23 | Fuji Electric Co Ltd | Mos type semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563876A (en) * | 1978-11-08 | 1980-05-14 | Sony Corp | Field-effect semiconductor device |
| JPS5980969A (en) * | 1982-11-01 | 1984-05-10 | Nec Corp | Manufacture of field-effect transistor |
| EP0199293B2 (en) * | 1985-04-24 | 1995-08-30 | General Electric Company | Insulated gate semiconductor device |
-
1987
- 1987-01-13 JP JP62005664A patent/JP2511010B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63173372A (en) | 1988-07-16 |
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