JPH03154379A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable high function advancement, high integration advancement, and high speed advancement by forming vertical MOS transistor structure wherein a high concentration impurity region formed at the bottom of a trench is made a source region and a conductive film provided at the sidewall of the trench is made a gate electrode. CONSTITUTION:A vertical N-channel transistor, consisting of an n<+>-type source region 4a, an n<+>-type drain region 4b, an n<->-type drain region 5, and a gate electrode 8, is made in a p-type well region 2. Element isolation is done by the insulating film 6 buried in a third trench 16, and the n<+>-type drain region 4 band the n<->-type drain region 5 form flat diffusion layers at the bottom. Moreover, a buried conductive layer 11 is made on the n<+>-type source region 4a, which optimizes the concentration of the n<->-type drain region 5 and each size. Hereby, a ultrahigh breakdown strength element is obtained, and high speed advancement is possible by reducing offset resistance to a fixed value, and further a minute vertical MOS field effect transistor can be made in self alignment, and high integration advancement becomes possible.

Description

[Detailed Description of the Invention] [Summary] A first high-concentration impurity of an opposite conductivity type defined by a third I~ trench embedded with an insulating film and a first trench, and formed in a semiconductor substrate of one conductivity type. A low concentration impurity region directly in contact with the bottom of the trench and the high concentration impurity region is used as a drain region, a second high concentration impurity region of the opposite conductivity type formed at the bottom of the first trench is used as a source region, Since the gate electrode is a conductive film provided on the side wall of the trench via a gate insulating film, the bottom of the high concentration impurity region can be formed flat, and the bottom of the high concentration impurity region can be completely flattened. MO with extremely high junction breakdown voltage by forming a train region surrounded by a low concentration impurity region
High functionality due to the ability to form a 5 field effect transistor, high integration due to the ability to form a low concentration offset/somatic region in the self-line, and the ability to form a 1f type MO8 field effect transistor that does not require a gate electrode area on the surface. Semiconductor device 9 that enables high speed by reducing resistance to a constant value [Industrial field of application] The present invention relates to an MIS type semiconductor device, and particularly relates to an MO3 field effect transistor having a high junction breakdown voltage. .

Since bf, regarding high-voltage MO3 field effect transistors, 1 is the MO3 field effect transistor with a normal structure? Only the drain region of the helangistor is modified, and a low concentration impurity region that is in contact with the high concentration impurity region and becomes a so-called off-cellar I region is provided between the high concentration impurity region and the channel region directly under the gate electrode, and the high concentration impurity region and the channel are The stopper areas are separated from each other. Like the manufacturing of ordinary MOS field effect transistors, it is relatively simple, but since the high concentration impurity region of the drain region cannot be formed in the self-alignment line, the offset resistance varies depending on alignment, making it difficult to increase the speed. Because of the need for positioning margins for the formation of the concentrated impurity region and the channel stopper region, it is impossible to measure the high integration density, and because the high concentration impurity region of the drain region cannot be formed flat, electric field concentration occurs in the curved portion of the diffusion layer. Problems such as the inability to sufficiently increase the breakdown voltage of the junction and the inability to achieve high functionality have become prominent. Therefore, there is a need for a means for forming a highly integrated high voltage element with a constant offset resistance and sufficient junction voltage resistance.

[Prior Art] FIG. 5 is a schematic side sectional view of a conventional semiconductor device, and 51 is a p
- type silicon (Si) substrate, 52 is a p-type well head mounted, 5
3 is a p-type stopper region, 54a is an n-type source region, 541) is an n-type stopper region, and 55 is an n-type stopper region.
- type offset I- region, 5G is a field oxide film, 57
is a gate oxide film, 58 is a gate electrode, 59 is a block oxide film, 60 is a phosphosilicate glass (PSC) film, and 61 is an AI
Shows wiring.

In the figure, a p-type well region 52 is selectively provided on a p-type silicon (Si) substrate 51, and the p-type well region 52 includes an n++ source region 54a, an n+-type drain region 54b, and an n-type offset region. A high-voltage N-channel transistor is formed of a solar cell region 55 and a gate electrode 58, and a breakdown voltage of about 00 V is obtained by optimally selecting the concentration of the n-type offset region 1 to the region and the size of each region. The 9p ten type channel strike/river region 53 is formed apart from the n ten type train region 54b. Since the n-type drain region cannot be formed on a self-aligned line, the offset resistance will vary depending on the alignment, and alignment margins are required to form the n-type drain region and the p-type channel stopper region, making it difficult for highly integrated chips. However, because the depletion layer expands due to the presence of the n-type offset region 1~, the junction breakdown voltage can be increased to some extent, but the electric field concentrates at the curve of the n-type drain region, which increases the upper limit of the junction breakdown voltage. However, there were drawbacks such as the inability to obtain extremely high junction breakdown voltage.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional example, it was not possible to form a low concentration region in which the offset-node resistance does not fluctuate, and the alignment margin It was not possible to form a highly integrated high-voltage device that did not require a high breakdown voltage, and it was also impossible to form a high-voltage device with an extremely high junction breakdown voltage that did not cause local electric field concentration.

Means for Solving Problem U] The above problem is caused by a first high concentration impurity region of an opposite conductivity type formed in a semiconductor substrate of one conductivity type, and a first high concentration impurity region formed directly on the bottom of the first high concentration impurity region. a low concentration impurity region of an opposite conductivity type formed in contact with each other, a channel region of one conductivity type formed under the low concentration impurity region, and a portion of the first high concentration impurity region and the low concentration impurity region. a first trench formed in the semiconductor substrate, a gate insulating film formed on the sidewalls and bottom of the first trench, and a gate insulating film formed on the sidewall of the first trench via the gate insulating film. a second high concentration impurity region of an opposite conductivity type formed at the bottom of the first trench;
This problem is solved by the semiconductor device of the present invention, which includes a conductive region to which a fixed voltage is applied to a high concentration impurity region.

1 Effect] That is, in the semiconductor device of the present invention, the third trench and the first trench in which the insulating film is embedded,
A first high concentration impurity region of the opposite conductivity type formed on a semiconductor substrate of one conductivity type and a low concentration impurity region directly in contact with the bottom of the high concentration impurity region are used as a drain region, and a drain region is formed at the bottom of the first trench. The structure is formed such that a second high concentration impurity region of the opposite conductivity type serves as a source region, and a conductive film provided on the side wall of the first trench with a gate insulating film interposed therebetween serves as a gate electrode. Therefore, the bottom of the high-concentration impurity region can be formed flat, and the drain region can be formed in which the bottom of the high-concentration impurity region is completely surrounded by the low-concentration impurity region. It is possible to form a high breakdown voltage element with an extremely high junction breakdown voltage in which electric field concentration does not occur. Furthermore, since a low concentration region that expands the depletion layer can be formed in the self-alignment line, the so-called off-cellar resistance can be reduced to a constant value, making it possible to increase the speed. Furthermore, since no gate electrode area on the surface is required and the entire region can be formed as a self-line, a fine vertical MO8 field effect transistor can be formed, making it possible to achieve high integration. In other words, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly integrated, and high-speed semiconductor integrated circuits.

[Examples] The present invention will be specifically described below with reference to illustrated examples. FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIG. 3 is a schematic side sectional view of the semiconductor device of the present invention. A schematic side sectional view of the third embodiment of the device, FIGS. 4(a) to (
e) is a process sectional view of an embodiment of the manufacturing method for a semiconductor device of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

FIG. 1 shows a first embodiment of the semiconductor device of the present invention when a p-type silicon substrate is used, and 1 is 1014C1ll-
3 is a p-type silicon substrate of about 3, 2 is a p-type trench region of about 1015cm-3, 3 is a p-type channel stopper region of about 1017CI11-3, 4a is a 1020CII
n-type source region of about l-3, 4b is 10 cm
5 is an n-type drain region (offset region) of about 10 cm, 6 is a buried insulating film for trench element isolation, 7 is a gate acid 1 arsenic film of about 250 nm, and 8 is an n-type drain region (offset region) of about 1 cm. A gate electrode of about 250 nm, 9 a side wall insulating film with a width of about 500 nm, 10 an insulating film between the gate electrode 7' and source electrode of about 250 nm, 11 a buried conductive film (selective vapor growth tungsten film), 12 a 50 nm
The block oxide film of about m, 13 is 0.6. Phosphorsilicate glass (PSG) film of about LLm, 14 is A of about IPm
1 wiring, 15 is a first trench with a depth of about 8/Am, 1
G indicates a third trench having a depth of approximately 10/JJ11.

In the figure, a p-type well region 2 for selectively defining a threshold voltage is formed in a p-type silicon substrate 1, and an n+ type source region Aa-n+ type train region is formed in the p-type well region 2. A vertical N-channel transistor is formed of a jib, an n-type drain region (offset region) 5, and a gate electrode 8. Element isolation is done by third trench 1
The n-type drain region 4) and the n-type train region (offset region) 5 form a flat bottom diffusion layer. Further, a buried conductive film (3″A selective vapor growth tungsten film) 11 is formed on the n-type source region 4a to which a fixed voltage is applied from the A1 wiring 14.N-type drain region (offset region) By optimizing the concentration of 5 and each size, an ultra-high voltage element with a withstand voltage of about 200 V has been obtained. Since it is possible to form a drain region in which the bottom of the type drain region is completely surrounded by an n-type train region (offset region), an extremely wide depletion layer can be obtained, and an extremely high junction without local electric field concentration can be achieved. It is possible to form a high breakdown voltage element with a breakdown voltage.Also, since a low concentration region that expands the depletion layer can be formed in the self-alignment line, the resistance of the so-called off-cell I can be reduced to a constant value, and high-speed f-hi is possible. Further, since no gate electrode area on the surface is required and the entire region can be formed as a self-line, a fine reduced-type MO3 field effect transistor can be formed, thereby making it possible to achieve high integration.

FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, in which 1 to 1G are the same as in FIG. 1 shows a wrench.

In the figure, a second trench 18 reaching the p-type silicon substrate is provided in a part of the n++ source region, and the second trench 18 is filled with a conductive film (selected "H-shaped vapor phase growth tungsten film") 11.

This buried conductive film (selective chemical vapor deposition tungsten film) 11 applies a fixed voltage from the p-type silicon substrate to the n+ type source region, and the buried conductive film (
The structure is the same as that of the first embodiment except that the first trench 15 on the selective chemical vapor deposition tungsten film 11 is filled with a buried insulating film 17. In this embodiment, in addition to the effects of the first embodiment, since no AI wiring is formed to apply a fixed voltage to the n-type source region, the degree of freedom in wiring can be increased, and high integration is possible. becomes.

FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention, and 1.3 to 1G are the same as in FIG.
indicates a p-type channel region.

In the figure, the n-type drain region (offset region) 5 extends to the lower end of the gate electrode 8, and the p-type channel region 19 is formed to surround the n-type source head 4a at equal intervals. The second embodiment has the same structure as the first embodiment except that the second embodiment has the same structure as that of the first embodiment and that no n-type well region is formed. In this embodiment, in addition to the effects of the first embodiment, since the n-type drain region (offset region) can be made longer, it is possible to further increase the withstand voltage and reduce the on-resistance, so that even higher speeds are possible. .

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4(a) to (e) and FIG. A film 20 and a nitride film 21 are grown. Next, using a normal photolithography technique and using a resist (not shown) as a mask layer, boron is ion-implanted to form the n-type well region 2, and phosphorus is ion-implanted. 9 to selectively and sequentially define n-type well regions (not shown), respectively.Next, high temperature running is performed to form n-type well regions 2 and n-type well regions (not shown) having desired depths. Unnecessary resist is removed.Next, the nitride film 21 is coated with the nitride film 21, using the resist (not shown) as a mask layer, using a conventional photolithography technique.
20. Part of the p-type silicon substrate 1 (depth approximately io7Am) is selectively and sequentially etched to form a third trench 1G.
form. Then the resist is removed. Next, using a conventional photolithography technique, using a resist (not shown) and the nitride film 21 as a mask layer, boron ions are implanted to form the p-type channels I and sober regions 3, and phosphorus is ion-implanted. Then, select the n-type channel, the loop region I to the tube region (not shown), respectively, and then trench 1G of node 3.
Form at the bottom. Next, ``unnecessary gas I'' is removed. Next, a chemical vapor deposition acid film 6 is grown, anisotropic dry etching is performed, and the third trench 1G is filled with the resist I (not shown). Buried Mf for trench element isolation! ! Using 6 as a mask layer, phosphorus is ion-implanted to define an n-type drain region 5. Next, the resist is removed and a high temperature heat treatment is performed to form an n-type drain region 5 having a desired depth.

No. 4113(b) Next, using a normal photolithography technique and using a resist (not shown) as a mask layer, the nitride film 21, oxide film 20, and a portion of the p-type silicon substrate 1 (approximately 87 m in depth) are formed. A first trench 15 is formed by selectively sequentially etching. Next, the resist is removed. Next, using a normal photolithography technique (Jfir) and using the nitride film 21 and the buried oxide film 6 for trench element isolation as mask layers, arsenic ions are implanted to form the n-type source inclined wall 4a.
is defined at the bottom of the first trench 15.

FIG. 4(C) Next, gate oxide pA7 is grown. Next, a polycrystalline silicon film containing impurities is grown, anisotropically dry etched, and buried in the first trench 15.
Over-etching is performed to a certain extent to leave a shallow first trench 15 on the polycrystalline silicon film 8 that will become the gate electrode. Next, a chemical vapor deposition oxide film is grown and anisotropic dry etching is performed to leave the oxide film 9 on the sidewalls of the remaining shallow first trenches 15.

FIG. 4(1) Next, anisotropic dry etching is performed using the remaining sidewall oxide film 9 as a mask layer, and the polycrystalline silicon film at the center of the polycrystalline silicon film 8, which will become the gate electrode, is etched away.

Next, thermal oxidation is performed to form an oxide film on the side walls of the gate electrode 8 and the n+ type source region i4a.Next, anisotropic tri-etching is performed to remove the oxide film on the n+ type source region 4a, and the gate electrode 8 is etched. An oxide film 10 is left on the side wall of the electrode 8.

FIG. 4(e) Next, a selective vapor phase epitaxy tungsten film 11 is grown on the exposed n+ type source region 4a, completely filling the first trench 15. Next, the unnecessary nitride arsenal film 21 and #(heat Jl! 20) are etched away.Next, a thin acid arsenal film (not shown) for ion implantation is grown.

Next, using a normal film lithography technique and using a resist (not shown) and a buried acid film 6 for RI outside the trench element as a mask layer, arsenic is ion-implanted.
Define the 10-shaped train area (old). Next, the unnecessary thin acid 1 arsenic film for ion implantation is etched away.
The semiconductor device is completed by growing the arsenic film 12 and the phosphosilicate glass CPSG film 13, controlling the depth of each impurity region by high-temperature heat treatment, forming a window in the electrode contact T, forming the AI wiring 14, etc.

In the above embodiment, all the element isolation regions are formed of trenches and trench-embedded insulating films.
In order to simplify the manufacturing process, it may be formed by the usual LOCO8 method using selective oxidation. However, LOCO
In the case of method 3, the high concentration drain region has an electric field concentration area on the field acid film side, so there is a drawback that the resulting withstand voltage is slightly lower. By optimizing the concentration of the regions and the size of each region, it can also be used for short channel transistors having a vertical LDD structure. In this case, since the low concentration region can be formed only in the drain region by self-line, the speed can be further increased compared to a short channel transistor having a normal LDD structure.9 As shown in the above embodiments, According to the semiconductor device of the present invention, the bottom of the n-type drain region can be formed flat, and a train region can be formed in which the bottom of the n-type drain region is completely surrounded by the n-type train region (offset region). As a result, it is possible to form a high breakdown voltage element with an extremely large depletion layer spread and an extremely high breakdown voltage without causing local electric field concentration. Furthermore, since a low concentration region that expands the depletion layer can be formed in the self-alignment line, the so-called offset resistance can be reduced to a constant value, making it possible to increase the speed. Further, since no gate electrode area on the surface is required and the entire region can be formed as a self-line, a fine vertical MO8 field effect transistor can be formed, thereby making it possible to achieve high integration.

[Effects of the Invention] As described above, according to the present invention, in an MIS type semiconductor device, a trench is formed on the surface of a semiconductor substrate with a periphery defined by a trench and a trench-embedded insulating film, and the bottom is surrounded by a low concentration impurity region. Jfif type, in which the high concentration impurity region formed at the bottom of the trench is used as the drain region, the high concentration impurity region formed at the bottom of the trench is used as the source region, and the conductive film provided on the sidewalls of the trench from I to I through a gate insulating film is used as the gate electrode. Since the MOS transistor structure is formed, the bottom of the high concentration impurity region can be formed flat, and the drain region can be formed in which the bottom of the high concentration impurity region is completely surrounded by the low concentration impurity region, thereby improving the junction breakdown voltage. Very high MO
5 High functionality due to the ability to form a field effect transistor, high integration due to the ability to form a so-called low concentration offset region in the self-alignment line, and the ability to form a reduced type MO3 field effect transistor that does not require the area of the gate electrode on the surface. By reducing the offset resistance to a constant value, it is possible to perform high-speed 1-hi. In other words, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly integrated, and high-speed semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of a semiconductor device of the present invention, and FIG. 3 is a semiconductor device of the present invention. FIG. 7 is a schematic side sectional view of a third embodiment of the device. 4(a) to 4(e) are process cross-sectional views of an embodiment of the manufacturing method for a semiconductor device of the present invention, and FIG. 5 is a schematic side cross-sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon substrate, and 2 is a p-type well region. 3 is a p-type channel stopper region, 4a is an n-type source region, 4b is an n-type drain region, 5 is an n-type drain region (offset region), 6 is a buried insulating film for trench isolation, and 7 is a gate 8 is a gate electrode, 9 is a sidewall insulating film, 10 is an insulating film between the gate electrode/source electrode, and 11 is a buried conductive film (selective vapor phase growth tungsten film). 2 is a block oxide film, 3 is a phosphosilicate glass (PSG) film, 4 is an A1 wiring, 5 is a first trench, 6 is a third trench, 7 is a first trench-embedding insulating film, 8 is a second trench 19 indicates a p-type channel region.

Claims (5)

[Claims] (1) A first high concentration impurity region of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, and a low concentration impurity region of an opposite conductivity type formed in direct contact with the bottom of the first high concentration impurity region. a channel region of one conductivity type formed under the low concentration impurity region, and a first region formed in the semiconductor substrate defining a part of the first high concentration impurity region and the low concentration impurity region. a trench, a gate insulating film formed on the side walls and bottom of the first trench, a gate electrode formed on the side walls of the first trench via the gate insulating film, and a bottom of the first trench. 1. A semiconductor device comprising: a second heavily doped impurity region of an opposite conductivity type; and a conductive region to which a fixed voltage is applied to the second heavily doped region. (2) The semiconductor according to claim 1, wherein the conductive region comprises a conductive film formed at the center of the gate electrode via an insulating film and a wiring body connected to the conductive film. Device. (3) The conductive region is formed in a part of the second high concentration impurity region and is made of a conductive film in which a second trench reaching the semiconductor substrate is buried. 1. Semiconductor device described in Section 1. (4) The first high concentration impurity region and the low concentration impurity region are defined by the first trench and a third trench filled with an insulating film. semiconductor devices. (5) The low concentration impurity region extends to the lower end of the gate electrode, and the second high concentration impurity region is surrounded by the channel region at approximately equal intervals. The semiconductor device according to item 1.