JPH0456360A - Metal-insulator semiconductor field-effect transistor - Google Patents

Abstract

PURPOSE:To increase a speed and achieve high integration by forming a buried metallic or metallic silicide film in a semiconductor substrate just under a gate electrode and forming opposite-conductivity-type high-concentration impurity source and drain regions at both ends of the gate electrode. CONSTITUTION:A gate electrode 8 is made on an n<-> type silicon substrate 1 and p<+> type source and drain regions 3a and 3b are made in self-aligned manner at both ends of the gate electrode 8. A shallow trench 4 is made in the n<-> type silicon substrate 1 just under the gate electrode 8 at equal distances from both ends thereof and filled with a selective chemical gas phase growth tungsten silicide film 5 to form a P channel MIS field effect transistor. Therefore, the ON resistance of the channel is decreased and a speed is increased by forming the trench filling metallic or metallic silicide film 5 forming a Schottky barrier. The depletion layer of the p<+> type drain region 3b spreads little and high integration is achieved by shortening the gate.

Description

[Detailed Description of the Invention] [Summary] A gate electrode is provided on an n-type semiconductor substrate via a gate oxide film, p+ type source/drain regions are provided at both ends of the gate electrode, and p+ type source/drain regions are provided on both ends of the gate electrode. A P-channel MIS field effect transistor is formed in which a trench is provided in the n-type semiconductor substrate directly below the gate electrode, and the trench is buried with a metal film or metal silicide film. By forming a metal film or metal silicide film that forms a Schottky barrier between the semiconductor substrate and the semiconductor substrate in a part of the channel region, the transfer conductance can be increased, thereby increasing the speed. The metal silicide film can suppress the spread of the depletion layer in the train region and increase the punch-through breakdown voltage, making it possible to miniaturize the gate length and achieve high integration. Field of Application] The present invention relates to MIS type semiconductor devices, and in particular to P-channel M, which has low mobility and is difficult to improve transfer conductance.
9 Regarding increasing the speed of IS field effect transistors Conventionally, in order to increase the speed of P-channel MIS field effect transistors, conventional MIS field effect transistors were formed in which highly doped source/drain regions were provided in self-alignment lines at both ends of the gate electrode. The transfer conductance has been improved by miniaturizing the gate length, that is, by shortening the channel length, but currently the only ion species that forms the source and drain regions is boron, which has a large diffusion coefficient. The drain region is formed deeply,
Therefore, the lateral diffusion under the gate electrode is large and punch-through phenomenon easily occurs, which makes it difficult to further reduce the gate length, and this problem has become a major problem in the literature. ing. Therefore, there is a need for a means for forming a high-speed, highly integrated P-channel MIS field effect transistor that can improve the transfer conductance and further miniaturize the gate length.

[Prior Art] FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor, in which 51 is an n-type silicon (Si) substrate, 52 is an n-type silicon (Si) substrate, and 52 is an n-type silicon (Si) substrate.
53 is a p-type channel stopper region, 53 is a p-type source train region, 54 is a field oxide film, 55 is a gate oxide film, 56 is a gate electrode, 57 is an oxide film for impurity blocking,
58 is a phosphosilicate glass (PSG) film, and 59 is an A1 wiring.

In the figure, a gate electrode 56 is provided on an n-type silicon (Si) substrate 51 with a gate oxide film 55 interposed therebetween.
A p-type source train region 5 is provided at both ends of the gate electrode 56.
A P-channel short-channel MIS field-effect transistor of conventional structure is formed.

Although it is extremely simple and easy to manufacture, the highly concentrated source/drain regions formed by boron ion implantation are formed deep, resulting in large lateral diffusion under the gate electrode and large curvature of the diffusion layer. Since the depletion layer spreads widely and punch-through occurs easily, the gate length cannot be miniaturized, making it difficult to achieve high integration.The on-resistance of the channel is large, making it difficult to improve the transfer conductance and making it difficult to increase speed. There were some drawbacks.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional examples, in the conventional conventional P-channel sysjeet channel MIS field effect transistor, high concentration Since the source/drain region cannot be formed shallowly, lateral diffusion under the gate electrode is large, easily causing punch-through phenomenon.
In short, it was difficult to further reduce the gate length, making it difficult to achieve high integration.Due to the difficulty of reducing the gate length, it was difficult to reduce the channel on-resistance, and it was difficult to improve the transfer conductance, so it was difficult to achieve higher speeds. That was difficult.

[Means for Solving the Problems 1] The above problem consists of a semiconductor substrate of one conductivity type, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a semiconductor substrate of one conductivity type. a buried metal film or metal silicide film provided on the semiconductor substrate immediately below the gate electrode equidistant from both ends of the gate electrode; and a source made of a high concentration impurity of an opposite conductivity type provided at both ends of the gate electrode. The problem is solved by the MIS field effect transistor of the present invention, which comprises a drain region.

[Function] In other words, in the semiconductor device of the present invention, a gate electrode is provided on an n-type semiconductor substrate via a gate oxide film, p-type source train regions are provided at both ends of the gate electrode, and the gate electrode A P-channel MIS field effect transistor is formed in which a trench is provided in the n-type semiconductor substrate immediately below the gate electrode at an equal distance from both ends of the transistor, and the trench is buried with a metal film or metal silicide film. There is. Therefore, by forming a trench-embedding metal film or metal silicide film in a part of the channel region to form a Schottky barrier between the gate electrode and the semiconductor substrate, the on-resistance of the channel can be reduced. A metal film or metal silicide film formed by burying a trench provided in a part of the channel region can suppress the expansion of the depletion layer in the drain region, and increase the speed by increasing the transfer conductance. Since the punch-through breakdown voltage can be increased, the gate length can be made finer, thereby making it possible to achieve higher integration. In other words, it is possible to obtain a MIS field effect transistor that allows formation of extremely high-speed and highly integrated semiconductor integrated circuits.

[Example] The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view of a first embodiment of the MIS field effect transistor of the present invention, and FIG. 2 is a schematic side sectional view of the MIS field effect transistor of the present invention.
FIG. 3 is a schematic side sectional view of a second embodiment of a field effect transistor; FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention; FIGS.
e) is a process cross-sectional view of an embodiment of the manufacturing method for an MIs field effect transistor of the present invention.

Identical objects are indicated by the same numbers and symbols throughout the figures.

Figure 1 shows the MI of the present invention when using an n-type silicon substrate.
This is a schematic side sectional view of the first embodiment of the S field effect transistor, in which 1 is an n-type silicon substrate of about 10 C-, 2 is an n-type channel stopper region of about 10 C, and 3a is a p++ of about 10 C1. Source area, 3b
is a p+ type drain region 4 of approximately 1020 cm-3 in depth, 5 is a trench-embedding metal film or metal silicide film (selective chemical vapor deposition tungsten silicide film), and 6 is a field oxidation of approximately 600 n- film, 7 is a gate oxide film of about 18n-, 8 is 300 r
A gate electrode of about um, 9 an oxide film for impurity blocking of about 351, and 10 a 6G.

A phosphosilicate glass (PSC) film of about n- thickness, and 11 indicate about one A1 wiring.

In the figure, a gate electrode 8 is provided on an n-type silicon substrate 1 via a gate oxide M7, and p-type source/drain regions (3a, 3b ) is provided, and an n-
A P-channel MI having a structure in which a shallow trench 4 is provided in a type silicon substrate 1, and this trench 4 is buried with a selective chemical vapor deposition tungsten silicide film 5.
An S field effect transistor is formed. Therefore, it is possible to self-line the gate electrode 8 and form a trench-buried metal film or metal silicide film 5 in a part of the channel region to form a Schottky barrier between it and the n-type silicon substrate 1. The metal film or metal silicide film 5 formed by filling the trench 4 provided in a part of the channel region improves the speed by reducing the on-resistance and increasing the transfer conductance. Spreading can be suppressed and p-type source/drain regions (3a, 3b)
Since it is possible to increase the punch-through breakdown voltage between the gates, it is possible to miniaturize the gate length, thereby making it possible to achieve high integration.

FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention, and 1 to 69 to 11 are first
The same thing as in the figure, 7a is the first gate oxide film, 7b is the second gate oxide film.
8a is the first gate electrode, 8b is the second gate oxide film,
The gate electrode 12 indicates an n-type impurity region.

In the figure, a trench-embedded metal film or metal silicide film (selective chemical vapor deposition tungsten silicide M) 5 is formed in the self-line directly under the first gate electrode 8a via the first gate oxide film 7a. , a second gate electrode 8b (sidewall gate electrode) is in contact with the first gate electrode 8a, and a second gate electrode 8b (sidewall gate electrode) is in contact with the first gate electrode 8a, and a second gate electrode 8b (sidewall gate electrode) is formed on the sidewall of the first gate electrode 8a. Membrane 7
b, and is also formed via DSA (Diffus
P-type source/drain regions (3a, 3b) and n-type impurity region 12 (the surface is inverted to become a channel region) are formed in the second gate electrode 8b on the self-alignment line using the self-alignment (edSelf-Alignment) technology. In this embodiment, since the present embodiment can be formed more finely than the first embodiment, higher speed and higher integration can be expected.

FIG. 3 is a schematic side sectional view of the third embodiment of the MIS field effect transistor of the present invention, where 1 to 3b, 6 to 11, are the same as in FIG. 1, 4a is the first trench, and 4b is the second trench. The trench 5b indicates a second trench-embedded metal film or metal silicide film (selective chemical vapor deposition tungsten silicide film).

In the figure, a gate oxide film 7 and a gate electrode 8 are embedded in a first trench 4a provided in an n-type silicon substrate 1, a first self-line is formed inside the first trench 4a, and a self-line is formed in the trench 4a. A second trench 4b is provided in the second trench 4b, and a metal film or metal silicide film (selective chemical vapor deposition tungsten silicide film) 5b is provided in the second trench 4b.
is buried, and p-type source/drain regions (3a, 3b) are formed in the self-line in the first trench 4a.

In this example, it can be formed finer than in the first example, resulting in higher speed and higher integration.Since the gate electrode can be buried in the first trench, it is possible to flatten it and improve reliability. It becomes possible.

Next, an embodiment of the method for manufacturing an MTS field effect transistor according to the present invention will be described with reference to FIGS. 4(a) to 4(e). However, only the manufacturing method for forming the MIS field effect transistor of the present invention will be described here, and the manufacturing method for forming various elements (other transistors, resistors, capacitors, etc.) mounted on general semiconductor integrated circuits will be described. is omitted.

FIG. 4(a) By applying a conventional technique, an n-type channel stopper region 2 and a field oxide film 6 of about 600n- are formed on an n-type silicon substrate 1.

FIG. 4(b) Next, a chemical vapor deposition oxide film 13 of about 350 nm is grown using a conventional photolithography technique and using a resist (not shown) as a mask layer. selectively dry etching. Then the resist is removed. Next, a base oxide film 14 of about 20n- is grown. Next, a nitride film of about 400 nIl is grown. Next, anisotropic dry etching is performed to leave the nitride film 15 on the sidewalls of the remaining chemical vapor grown oxide film 13.Next, the base oxide film 14 is etched away using the nitride film 15 as a mask layer.

Next, using the nitride film 15 and the chemical vapor grown oxide film 13 as mask layers, the n-type silicon substrate 1 is etched to a depth of approximately 1.5 cm. A trench 4 of the 11th order is formed.

FIG. 4(C) Next, the trench 4 is filled with a tungsten silicide film 5 by selective chemical vapor deposition.

FIG. 4(d) Next, the nitride film 15 is etched away using boiled phosphoric acid (9).The base oxide film 14 is then etched away.

Next, a gate oxide film 7 of about 18n- is grown.Next, a polycrystalline silicon film containing impurities is grown and anisotropic dry etching is performed to form a buried gate electrode 8 in the opening of the chemical vapor grown oxide film 13. 9. FIG. 4(e) Next, the remaining chemical vapor grown oxide film 13 is removed by etching. Next, an impurity blocking oxide film 9 of about 35n- is grown. Next, using a conventional photolithography technique, using a resist (not shown), gate electrode 8, and field oxide film 6 as mask layers, boron ions are implanted to form p-type source/drain regions (3a, 3b). . Then, the resist is removed.

Next, by applying conventional techniques, a phosphosilicate glass (PSG) film 10 is grown, the impurity diffusion region is activated and the depth is controlled by high-temperature heat treatment, an electrode contact window is formed, and an AI wiring 11 is formed. etc. to perform P channel MI
Completes the S field effect transistor.

As shown in the embodiments above, according to the MIS field effect transistor of the present invention, the trench-embedded metal is self-lined to the gate electrode and formed in a part of the channel region to form a Schottky barrier between it and the semiconductor substrate. By forming a metal film or metal silicide film, the on-resistance of the channel can be reduced and the transfer conductance can be increased, thereby increasing the speed. Since the spread of the depletion layer in the drain region can be suppressed and the bunch-through breakdown voltage between the source train regions can be increased, the gate length can be made finer, thereby making it possible to achieve higher integration.

[Effects of the Invention] As explained above, according to the present invention, in a MIS field effect transistor, a metal film or a metal silicide film that forms a Schottky barrier between the semiconductor substrate and a part of the channel region can be formed. The metal film or metal silicide film formed in a part of the channel region can suppress the spread of the depletion layer in the drain region and increase the bunch-through breakdown voltage. , it is possible to achieve high integration by miniaturizing the gate length. In other words, it is possible to obtain a MIS field effect transistor that enables the formation of extremely high-speed and highly integrated semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of the MIS field effect transistor of the present invention, and FIG. 2 is a schematic side sectional view of the MIS field effect transistor of the present invention.
FIG. 3 is a schematic side sectional view of a second embodiment of a field effect transistor; FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention; FIGS.
e) is a process sectional view of an embodiment of the manufacturing method for an MIS field effect transistor of the present invention, and FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor. In the figure, 1 is an n-type silicon substrate, 2 is an n-type channel stopper region, 3a is a p-type source region, 3b is a p-type drain region, 4.4a and 4b are trenches, and 5.5b is a trench-filled metal. film or metal silicide film (selective chemical vapor deposition tungsten silicide film), 6 is a field oxide film, 7.7a, 1b are gate oxide films, 8.8a, 8b are gate electrodes, 9 is an oxide film for impurity blocking, 10 11 is an AI wiring, and 12 is an n-type impurity region.

Claims (2)

[Claims] (1) A semiconductor substrate of one conductivity type, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and the gate electrode equidistant from both ends of the gate electrode. It is characterized by comprising a buried metal film or a metal silicide film provided directly below the semiconductor substrate, and source/drain regions made of high concentration impurities of opposite conductivity type provided at both ends of the gate electrode. MIS field effect transistor. (2) The gate electrode includes a first gate electrode provided on a gate insulating film, and a second gate electrode in contact with the first gate electrode and provided on a side wall of the first gate electrode. The MIS field effect transistor according to claim 1, characterized in that the MIS field effect transistor comprises: