JPH05299648A - Mis field effect transistor - Google Patents
Mis field effect transistorInfo
- Publication number
- JPH05299648A JPH05299648A JP3177334A JP17733491A JPH05299648A JP H05299648 A JPH05299648 A JP H05299648A JP 3177334 A JP3177334 A JP 3177334A JP 17733491 A JP17733491 A JP 17733491A JP H05299648 A JPH05299648 A JP H05299648A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- region
- drain region
- type
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 43
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 230000010354 integration Effects 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 description 25
- 108091006146 Channels Proteins 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 230000005684 electric field Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 239000005360 phosphosilicate glass Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000002040 relaxant effect Effects 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＭＩＳ型半導体装置に係
り、特に高い接合耐圧を有する高集積なＭＩＳ電界効果
トランジスタに関する。従来、高耐圧のＭＩＳ電界効果
トランジスタに関しては、印加される高電圧による電界
の集中を緩和させ、接合の耐圧を上昇させるために、通
常構造のＭＩＳ電界効果トランジスタのドレイン領域の
みを修正し、高濃度不純物領域からなるドレイン領域と
ゲート電極直下のチャネル領域間に、高濃度不純物領域
に接して、いわゆるオフセット領域となる低濃度不純物
領域を設け、且つチャネルストッパー領域を高濃度不純
物領域に接触させないように離間して形成していた。従
来構造の高耐圧のＭＩＳ電界効果トランジスタの製造
は、通常のＭＩＳ電界効果トランジスタの製造同様に比
較的簡単であるが、耐圧を十分確保するためには極めて
大きな面積を有する低濃度不純物領域が必要で、高集積
化が計れないこと、低濃度不純物領域長を一定に形成で
きないため、低濃度不純物領域（オフセット領域）の抵
抗が変動するので高速化が難しいこと、高濃度不純物領
域からなるドレイン領域の拡散層を平坦に形成できない
ため、拡散層のカーブの部分に電界の集中が起こり、接
合の耐圧を十分増大できないので高機能化が達成できな
いこと等の問題が顕著になってきている。そこで、微細
なレイアウト面積で、一定な抵抗を持つ低濃度不純物領
域を形成でき、十分な耐圧が確保できる高速且つ高集積
な高耐圧のＭＩＳ電界効果トランジスタを形成できる手
段が要望されている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device, and more particularly to a highly integrated MIS field effect transistor having a high junction breakdown voltage. Conventionally, with respect to a high breakdown voltage MIS field effect transistor, in order to reduce the concentration of an electric field due to a high voltage applied and to increase the breakdown voltage of the junction, only the drain region of a MIS field effect transistor having a normal structure is modified to A low-concentration impurity region, which is a so-called offset region, is provided between the drain region formed of the high-concentration impurity region and the channel region immediately below the gate electrode, in contact with the high-concentration impurity region, and the channel stopper region is not in contact with the high-concentration impurity region. Were formed separately. Manufacturing of a high breakdown voltage MIS field effect transistor having a conventional structure is relatively easy as in the case of manufacturing a normal MIS field effect transistor, but a low concentration impurity region having an extremely large area is required to sufficiently secure the breakdown voltage. Therefore, high integration cannot be achieved, and the length of the low-concentration impurity region cannot be formed uniformly. Therefore, the resistance of the low-concentration impurity region (offset region) varies, which makes it difficult to increase the speed, and the drain region including the high-concentration impurity region Since the diffusion layer cannot be formed flat, an electric field is concentrated in the curved portion of the diffusion layer, and the breakdown voltage of the junction cannot be sufficiently increased, so that problems such as high performance cannot be achieved have become remarkable. Therefore, there is a demand for a means capable of forming a low-concentration impurity region having a constant resistance with a fine layout area and capable of forming a high-speed and highly-integrated high-breakdown-voltage MIS field-effect transistor capable of ensuring a sufficient withstand voltage.
【０００２】[0002]
【従来の技術】図５は従来のＭＩＳ電界効果トランジス
タの模式側断面図で、51はｐ- 型シリコン基板、52はｐ
型チャネルストッパー領域、53はｎ+ 型ドレイン領域、
54はｎ型ドレイン領域（オフセット領域）、55はｎ+ 型
ソース領域、56はフイ ールド酸化膜、57はゲート酸化
膜、58はゲート電極、59は不純物ブロック用酸化膜、60
は燐珪酸ガラス（ＰＳＧ）膜、61はAl配線を示してい
る。同図においては、ｐ- 型シリコン基板51にｎ+ 型ド
レイン領域53、ｎ型ドレイン領域（オフセット領域）5
4、ｎ+ 型ソース領域55、ゲート電極57からなる、いわ
ゆるオフセットゲート構造の高耐圧のＮチャネルＭＩＳ
電界効果トランジスタが形成されており、ｐ型チャネル
ストッパー領域52はｎ+ 型ドレイン領域53とは離れて形
成されている。ここではｎ型ドレイン領域（オフセット
領域）54の濃度及び各領域のサイズを最適に選択して、
約60Ｖの耐圧が得られている。従来例では、ｎ型ドレイ
ン領域（オフセット領域）54がセルフアラインに形成で
きないため、位置合わせずれによりｎ型ドレイン領域
（オフセット領域）54の抵抗が変動するので高速化に難
があること、接合耐圧を上昇させるために形成するｎ型
ドレイン領域（オフセット領域）54が極めて広いレイア
ウト面積を必要とするので高集積化が計れないこと、ｎ
型ドレイン領域（オフセット領域）54の存在により、空
乏層が広がるため、ある程度の接合耐圧の上昇は得られ
るが、ｎ+型ドレイン領域53の拡散層のカーブの箇所に
電界が集中し、接合耐圧の上限がきめられるので、極め
て高い接合耐圧が得られないこと等の欠点があった。2. Description of the Related Art FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor, in which 51 is a p - type silicon substrate and 52 is a p-type silicon substrate.
Type channel stopper region, 53 is an n + type drain region,
54 n-type drain region (offset regions), the n + -type source region 55, the full Lee Rudo oxide film 56, the gate oxide film 57, 58 is a gate electrode, 59 is an impurity blocking oxide film, 60
Is a phosphosilicate glass (PSG) film, and 61 is an Al wiring. In the figure, an n + type drain region 53 and an n type drain region (offset region) 5 are formed on ap − type silicon substrate 51.
4, a high breakdown voltage N-channel MIS having an so-called offset gate structure composed of an n + type source region 55 and a gate electrode 57.
A field effect transistor is formed, and the p-type channel stopper region 52 is formed apart from the n + -type drain region 53. Here, the concentration of the n-type drain region (offset region) 54 and the size of each region are optimally selected,
A breakdown voltage of about 60V is obtained. In the conventional example, since the n-type drain region (offset region) 54 cannot be formed in self-alignment, the resistance of the n-type drain region (offset region) 54 changes due to misalignment, which makes it difficult to increase the speed and the junction breakdown voltage. Since the n-type drain region (offset region) 54 formed for increasing the voltage requires an extremely large layout area, high integration cannot be achieved.
Since the depletion layer spreads due to the presence of the type drain region (offset region) 54, the junction breakdown voltage can be increased to some extent, but the electric field is concentrated at the curved portion of the diffusion layer of the n + type drain region 53, and the junction breakdown voltage is increased. However, there is a drawback in that an extremely high junction withstand voltage cannot be obtained because the upper limit of is determined.
【０００３】[0003]
【発明が解決しようとする課題】本発明が解決しようと
する課題は、従来例に示されるように、従来のオフセッ
トゲート構造の高耐圧のＭＩＳ電界効果トランジスタに
おいては、製造バラツキによらない低濃度ドレイン領域
の抵抗が得られないので高速化が難しかったこと、微細
なレイアウト面積で十分な接合耐圧を確保できる低濃度
ドレイン領域が形成できなかったので高集積化が計れな
かったこと、平坦な拡散層を持つ高濃度ドレイン領域が
形成できなかったので極めて高い接合耐圧が得られなか
ったことである。The problem to be solved by the present invention is, as shown in the conventional example, that in a conventional high withstand voltage MIS field effect transistor having an offset gate structure, a low concentration which does not depend on manufacturing variations. It was difficult to increase the speed because the resistance of the drain region could not be obtained, and it was not possible to form a low-concentration drain region that could secure a sufficient junction breakdown voltage in a fine layout area, so high integration could not be achieved, and flat diffusion This means that a very high junction breakdown voltage could not be obtained because the high-concentration drain region having a layer could not be formed.
【０００４】[0004]
【課題を解決するための手段】上記課題は、一導電型半
導体基板と、前記半導体基板に設けられた第１のトレン
チと、前記第１のトレンチに埋め込まれた第１の絶縁膜
と、前記第１のトレンチと離間して前記半導体基板に設
けられた第２のトレンチと、前記第２のトレンチの側面
及び底面の前記半導体基板に設けられた反対導電型の低
濃度ドレイン領域と、前記低濃度ドレイン領域の一部に
接し、前記第１及び第２のトレンチ間の前記半導体基板
に設けられた反対導電型の高濃度ドレイン領域と、前記
第２のトレンチに埋め込まれた第２の絶縁膜と、前記半
導体基板上に設けられたゲート酸化膜と、前記ゲート酸
化膜上及び前記第２の絶縁膜上の一部に延在して設けら
れたゲート電極と、前記低濃度及び高濃度ドレイン領域
の反対側の前記ゲート電極端に整合し、前記半導体基板
に設けられた反対導電型の高濃度ソース領域とを備えて
なる本発明のＭＩＳ電界効果トランジスタによって解決
される。Means for Solving the Problems The above problems include a semiconductor substrate of one conductivity type, a first trench provided in the semiconductor substrate, a first insulating film embedded in the first trench, A second trench provided in the semiconductor substrate at a distance from the first trench; a low-concentration drain region of opposite conductivity type provided in the semiconductor substrate on a side surface and a bottom surface of the second trench; A high-concentration drain region of opposite conductivity type provided in the semiconductor substrate between the first and second trenches, which is in contact with a part of the concentration drain region, and a second insulating film embedded in the second trench. A gate oxide film provided on the semiconductor substrate, a gate electrode provided on the gate oxide film and a part of the second insulating film, and the low concentration and high concentration drains. On the opposite side of the area DOO electrostatic extremely consistent, it is solved by the MIS field effect transistor of the invention comprising a heavily doped source region of the opposite conductivity type provided in the semiconductor substrate.
【０００５】[0005]
【作 用】即ち、本発明のＭＩＳ電界効果トランジス
タにおいては、一導電型半導体基板に第１のトレンチが
設けられ、第１のトレンチは底面に一導電型のチャネル
ストッパー領域を備え、第１の絶縁膜で埋め込まれた素
子分離領域を形成している。第１のトレンチより離間し
て第２のトレンチが設けられ、第２のトレンチは側面及
び底面に反対導電型の低濃度ドレイン領域を備え、第２
の絶縁膜で埋め込まれており、この低濃度ドレイン領域
の一部に接して、第１及び第２のトレンチ間の半導体基
板に反対導電型の高濃度ドレイン領域が設けられてい
る。又、半導体基板表面にはゲート酸化膜が設けられ、
ゲート酸化膜上には第２のトレンチを埋め込んだ第２の
絶縁膜上の一部に延在したゲート電極が設けられ、高濃
度ドレイン領域と反対側のゲート電極端に整合して、低
濃度ドレイン領域と離間した高濃度ソース領域が設けら
れている構造を有するＭＩＳ電界効果トランジスタが形
成されている。したがって、第２のトレンチの側面及び
底面に低濃度ドレイン領域を形成できるため、低濃度ド
レイン領域の抵抗をトレンチの深さにより一定に形成で
きることによる高速化を、表面上のレイアウト面積の微
細な低濃度ドレイン領域を形成できることによる高集積
化を、空乏層の広がりを十分確保できる低濃度ドレイン
領域を形成できること、さらに第１及び第２のトレンチ
間に平坦な拡散層を持つ高濃度ドレイン領域を形成で
き、しかも印加電圧が異なるゲート電極と高濃度ドレイ
ン領域間に厚い第２の絶縁膜を介して形成できること等
により、高電圧による電界の集中を緩和できるので、接
合耐圧を大幅に増大できることによる高性能化を可能に
することができる。又、一部の構造を変更し、高濃度ソ
ース領域の近傍にのみ微細なチャネル領域を形成し、且
つ高濃度ドレイン領域を低濃度ドレイン領域で完全に包
含することにより閾値電圧を低減できるので、伝達コン
ダクタンスを上昇できることによる高速化及び高濃度ド
レイン領域におけるさらなる電界集中の緩和により、接
合耐圧をより増大できることによる高性能化を、Ｐチャ
ネルＭＩＳ電界効果トランジスタに限定すれば、第２の
トレンチの底部に低濃度ドレイン領域とオーミック接続
できるメタル層を埋め込むことにより、接合耐圧の増大
特性に影響を与えることなく低濃度ドレイン領域の抵抗
を低減できるので伝達コンダクタンスを上昇できること
による高速化を可能にすることもできる。即ち、極めて
高性能、高速且つ高集積な半導体集積回路の形成を可能
としたＭＩＳ電界効果トランジスタを得ることができ
る。[Operation] That is, in the MIS field-effect transistor of the present invention, a first conductivity type semiconductor substrate is provided with a first trench, and the first trench is provided with a first conductivity type channel stopper region on a bottom surface thereof. An element isolation region embedded with an insulating film is formed. A second trench is provided spaced apart from the first trench, the second trench having a low-concentration drain region of opposite conductivity type on a side surface and a bottom surface,
Of the low-concentration drain region, and a high-concentration drain region of opposite conductivity type is provided in the semiconductor substrate between the first and second trenches in contact with a part of the low-concentration drain region. Further, a gate oxide film is provided on the surface of the semiconductor substrate,
A gate electrode is provided on the gate oxide film, the gate electrode extending partly on the second insulating film filling the second trench, and aligned with the end of the gate electrode opposite to the high-concentration drain region to reduce the concentration of the low-concentration drain. A MIS field effect transistor having a structure in which a high-concentration source region separated from the drain region is provided is formed. Therefore, since the low-concentration drain region can be formed on the side surface and the bottom surface of the second trench, the resistance of the low-concentration drain region can be made constant according to the depth of the trench, thereby increasing the speed and reducing the layout area on the surface. High integration due to the formation of the concentrated drain region, formation of a low-concentration drain region capable of sufficiently ensuring the expansion of the depletion layer, and formation of a high-concentration drain region having a flat diffusion layer between the first and second trenches In addition, since the thick second insulating film can be formed between the gate electrode and the high-concentration drain region having different applied voltages, the concentration of the electric field due to the high voltage can be relaxed, so that the junction breakdown voltage can be significantly increased. Performance can be enabled. Further, the threshold voltage can be reduced by changing a part of the structure, forming a fine channel region only near the high-concentration source region, and completely including the high-concentration drain region in the low-concentration drain region, If the P-channel MIS field-effect transistor is limited to the P-channel MIS field-effect transistor, it is possible to improve the performance by increasing the junction breakdown voltage by increasing the speed by increasing the transfer conductance and relaxing the electric field concentration in the high-concentration drain region. By embedding a metal layer in ohmic contact with the low-concentration drain region, it is possible to reduce the resistance of the low-concentration drain region without affecting the junction breakdown voltage increase characteristics, and thus to increase the transfer conductance and thus speed up. You can also That is, it is possible to obtain a MIS field-effect transistor capable of forming a semiconductor integrated circuit having extremely high performance, high speed, and high integration.
【０００６】[0006]
【実施例】以下本発明を、図示実施例により具体的に説
明する。図１は本発明のＭＩＳ電界効果トランジスタに
おける第１の実施例の模式側断面図、図２は本発明のＭ
ＩＳ電界効果トランジスタにおける第２の実施例の模式
側断面図、図３は本発明のＭＩＳ電界効果トランジスタ
における第３の実施例の模式側断面図、図４(a) 〜(e)
は本発明のＭＩＳ電界効果トランジスタにおける製造方
法の一実施例の工程断面図である。全図を通じ同一対象
物は同一符号で示す。図１はｐ型シリコン基板を用いた
際の本発明のＭＩＳ電界効果トランジスタにおける第１
の実施例の模式側断面図で、１は1016cm-3程度のｐ- 型
シリコン基板、２は1017cm-3程度のｐ型チャネルストッ
パー領域、３は深さ６μm程度の第１のトレンチ（素子
分離用）、４は第１の絶縁膜（第１のトレンチ埋め込み
用）、５は深さ５μm程度の第２のトレンチ（ゲート電
極／ｎ+ 型ドレイン領域間の分離領域形成用）、６は第
２の絶縁膜（第２のトレンチ埋め込み用）、７は1016cm
-3〜1017cm-3程度のｎ型ドレイン領域、８は1020cm-3程
度のｎ+ 型ドレイン領域、９は1020cm-3程度のｎ+ 型ソ
ース領域、10は50nm程度のゲート酸化膜、11はゲート長
３μm程度のゲート電極、12は35nm程度の不純物ブロッ
ク用酸化膜、13は0.6μm 程度の燐珪酸ガラス（ＰＳ
Ｇ）膜、14は１μm程度のAl配線を示している。同図に
おいては、ｐ- 型シリコン基板１に第１のトレンチ３が
設けられ、第１のトレンチ３は底面にｐ型チャネルスト
ッパー領域２を備え、第１の絶縁膜４で埋め込まれた素
子分離領域を形成している。第１のトレンチ３より離間
して第２のトレンチ５が設けられ、第２のトレンチ５は
側面及び底面にｎ型ドレイン領域７を備え、第２の絶縁
膜６で埋め込まれており、このｎ型ドレイン領域７の一
部に接して、第１及び第２のトレンチ（３、５）間のｐ
- 型シリコン基板１にｎ+型ドレイン領域８が設けられ
ている。又、ｐ- 型シリコン基板１表面にはゲート酸化
膜10が設けられ、ゲート酸化膜10上には第２のトレンチ
５を埋め込んだ第２の絶縁膜６上の一部に延在したゲー
ト電極11が設けられ、ｎ+ 型ドレイン領域８と反対側の
ゲート電極11端に整合して、ｎ型ドレイン領域７と離間
したｎ+ 型ソース領域９が設けられている構造を有する
ＮチャネルのＭＩＳ電界効果トランジスタが形成されて
いる。したがって、第２のトレンチ５の側面及び底面に
ｎ型ドレイン領域７を形成できるため、ｎ型ドレイン領
域７の抵抗をトレンチの深さにより一定に形成できるこ
とによる高速化を、表面上のレイアウト面積の微細なｎ
型ドレイン領域７を形成できることによる高集積化を、
空乏層の広がりを十分確保できるｎ型ドレイン領域７を
形成できること、さらに第１及び第２のトレンチ間
（３、５）に平坦な拡散層を持つｎ+ 型ドレイン領域８
を形成でき、しかも印加電圧が異なるゲート電極11とｎ
+ 型ドレイン領域８間に厚い第２の絶縁膜６を介して形
成できること等により、高電圧による電界の集中を緩和
できるので、接合耐圧を大幅に増大できることによる高
性能化を可能にすることができる。なお、本実施例にお
いては約200 Ｖの接合耐圧を有するＭＩＳ電界効果トラ
ンジスタを得ることができる。図２は本発明のＭＩＳ電
界効果トランジスタにおける第２の実施例の模式側断面
図で、１〜14は図１と同じ物を、15はｎ- 型不純物領
域、16はｐ型不純物領域を示している。同図において
は、ｎ+ 型ソース領域９の底面及び側面に沿ってｐ型不
純物領域16（ゲート電極下の表面領域がチャネル領域と
なる）が設けられ、ｎ+ 型ドレイン領域８、ｎ型ドレイ
ン領域７及びｐ型不純物領域16を包含するｎ- 型不純物
領域15が設けられている以外は図１と同じ構造に形成さ
れている。本実施例においては、第１の実施例の効果に
加え、いわゆるＤＳＡ（Ｄｉｆーｆｕｓｉｏｎ Ｓｅｌ
ｆ Ａｌｉｇｎｅｄ）法により微細なチャネル領域16が
形成でき、閾値電圧を低減できるので、伝達コンダクタ
ンスを上昇できることによる高速化及びｎ+ 型ドレイン
領域８におけるさらなる電界集中の緩和により、接合耐
圧をより増大できることによる高性能化を可能にするこ
ともできる。図３は本発明のＭＩＳ電界効果トランジス
タにおける第３の実施例の模式側断面図で、Ｐチャネル
ＭＩＳ電界効果トランジスタを構成した場合で、３〜
６、10〜14は図１と同じ物を、17はｎ- 型シリコン基
板、18はｎ型チャネルストッパー領域、19はｐ型ドレイ
ン領域、20はｐ+ 型ドレイン領域、21はｐ+ 型ソース領
域、22は埋め込みメタル層を示している。同図において
は、半導体基板17、チャネルストッパー領域18及びソー
スドレイン領域（19、20、21）の導電型をすべて反対に
し、第２のトレンチ５の底部にメタル層22を埋め込んで
いる以外は図１と同じ構造に形成されている。本実施例
においては、第１の実施例の効果に加え、第２のトレン
チ５の底部にｐ型ドレイン領域19とオーミック接続でき
るメタル層22を埋め込むことにより、接合耐圧の増大特
性に影響を与えることなくｐ型ドレイン領域19の抵抗を
低減できるので伝達コンダクタンスを上昇できることに
よる高速化を可能にすることもできる。次いで本発明に
係るＭＩＳ電界効果トランジスタの製造方法の一実施例
について図４(a) 〜(e) 及び図１を参照して説明する。
ただし、ここでは本発明のＭＩＳ電界効果トランジスタ
の形成に関する製造方法のみを記述し、一般の半導体集
積回路に搭載される各種の素子（他のトランジスタ、抵
抗、容量等）の形成に関する製造方法の記述は省略す
る。 図４(a) ｐ- 型シリコン基板１に30nm程度の酸化膜23及び50nm程
度の窒化膜24を成長する。次いで通常のフォトリソグラ
フィー技術を利用し、レジスト（図示せず）をマスク層
として、窒化膜24及び酸化膜23を選択的に順次エッチン
グする。次いで露出したｐ- 型シリコン基板１を６μm
程度エッチングし、素子分離用の第１のトレンチ３を形
成する。次いでレジスト（図示せず）を除去する。次い
で20nm程度のイオン注入用の酸化膜（図示せず）を成長
する。次いで窒化膜24をマスク層として、硼素をイオン
注入する。次いで熱処理をおこない、第１のトレンチ３
の底面にｐ型チャネルストッパー領域２を形成する。次
いでイオン注入用の酸化膜（図示せず）をエッチング除
去する。次いで化学気相成長酸化膜４を成長し、異方性
ドライエッチングして、第１のトレンチ３に埋め込み、
素子分離領域を形成する。 図４(b) 次いで通常のフォトリソグラフィー技術を利用し、レジ
スト（図示せず）及び酸化膜４をマスク層として、窒化
膜24及び酸化膜23を選択的に順次エッチングする。次い
で露出したｐ- 型シリコン基板１を５μm程度エッチン
グし、第２のトレンチ５を形成する。次いでレジスト
（図示せず）を除去する。次いで20nm程度のイオン注入
用の酸化膜（図示せず）を成長する。次いで窒化膜24及
び酸化膜４をマスク層として、第２のトレンチ５の側面
及び底面に燐を斜めイオン注入する。次いでイオン注入
用の酸化膜（図示せず）をエッチング除去する。 図４(c) 次いで化学気相成長酸化膜６を成長し、異方性ドライエ
ッチングして、第２のトレンチ５に埋め込む。次いで熱
処理をおこない、第２のトレンチ５の側面及び底面にｎ
型ドレイン領域７を形成する。次いで不要の窒化膜24及
び酸化膜23をエッチング除去する。 図４(d) 次いで50nm程度のゲート酸化膜10を成長する。次いで30
0 nm程度の不純物を含む多結晶シリコン膜を成長する。
次いで通常のフォトリソグラフィー技術を利用し、レジ
スト（図示せず）をマスク層として、多結晶シリコン膜
を異方性ドライエッチングし、ゲート電極11を形成す
る。次いでレジスト（図示せず）を除去する。 図４(e) 次いで通常のフォトリソグラフィー技術を利用し、レジ
スト（図示せず）、ゲート電極11、酸化膜４及び酸化膜
６をマスク層として、砒素をイオン注入して、ｎ+ 型ド
レイン領域８及びｎ+ 型ソース領域９を画定する。次い
でレジスト（図示せず）を除去する。 図１ 次いで不要部のゲート酸化膜10をエッチング除去する。
次いで通常の技法を適用することにより、不純物ブロッ
ク用酸化膜12及び燐珪酸ガラス（ＰＳＧ）膜13の成長、
高温熱処理による不純物拡散領域の活性化及び深さの制
御、電極コンタクト窓の形成、Al配線14の形成等をおこ
なってＭＩＳ電界効果トランジスタを完成する。以上実
施例に示したように、本発明のＭＩＳ電界効果トランジ
スタによれば、第２のトレンチの側面及び底面に低濃度
ドレイン領域を形成できるため、低濃度ドレイン領域の
抵抗をトレンチの深さにより一定に形成できることによ
る高速化を、表面上のレイアウト面積の微細な低濃度ド
レイン領域を形成できることによる高集積化を、空乏層
の広がりを十分確保できる低濃度ドレイン領域を形成で
きること、さらに第１及び第２のトレンチ間に平坦な拡
散層を持つ高濃度ドレイン領域を形成でき、しかも印加
電圧が異なるゲート電極と高濃度ドレイン領域間に厚い
第２の絶縁膜を介して形成できること等により、高電圧
による電界の集中を緩和できるので、接合耐圧を大幅に
増大できることによる高性能化を可能にすることができ
る。又、一部の構造を変更し、高濃度ソース領域の近傍
にのみ微細なチャネル領域を形成し、且つ高濃度ドレイ
ン領域を低濃度ドレイン領域で完全に包含することによ
り閾値電圧を低減できるので、伝達コンダクタンスを上
昇できることによる高速化及び高濃度ドレイン領域にお
けるさらなる電界集中の緩和により、接合耐圧をより増
大できることによる高性能化を、ＰチャネルＭＩＳ電界
効果トランジスタに限定すれば、第２のトレンチの底部
に低濃度ドレイン領域とオーミック接続できるメタル層
を埋め込むことにより、接合耐圧の増大特性に影響を与
えることなく低濃度ドレイン領域の抵抗を低減できるの
で伝達コンダクタンスを上昇できることによる高速化を
可能にすることもできる。EXAMPLES The present invention will be described in detail below with reference to illustrated examples. FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field effect transistor of the present invention, and FIG.
Schematic side sectional view of the second embodiment of the IS field effect transistor, FIG. 3 is a schematic side sectional view of the third embodiment of the MIS field effect transistor of the present invention, FIGS. 4 (a) to 4 (e).
FIG. 6 is a process cross-sectional view of an example of the method for manufacturing the MIS field effect transistor of the present invention. The same object is denoted by the same symbol throughout the drawings. FIG. 1 shows a first MIS field effect transistor of the present invention when a p-type silicon substrate is used.
1 is a p - type silicon substrate of about 10 16 cm -3 , 2 is a p-type channel stopper region of about 10 17 cm -3 , and 3 is a first depth of about 6 μm. Trenches (for element isolation), 4 is a first insulating film (for embedding the first trench), 5 is a second trench having a depth of about 5 μm (for forming an isolation region between the gate electrode / n + type drain region) , 6 is the second insulating film (for filling the second trench), 7 is 10 16 cm
-3 to 10 17 cm -3 about n type drain region, 8 about 10 20 cm -3 about n + type drain region, 9 about 10 20 cm -3 about n + type source region, 10 about 50 nm. Gate oxide film, 11 is a gate electrode with a gate length of about 3 μm, 12 is an oxide film for impurity blocking with a thickness of about 35 nm, 13 is phosphosilicate glass (PS with a thickness of about 0.6 μm).
G) film, 14 shows Al wiring of about 1 μm. In the figure, a p − type silicon substrate 1 is provided with a first trench 3, a first trench 3 is provided with a p type channel stopper region 2 on the bottom surface, and an element isolation film filled with a first insulating film 4 is provided. Forming a region. A second trench 5 is provided apart from the first trench 3, the second trench 5 is provided with an n-type drain region 7 on a side surface and a bottom surface, and is filled with a second insulating film 6. In contact with a part of the type drain region 7, p between the first and second trenches (3, 5)
An n + type drain region 8 is provided on the − type silicon substrate 1. Further, a gate oxide film 10 is provided on the surface of the p − type silicon substrate 1, and a gate electrode extending on a part of the second insulating film 6 in which the second trench 5 is embedded on the gate oxide film 10. An N channel MIS having a structure in which 11 is provided and an n + type source region 9 is provided which is aligned with the end of the gate electrode 11 opposite to the n + type drain region 8 and is separated from the n type drain region 7. A field effect transistor is formed. Therefore, the n-type drain region 7 can be formed on the side surface and the bottom surface of the second trench 5, so that the resistance of the n-type drain region 7 can be made constant depending on the depth of the trench, thereby increasing the speed and reducing the layout area on the surface. Fine n
High integration due to the formation of the mold drain region 7,
It is possible to form the n-type drain region 7 capable of sufficiently ensuring the expansion of the depletion layer, and further, the n + -type drain region 8 having a flat diffusion layer between the first and second trenches (3, 5).
Can be formed and the applied voltage is different from that of the gate electrodes 11 and n.
Since the thick second insulating film 6 can be formed between the + type drain regions 8 and the like, the concentration of the electric field due to the high voltage can be alleviated, so that the junction breakdown voltage can be greatly increased and the performance can be improved. it can. In this embodiment, a MIS field effect transistor having a junction breakdown voltage of about 200 V can be obtained. FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention. 1 to 14 are the same as those in FIG. 1, 15 is an n − type impurity region, and 16 is a p type impurity region. ing. In the figure, a p-type impurity region 16 (the surface region under the gate electrode serves as a channel region) is provided along the bottom surface and side surface of the n + -type source region 9, and the n + -type drain region 8 and the n-type drain region 8 are formed. The structure is the same as that of FIG. 1 except that an n − type impurity region 15 including the region 7 and the p type impurity region 16 is provided. In addition to the effect of the first embodiment, the present embodiment has a so-called DSA (Dif-fusion Sel).
Since the fine channel region 16 can be formed by the f Aligned) method and the threshold voltage can be reduced, the junction breakdown voltage can be further increased by speeding up by increasing the transfer conductance and further relaxing the electric field concentration in the n + type drain region 8. It is possible to improve the performance by FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field-effect transistor of the present invention, which shows a case where a P-channel MIS field-effect transistor is constructed.
6, 10 to 14 are the same as those in FIG. 1, 17 is an n - type silicon substrate, 18 is an n-type channel stopper region, 19 is a p-type drain region, 20 is a p + -type drain region, 21 is a p + -type source A region, 22 is a buried metal layer. In the figure, the semiconductor substrate 17, the channel stopper region 18, and the source / drain regions (19, 20, 21) are all opposite in conductivity type, and a metal layer 22 is buried in the bottom of the second trench 5. It is formed in the same structure as 1. In the present embodiment, in addition to the effect of the first embodiment, by embedding a metal layer 22 capable of ohmic-connecting with the p-type drain region 19 at the bottom of the second trench 5, the junction breakdown voltage increasing characteristics are affected. Since the resistance of the p-type drain region 19 can be reduced without increasing, the transfer conductance can be increased, and thus the speed can be increased. Next, an embodiment of a method of manufacturing a MIS field effect transistor according to the present invention will be described with reference to FIGS. 4 (a) to 4 (e) and FIG.
However, here, only the manufacturing method relating to the formation of the MIS field-effect transistor of the present invention will be described, and the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted in a general semiconductor integrated circuit will be described. Is omitted. 4A, an oxide film 23 of about 30 nm and a nitride film 24 of about 50 nm are grown on the p − type silicon substrate 1. Next, using a normal photolithography technique, the nitride film 24 and the oxide film 23 are selectively and sequentially etched using a resist (not shown) as a mask layer. Then, expose the exposed p − -type silicon substrate 1 to 6 μm
Etching to some extent to form a first trench 3 for element isolation. Then, the resist (not shown) is removed. Then, an oxide film (not shown) for ion implantation having a thickness of about 20 nm is grown. Next, boron is ion-implanted using the nitride film 24 as a mask layer. Then, heat treatment is performed to form the first trench 3
A p-type channel stopper region 2 is formed on the bottom surface of the. Next, the oxide film (not shown) for ion implantation is removed by etching. Then, a chemical vapor deposition oxide film 4 is grown, anisotropic dry etching is performed, and the first trench 3 is buried.
An element isolation region is formed. 4B, using a normal photolithography technique, the nitride film 24 and the oxide film 23 are selectively sequentially etched using the resist (not shown) and the oxide film 4 as a mask layer. Then, the exposed p − type silicon substrate 1 is etched by about 5 μm to form a second trench 5. Then, the resist (not shown) is removed. Then, an oxide film (not shown) for ion implantation having a thickness of about 20 nm is grown. Then, phosphorus is obliquely ion-implanted into the side surface and the bottom surface of the second trench 5 using the nitride film 24 and the oxide film 4 as a mask layer. Next, the oxide film (not shown) for ion implantation is removed by etching. 4C, a chemical vapor deposition oxide film 6 is grown, and anisotropic dry etching is performed to fill the second trench 5. Then, a heat treatment is performed to remove n on the side surface and the bottom surface of the second trench 5.
The mold drain region 7 is formed. Then, the unnecessary nitride film 24 and oxide film 23 are removed by etching. 4 (d) Next, a gate oxide film 10 having a thickness of about 50 nm is grown. Then 30
A polycrystalline silicon film containing impurities of about 0 nm is grown.
Then, using a normal photolithography technique, the polycrystal silicon film is anisotropically dry-etched using a resist (not shown) as a mask layer to form a gate electrode 11. Then, the resist (not shown) is removed. Next, using a normal photolithography technique, arsenic is ion-implanted using a resist (not shown), the gate electrode 11, the oxide film 4 and the oxide film 6 as a mask layer, and an n + type drain region is formed. 8 and an n + type source region 9 are defined. Then, the resist (not shown) is removed. Then, the unnecessary portion of the gate oxide film 10 is removed by etching.
Then, by applying a usual technique, the growth of the impurity blocking oxide film 12 and the phosphosilicate glass (PSG) film 13,
The MIS field effect transistor is completed by activating the impurity diffusion region and controlling the depth thereof by high temperature heat treatment, forming an electrode contact window, forming an Al wiring 14, and the like. As described in the above embodiments, according to the MIS field-effect transistor of the present invention, since the low-concentration drain region can be formed on the side surface and the bottom surface of the second trench, the resistance of the low-concentration drain region depends on the depth of the trench. It is possible to form a low-concentration drain region capable of ensuring a sufficient spread of the depletion layer, high integration due to formation of a constant layout area, high integration due to formation of a fine layout area on the surface, and first and A high-concentration drain region having a flat diffusion layer can be formed between the second trenches, and a thick second insulating film can be formed between the gate electrode and the high-concentration drain region having different applied voltages. Since the concentration of the electric field due to can be alleviated, the junction breakdown voltage can be significantly increased, and high performance can be achieved. Further, the threshold voltage can be reduced by changing a part of the structure, forming a fine channel region only near the high-concentration source region, and completely including the high-concentration drain region in the low-concentration drain region, If the P-channel MIS field-effect transistor is limited to the P-channel MIS field-effect transistor, it is possible to improve the performance by increasing the junction breakdown voltage by increasing the speed by increasing the transfer conductance and relaxing the electric field concentration in the high-concentration drain region. By embedding a metal layer in ohmic contact with the low-concentration drain region, it is possible to reduce the resistance of the low-concentration drain region without affecting the junction breakdown voltage increase characteristics, and thus to increase the transfer conductance and thereby speed up the process. You can also
【０００７】[0007]
【発明の効果】以上説明のように本発明によれば、ＭＩ
Ｓ電界効果トランジスタにおいて、第２のトレンチの側
面及び底面にセルフアラインで低濃度ドレイン領域を形
成できるため、抵抗を一定に形成できることによる高速
化を、表面上のレイアウト面積を微細に形成できること
による高集積化を、さらにゲート電極との間に厚い絶縁
膜を持ち、拡散層が平坦な高濃度ドレイン領域を形成で
きるため、接合耐圧を大幅に増大できる（約200 Ｖの耐
圧保証が可能）ことによる高性能化を可能にすることが
できる。即ち、極めて高性能、高速且つ高集積な半導体
集積回路の形成を可能としたＭＩＳ電界効果トランジス
タを得ることができる。As described above, according to the present invention, MI
In the S field effect transistor, since the low-concentration drain region can be formed on the side surface and the bottom surface of the second trench by self-alignment, the speed can be increased due to the constant formation of the resistance, and the high-speed due to the formation of a fine layout area on the surface. Due to the integration, the junction breakdown voltage can be significantly increased (a breakdown voltage of about 200 V can be guaranteed) because a high-concentration drain region having a thick insulating film with the gate electrode and a flat diffusion layer can be formed. It is possible to achieve high performance. That is, it is possible to obtain a MIS field-effect transistor capable of forming a semiconductor integrated circuit having extremely high performance, high speed, and high integration.
【図１】 本発明のＭＩＳ電界効果トランジスタにおけ
る第１の実施例の模式側断面図FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field effect transistor of the present invention.
【図２】 本発明のＭＩＳ電界効果トランジスタにおけ
る第２の実施例の模式側断面図FIG. 2 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention.
【図３】 本発明のＭＩＳ電界効果トランジスタにおけ
る第３の実施例の模式側断面図FIG. 3 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention.
【図４(a) 〜(e) 】 本発明のＭＩＳ電界効果トランジ
スタにおける製造方法の一実施例の工程断面図4 (a) to 4 (e) are process cross-sectional views of an example of a method of manufacturing the MIS field effect transistor of the present invention.
【図５】 従来のＭＩＳ電界効果トランジスタの模式側
断面図FIG. 5 is a schematic side sectional view of a conventional MIS field effect transistor.
１ ｐ- 型シリコン基板 ２ ｐ型チャネルストッパー領域 ３ 第１のトレンチ（素子分離用） ４ 第１の絶縁膜（第１のトレンチ埋め込み用） ５ 第２のトレンチ（ゲート電極／ｎ+ 型ドレイン領域
間の分離領域形成用） ６ 第２の絶縁膜（第２のトレンチ埋め込み用） ７ ｎ型ドレイン領域 ８ ｎ+ 型ドレイン領域 ９ ｎ+ 型ソース領域 10 ゲート酸化膜 11 ゲート電極 12 不純物ブロック用酸化膜 13 燐珪酸ガラス（ＰＳＧ）膜 14 Al配線 15 ｎ- 型不純物領域 16 ｐ型不純物領域 17 ｎ- 型シリコン基板 18 ｎ型チャネルストッパー領域 19 ｐ型ドレイン領域 20 ｐ+ 型ドレイン領域 21 ｐ+ 型ソース領域 22 埋め込みメタル層DESCRIPTION OF SYMBOLS 1 p − type silicon substrate 2 p type channel stopper region 3 first trench (for element isolation) 4 first insulating film (for filling first trench) 5 second trench (gate electrode / n + type drain region) 6) Second insulating film (for filling second trench) 7 n-type drain region 8 n + -type drain region 9 n + -type source region 10 gate oxide film 11 gate electrode 12 impurity block oxidation Film 13 Phosphosilicate glass (PSG) film 14 Al wiring 15 n − type impurity region 16 p type impurity region 17 n − type silicon substrate 18 n type channel stopper region 19 p type drain region 20 p + type drain region 21 p + type Source region 22 Embedded metal layer
Claims (3)
設けられた第１のトレンチと、前記第１のトレンチに埋
め込まれた第１の絶縁膜と、前記第１のトレンチと離間
して前記半導体基板に設けられた第２のトレンチと、前
記第２のトレンチの側面及び底面の前記半導体基板に設
けられた反対導電型の低濃度ドレイン領域と、前記低濃
度ドレイン領域の一部に接し、前記第１及び第２のトレ
ンチ間の前記半導体基板に設けられた反対導電型の高濃
度ドレイン領域と、前記第２のトレンチに埋め込まれた
第２の絶縁膜と、前記半導体基板上に設けられたゲート
酸化膜と、前記ゲート酸化膜上及び前記第２の絶縁膜上
の一部に延在して設けられたゲート電極と、前記低濃度
及び高濃度ドレイン領域の反対側の前記ゲート電極端に
整合し、前記半導体基板に設けられた反対導電型の高濃
度ソース領域とを備えてなることを特徴とするＭＩＳ電
界効果トランジスタ。1. A semiconductor substrate of one conductivity type, a first trench provided in the semiconductor substrate, a first insulating film embedded in the first trench, and a first trench isolated from the first trench. A second trench provided in the semiconductor substrate, a low-concentration drain region of opposite conductivity type provided in the semiconductor substrate on a side surface and a bottom surface of the second trench, and a part of the low-concentration drain region are in contact with each other. A high-concentration drain region of opposite conductivity type provided in the semiconductor substrate between the first and second trenches, a second insulating film embedded in the second trench, and provided on the semiconductor substrate. A gate oxide film, a gate electrode provided on the gate oxide film and a part of the second insulating film, and the gate electrode on the opposite side of the low concentration and high concentration drain regions. Extremely matched, said semi-conductor MIS field-effect transistor, characterized by comprising a heavily doped source region of the opposite conductivity type formed on the substrate.
同等の幅を持ち、低濃度のドレイン領域と離間して、一
導電型半導体基板に一導電型の不純物領域が設けられ、
前記一導電型の不純物領域、高濃度ドレイン領域及び低
濃度ドレイン領域を包含して、一導電型半導体基板に反
対導電型の不純物領域が設けられていることを特徴とす
る特許請求の範囲請求項１記載のＭＩＳ電界効果トラン
ジスタ。2. A one-conductivity-type impurity region is provided in a one-conductivity-type semiconductor substrate along a side surface and a bottom surface of the source region and having a substantially equal width and spaced from a low-concentration drain region.
9. An impurity region of opposite conductivity type is provided on a semiconductor substrate of one conductivity type, including the impurity region of one conductivity type, a high concentration drain region and a low concentration drain region. 1. The MIS field effect transistor according to 1.
第２の絶縁膜で埋め込まれていることを特徴とする特許
請求の範囲請求項１記載のＭＩＳ電界効果トランジス
タ。3. The second trench has a metal layer at the bottom,
The MIS field effect transistor according to claim 1, wherein the MIS field effect transistor is embedded with a second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3177334A JPH05299648A (en) | 1991-06-22 | 1991-06-22 | Mis field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3177334A JPH05299648A (en) | 1991-06-22 | 1991-06-22 | Mis field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05299648A true JPH05299648A (en) | 1993-11-12 |
Family
ID=16029160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3177334A Pending JPH05299648A (en) | 1991-06-22 | 1991-06-22 | Mis field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05299648A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003249646A (en) * | 2001-12-18 | 2003-09-05 | Fuji Electric Co Ltd | Semiconductor device |
| US6730961B2 (en) | 2001-12-18 | 2004-05-04 | Fuji Electric Co., Ltd. | Semiconductor device |
| US6861702B2 (en) | 2001-05-11 | 2005-03-01 | Fuji Electric Co., Ltd. | Semiconductor device |
| JP2006173357A (en) * | 2004-12-15 | 2006-06-29 | Fuji Electric Device Technology Co Ltd | Semiconductor device and its manufacturing method |
| US7312133B2 (en) | 2001-05-18 | 2007-12-25 | Fuji Electric Holdings Co., Ltd. | Method of manufacturing semiconductor device |
| JP2011249354A (en) * | 2010-05-21 | 2011-12-08 | Sharp Corp | Manufacturing method of semiconductor device |
| JP2013135233A (en) * | 2011-12-22 | 2013-07-08 | Samsung Electronics Co Ltd | Semiconductor element and forming method thereof |
-
1991
- 1991-06-22 JP JP3177334A patent/JPH05299648A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861702B2 (en) | 2001-05-11 | 2005-03-01 | Fuji Electric Co., Ltd. | Semiconductor device |
| US7312133B2 (en) | 2001-05-18 | 2007-12-25 | Fuji Electric Holdings Co., Ltd. | Method of manufacturing semiconductor device |
| JP2003249646A (en) * | 2001-12-18 | 2003-09-05 | Fuji Electric Co Ltd | Semiconductor device |
| US6730961B2 (en) | 2001-12-18 | 2004-05-04 | Fuji Electric Co., Ltd. | Semiconductor device |
| JP4524989B2 (en) * | 2001-12-18 | 2010-08-18 | 富士電機システムズ株式会社 | Semiconductor device |
| JP2006173357A (en) * | 2004-12-15 | 2006-06-29 | Fuji Electric Device Technology Co Ltd | Semiconductor device and its manufacturing method |
| JP2011249354A (en) * | 2010-05-21 | 2011-12-08 | Sharp Corp | Manufacturing method of semiconductor device |
| JP2013135233A (en) * | 2011-12-22 | 2013-07-08 | Samsung Electronics Co Ltd | Semiconductor element and forming method thereof |
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