JP2011249354A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device capable of downsizing a laterally diffused metal oxide semiconductor (LDMOS) transistor and reducing the manufacturing cost thereof.SOLUTION: According to this invention, there is provided a manufacturing method for a semiconductor device comprising: a step of forming a trench on a semiconductor substrate; a step of forming a silicon layer on the trench; a step of introducing a first conductive type impurity into the silicon layer; a step of diffusing the impurity in the silicon layer by heating the silicon layer introduced with the impurity in an inert atmosphere; a step of heating the silicon layer diffused with the impurity in an oxidative atmosphere; and a step of forming a drain contact region introduced with the first conductive type impurity and a body region introduced with a second conductive impurity so as to sandwich the trench between the drain contact region and the body region.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As a high-current switching element for power supply, there is an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor. Since this LDMOS has a high breakdown voltage and a low on-resistance, it is used as a so-called power semiconductor device.

FIG. 6 shows an example of this LDMOS transistor. The LDMOS transistor includes a P-type body region 212, an STI (shallow trench isolation) region 210 and a drain diffusion region 216 formed in an N-type well region (HV-NWELL) 202 on a P-type semiconductor substrate 201. . Further, in the P-type body region 212, an N ⁺ -type source diffusion region 215 and a P ⁺ diffusion region 217 that is an electrode extraction portion of the P-type body region 212 are formed, and part of the P-type body region 212 and the STI region 210 are formed. A gate electrode 214 is formed thereon via a gate oxide film 213. Further, in this LDMOS transistor, an N-type drift layer 209 which is an N-type impurity diffusion layer is formed below the STI region 210 so as to surround the region 210 in order to reduce the on-resistance.

  The LDMOS transistor having such a structure can improve the high breakdown voltage and the low on-resistance in a trade-off relationship by adjusting the impurity concentration of the N-type well region 202 and the N-type drift layer 209. It is widely used in LDMOS transistors that require a breakdown voltage of ˜150V.

  It is known that the N-type drift layer 209 of the LDMOS transistor is formed by ion implantation from an opening formed in the photoresist film through a selective oxide film using a well-known photolithography technique. (For example, Patent Document 1). Here, it is known that the selective oxide film can be formed by a LOCOS oxidation method, and this selective oxide film can be replaced with an STI structure (see, for example, Patent Document 1).

JP-A-2005-150300

However, when the drift layer is formed by the above-described formation method, it is necessary to provide a margin in the design of the LDMOS transistor in consideration of alignment and line width deviation caused by the photolithography technique.
For example, in the case of the LDMOS transistor of FIG. 6, it is necessary to secure a distance (space) between the P-type body region 212 and the N-type drift layer 209 in order to give the LDMOS transistor withstand voltage. In consideration of variations in the position of the mask pattern to be exposed, it is necessary to form a drift layer by disposing a photoresist film. Further, (2) the width of the mask pattern transferred to the photoresist film (for example, the line width of the mask pattern) determines the width of the N-type drift layer 209. In contrast, the N-type drift layer 209 needs to be formed.
For this reason, the size of the LDMOS transistor is increased, and the area occupied on the wafer is increased, resulting in an increase in manufacturing cost. Therefore, a manufacturing method that reduces the size of the LDMOS transistor and reduces the manufacturing cost is desired.

  The present invention has been made in view of such circumstances, and provides a manufacturing method for reducing the size of the LDMOS transistor and reducing the manufacturing cost.

  According to the present invention, a step of forming a trench on a semiconductor substrate, a step of forming a silicon layer on the trench, a step of introducing an impurity of a first conductivity type into the silicon layer, and the introduction of the impurity. The step of diffusing the impurities into the silicon layer by heating the silicon layer in an inert atmosphere, the step of heating the silicon layer in which the impurities are diffused in an oxidizing atmosphere, and sandwiching the trench Forming a drain contact region into which the first conductivity type impurity is introduced and a body region into which the second conductivity type impurity is introduced, and heating the silicon layer in an oxidizing atmosphere. The silicon layer is heated in an oxidizing atmosphere to oxidize the silicon layer to form an oxide layer and diffuse the impurities to the trench surface Allowed by the manufacturing method of a semiconductor device and forming a drift region between the body region and the drain contact region is provided.

According to the method of manufacturing a semiconductor device of the present invention, the silicon layer formed on the trench is oxidized to form an oxide layer, and the impurity is diffused into the trench surface, so that the body region and the drain contact region are formed. Since a drift region is formed between the body region and the drain contact region, a method for manufacturing a semiconductor device can be provided in which the element can be separated by a trench and the drift region can be disposed so as to surround the trench by self-alignment. . Since the drift region can be formed between the body region and the drain contact region without using a photolithography technique, a manufacturing method is provided that reduces the manufacturing cost compared to a method of manufacturing the drift region by a photolithography technique. The In addition, since the drift region is formed by diffusing the impurity, a manufacturing method is provided in which the position of the drift region is less likely to vary than in the photolithography technique. Therefore, a manufacturing method is provided that reduces the size of the semiconductor device and reduces the manufacturing cost.
In addition, since the drift region is disposed between the body region and the drain contact region so as to surround the trench, a method for manufacturing a semiconductor device with low on-resistance is provided.
Further, since the drain contact region and the body region are formed so as to sandwich the region where the drift region is formed, a method for manufacturing a semiconductor device suitable for increasing the breakdown voltage is provided. That is, if the impurity concentration in the drift region between the drain contact region and the body region is set lower than the impurity concentration in the drain contact region, a semiconductor device with a high breakdown voltage can be manufactured.

It is sectional drawing for demonstrating the process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing for demonstrating the process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing for demonstrating the process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing for demonstrating the process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing for demonstrating the modification of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the LDMOS transistor which concerns on background art.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a trench on a semiconductor substrate, a step of forming a silicon layer on the trench, a step of introducing an impurity of a first conductivity type into the silicon layer, Heating the silicon layer doped with impurities under an inert atmosphere to diffuse the impurities into the silicon layer; heating the silicon layer with impurities diffused under an oxidizing atmosphere; Forming a drain contact region into which the first conductivity type impurity is introduced and a body region into which the second conductivity type impurity is introduced so as to sandwich the trench, and the silicon layer under an oxidizing atmosphere. In the heating step, the silicon layer is heated in an oxidizing atmosphere to oxidize the silicon layer to form an oxide layer and to remove the impurities. It is diffused into inch surface, and forming a drift region between the body region and the drain contact region.

  Here, the step of introducing the first conductivity type impurity into the silicon layer may introduce the impurity into a partial region of the silicon layer on a region where the drift region is formed. That is, in the step of introducing the first conductivity type impurity into the silicon layer, the impurity may be introduced into a part of the silicon layer in a region including the region where the trench is formed.

  The step of forming a trench on the semiconductor substrate is a step of introducing a first conductivity type impurity into a partial region of the semiconductor substrate to form a well region, and then forming a trench in the well region. There may be. A drain contact region and a body region are formed in the well region so as to sandwich the trench, and the well region (a region other than the trench and the body region) functions as a drain region. That is, a region corresponding to the drain region is formed by introducing a first conductivity type impurity into a partial region in the semiconductor substrate to form a well region.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the silicon layer may be a step of forming a silicon layer having a thickness of 20 to 100 nm. If the silicon layer has a thickness of 20 nm or more, the introduced impurities are easily diffused uniformly. If the silicon layer has a thickness of 100 nm or less, the silicon layer is oxidized to form an oxide layer by stress. Defects are less likely to occur.

Further, the step of introducing the impurity may be a step of introducing arsenic or antimony as the impurity. In the case of the N-type conductivity type, a V-valent element such as phosphorus, arsenic, or antimony is usually used as an impurity.
According to the manufacturing method of the present invention, since the impurity is introduced into the silicon layer, the impurity is diffused into the silicon layer, and the impurity is diffused into the trench surface to form the drift region. There is no restriction on the depth of the impurity distribution. In other words, when the drift region is formed by using the conventional ion implantation method, it is difficult to use arsenic or antimony because the drift region is inside the semiconductor substrate. Arsenic or antimony can be used as an impurity for forming the region.
On the other hand, when the drift region is formed using arsenic or antimony as an impurity, even if the temperature for heating in the step of forming the drift region by diffusing the impurity into the trench surface varies, the drift region width and depth are affected. Few. For this reason, the drift region can be manufactured with high accuracy. According to this manufacturing method, a manufacturing method for reducing the size of the semiconductor device and reducing the manufacturing cost is provided.

The step of introducing the impurity includes a step of introducing a first conductivity type impurity into the silicon layer on the bottom surface of the trench, and a step of introducing a first conductivity type impurity into the silicon layer on the side surface of the trench. And a process comprising:
According to this manufacturing method, since the first conductivity type impurity is introduced into the silicon layer on the bottom and side surfaces of the trench, the impurity is uniformly introduced into the silicon layer on the trench.
Further, the step of introducing the impurity may be a step of rotating and implanting the impurity at a predetermined angle with respect to a normal direction of the semiconductor substrate.
According to this manufacturing method, since the impurity is rotationally implanted at the predetermined angle, the impurity is uniformly introduced into the silicon layer on the trench.

  Here, the rotation implantation is, for example, in the case of ion implantation, in which ions are implanted into the silicon layer by relatively rotating an ion source and a semiconductor substrate. In another embodiment to which this rotational implantation is applied, for example, impurities are introduced from a predetermined direction with respect to a plane parallel to the semiconductor substrate at a predetermined angle with respect to the normal direction of the semiconductor substrate. There is a step of introducing the impurity comprising a step and a step of introducing the impurity at the angle from the direction after rotating the semiconductor substrate. According to this embodiment, since the first conductivity type impurity is introduced in the predetermined direction and the predetermined angle, the impurity is uniformly introduced into the silicon layer on the trench.

In another aspect, the step of introducing the impurity may be a step of introducing the impurity at a plurality of twist angles with respect to the trench. The step of introducing the impurity into the silicon layer in the region where the trench is formed introduces the impurity at a predetermined angle with respect to the normal direction of the semiconductor substrate (for example, obliquely with respect to the normal direction of the substrate). However, here, introducing the impurity at a plurality of twist angles means that the impurity is introduced into the trench (for example, the groove of the trench) when the impurity is introduced at a predetermined angle with respect to the normal direction of the semiconductor substrate. Direction) After introducing an impurity from one direction on the semiconductor substrate plane, the impurity is introduced from another direction. That is, when the impurity introduction direction with respect to the normal direction (Z axis) of the semiconductor substrate is defined as a tilt angle, the twist angle refers to the impurity introduction direction in a plane (XY plane) parallel to the semiconductor substrate. .
According to this manufacturing method, since the impurity is introduced into the trench at a plurality of twist angles, the impurity is uniformly introduced into the silicon layer on the trench.
Thus, according to these manufacturing methods, since the impurity is uniformly introduced into the silicon layer on the trench, a drift region in which the impurity is more uniformly diffused can be formed. Therefore, the drift region can be manufactured with high accuracy.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode through an insulating film on a part of a region in which the body region is formed, and another step in the region in which the body region is formed. And a step of forming a source region into which the first conductivity type impurity is introduced in the portion.
According to this configuration, a method for manufacturing an LDMOS transistor suitable for increasing the breakdown voltage is provided.
Here, the step of forming the drain region and the step of forming the source region introduce a first conductivity type impurity having a concentration higher than the concentration of the first conductivity type impurity diffused in the drift region.

The method of manufacturing a semiconductor device according to the present invention further comprises a step of introducing a first conductivity type impurity into a part of the semiconductor substrate to form a well region, and a step of forming a trench on the semiconductor substrate. And a step of forming a trench in the well region.
According to this configuration, since the impurity concentration of the well region and the impurity concentration of the drift region can be adjusted, a manufacturing method suitable for a semiconductor device having a high breakdown voltage and a low on-resistance is provided.

  Note that the first conductivity type impurity means an N-type impurity or a P-type impurity. When the first conductivity type impurity is an N type impurity, the second conductivity type impurity is a P type impurity, and when the first conductivity type impurity is a P type impurity, the second conductivity type impurity is: N-type impurities.

  Hereinafter, embodiments of the present invention will be specifically described with reference to FIGS. The embodiments described below are merely specific examples of the present invention, and the present invention is not limited thereto.

[Embodiment 1]
1 to 4 are cross-sectional views for explaining steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The manufacturing method of the semiconductor device according to this embodiment is a manufacturing method for manufacturing an LDMOS transistor. Since a semiconductor substrate in which a well region is formed is used as a semiconductor substrate, the formation of the well region will be described.

First, as shown in FIG. 1A, an N-type well region 2 is formed by introducing an N-type impurity into a P-type semiconductor substrate 1. A P-type semiconductor substrate 1 is prepared as a semiconductor substrate, and an opening is formed in the photoresist mask on one surface (upper surface in FIG. 1) of the P-type semiconductor substrate 1 using a known photolithography technique. Next, phosphorus, which is an N-type impurity, is ion-implanted from the surface where the photoresist mask is formed at an energy of 4 keV and a dose of 8 × 10 ¹² / cm ² . Next, the P-type semiconductor substrate 1 implanted with phosphorus is annealed at 1200 ° C. for 10 hours. As a result, an N-type well region 2 that becomes the drain region of the LDMOS transistor is formed.

  Next, as shown in FIG. 1B, a pad oxide film 3 and a nitride film 4 having openings are formed in the P-type semiconductor substrate 1 in which the N-type well region 2 is formed. A pad oxide film 3 is formed with a thickness of about 30 nm on the surface of the P-type semiconductor substrate 1 where the N-type well region 2 is formed, and then a nitride film 4 is formed with a thickness of about 200 nm. Next, openings are formed in the formed pad oxide film 3 and nitride film 4 using a photoresist mask in which openings are formed by a well-known photolithography technique. This opening corresponds to a portion where a trench is formed, that is, an element isolation region, and is provided in a partial region inside the N-type well region 2 and a partial region at the boundary of the N-type well region 2. In FIG. 1 (b), two locations (locations corresponding to 5A in FIG. 1 (c)) inside the N-type well region 2 and two locations (5B in FIG. 1 (c)) at the boundary of the N-type well region 2. Corresponding portions), each forming an opening. In this embodiment, the opening at the boundary of the N-type well region 2 reaches the outside of the N-type well region 2 from the boundary of the N-type well region 2.

  Next, as shown in FIG. 1C, a trench 5 is formed in the P-type semiconductor substrate 1 using the pad oxide film 3 and the nitride film 4 in which the openings are formed as a mask. The trenches 5A and 5B of the P-type semiconductor substrate 1 are formed by etching the P-type semiconductor substrate 1 using the pad oxide film 3 and the nitride film 4 as a mask. The depth of the trenches 5A and 5B shown in FIG. 1C is 300 nm, and the width is 0.4 to 100 μm. As a result, a trench 5A is formed inside the N-type well region 2, and a trench 5B is formed at the boundary of the N-type well region 2.

Next, as shown in FIG. 2D, a polysilicon film 6 is formed on the surface of the P-type semiconductor substrate 1 where the trenches 5A and 5B are formed. The polysilicon film 6 is formed with a film thickness of, for example, 30 nm on the entire surface of the P-type semiconductor substrate 1 in which the trenches 5A and 5B are formed. The polysilicon film 6 may be lightly formed with a layer thickness of 20 to 100 nm. If the polysilicon film 6 has a layer thickness of 20 nm or more, impurities described later are easily diffused uniformly, and if the polysilicon film 6 has a layer thickness of 100 nm or less, defects due to stress occur due to oxidation of the polysilicon film 6 described later. Is unlikely to occur.
Further, as will be described later, since the trench 5A is buried, the thickness of the polysilicon film 6 is set to the width of the trench 5A (element isolation region, also referred to as isolation region) so that the trench 5A is not filled with the polysilicon film 6. To be decided. Preferably, it is formed with a film thickness of 20% or less with respect to the minimum trench width of the trench 5A, and more preferably with a film thickness of 10% or less with respect to the minimum trench width of the trench 5A. In this embodiment, since the minimum trench width of the trench 5A is 0.4 μm, the polysilicon film 6 is formed with a thickness of 30 nm.
The polysilicon film 6 may be a silicon film, and an amorphous silicon film 6 may be formed instead of the polysilicon film 6.

Next, as shown in FIG. 2E, an N-type impurity is introduced into the polysilicon film 6 in the region where the trench 5A is formed. First, a photoresist mask 7 having an opening on the polysilicon film 6 is formed by using a well-known photolithography technique. This opening is formed in the upper portion of the trench 5A, and in this embodiment, in the region between the trench 5A and the trench 5A and the trench 5A (region where an N-type drift layer and a P-type body region described later are disposed). An opening is formed. Next, arsenic, which is an N-type impurity, is ion-implanted through the photoresist mask 7 with an energy of 20 keV and a dose of 1 × 10 ¹² / cm ² .
In addition to arsenic, antimony may be used as the N-type impurity. The N-type drift layer 9 described later functions equivalent to arsenic even when antimony is used.

Next, as shown in FIG. 2F, the arsenic is diffused into the polysilicon film 6 by heating the polysilicon film 6 introduced with arsenic in an inert atmosphere. The photoresist mask 7 is removed, and the P-type semiconductor substrate 1 is annealed at 800 ° C. for 1 hour in an inert atmosphere (for example, N ₂ atmosphere).

Next, by heating the polysilicon film 6 in which arsenic has been diffused in an oxidizing atmosphere, the polysilicon film 6 is oxidized to form an oxide film 8 and arsenic is diffused to the surface of the trench 5A to form an N-type drift layer 9. Form. For example, the polysilicon film 6 in which arsenic is diffused is annealed at 850 ° C. for 40 minutes in an atmosphere of dry O ₂ . As a result, the polysilicon film 6 is oxidized to form an oxide film 8. Further, arsenic is diffused on the surface of the trench 5A to form the N-type drift layer 9.
In addition to the dry O ₂ , the oxidizing atmosphere may be an atmosphere by so-called H ₂ —O ₂ combustion.

  Next, as shown in FIG. 3G, a silicon oxide film 10 is formed on the entire surface of the P-type semiconductor substrate 1 on which the oxide film 8 is formed, and the surface on which the silicon oxide film 10 is formed is polished. Then, the nitride film 4 is exposed. A silicon oxide film 10 having a thickness of 800 nm is formed by using a high density plasma CVD (High Density Plasma CVD) method, and the oxide film 8 is covered with the silicon oxide film 10 and the trenches 5A and 5B are filled (trench filling). . Next, the surface of the P-type semiconductor substrate 1 on which the silicon oxide film 10 is formed is polished by CMP to flatten the surface, and part of the silicon oxide film 10 and the oxide film 8 are removed. Polishing is performed until the nitride film 4 is exposed on the surface.

Next, as shown in FIG. 3H, a P-type body region 12 into which a P-type impurity has been introduced is formed in a region sandwiched between the trenches 5A. First, the pad oxide film 3 and the nitride film 4 are removed (entire etching) to form a through oxide film 11. The through oxide film 11 is formed with a thickness of 20 nm. Next, using a well-known photolithography technique, a photoresist mask having an opening corresponding to a region sandwiched between the trenches 5A is formed on the through oxide film 11, and P-type impurities are formed through this photoresist mask. Boron is ion-implanted. This boron ion implantation is performed three times. The ion implantation conditions are, for example, that the first ion implantation has an energy of 200 keV and a dose amount of 8 × 10 ¹³ / cm ² , and the second ion implantation has an energy of 80 keV and a dose amount of 1 × 10 ¹² / cm ^2. The third ion implantation has an energy of 20 keV and a dose of 3 × 10 ¹¹ / cm ² . By this boron ion implantation, a P-type body region 12 is formed. After the boron ion implantation, the photoresist mask on the through oxide film 11 is removed, and the through oxide film 11 is also removed.
Note that the region sandwiched between the trenches 5A, that is, the region where the P-type body region 12 is disposed is a region adjacent to the N-type drift layer 9 in a plan view, and as shown in FIG. It may be a region adjacent to the mold drift layer 9 with a predetermined region in between.

  Next, as shown in FIG. 3I, a gate insulating film 13 is formed on the P-type semiconductor substrate 1 on which the body region is formed, and a gate electrode 14 is formed on the formed gate insulating film 13. . A gate insulating film 13 is formed to a thickness of 7 nm on the surface of the P-type semiconductor substrate 1, polysilicon is formed on the entire surface of the P-type semiconductor substrate 1 on the gate insulating film 13, and a known photolithography technique is used. The gate electrode 14 is formed by dry etching. The gate electrode 14 is disposed so as to straddle the P-type body region 12 and the trench 5A (N-type drift layer 9). That is, they are arranged so as to overlap with a part of the P-type body region 12 and a part of the N-type drift layer 9 in a plane.

Next, as shown in FIG. 4J, an N-type source diffusion region 15 and an N-type drain diffusion region 16 (also referred to as a drain contact region) are formed, and a P-type body extraction diffusion region 17 is formed.
The N-type source diffusion region 15 and the N-type drain diffusion region 16 are formed by using, for example, a well-known photolithography technique by ionizing phosphorus of an N-type impurity with an energy of 20 keV and a dose of 1.0 × 10 ¹⁴ / cm ² . inject. Here, the N-type source diffusion region 15 is disposed adjacent to the region in the P-type body region 12 where the P-type body extraction diffusion region 17 is disposed. The N-type drain diffusion region 16 is separated from the P-type body region 12 by the trench 5 </ b> A and is disposed in a region adjacent to the N-type drift layer 9. That is, the N-type drain diffusion region 16 and the P-type body region 12 are arranged so as to sandwich the N-type drift layer 9.
On the other hand, the P-type body extraction diffusion region 17 uses a well-known photolithography technique, for example, using BF ₂ as an ion species for boron of a P-type impurity, with BF ₂ having an energy of 20 keV and a dose amount of 3.0 × 10 ^15. Ion implantation at / cm ² . The P-type body extraction diffusion region 17 is disposed adjacent to the region in the P-type body region 12 where the N-type source diffusion region 15 is disposed.

Next, as shown in FIG. 4K, a well-known interlayer insulating film 18 is formed on the surface of the P-type semiconductor substrate 1 on which the gate electrode 14 is formed, and a well-known contact hole is formed to form a contact plug 19. Then, the common electrode 20, the drain electrode 21, and the gate extraction electrode 22 connected to the P-type body and the source are formed.
Thus, the LDMOS transistor is manufactured.

  In the above embodiment, the N-type impurity is substantially perpendicular to the P-type semiconductor substrate 1 in the step of introducing the N-type impurity into the polysilicon film 6 in the region where the trench 5A is formed (FIG. 2E). Although ion implantation is performed from the direction, for example, N-type impurities may be implanted from an oblique direction. FIG. 5 is a diagram for explaining a modification of the step of introducing an N-type impurity into the polysilicon film 6 in the region where the trench 5A is formed. In FIG. 5, a plane parallel to the surface of the P-type semiconductor substrate 1 is defined as an XY plane, and a direction orthogonal to the XY plane is defined as a Z direction.

As shown in FIG. 5, an N-type impurity (for example, arsenic) may be ion-implanted by providing a tilt angle. Here, the tilt angle refers to the incident angle of ions with respect to the normal direction (Z direction in FIG. 5) of the surface of the P-type semiconductor substrate 1 (θ shown in FIG. 5). For example, ion implantation may be performed under the conditions of a tilt angle of 30 degrees, an energy of 20 keV, and a dose of 1.0 × 10 ¹² / cm ² .

  Further, the N-type impurity may be ion-implanted a plurality of times, and the twist angle may be different between the ion implantations. Here, the twist angle is the groove direction of the trenches 5A and 5B (in FIG. 5, the direction orthogonal to the XZ plane) when ions are implanted from an oblique direction with respect to the normal direction of the P-type semiconductor substrate 1 surface. That is, the incident angle of ions with respect to the Y direction). For example, under the above-described ion implantation conditions (tilt angle 30 degrees), the first ion implantation is performed at a twist angle of 90 degrees (in the direction of the X-axis arrow in FIG. 5). The second ion implantation may be performed at a twist angle of 270 degrees (opposite to the X-axis arrow in FIG. 5).

Further, without providing a tilt angle (that is, tilt angle 0 degree), an N-type impurity is introduced into the silicon layer 6 on the bottom surface of the trench by ion implantation of the N-type impurity, and then a tilt angle is provided (for example, tilt angle). The N-type impurity may be introduced into the silicon layer 6 on the side surface of the trench by ion implantation of the N-type impurity. When the N-type impurity is ion-implanted with this tilt angle, ions may be implanted by a so-called rotational implantation method. For example, ion implantation is performed at a tilt angle of 0 degree, an energy of 20 keV, and a dose amount of 5.0 × 10 ¹¹ / cm ² , and then a rotation of a tilt angle of 30 degrees, an energy of 20 keV, and a dose amount of 5.0 × 10 ¹¹ / cm ² . An injection is recommended.

  In addition, two or more ion implantations may be performed, and in the rotational implantation, a P-type semiconductor substrate may be rotated (in addition to a scanning method that rotates an ion beam, a semiconductor substrate may be (It may be a scanning method that rotates).

  According to the conventional manufacturing method of an LDMOS transistor, a margin of 0.2 μm or more is ensured between the P-type body region 212 and the N-type drift layer 209 in order to give the LDMOS transistor withstand voltage, and further, a mask pattern line. Considering the width variation of 0.1 μm, a total margin of 0.3 μm or more is required. For example, the distance (half pitch; H shown in FIG. 6) between the central portion of the P-type body extraction diffusion region 217 and the central portion of the drain diffusion region 216 of the LDMOS transistor is 5.0 μm when the above margin is not considered. However, considering the above margin, the size becomes 5.3 μm, which is about 6% larger. In the LSI circuit for power supply, the ratio of the LDMOS transistor in the area is 20% to 80%. Therefore, the increase in the size of the LDMOS transistor as described above leads to an increase in manufacturing cost.

  However, according to the manufacturing method according to this embodiment, the N-type drift layer 9 is formed by oxidizing the polysilicon film 6 to form the oxide film 8 and diffusing arsenic on the surface of the trench 5A. For this reason, the causes of variations in the N-type drift layer 9 are limited to those caused by the concentration of the introduced impurity and those caused by temperature variations during impurity diffusion. It is only about%. For example, when the depth of the N-type drift layer 9 is 0.3 μm, the variation is only 0.03 μm.

  According to the manufacturing method according to this embodiment, the margin that has conventionally been required to be about 0.3 μm or more can be reduced to a margin of about 0.03 μm. Considering the half pitch of the LDMOS transistor, the conventional half pitch size of 5.3 μm can be formed with a half pitch size of 5.03 μm. For this reason, the size of the LDMOS transistor can be reduced by about 5.1%, and as a result, the manufacturing cost can be reduced.

  The present invention is not limited to the above-described embodiments and examples, and various modifications are possible within the scope of the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention. For example, regarding the conductivity type of the impurity, a form in which the N type and the P type are interchanged is included in the technical scope. The above embodiment can also be applied to an N-type semiconductor substrate.

1 P-type semiconductor substrate (semiconductor substrate)
2 N-type well region (well region)
3 Pad oxide film 4 Nitride film 5, 5A, 5B Trench 6 Polysilicon film (silicon layer)
7 Photoresist mask 8 Oxide film 9 N-type drift layer (drift region)
10 Silicon oxide film 11 Through oxide film 12 P-type body region (body region)
13 Gate insulating film (insulating film)
14 Gate electrode 15 N-type source diffusion region (source region)
16 N-type drain diffusion region (drain contact region)
17 P-type body extraction diffusion region 18 Interlayer insulating film 19 Contact plug 201 P-type semiconductor substrate 202 N-type well region (HV-NWELL)
209 N-type drift layer 210 STI region 212 P-type body region 213 Gate oxide film 214 Gate electrode 215 N ⁺ -type source diffusion region 216 Drain diffusion region 217 P ⁺ diffusion region

Claims (6)

Forming a trench on the semiconductor substrate;
Forming a silicon layer on the trench;
Introducing a first conductivity type impurity into the silicon layer;
Diffusing the impurities into the silicon layer by heating the silicon layer into which the impurities are introduced in an inert atmosphere;
Heating the silicon layer in which the impurities are diffused in an oxidizing atmosphere;
Forming a drain contact region into which the first conductivity type impurity is introduced and a body region into which the second conductivity type impurity is introduced so as to sandwich the trench;
With
The step of heating the silicon layer in an oxidizing atmosphere includes heating the silicon layer in an oxidizing atmosphere to oxidize the silicon layer to form an oxide layer and diffuse the impurities to the trench surface, A method of manufacturing a semiconductor device, wherein a drift region is formed between a body region and the drain contact region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the silicon layer is a step of forming a silicon layer having a thickness of 20 to 100 nm. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of introducing the impurity is a step of introducing arsenic or antimony as the impurity. Introducing the impurity includes introducing a first conductivity type impurity into the silicon layer on the bottom surface of the trench; introducing a first conductivity type impurity into the silicon layer on the side surface of the trench; The method for manufacturing a semiconductor device according to claim 1, wherein the method comprises: The method of manufacturing a semiconductor device according to claim 1, wherein the step of introducing the impurity is a step of rotating and implanting the impurity at a predetermined angle with respect to a normal direction of the semiconductor substrate. Forming a gate electrode through an insulating film on a portion in the region where the body region is formed;
Forming a source region doped with an impurity of a first conductivity type in another part of the region where the body region is formed;
The method for manufacturing a semiconductor device according to claim 1, further comprising:

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