CN209981217U - Semiconductor structure - Google Patents

Abstract

The embodiment of the utility model provides a semiconductor structure is related to, include: the device comprises a substrate, a grid structure and a control circuit, wherein the substrate is internally provided with the grid structure, and the top surface of the grid structure is exposed out of the substrate; the doped regions are positioned on two opposite sides of the grid structure; the interlayer dielectric layer covers the doped region and the grid structure, a contact hole is formed in the interlayer dielectric layer, and the contact hole exposes the surface of the doped region; the undoped semiconductor layer is positioned at the bottom of the contact hole and positioned on the surface of the doped region; the upper semiconductor layer is positioned in the contact hole, the upper semiconductor layer is positioned on the undoped semiconductor layer, and doped ions are arranged in the upper semiconductor layer. The utility model discloses can reduce the GIDL electric current of device, reduce static consumption.

Description

Semiconductor structure

Technical Field

The utility model relates to the field of semiconductor technology, in particular to semiconductor structure.

Background

With the progress of semiconductor manufacturing technology and the increasing demand for convenience of electronic devices, the trend of high integration and miniaturization of circuits is the current trend, and semiconductor structures are widely used in digital circuits and analog circuits, mainly represented by Metal-Oxide-semiconductor field-Effect transistors (MOSFETs).

At present, in order to improve the performance of integrated circuits and reduce the cost of chip manufacturing, manufacturers are continuously developing MOSFETs with smaller sizes. The success of MOSFETs in digital signal processing comes from the invention of CMOS logic circuits, which has the greatest advantage of theoretically not having static power dissipation, which can greatly increase the standby time of mobile electronic devices. However, as the size of the MOSFET is continuously reduced, leakage current phenomena causing static power consumption are gradually developed, which mainly include sub-threshold leakage current, gate leakage current, and gate-induced drain leakage (GIDL). GIDL current dominates leakage current when devices in the circuit are in a standby state or an off state. Therefore, how to shut down or reduce the GIDL current of the device has become a critical issue in the reliability of battery-powered technology.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a semiconductor structure reduces semiconductor structure's GIDL effect.

In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the device comprises a substrate, a grid structure and a control circuit, wherein the substrate is internally provided with the grid structure, and the top surface of the grid structure is exposed out of the substrate; the doped regions are positioned on two opposite sides of the grid structure; the interlayer dielectric layer covers the doped region and the grid structure, a contact hole is formed in the interlayer dielectric layer, and the contact hole exposes the surface of the doped region; the undoped semiconductor layer is positioned at the bottom of the contact hole and positioned on the surface of the doped region; the upper semiconductor layer is positioned in the contact hole, the upper semiconductor layer is positioned on the undoped semiconductor layer, and doped ions are arranged in the upper semiconductor layer.

Compared with the prior art, the embodiment of the utility model provides a technical scheme has following advantage:

the embodiment of the utility model provides a semiconductor structure, in the contact hole in the interlayer dielectric layer, the upper semiconductor layer that has the doping ion is located undoped semiconductor layer top to make the doping ion in the upper semiconductor layer diffuse to undoped semiconductor layer after being activated. The undoped semiconductor layer plays a role in preventing doped ions from diffusing into the doped region below the contact hole, so that the problem that the concentration of the doped ions in the overlapped region of the doped region and the grid structure is increased is solved, namely the undoped semiconductor layer is beneficial to indirectly reducing the concentration of the doped ions in the overlapped region of the doped region and the grid structure, the GIDL effect is further reduced, and the electrical performance of the semiconductor structure is improved.

In addition, the undoped semiconductor layer and the upper semiconductor layer are made of the same material, so that the contact resistance between the undoped semiconductor layer and the upper semiconductor layer is small, and the conductivity of the conductive plug is improved.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure;

fig. 2 to fig. 6 are schematic cross-sectional structures corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As can be seen from the background, the prior art semiconductor structure exhibits GIDL effects.

Fig. 1 is a schematic structural diagram of a semiconductor structure. Referring to fig. 1, a semiconductor structure includes: a substrate 21, wherein the substrate 21 is provided with a gate structure 23, and the top surface of the gate structure 23 is exposed out of the substrate 21; doped regions 24, the doped regions 24 being located at opposite sides of the gate structure 23; the interlayer dielectric layer 27, the doping region 24 and the gate structure 23 are covered by the interlayer dielectric layer 27, a contact hole is formed in the interlayer dielectric layer 27, and the surface of the doping region 24 is exposed by the contact hole; and a semiconductor layer 26, wherein the semiconductor layer 26 fills the contact hole, and the semiconductor layer 26 is located on the surface of the doped region 24.

In the process steps for fabricating the semiconductor structure described above, there is a problem that high concentration ions in the semiconductor layer 26 diffuse into the active region. The analysis finds that the reasons for the above problems are as follows: before the thermal annealing process step, in order to ensure that the manufactured semiconductor layer 26 has good conductivity, doping ions with a concentration higher than that of the doping region 24 are generally implanted into the semiconductor layer 26, and the thermal annealing process step activates the doping ions in the semiconductor layer 26, and the doping ions are transferred to the doping region 24 due to diffusion caused by concentration difference, so that the concentration of the doping ions in the overlapping region of the doping region 24 and the gate structure 23 is increased, and the GIDL effect is enhanced.

In order to solve the above problem, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, which forms an undoped semiconductor layer on the bottom of a contact hole, and forms an upper semiconductor layer with doped ions on the undoped semiconductor layer, so that the doped ions in the upper semiconductor layer are diffused into the undoped semiconductor layer during the thermal annealing process of the semiconductor structure, and the concentration of the doped ions in the overlap region between the doped region and the gate structure is not affected, thereby reducing the GIDL effect.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the present invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

The following describes a method for fabricating a semiconductor structure according to an embodiment of the present invention in detail with reference to the accompanying drawings.

Fig. 2 to fig. 6 are schematic cross-sectional structures corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 2, a substrate 11 is provided, the substrate 11 having a gate structure 13 therein, the substrate 11 exposing the top surface of the structure 13, and doped regions 14 formed in the substrate 11 on opposite sides of the gate structure 13.

In the present embodiment, an isolation structure 12 is further formed in the substrate 11, and the material of the isolation structure may be silicon oxide or silicon nitride.

In the present embodiment, two gate structures 13 are formed in the substrate. In other embodiments, the number of the gate structures may be one, three, or any positive natural number, and may be set according to actual needs. The gate structure 13 includes a gate dielectric layer 101, a gate electrode 102, and a passivation layer 103.

The process steps for forming the gate structure 13 are as follows:

a patterned photoresist is formed on the substrate 11, and the pattern of the gate structure 13 to be formed is defined by the patterned photoresist. And performing an etching process to remove the substrate at the position where the gate structure 13 needs to be formed, and forming a trench to be filled with the gate structure 13. Wherein, the etching method is preferably dry silicon etching. After the etching process, the gate dielectric layer 101 is formed by a high temperature oxidation process at a temperature of, for example, 900 to 1200 ℃. The high temperature oxidation process forms an oxide layer on the trench surface in the substrate 11, which serves as the gate dielectric layer 101, and forms an intermediate oxide layer (not shown) on the top surface of the substrate. In the present embodiment, the oxide layer formed on the top surface of the substrate 11 remains. In other embodiments, the intermediate oxide layer at the top surface of the substrate may be removed.

The gate electrode 102 is formed by depositing a material on the gate dielectric layer 101 and etching back by a dry etching process so that the gate electrode 102 covers a part of the surface of the gate dielectric layer 101. The gate 102 is formed and then deposited or filled again to form the passivation layer 103. The passivation layer 103 also needs to be etched back or planarized after deposition or filling, non-limiting examples of which include mechanical planarization methods and chemical mechanical polishing planarization methods.

In this embodiment, the top surface of the passivation layer 103 is flush with the surface of the intermediate oxide layer. In other embodiments, the top surface of the passivation layer 103 is flush with the top surface of the substrate 11.

The doped region 14 may be formed by ion implantation and diffusion processes. In this embodiment, the ion implantation and diffusion process is performed after the high temperature oxidation process. Because the high-temperature oxidation process forms an intermediate oxidation layer on the top surface of the substrate 11, the intermediate oxidation layer can effectively relieve the problem of damage to the substrate 11 caused by bombardment of high-energy ions in the ion implantation process, and the existence of the intermediate oxidation layer can save the step of forming an ion implantation protection layer. In other embodiments, the ion implantation process may also be performed before the high temperature oxidation process.

After the ion implantation process is performed to form the doped region, a thermal annealing process may be performed to further activate the dopant ions in the doped region 14 and diffuse the dopant ions to form source/drain regions (S/D) with more uniform particle distribution, and furthermore, the thermal annealing process may further drive the ion migration to make the dopant ion concentration in the doped region 14 decrease in a direction away from the top surface, which has a concentration gradient and the maximum dopant ion concentration is located in the top region of the doped region, so that the concentration difference between the dopant ion concentration in the top region of the doped region 14 and the dopant ion concentration in other regions contacting with the top of the doped region is reduced without increasing the total amount of dopant ions in the doped region 14, so that the ion diffusion of high-concentration dopant ions to the low-concentration region due to activation can be reduced in the subsequent thermal annealing process, the problem that the concentration of doped ions in the overlapped region of the doped region and the grid structure is increased is solved, the concentration of the doped ions in the overlapped region of the doped region and the grid structure is indirectly reduced, the GIDL effect is further reduced, and the electrical performance of the semiconductor structure is improved. The temperature of the thermal annealing process is, for example, 900 deg.c to 1100 deg.c.

Referring to fig. 3, an interlayer dielectric layer 17 is formed on the substrate 11, and the interlayer dielectric layer 17 covers the doped region 14 and the gate structure 13.

In the present embodiment, an interlevel dielectric layer 17 is deposited and planarized, non-limiting examples of which include mechanical planarization methods and chemical mechanical polishing planarization methods.

The interlevel dielectric layer 17 is typically an oxide or nitride.

Referring to fig. 4, a contact hole 18 is formed in the interlayer dielectric layer 17, and the contact hole 18 exposes the surface of the doped region 14.

In this embodiment, the process of forming the contact hole includes: firstly, a patterned photoresist layer is formed on the surface of the interlayer dielectric layer 17, the position, the size and the like of a contact hole 18 to be formed are set on the photoresist layer, then the interlayer dielectric layer 17 is etched by taking the patterned photoresist as a mask, the surface of the doped region 14 is stopped to form the contact hole 18, and the contact hole 18 penetrates through the interlayer dielectric layer 17 and an intermediate oxide layer (not shown) positioned on the top surface of the substrate.

After the etching is completed, the patterned photoresist layer is removed, and an ashing method or other suitable methods may be used.

Referring to fig. 5, an undoped semiconductor layer 15 is formed at the bottom of the contact hole 18, and the undoped semiconductor layer 15 is in surface contact with the doped region 14.

The undoped semiconductor layer 15 is located on the top surface of the doped region 14, and is undoped with N-type ions or P-type ions, so that the doped ions at other positions in the contact hole 18 are prevented from diffusing into the doped region 14 below the contact hole 18 due to ion activation in the subsequent thermal annealing treatment process, and the doped ions can diffuse into the undoped semiconductor layer 15, so that the problem that the concentration of doped ions in the overlapping region of the doped region 14 and the gate structure 13 is increased can be avoided.

The concentration of the doped ions in the doped region 14 in contact with the undoped semiconductor layer 15 is distributed in a descending manner in the direction away from the undoped semiconductor layer, and the descending distribution can reduce the ion diffusion of the high-concentration doped ion region to the low-concentration doped ion region generated by the ion activation on the premise of not increasing the total amount of the doped ions in the doped region 14, thereby avoiding the problem that the concentration of the doped ions in the overlapped region of the doped region and the grid structure is increased, indirectly reducing the concentration of the doped ions in the overlapped region of the doped region and the grid structure, further reducing the GIDL effect and improving the electrical performance of the semiconductor structure.

In this embodiment, before the deposition of the undoped semiconductor layer 15, a pre-cleaning step is performed to remove the native oxide layer and reduce the contact resistance between the undoped semiconductor layer 15 and the doped region 14. The precleaning may be performed using any suitable method known to those skilled in the art, such as using a cleaning solution comprising hydrofluoric acid, and the like. In other embodiments, this step may not be performed when no oxide layer is present.

The undoped semiconductor layer 15 may be formed using a chemical vapor deposition method, a physical vapor deposition method, or the like, and the thickness of the undoped semiconductor layer 15 may be controlled by adjusting process parameters such as the length of the deposition time.

In the present embodiment, the method of forming the undoped semiconductor layer 15 includes: forming a sacrificial semiconductor layer filling the contact hole 18; part of the thickness of the sacrificial semiconductor layer is removed and the remaining sacrificial semiconductor layer serves as an undoped semiconductor layer 15. The material of the undoped semiconductor layer 15 includes polysilicon, polycrystalline germanium, or polycrystalline silicon germanium.

In the present embodiment, the thickness of the undoped semiconductor layer 15 is 10 to 20 nm. The thickness of the undoped semiconductor layer is related to the subsequent thermal annealing process, and the higher the temperature in the thermal annealing process and the longer the heat treatment time, the thicker the undoped semiconductor layer 15, and in this embodiment, the diffusion due to the ion activation can be blocked when the thickness is 10-20 nm. In other embodiments, when the temperature environment or the heat treatment time of the thermal annealing treatment process is changed, the thickness of the undoped semiconductor layer is not limited to 10-20 nm.

Referring to fig. 6, an upper semiconductor layer 16 filling the contact hole (not shown) is formed on the surface of the undoped semiconductor layer 15, and the upper semiconductor layer 15 has doping ions.

In the present embodiment, in the process step of forming the upper semiconductor layer 16 on the undoped semiconductor layer 15, the doping ions in the upper semiconductor layer 16 are doped with the same type of doping ions as the doping ions in the doping region 14, and the type of doping ions includes N-type ions and P-type ions. The concentration of the dopant ions in the upper semiconductor layer 16 is greater than the concentration of the dopant ions in the top region of the doped region 14, which is the region of the doped region 14 near the undoped semiconductor layer 15.

It should be noted that, in other embodiments, after the process step of forming the upper semiconductor layer 16, the upper semiconductor layer 16 may be doped with dopant ions of the same type as the dopant ions in the doped region 14. If material remains on the surface of the ild 17 after the formation of the upper semiconductor layer 16, etching back or CMP may be performed to remove excess material.

In other embodiments, the method for forming the undoped semiconductor layer and the upper semiconductor layer may further include: forming an undoped semiconductor layer at the bottom and the side wall of the contact hole; and forming an upper semiconductor layer on the surface of the undoped semiconductor layer, and doping ions in the upper semiconductor layer during or after the process step of forming the upper semiconductor layer.

The undoped semiconductor layer 15 functions to block the dopant ions in the upper semiconductor layer 16 from diffusing into the doped region 14 below the contact hole, thereby avoiding the problem of the dopant ion concentration of the overlapping region of the doped region 14 and the gate structure 13 becoming large. In addition, the doped region under the undoped semiconductor layer 15 has a concentration of doped ions that decreases in a direction away from the undoped semiconductor layer, and the gradient distribution can reduce the effect of diffusion of the doped ions in the upper semiconductor layer 16 into the doped region 14 without increasing the total amount of the doped ions in the doped region 14, and is matched with the blocking of the undoped semiconductor layer 15.

In the present embodiment, in order to ensure that the conductive medium in the contact hole has good conductive performance, the material of the upper semiconductor layer 16 is the same as that of the undoped semiconductor layer 15, so that the contact resistance between the undoped semiconductor layer 15 and the upper semiconductor layer 16 is small, and the undoped semiconductor layer 15 and the upper semiconductor layer 16 together fill the contact hole and form a conductive plug.

After the above-described method for fabricating the semiconductor structure is performed, a thermal annealing process may be performed, which is used to activate the dopant ions in the upper semiconductor layer 16, and any suitable annealing method may be used for the thermal annealing process, such as furnace annealing, spike annealing, laser annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light source (e.g., halogen lamp, arc lamp, graphite heating) rapid annealing.

In the thermal annealing process, the doped ions in the upper semiconductor layer 16 are activated, and the undoped semiconductor layer 15 is formed, so that the doped ions originally diffused to the doped region 14 below the contact hole enter the undoped semiconductor layer 15, thereby avoiding the problem that the concentration of the doped ions in the overlapped region of the doped region 14 and the gate structure 13 is increased, meanwhile, the undoped semiconductor layer 15 plays a role of receiving the activated and diffused doped ions, i.e., the doped ions in the upper semiconductor layer 16 are diffused and transferred into the undoped semiconductor layer 15, so that the undoped semiconductor layer 15 has good conductivity, and finally, the upper semiconductor layer 16 and the undoped semiconductor layer 15 of the contact hole have similar concentrations of the doped ions. Before the thermal annealing process, the concentration of the doped ions in the upper semiconductor layer 16 is 1.0E 21-1.0E 22Atom/cm³After the annealing process, the concentration of the doped ions in the undoped semiconductor layer 15 is more than 1.0E20Atom/cm³。

In this embodiment, the contact hole is filled with the undoped semiconductor layer 15 and the upper semiconductor layer 16 having the doped ions, which together constitute a conductive plug. In the subsequent thermal annealing process, the undoped semiconductor layer 15 blocks the doped ions in the upper semiconductor layer 16 from diffusing to the doped region 14 below the contact hole, and the doped ions diffuse into the undoped semiconductor layer 15, so that the undoped semiconductor layer 15 has good conductivity. The doped region under the undoped semiconductor layer 15 has a concentration of doping ions decreasing in a direction away from the undoped semiconductor layer, and the gradient distribution can reduce the diffusion effect of the doping ions in the upper semiconductor layer 16 into the doped region 14 without increasing the total amount of the doping ions in the doped region 14, and is matched with the blocking effect of the undoped semiconductor layer 15. In addition, since the undoped semiconductor layer 15 and the upper semiconductor layer 16 are the same material, there is a small contact resistance therebetween. Therefore, on the premise of not affecting the conductivity of the conductive plug, the embodiment avoids the problem that the concentration of the doped ions in the overlapping region of the doped region and the gate structure is increased, indirectly reduces the concentration of the doped ions in the overlapping region of the doped region and the gate structure, further reduces the GIDL effect, and improves the electrical performance of the semiconductor structure.

Correspondingly, the embodiment of the utility model provides a semiconductor structure is still provided.

Referring to fig. 6, the semiconductor structure includes: a substrate 11, wherein the substrate 11 is provided with a gate structure 13, and the substrate 11 exposes the top surface of the gate structure 13; the doped regions 14, the doped regions 14 are located at two opposite sides of the gate structure 13; the interlayer dielectric layer 17, the interlayer dielectric layer 17 covers the doped region 14 and the grid structure 13, a contact hole is formed in the interlayer dielectric layer 17, and the contact hole exposes the surface of the doped region 14; an undoped semiconductor layer 15, wherein the undoped semiconductor layer 15 is positioned at the bottom of the contact hole, and the undoped semiconductor layer 15 is positioned on the surface of the doped region 14; an upper semiconductor layer 16, wherein the upper semiconductor layer 16 is located in the contact hole, the upper semiconductor layer 16 is located on the undoped semiconductor layer 15, and the upper semiconductor layer 16 has doped ions therein.

The semiconductor structure provided in the present embodiment will be described in detail below with reference to the accompanying drawings.

In the present embodiment, the gate structure 13 is located in the substrate 11, which can make the overall structure more compact; the substrate 11 exposes the top surface of the gate structure 13 to facilitate subsequent electrical connections.

In the present embodiment, the gate structure 13 includes a gate dielectric layer 101, a gate electrode 102, and a passivation layer 103. And an intermediate oxide layer (not shown) is also formed between the substrate 11 and the interlayer dielectric layer 17 in the same high temperature oxidation process step as the gate dielectric layer 101. In other embodiments, the interlevel dielectric layer 17 overlies the top surface of the substrate 11 and is in contact with the substrate 11.

The gate dielectric layer 101 may be formed of a conventional oxide such as silicon dioxide. The gate 102 may be made of a semiconductor material commonly used in the art, such as polysilicon, etc., but is not limited to one.

The passivation layer 103 functions to protect the gate, and the material is typically an oxide or nitride.

The doped regions 14 on both sides of the gate structure 13 are highly doped source/drain. The dopant ions in the doped region 14 may be either P-type ions or N-type ions. Wherein, the P-type dopant ions include, but are not limited to, boron ions, indium ions, or a combination thereof, and the N-type dopant ions include, but are not limited to, phosphorus ions, arsenic ions, or a combination thereof.

In the present embodiment, the concentration of the dopant ions in the doped region 14 decreases in a direction away from the interlayer dielectric layer 17, the maximum concentration of the dopant ions in the doped region 14 is the top region of the doped region 14, and the top region of the doped region 14 is the region close to the undoped semiconductor layer 15. The advantage of having a concentration gradient and having the maximum dopant ion concentration located in the top region of the doped region is that, on the premise of not increasing the total amount of dopant ions in the doped region 14, the concentration difference between the dopant ion concentration in the top region of the doped region 14 and the dopant ion concentration in the upper semiconductor layer 16 is reduced, so that in the subsequent thermal annealing process, the ion diffusion of the dopant ions in the upper semiconductor layer 16 to the low ion concentration region due to activation can be reduced, and the GIDL effect is reduced.

In the present embodiment, there are two gate structures 13, the doped regions 14 are located at two opposite sides of the gate structure 13, and two adjacent gate structures 13 share the doped region 14 located at the middle position thereof. In other embodiments, the number of gate structures may be any positive natural number.

The number of contact holes in the interlayer dielectric layer 17 is the same as that of the doped region 14, and the contact holes expose the top surface of the doped region 14. When an intermediate oxide layer is present, the contact hole also needs to penetrate through the intermediate oxide layer.

In the present embodiment, the undoped semiconductor layer 15 is located at the bottom of the contact hole and at the surface of the doped region 14. The material of the undoped semiconductor layer 15 includes polysilicon, poly germanium, and poly silicon germanium. The undoped semiconductor layer 15 is undoped with N-type or P-type ions. In other embodiments, the undoped semiconductor layer is also located on the contact hole sidewall.

In this embodiment, the thickness of the undoped semiconductor layer 15 is 10 to 20 nm.

The upper semiconductor layer 16 is located in the contact hole and above the undoped semiconductor layer 15, and fills the contact hole. In the present embodiment, the concentration of the dopant ions in the upper semiconductor layer 16 is 1.0E 21-1.0E 22Atom/cm³Greater than the dopant ion concentration within the doped region 14. The type of the doping ions in the upper semiconductor layer 16 is the same as the type of the doping ions in the doped region 14, and the doping ions may be either N-type ions or P-type ions.

In the present embodiment, the material of the upper semiconductor layer 16 is the same as that of the undoped semiconductor layer 15, and the contact resistance therebetween is small. The material of the upper semiconductor layer 16 includes polysilicon, polycrystalline germanium, or polycrystalline silicon germanium.

In this embodiment, the contact hole is filled with the undoped semiconductor layer 15 and the upper semiconductor layer 16 having the doped ions, which together constitute a conductive plug. The undoped semiconductor layer 15 plays a role of blocking doped ions in the upper semiconductor layer 16 from diffusing to the doped region 14 below the contact hole, and the doped ions diffusing downwards enter the undoped semiconductor layer 15, so that the undoped semiconductor layer 15 has good conductivity. The doped region under the undoped semiconductor layer 15 has a concentration of doping ions decreasing in a direction away from the undoped semiconductor layer 15, and the gradient distribution can reduce the diffusion effect of the doping ions in the upper semiconductor layer 16 into the doped region 14 without increasing the total amount of the doping ions in the doped region 14, and is matched with the blocking effect of the undoped semiconductor layer 15. In addition, since the undoped semiconductor layer 15 and the upper semiconductor layer 16 are the same material, there is a small contact resistance therebetween. Therefore, on the premise of not affecting the conductivity of the conductive plug, the embodiment avoids the problem that the concentration of the doped ions in the overlapping region of the doped region and the gate structure is increased, indirectly reduces the concentration of the doped ions in the overlapping region of the doped region and the gate structure, further reduces the GIDL effect, and improves the electrical performance of the semiconductor structure.

It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (8)

1. A semiconductor structure, comprising:

the device comprises a substrate, a grid structure and a control circuit, wherein the substrate is internally provided with the grid structure, and the top surface of the grid structure is exposed out of the substrate;

the doped regions are positioned on two opposite sides of the grid structure;

the interlayer dielectric layer covers the doped region and the grid structure, a contact hole is formed in the interlayer dielectric layer, and the contact hole exposes the surface of the doped region;

the undoped semiconductor layer is positioned at the bottom of the contact hole and positioned on the surface of the doped region;

the upper semiconductor layer is positioned in the contact hole, the upper semiconductor layer is positioned on the undoped semiconductor layer, and doped ions are arranged in the upper semiconductor layer.

2. The semiconductor structure of claim 1, wherein the undoped semiconductor layer is the same material as the upper semiconductor layer.

3. The semiconductor structure of claim 1, wherein the thickness of the undoped semiconductor layer is 10-20 nm.

4. The semiconductor structure of claim 1, wherein the undoped semiconductor layer is located on a surface of a sidewall of the contact hole.

5. The semiconductor structure of claim 1, wherein a type of dopant ions in the upper semiconductor layer is the same as a type of dopant ions in the doped region.

6. The semiconductor structure of claim 5, wherein the type of dopant ions in the upper semiconductor layer comprises P-type or N-type.

7. The semiconductor structure of claim 5, wherein the upper semiconductor layer has a dopant ion concentration greater than a dopant ion concentration of an interface of the doped region with the undoped semiconductor layer.

8. The semiconductor structure of claim 1, wherein a dopant ion concentration of the doped region decreases in a direction away from the interlevel dielectric layer.

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