KR20040029539A - Contact Plug Structure Of Semiconductor Device And Method Of Forming The Same - Google Patents

Abstract

PURPOSE: A contact plug structure of a semiconductor device and a forming method thereof are provided to form a contact plug on an elevated junction and form a shallow junction by using a silicon epitaxial growth method. CONSTITUTION: A plurality of gate patterns(145) is formed on a semiconductor substrate(100). A conductive layer is formed on the semiconductor substrate(100) between the gate patterns(145). A gate spacer(200) for exposing an upper face of the conductive layer is formed at both sidewalls of the gate patterns(145). The exposed conductive layer is etched by using the gate spacer(200) as an etch mask. A conductive layer pattern(185) having a concave groove is formed by etching the exposed conductive layer. A contact plug(210) for filling up the concave groove is formed.

Description

Contact plug structure of semiconductor device and method of forming the same {Contact Plug Structure Of Semiconductor Device And Method Of Forming The Same}

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a contact plug structure of a semiconductor device and a method for forming the same.

In general, semiconductor devices have contact plugs electrically connected to an impurity region used as a source / drain.

1 is a process cross-sectional view illustrating a method of forming a contact plug according to the prior art.

Referring to FIG. 1, an isolation layer 20 is formed in a predetermined region of a semiconductor substrate 10 to define an active region. A gate oxide film 25 is formed on the active region. The gate conductive layer 30 and the capping layer 40 are sequentially stacked on the semiconductor substrate on which the gate oxide layer 25 is formed, and then patterned to form a gate pattern 45 crossing the active region.

A low concentration ion implantation process using the gate pattern 45 as a mask is performed to form a low concentration impurity region 70 in the active region. A gate spacer 50 made of a silicon nitride film is formed on sidewalls of the gate pattern 45. A high concentration ion implantation process using the gate spacer 50 as a mask is performed to form a high concentration impurity region 80 in the active region.

An interlayer insulating film is formed on the entire surface of the semiconductor substrate on which the high concentration impurity region 80 is formed, and then patterned to form a contact hole 65 exposing an upper surface of the high concentration impurity region 80. The contact hole 65 is formed using an etch selectivity of the capping layer 40 and the gate spacer 50 with respect to an etch recipe for etching the interlayer insulating layer. This etching method is commonly referred to as a self-aligning contact hole forming method. For this purpose, the capping film 40 and the gate spacer 50 are usually formed of a silicon nitride film. Thereafter, a contact plug 60 is formed to connect the high concentration impurity region 80 through the contact hole 65.

On the other hand, with high integration of semiconductor devices, the area of unit cells is decreasing. Accordingly, the contact area between the high concentration impurity region 80 and the contact plug 60 is also reduced. The decrease in the contact area has a problem of causing an increase in the contact resistance. In order to minimize such a problem of resistance increase, a method of increasing the contact area of the contact plug 60 and the high concentration impurity region 80 has been proposed.

Figure 2 is a process cross-sectional view for explaining a method of forming a contact plug structure according to the prior art proposed to increase the contact area.

Referring to FIG. 2, after forming the contact hole 65 exposing the semiconductor substrate 10 by patterning the interlayer insulating layer, the exposed semiconductor substrate 10 is etched to a predetermined depth (99). As a result, the contact area between the contact plug 60 and the high concentration impurity region 80 increases, so that the contact resistance of the contact plug 60 may decrease. However, this method of recessing the semiconductor substrate increases the depth h ₁ of the impurity region used as the source / drain. Accordingly, the above method of recessing the semiconductor substrate is inappropriate for forming a shallow junction region required for high integration.

An object of the present invention is to provide a method for forming a contact plug structure capable of reducing contact resistance.

Another object of the present invention is to provide a contact plug structure having a low contact resistance.

1 and 2 are process cross-sectional views illustrating a contact plug structure of a semiconductor device according to the prior art.

3 to 7 are process cross-sectional views illustrating a method of forming a contact plug structure of a semiconductor device according to an embodiment of the present invention.

8 are process cross-sectional views illustrating a method of forming a contact plug structure of a semiconductor device according to another embodiment of the present invention.

9 is a perspective view illustrating a contact plug structure of a semiconductor device according to an exemplary embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a method for forming a contact plug structure of a semiconductor device comprising the step of forming a silicon epitaxial layer on the junction region. The method forms a plurality of gate patterns on a semiconductor substrate, forms a conductive film on the semiconductor substrate between the gate patterns, and then forms gate spacers that expose the top surface of the conductive film on both sidewalls of the gate pattern. It includes a step. Thereafter, the exposed conductive layer is etched using the gate spacer as an etching mask to form a conductive layer pattern having a concave groove. Next, the contact plug which fills the said recessed groove is formed so that it may connect to the said conductive film pattern.

Preferably, after the gate pattern is formed, a thermal oxidation process is performed to form an oxide film on sidewalls of the gate pattern in order to heal etching damage. Next, before forming the conductive film, sidewall spacers covering sidewalls of the gate pattern are further formed. In this case, the sidewall spacer is preferably formed of a silicon nitride film.

The forming of the conductive film preferably includes forming a silicon film on the semiconductor substrate using a silicon epitaxial growth technique, and then implanting impurities into the silicon film.

The forming of the gate spacer may include forming a spacer insulating film on the entire surface of the semiconductor substrate including the conductive film, and then anisotropically etching the spacer insulating film until the conductive film is exposed. Meanwhile, the concave groove of the conductive layer pattern may be formed by performing an anisotropic etching process for forming the gate spacer by an excessive etching method.

In addition, the concave groove of the conductive film pattern may be formed to expose the upper surface of the semiconductor substrate between the gate spacers.

In order to achieve the above another technical problem, the present invention provides a contact plug structure of a semiconductor device that can increase the contact area of the contact plug. The structure is connected to a plurality of gate patterns disposed on a semiconductor substrate, gate spacers disposed on both upper sidewalls of the gate patterns, a conductive film pattern interposed between the gate spacer and the semiconductor substrate, and the conductive film pattern. It includes a contact plug. In this case, the conductive film pattern has a concave groove, the contact plug is characterized in that filling the concave groove.

An impurity region used as a source / drain is disposed on the semiconductor substrate under the conductive film pattern. In addition, the concave groove may expose the semiconductor substrate. In this case, the contact plug directly contacts an impurity region used as the source / drain.

Preferably, the conductive film pattern is polycrystalline silicon containing impurities of the same conductivity type as the impurity region. In addition, a sidewall spacer made of a silicon nitride film may be disposed between the conductive film pattern and the gate pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

3 to 7 are process cross-sectional views illustrating a method of forming a contact plug structure according to an exemplary embodiment of the present invention.

Referring to FIG. 3, an isolation layer 110 defining an active region is formed in a predetermined region of the semiconductor substrate 100. The device isolation layer 110 may be formed using conventional trench device isolation techniques. Accordingly, the device isolation layer 110 is a silicon oxide layer filling the trench 105 disposed while defining the active region. After the device isolation layer 110 is formed, a series of impurity implantation processes for forming a well region may be further performed.

A gate insulating layer 120 is formed in the active region. The gate insulating film 120 is preferably a silicon oxide film formed by thermally oxidizing the active region. A gate conductive layer and a capping layer are sequentially formed on the gate insulating layer 120. Subsequently, the capping layer and the gate conductive layer are patterned in order to form the gate electrode 130 and the capping pattern 140 that are sequentially stacked. The gate electrode 130 and the capping pattern 140 form a gate pattern 145 crossing the active region. The patterning process for forming the gate pattern 145 may include anisotropic etching using plasma.

It is preferable that the said gate conductive film is polycrystalline silicon containing an impurity. The capping layer may be used as an anti-reflection layer or an etching mask in a patterning process for forming the gate pattern 145. To this end, the capping film is preferably at least one of a silicon oxynitride film, a silicon nitride film and a silicon oxide film.

Referring to FIG. 4, a low concentration impurity region 170 is formed in the active region between the gate patterns 145 by performing a low concentration ion implantation process using the gate pattern 145 as an ion implantation mask.

As described above, the etching process for forming the gate pattern 145 is performed by an anisotropic etching method using plasma. Accordingly, etching damage by the plasma may occur on sidewalls of the gate pattern 145. In order to cure such etching damage, it is preferable to further perform a thermal oxidation process after forming the gate pattern 145.

By the thermal oxidation process, an oxide film 150 is formed on sidewalls of the gate electrode 130. Accordingly, the lower surface and the side surface of the gate electrode 130 are covered with a silicon oxide film formed through a thermal oxidation process. Thereafter, sidewall spacers 160 exposing the low concentration impurity region 170 are formed on sidewalls of the gate pattern 145 on which the oxide layer 150 is formed. The sidewall spacer 160 may be formed of a silicon nitride film. Meanwhile, the ion implantation process for forming the low concentration impurity region 170 may be performed after the oxide film 150 or the sidewall spacer 160 is formed.

Referring to FIG. 5, a conductive layer 180 is formed on the active region exposed between the sidewall spacers 160. Accordingly, the conductive film 180 is electrically connected to the low concentration impurity region 170.

Preferably, the conductive layer 180 is a silicon layer formed using a silicon epitaxial growth technique. Since the silicon layer thus formed does not usually contain impurities, it does not have conductivity. Therefore, after the silicon layer is grown, an impurity implantation step is further performed. The impurity implantation process is preferably an ion implantation process, and the impurity implantation is preferably of the same conductivity type as the low concentration impurity region 170. In addition, the ion implantation process is performed at a higher dose than the ion implantation process for forming the low concentration impurity region 170. Accordingly, the conductive layer 180 exhibits a high impurity concentration, and the impurities included in the conductive layer 180 diffuse into the active region to form the high concentration impurity region 190.

The high concentration impurity region 190 may be formed through an ion implantation process in which impurities pass through the conductive layer 180. To this end, it is preferable that the conductive layer 180 is not excessively thick. In addition, the high concentration and low concentration impurity regions 190 and 170 form a junction region having a lightly doped drain (LDD) structure. The conductive layer 180 and the gate electrode 130 having conductivity are insulated by the oxide layer 130 and the sidewall spacer 140.

Referring to FIG. 6, after forming a spacer insulating film on the entire surface of the semiconductor substrate on which the conductive film 180 is formed, anisotropic etching is performed to form a gate spacer 200 exposing the top surface of the conductive film 180. . Accordingly, the gate spacer 200 covers the gate pattern 145, more precisely, the upper sidewall of the sidewall spacer 140.

By using the gate spacer 140 as an etching mask, the exposed conductive layer 180 is anisotropically etched to form a conductive layer pattern 185 having a concave groove. In this case, the anisotropic etching process for forming the concave groove may be performed until the high concentration impurity region 190 is exposed, as shown. Accordingly, the conductive layer pattern 185 is disposed under the gate spacer 200 while contacting the upper surface of the high concentration impurity region 190.

Referring to FIG. 7, an interlayer insulating film is formed on the entire surface of the semiconductor substrate on which the conductive film pattern 185 is formed. The interlayer insulating film is preferably formed of a silicon oxide film. Thereafter, the interlayer insulating layer is patterned to form an interlayer insulating layer pattern having an opening exposing the high concentration impurity region 190 or the conductive layer pattern 185.

The opening may include forming a method of forming a self-aligned contact hole using an etching recipe having an etch selectivity with respect to the capping pattern 140 and the gate spacer 200. It is preferable to use.

After the plug conductive film is formed on the entire surface of the semiconductor substrate including the interlayer insulating layer pattern, the contact plug 210 filling the opening is formed by etching the entire surface. The contact plug 210 may be formed using various methods that are commonly used. The contact plug 210 formed as described above is electrically connected to the impurity regions 190 by filling the concave groove of the conductive layer pattern 185. Meanwhile, when the conductive layer pattern 185 is formed to expose the high concentration impurity region 190, the contact plug 210 may directly contact the high concentration impurity region 190.

In this case, since the conductive layer pattern 185 has a concave groove, the contact plug 210 may be in contact with the impurity regions 170 and 190 used as the source / drain, compared to the conventional technology described with reference to FIG. 1. The area is increased. Accordingly, an increase in contact resistance of the contact plug due to high integration of the semiconductor device can be minimized. In addition, since the conductive layer pattern 185 is disposed on the impurity regions 190, the conductive impurity region 190 may be shallower than the conventional technology described with reference to FIG. 2.

8 is a cross-sectional view illustrating a method of forming a contact plug structure of a semiconductor device in accordance with another embodiment of the present invention. This embodiment is different from the embodiment described with reference to FIGS. 3 to 7 in that the conductive film is patterned after the interlayer insulating film is formed. Therefore, the same content will be replaced with the description of the embodiment described with reference to FIGS. 3 to 7.

Referring to FIG. 8, after forming the gate spacer 200 described with reference to FIG. 6, an interlayer insulating layer 230 covering the entire surface of the resultant is formed. Accordingly, the interlayer insulating film 230 covers the upper surface of the conductive film 180 where the concave groove is not yet formed.

The interlayer insulating film 230 is patterned by using the above-described self-aligned contact hole forming method, thereby forming an interlayer insulating film pattern having an opening that exposes an upper portion of the conductive film 180. Thereafter, the exposed conductive layer 180 is etched to form a conductive layer pattern 185 of FIG. 7 having a concave groove for increasing a contact area of the contact plug. In this case, the concave groove may expose the high concentration impurity region 190. Subsequently, a contact plug (210 of FIG. 7) connected to the conductive film pattern 185 is formed while filling the opening and the concave groove. In this case, the area of the contact plug in contact with the impurity region 190 used as the source / drain increases.

9 is a perspective view illustrating a contact plug structure of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 9, an isolation layer 110 defining an active region is disposed in a predetermined region of the semiconductor substrate 100. On the semiconductor substrate on which the device isolation layer 110 is formed, a gate pattern 145 crossing the active region is disposed. The gate pattern 145 includes a gate electrode 130 and a capping pattern 140 that are sequentially stacked. The gate electrode 130 is preferably conductive polycrystalline silicon. A material of silicide or metal may be further used. The capping pattern 140 is preferably a silicon nitride film. A silicon oxynitride film or a silicon oxide film may be further used.

A gate insulating layer 120 is interposed between the gate electrode 130 and the active region. The gate insulating film 120 is preferably a silicon oxide film formed through a thermal oxidation process. An oxide layer 150 is disposed on sidewalls of the gate electrode 130, and sidewall spacers 160 are disposed on sidewalls of the gate pattern 145 on which the oxide layer 150 is formed. The oxide film 150 is also preferably a silicon oxide film formed through a thermal oxidation process. In addition, the sidewall spacer 160 is preferably a silicon nitride film.

The low concentration impurity region 170 is disposed in the active region between the gate patterns 145. The gate spacer 200 is disposed on the upper sidewall of the gate pattern 145. The gate spacer 200 is preferably made of a silicon nitride film. In addition, a conductive layer pattern 185 interposed between the gate spacer 200 and the active region is disposed between the gate patterns 145. The conductive layer pattern 185 is preferably made of silicon formed using a silicon epitaxial growth technique, and includes impurities to have conductivity. In this case, the impurities included in the conductive film pattern 185 may be the same conductivity type as the impurities included in the low concentration impurity region 170.

A high concentration impurity region 190 is disposed in the semiconductor substrate 100 under the gate spacer 200. In plan view, the high concentration impurity region 190 overlaps the low concentration impurity region 170. In this case, the low concentration impurity region 170 is wider than the width of the high concentration impurity region 190.

An interlayer insulating layer pattern 235 having an opening that exposes the conductive layer pattern 185 is disposed between the gate spacers 200. The opening of the interlayer insulating film pattern 235 is filled with a conductive contact plug 210. In this case, the conductive layer pattern 185 may have a concave groove between the gate spacers 200. In this case, an upper surface of the concave groove is lower than a lower surface of the gate spacer 200. Accordingly, the contact plug 210 is electrically connected to the conductive layer pattern 185 and the impurity regions 190 and 170 by filling the concave groove of the conductive layer pattern 185.

In addition, the concave groove of the conductive layer pattern 185 may be an opening that exposes the semiconductor substrate 100. In this case, the contact plug 210 directly contacts the high concentration impurity region 190.

According to the present invention, contact plugs are formed on elevated junctions by silicon epitaxial growth techniques. As a result, a shallow junction region can be formed, and a highly integrated semiconductor device can be manufactured. In addition, by forming the concave groove in the raised joint region, the contact resistance of the contact plug can be reduced. As a result, a semiconductor device having low power consumption and fast operating speed can be manufactured.

Claims (12)

Forming a plurality of gate patterns on the semiconductor substrate; Forming a conductive film on the semiconductor substrate between the gate patterns; Forming gate spacers exposing top surfaces of the conductive layer on both sidewalls of the gate pattern; Etching the exposed conductive layer using the gate spacers as an etching mask to form a conductive layer pattern having a concave groove; And Forming a contact plug filling the concave groove to connect to the conductive film pattern. The method of claim 1, And forming a gate pattern, and then performing a thermal oxidation process. The method of claim 1, And forming sidewall spacers covering sidewalls of the gate pattern prior to forming the conductive layer, wherein the sidewall spacers are formed of a silicon nitride film. The method of claim 1, Forming the conductive film Forming a silicon film on the semiconductor substrate using a silicon epitaxial growth technique; And And implanting impurities into the silicon film. . The method of claim 1, Forming the gate spacer Forming a spacer insulating film on an entire surface of the semiconductor substrate including the conductive film; And And anisotropically etching the spacer insulating film until the conductive film is exposed. The method of claim 5, wherein The concave groove of the conductive layer pattern is formed by performing an anisotropic etching process for forming the gate spacer by the excessive etching method. The method of claim 1, The concave groove of the conductive film pattern is formed to expose the upper surface of the semiconductor substrate between the gate spacers. A plurality of gate patterns disposed on the semiconductor substrate; Gate spacers disposed on both upper sidewalls of the gate patterns; A conductive film pattern interposed between the gate spacer and the semiconductor substrate; And a contact plug connected to the conductive film pattern, wherein the conductive film pattern has a concave groove and the contact plug fills the concave groove. The method of claim 8, And the concave groove exposes the semiconductor substrate. The method of claim 8, And a dopant region used as a source / drain on the semiconductor substrate under the conductive layer pattern. The method of claim 10, And the conductive film pattern is polycrystalline silicon containing impurities of the same conductivity type as the impurity region. The method of claim 8, And a sidewall spacer made of a silicon nitride film between the conductive film pattern and the gate pattern.