JP2000294799A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the aspect ratio of a gate electrode without a limitation by the height of the gate electrode in the width of an LDD by forming an n+ type impurity region as a high-concentration impurity region first and forming an n- type impurity region as a low-concentration impurity region. SOLUTION: An oxide film and a conductive film are formed onto a p-type semiconductor substrate, and a gate insulating film 12 and a section 11 as a gate electrode are formed. The first impurity region 13 having large impurity concentration is formed. The surface of the section 11 as the gate electrode is etched in an isotropic manner, and the gate electrode 15 is formed. The second impurity region 16 having low impurity concentration is formed, using the gate electrode 15 as a mask. Accordingly, the width L of an LDD can be controlled extremely delicately, and L can be changed arbitrarily from 10 nm to 0.1 μm. Channel length W at that time reaches 0.5 μm or less. Thus, an LDD region can be formed without a limitation by an aspect ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an insulated gate field effect type semiconductor device (semiconductor device) which is excellent in high speed and can be highly integrated. The semiconductor device according to the present invention is used for a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like.

[0002]

2. Description of the Related Art Many researches and developments have been made on miniaturization and high integration of semiconductor devices. In particular, MOSF
A remarkable progress has been made in the miniaturization technology of an insulated gate field effect type semiconductor element called ET. MOS stands for Metal
-Oxide-An abbreviation for Semiconductor. A metal is not limited to a pure metal, but is used in a broad sense including a semiconductor material having sufficiently high electrical conductivity and an alloy of a semiconductor and a metal. In addition, instead of an oxide between a metal and a semiconductor, not only a pure oxide but also an insulating material having a sufficiently high resistance such as a nitride may be used. Is MOS
Although the term is not correct, in the present specification, a field-effect element having such a structure, including a nitride and other insulators, will be referred to as a MOSFET hereinafter.

The miniaturization of a MOSFET is performed by reducing the width of a gate electrode. Reducing the width of the gate electrode means reducing the length of the underlying channel region, i.e., the channel length, which reduces the time required for carriers to pass through the channel length. As a result, the speed is increased as well as the integration becomes higher.

[0004] However, this also causes another problem (short channel effect). The most important of these is the hot electron problem. As before,
In a structure in which a channel region doped with impurities of opposite polarity is sandwiched between impurity regions of a source and a drain having sufficiently high impurity concentrations, the voltage applied to the source and the drain increases as the channel region is narrowed. The electric field near the boundary between the channel region and the impurity region increases. As a result, the operation of the MOSFET becomes extremely unstable.

[0005] The structure of a new MOSFET proposed to solve such a problem is a lightly-doped LDD (LDD).
ped-Drain). This is typically shown in FIG.
It is shown in (D). In FIG. 2D, a region 27 having a low impurity concentration provided shallower than a region 26 having a high impurity concentration is referred to as an LDD. By providing such a region, the electric field near the boundary between the channel region and the impurity region can be reduced, and the operation of the element can be stabilized.

The LDD is usually formed as shown in FIG. FIG. 2 shows an example of an NMOS, but a PMOS may be formed similarly. First, an oxide film and a conductive film are formed on a p-type semiconductor substrate, and these are etched to form a gate insulating film 22 and a gate electrode 21 as shown in FIG. Then, using this gate electrode as a mask, impurity region 23 having a relatively low impurity concentration (indicated by n ^{− in the} symbol) is formed in a self-aligned (self-aligned) manner by, for example, ion implantation.

Next, an insulating film 24 such as PSG is formed thereon. Then, the insulating film 24 is removed by an anisotropic etching method (also referred to as a directional etching method) such as bias plasma etching, but as a result of the anisotropic etching, PSG is not etched on the side surfaces of the gate electrode. Thus, the shape remains as shown by 25 in FIG. This residue is called a spacer. Using the spacer 25 as a mask, the impurity concentration is high in a self-aligned manner (represented by n ^{+ in the} symbol).
Impurity region 26 is formed. This n ⁺ -type impurity region is used as a source and a drain of the FET.

It has been shown that by adopting such an LDD structure, it is possible to reduce the channel length, which is said to be 0.5 μm as the limit in the conventional method, to 0.1 μm.

[0009]

However, this does not completely solve the problem of shortening the channel. Another problem is the problem of the resistance of the gate electrode caused by reducing the gate width. Even if the operating speed is improved by shortening the channel, if the resistance of the gate electrode is large, the propagation speed is reduced by compensating for that. In order to reduce the resistance of the gate electrode, for example, a metal silicide having a small resistivity is used instead of the conventionally used polycrystalline silicon having a high impurity concentration, or a low-resistance wiring such as aluminum is used in parallel with the gate electrode. Has been studied and adopted, but it is expected that the limit will be reached in situations where the width of the gate electrode is 0.3 μm or less.

As another solution in that case, it is conceivable to increase the ratio (aspect ratio) between the height and the width of the gate electrode. By increasing the aspect ratio of the gate electrode, it is possible to increase the cross-sectional area of the gate electrode and reduce the resistance. However, conventional LDD
Cannot increase the aspect ratio indefinitely due to a problem in its fabrication.

This is because the width of the spacer formed by anisotropic etching depends on the height of the gate electrode.
Usually, the width of the spacer was 20% or more of the height of the gate electrode. Therefore, when the width L of the LDD region 27 in FIG. 2 is 0.1 μm, the height h of the gate electrode is 0.1 μm.
It had to be 5 μm or less. If the height of the gate electrode is more than that, L will be 0.1 μm or more. This means that the resistance between the source and the drain increases, which is not desirable.

The height h of the gate electrode is 0.5 μm, the width W of the gate electrode is 1.0 μm, and the width L of the LDD is 0.1 μm.
Let m. By reducing the scale of this element,
If W is to be 0.5 μm, h must be 1.0 μm in order to maintain the resistance of the gate electrode. However, for that reason, L becomes 0.2 μm. That is, although the resistance of the gate electrode does not change,
State (voltage is applied to the gate electrode, and the resistance of the channel region is sufficiently smaller than the resistance of the n ⁻ region)
, The resistance between the source and the drain is doubled. On the other hand, since the channel length has been reduced by half, the element can be expected to respond at twice the speed. However, since the resistance between the source and the drain has doubled, this is canceled.
As a result, only high integration of the device has been achieved, but the speed remains the same. On the other hand, h must be 0.5 μm in order to keep L the same as in the prior art. However, in this case, the resistance of the gate electrode is doubled, and eventually high speed cannot be obtained.

In a typical example, the width of the spacer is 50% to 100% of the height of the gate electrode, which is a much more difficult condition than that shown above. Therefore, in the conventional LDD manufacturing method, the aspect ratio of the gate electrode is 1 or less, and often 0.2 or less. In addition, the spacer thus manufactured has a large variation in width,
This has caused variations in characteristics between elements and a reduction in product yield. As described above, the conventional LDD manufacturing method has provided stability in a short channel and accompanying high integration and high speed.
It presents a contradiction that hinders high integration.

The present invention proposes a completely new method for fabricating an LDD structure that can be implemented without any problem even with a gate electrode having a high aspect ratio of 1 or more. As described above, there is a problem that the aspect ratio of the wiring is unavoidable due to the miniaturization.

[0015]

FIG. 1 shows a typical example of the present invention. This is the case of an NMOS, but the same can be applied to a PMOS. First, an oxide film and a conductive film are formed on a p-type semiconductor substrate, and these are etched to form a gate insulating film 12 and a portion 11 to be a gate electrode as shown in FIG. Then, using the portion to be the gate electrode as a mask, the impurity concentration is high in the order of 1 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ by self-alignment (self-alignment), for example, by ion implantation. in represented as n ⁺⁾ first impurity region 13 is formed.

Next, the surface of the portion to be the gate electrode is isotropically etched, and the surface recedes. Finally, the gate electrode 15 remains. (FIG. 1 (B))
At this time, it is necessary that the etching rate of the material forming the portion to be the gate electrode is higher than the etching rate of the semiconductor material. Otherwise, the semiconductor substrate will be largely hollowed out simultaneously with the formation of the gate electrode.
The etching method may be wet etching by immersion in a liquid or dry etching in a reactive gas or plasma.
For example, if the material of the gate electrode is aluminum, it can be etched with hydrochloric acid, while silicon, which is a general semiconductor material, is not etched with hydrochloric acid, which is preferable. However, a method in which etching occurs anisotropically should not be adopted. That is, in the present invention, since at least the side surface of the portion to be the gate electrode needs to be etched, anisotropic etching such as bias plasma etching is not suitable.

In this example, the gate insulating film is also removed together with the portion to be the gate electrode. However, the same processing can be performed by leaving the gate insulating film. Even in that case, it is necessary that the etching rate of the material of the gate electrode is sufficiently higher than the etching rate of the material of the gate insulating film.

Now, the gate electrode thus formed is formed.
Using pole 15 as a mask, 1 × 10¹⁷
~ 5 × 10¹⁸cm^-3Small impurity concentration (in the symbol
Is n ^-A second impurity region 16 is formed.
You. This impurity formation can also be performed by ion implantation.
Good, and a film containing impurity elements is formed on it,
Is irradiated with an electron beam or laser light.
It may be scattered. Thus, the conventional LDD manufacturing method
LDD having the same shape as that obtained by the method can be obtained.
Wear. It ’s clear from the diagram that it ’s notable that
As described above, the width L of the LDD is limited by the height of the gate electrode.
Increase the aspect ratio of the gate electrode.
It is possible to do it.

According to the present invention, the width L of the LDD can be very finely controlled. For example, L can be arbitrarily changed from 10 nm to 0.1 μm. At this time, the channel length W can be 0.5 μm or less. L
That can be finely controlled is based, for example, on the fact that it is easy to control the etching rate and the etching depth.

Further, according to the present invention, as compared with the conventional LDD manufacturing method, it is not necessary to form an insulating film to be a spacer, so that the process is simplified and the productivity is improved.
Further, in the conventional LDD manufacturing method, first, an n ⁻ -type impurity region is formed. On the other hand, in the present invention, an n ⁺ -type impurity region is formed first, and then an n ^-- type impurity region is formed.
The n ⁻ -type impurity region must be formed as a sufficiently shallow impurity region. If this shallow impurity is first formed as in the conventional case, the subsequent process is performed so that the impurity region is not expanded by heat. Temperature had to be kept low. However, there is no such restriction in a process in which the step of forming the n ⁻ -type impurity region is performed later as in the present invention.

[0021]

[Embodiment 1] An embodiment using the present invention will be described. This embodiment shows a case where the present invention is applied to a complementary MOSFET device (CMOS) formed on a single crystal semiconductor substrate. This embodiment is shown in FIG. First, FIG.
As shown in (A), an n-type well 3 is formed on a p-type single crystal silicon semiconductor substrate by using a conventional integrated circuit manufacturing method.
3, field insulator 31, channel stopper (p ⁺
(Type) 32, n ⁺ -type impurity regions 34 and 36, p ⁺ -type impurity region 35, gate electrode 37 of n-type polycrystalline silicon doped with phosphorus (for NMOS) and 38 (PMOS).
To form).

The detailed manufacturing method is as follows.
First, if the impurity concentration is 10¹⁵cm^-3About p-type silicon
Phosphorus ions are implanted into the
Anneal at 0 ° C. for 3 to 10 hours to diffuse phosphorus ions,
Redistributed, impurity concentration 10 ¹⁶cm^-3About n-type well
33 are formed. Furthermore, BF_Two ⁺With ion implantation
Channels are formed by the so-called LOCOS method (local oxidation method).
The stopper 32 and the field insulator 31 are formed.

Thereafter, a thickness of 20 nm is formed by a thermal oxidation method.
Is formed, and portions 37 and 38 to be gate electrodes are formed by polycrystalline silicon having a phosphorus concentration of 10 ²¹ cm ⁻³ . At this time, the gate insulating film is not patterned. Then, arsenic ions are implanted by using a portion to be a gate electrode and, if necessary, another mask material as a mask, so that an impurity concentration of 1 is obtained.
The n ⁺ -type impurity regions 34 and 36 of 0 ²¹ cm ^-3 are formed, and BF ₂ ⁺ ions are implanted to obtain an impurity concentration of 10 ²¹ c.
An m ⁻³ p ⁺ -type impurity region 35 is formed. These impurity regions are activated by annealing at 900 ° C. for one hour, and become source and drain regions. Thus, FIG. 3A is obtained.

Next, as shown in FIG. 3B, a portion to be a gate electrode is etched by a high frequency plasma etching method. As the etching gas, carbon tetrafluoride CF ₄ was used, and 60% of chlorine was mixed therein.
The pressure during etching is 5 Pa, and the output of high frequency is 0.2
W / cm ² . In this manner, the side and top surfaces of the portion to be the gate electrode are etched by 10 nm to 0.1 μm, for example, 50 nm. Thus, the NMOS
Is formed, and a gate electrode 40 of a PMOS is formed.

Thereafter, a coating 4 of phosphorus pentoxide (P ₂ O ₅ )
1 and a film 42 of boron oxide (B ₂ O ₃ ) are formed by a CVD method or a coating method and are patterned. C
When forming a film by the VD method, phosphine (PH ₃ )
Alternatively, oxygen gas may be added to diborane (B ₂ H ₆ ) for thermal decomposition. Further, in the application method, phosphorus pentoxide or boron oxide may be mixed into fine particles of silica glass to form a paste, which may be applied by a spin coater.

Then, as shown in FIG. 3C, an excimer laser, for example, a KrF laser (wavelength 248 n
m, a pulse width of 10 nsec) to diffuse the impurity element in the film into the silicon substrate. At this time, when an ultraviolet laser such as an excimer laser is used, ultraviolet light has a large absorption in silicon, so that an extremely shallow impurity region can be formed. However, since it is difficult to finely control the impurity concentration by the doping method using a laser, it goes without saying that a conventional ion implantation method may be used. Also,
In this laser doping, the upper surface of the gate electrode 40 is doped with boron, but it is clear that the influence on the entire gate electrode is extremely small. Thus, n ⁻ -type impurity region 43 and p ⁻ -type impurity region 44 are formed.

Finally, a phosphor glass layer 45 is formed as an interlayer insulator as in the case of the conventional integrated circuit.
For forming the phosphorus glass layer, for example, a low pressure CVD method may be used. As a material gas, monosilane SiH ₄ , oxygen O _2, and phosphine PH ₃ are used and reacted at 450 ° C.

Thereafter, holes for forming electrodes are formed in the interlayer insulating film, and aluminum electrodes are formed. Thus, a complementary MOS device as shown in FIG. 3D is completed.

Embodiment 2 Using the present invention, an NMOS thin film transistor (hereinafter, referred to as TFT) is formed on an insulating substrate.
An example is described here. This embodiment will be described with reference to FIG. FIG. 4 shows two NMOS-TFTs.
Is shown. First, a silicon oxide layer 52 having a thickness of 50 to 300 nm is formed as a passivation film on an insulating substrate 51 made of synthetic quartz or the like by, for example, a sputtering method. It may be formed by a CVD method.

Then, an amorphous silicon layer is formed thereon by plasma CVD or low pressure CVD.
It is formed to a thickness of 10 to 100 nm, for example, 20 nm. Thereafter, the amorphous silicon layer is patterned into an island shape. Then, a silicon oxide film to be a gate insulating film having a thickness of 10
It is formed to a thickness of 100 nm, for example, 60 nm. Then, annealing is performed at 600 ° C. for 12 to 72 hours to crystallize the amorphous silicon layer and at the same time reduce the number of trap levels in the silicon oxide film.

Thereafter, an aluminum coating is applied, for example, to 5
Only a thickness of 00 nm is formed. The thickness of the aluminum film is determined in consideration of the conductivity required for the gate wiring. Then, the aluminum film and the silicon oxide film are etched by a known lithography method to form a portion 56 to be a gate electrode and a gate insulating film 55. At this time, the width of the portion to be the gate electrode is 100 to 500 n.
m, preferably 200-500 nm, for example 400 nm
And Then, by a known ion implantation method, His ions are implanted using the portion 56 to be the gate electrode as a mask. Thus, an n ⁺ impurity region 53 and a channel region 54 are formed. Thus, FIG. 4A is obtained.

Next, as shown in FIG. 4B, a portion to be a gate electrode is etched by a high frequency plasma etching method. Carbon tetrachloride CCl ₄ was used as an etching gas. The pressure during etching is 5Pa
The output of the high frequency was 0.2 W / cm ² . In this way, the side and top surfaces of the part to be the gate electrode are
Etch only from 0 nm to 0.1 μm, for example, 60 nm. Thus, the NMOS gate electrode 57 is formed.

Further, as shown in FIG. 4C, a newly formed gate electrode 5 is formed by a known ion implantation method.
Using n as a mask, n ⁻ -type impurity region 58 is formed in a self-aligned manner. Since the crystallinity of each of the impurity regions 53 and 58 formed as described above is significantly reduced by ion implantation, it is necessary to recover the crystallinity by laser annealing using an excimer laser. Here, when an excimer laser is used, the pulse is as short as 10 nsec, so that it is possible to prevent impurities from moving due to heat and blurring the interface of the impurity region. In particular, when the width of the LDD region 58 is only 60 nm as in the present embodiment, impurity ions are diffused by the lamp annealing method used for the conventional integrated circuit fabrication, which is not preferable.

Thereafter, a phosphorus glass layer 5 is used as a layer tube insulator.
9 is formed by the low pressure CVD method, and the electrode 60 is formed. Thus, the NMOS- as shown in FIG.
A TFT element is obtained.

[0035]

According to the present invention, L with very few restrictions
It has become possible to manufacture a DD-type MOSFET. As described in the text, the use of the present invention allows the LDD to be hardly limited by the aspect ratio of the gate electrode.
Regions can be formed. The width of the LDD region is also 10
It can be controlled very precisely in the range of １００100 nm. In particular, the present invention is an effective method for increasing the aspect ratio of the gate electrode, which is expected to progress in the future by shortening the channel.

Of course, the present invention can be applied to a conventional low-aspect-ratio gate electrode having an aspect ratio of 1 or less. Since the step of isotropic etching is not required, the effect of the present invention is remarkable.

Although the present invention has been described mainly with respect to a silicon-based semiconductor device, it is apparent that the present invention can be applied to a semiconductor device using other semiconductor materials such as gallium arsenide.

[Brief description of the drawings]

FIG. 1 shows an example of an LDD manufacturing method according to the present invention.

FIG. 2 shows an example of a conventional LDD manufacturing method.

FIG. 3 shows CM on a single crystal semiconductor substrate using the present invention.
An example of a method for manufacturing an OS is described.

FIG. 4 illustrates an example of a method for manufacturing an NMOS on an insulating substrate using the present invention.

[Explanation of symbols]

11 Portion to be Gate Electrode 12 Gate Insulating Film 13 n ⁺ Impurity Region 15 Gate Electrode 16 n ^- Impurity Region

[Procedure amendment]

[Submission date] March 30, 2000 (2003.3.3)
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

18. In any one of claims 13 to 17, the connecting portion between the gate insulating film is present beyond the end of the gate electrode, the low concentration impurity region and said source region and said drain region A semiconductor device which is aligned with an end of the gate insulating film.

19. In any one of claims 13 to 18, the upper surface of the low concentration impurity region is covered with the gate insulating film, an upper surface of the source region and the drain region is covered with the gate insulating film The low-concentration impurity region is formed by adding an impurity through a gate insulating film existing beyond the end of the gate electrode, and the source region and the drain region are formed by adding the impurity to the gate insulating film. A semiconductor device formed by adding an impurity without passing through the semiconductor device.

20. A any one of claims 1 to 19, wherein the semiconductor film, wherein a made of a material containing silicon.

21. A any one of claims 1 to 19, wherein the semiconductor film is a semiconductor device characterized by comprising a material containing gallium arsenide.

22. A any one of claims 1 to 21, a semiconductor device wherein the gate insulating film, characterized in that it consists of a material containing silicon oxide.

23. The any one of claims 1 to 22, wherein the gate electrode is a semiconductor device characterized by comprising a material containing polycrystalline silicon to which phosphorus is added.

24. In any one of claims 1 to 23, the electronic device characterized by having the semiconductor device.

25. The method of claim 24, wherein the electronic device, electronic device, wherein the microprocessor, a microcontroller, a microcomputer, or a semiconductor memory.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78

Claims (24)

[Claims] A substrate, an insulating film on the substrate, a channel forming region formed on the insulating film, two second impurity regions formed between the channel forming region, An island-shaped semiconductor film having two first impurity regions formed in contact with a second impurity region; a gate insulating film formed at least on the channel forming region; and a gate insulating film formed on the gate insulating film A semiconductor device having a gate electrode formed, and an interlayer insulating film formed above the gate electrode, the gate insulating film, and the first impurity region, wherein the impurity concentration of the first impurity region is ,
The concentration of the impurity in the second impurity region is higher than that of the second impurity region, the thickness of the semiconductor film is 10 nm to 100 nm, the semiconductor film is crystallized, and the channel length of the channel formation region is 0.5 μm or less. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the substrate is a quartz substrate. 3. A channel forming region formed on an insulating surface, two second impurity regions formed between the channel forming region, and a second impurity region formed in contact with the second impurity region. An island-shaped semiconductor film having two first impurity regions, a gate insulating film formed on at least the channel formation region, a gate electrode formed on the gate insulating film, the gate electrode, and the gate A semiconductor device having an insulating film and an interlayer insulating film formed above the first impurity region, wherein the concentration of the impurity in the first impurity region is higher than the concentration of the impurity in the second impurity region. And the thickness of the semiconductor film is 10 nm to 100 n.
m, wherein the semiconductor film is crystallized, and a channel length of the channel formation region is 0.5 μm or less. 4. The method according to claim 1, wherein
The semiconductor device according to claim 1, wherein the second impurity region is formed in contact with the channel formation region. 5. The method according to claim 1, wherein:
The semiconductor device, wherein the interlayer insulating film is formed in contact with the first impurity region. 6. The method according to claim 1, wherein
The semiconductor device, wherein the gate insulating film is not formed on the first impurity region. 7. The method according to claim 1, wherein
The semiconductor device according to claim 1, wherein the second impurity region is an n ^- type impurity region. 8. The method according to claim 1, wherein
The semiconductor device according to claim 1, wherein the first impurity region is an n ⁺ -type impurity region. 9. The method according to claim 1, wherein
The concentration of the impurity in the second impurity region is 1 × 1
A semiconductor device characterized by having a diameter of 0 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . 10. The semiconductor device according to claim 1, wherein the width of the second impurity region is 10 nm to 100 n.
m. 11. The gate insulating film according to claim 1, wherein the gate insulating film extends beyond an end of the gate electrode, and a junction between the second impurity region and the first impurity region. A semiconductor device which is aligned with an end of the gate insulating film. 12. The semiconductor device according to claim 1, wherein an upper surface of the second impurity region is covered with the gate insulating film, and an upper surface of the first impurity region is covered with the gate insulating film. The second impurity region is not
The first electrode is formed by adding an impurity through a gate insulating film existing over an end of the gate electrode;
Wherein the impurity region is formed by adding an impurity without passing through the gate insulating film. 13. A channel formation region, a source region and a drain region, and a low-concentration impurity region formed between the channel formation region and the source region and the drain region, formed on the insulating surface. An island-shaped semiconductor film, a gate insulating film formed on at least the channel formation region, a gate electrode formed on the gate insulating film, the gate electrode, the gate insulating film, the source region, and the drain A semiconductor device having an interlayer insulating film formed above a region, wherein the semiconductor film has a thickness of 10 nm to 100 nm, the semiconductor film is crystallized, and a channel length of the channel formation region is A semiconductor device having a thickness of 0.5 μm or less. The width of the low concentration impurity region is 10 nm to 100 nm. 14. The semiconductor device according to claim 13, wherein the interlayer insulating film is formed in contact with the source region and the drain region. 15. The semiconductor device according to claim 13, wherein the gate insulating film is not formed on the source region and the drain region. 16. The low-concentration impurity region according to claim 13, wherein:
A semiconductor device having a size of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . 17. The gate insulating film according to claim 13, wherein the gate insulating film extends beyond an end of the gate electrode, and a junction between the low-concentration impurity region and the source region and the drain region. A semiconductor device which is aligned with an end of the gate insulating film. 18. The semiconductor device according to claim 13, wherein an upper surface of the low-concentration impurity region is covered with the gate insulating film, and upper surfaces of the source region and the drain region are covered with the gate insulating film. The low-concentration impurity region is formed by adding an impurity through a gate insulating film existing beyond the end of the gate electrode, and the source region and the drain region are formed by adding the impurity to the gate insulating film. A semiconductor device formed by adding an impurity without passing through the semiconductor device. 19. The semiconductor device according to claim 1, wherein the semiconductor film is made of a material containing silicon. 20. The semiconductor device according to claim 1, wherein the semiconductor film is made of a material containing gallium arsenide. 21. The semiconductor device according to claim 1, wherein the gate insulating film is made of a material containing silicon oxide. 22. The semiconductor device according to claim 1, wherein the gate electrode is made of a material containing polycrystalline silicon to which phosphorus is added. 23. An electronic device according to claim 1, comprising the semiconductor device. 24. The electronic device according to claim 23, wherein the electronic device is a microprocessor, a microcontroller, a microcomputer, or a semiconductor memory.