JPH01764A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the structure of an MO8 field effect transistor.

[Conventional technology]

Conventional MO3 field effect transistor (MOS
It is abbreviated as FET. ) is an LDD (Lightly Doped Drain) with a polycrystalline silicon layer as a gate electrode in order to achieve higher speed, higher integration, and higher reliability.
) structure is adopted. Figure 2 shows this type of MOSFE.
It is a cross-sectional explanatory view showing the structure of T.

For example, in the n-channel ff1M03FET shown in FIG. 2, this transistor is formed on the main surface of the PW semiconductor substrate 1. A field oxide film 2 for isolation between elements is selectively formed in the P-type semiconductor substrate 1, and a gate electrode tffi 10 made of a polycrystalline silicon layer is provided in the element formation region via a gate film 5. There is. moreover,
Its gate electrode i.

A sidewall spacer 6 is provided on the sidewall of the gate electrode 10, and an n+ type source region 3, an n+ type drain region 4, and an n− type offset region 3as4a are formed in a self-aligned manner using the gate electrode 10 or the sidewall spacer 6 as a mask. ing. Further, a source region 3, a drain region 4,
The electrodes are drawn out from the ffltilo using aluminum (Aρ) or the like, but are omitted here.

[Problem that the invention seeks to solve]

According to the above-mentioned conventional MOSFET structure, there are a few problems in device characteristics mainly caused by the electrode structure as listed below.

(1) In conventional MOSFETs, the capacitance between the drain and the substrate is large, so the operating speed of the transistor is slow.

(2) In order to reduce the capacitance between the drain and the substrate, the area of the drain region may be reduced. However, according to the conventional structure shown in FIG. 2, the formation of the gate electrode, source/drain contact holes, and source/drain m+Xi is limited by the alignment of the phosphorography process, so that It is necessary to have a total path. Therefore, there is a limit to reducing the area of the drain region, and there is a limit to the above-mentioned speed increase and element density increase.

(3) With the miniaturization of devices, the junctions of diffusion layers such as source and drain regions become shallower, and contact holes become smaller, making it possible to stably form contact between the diffusion layer and wiring electrodes in the contact hole area. Shikoshichi becomes difficult.

(4) Since a polycrystalline silicon layer is used as the gate electrode, the wiring delay caused by this becomes an obstacle to increasing the speed of the device.

Therefore, the present invention aims to solve these problems.
The purpose of this is to significantly reduce parasitic capacitance by reducing the area of the parasitic region, and to create a structure that allows the use of metal as the gate electrode, thereby increasing the performance and density of MOSFETs. The aim is to achieve this goal.

[Means for solving problems]

A semiconductor device of the present invention is a semiconductor device having a MoS structure, in which a source region and a drain region are formed in a self-aligned manner by diffusion from polycrystalline silicon decay formed on an element formation region, and the polycrystalline silicon a sidewall spacer provided on a sidewall of the layer; an offset region of the source or drain/region adjacent to the source or drain region and below the sidewall spacer; A channel region defined in a self-aligned manner by a silicon layer and a sidewall spacer, and an insulating film provided on the sidewall spacer and polycrystalline silicon layer are formed on the channel region via a gate film. and a gate electrode.

(Function) In the present invention, the source/drain/region is formed in a self-aligned manner by impurity diffusion from the polycrystalline silicon layer, and the source/drain electrodes are drawn out using this polycrystalline silicon layer. The area of the parasitic region can be reduced without being limited by graphics technology, and the influence of the parasitic region on the device can be largely eliminated.Furthermore, since the diffusion layer is connected to the wiring layer via the polycrystalline silicon layer, contact Stable electrical contact is achieved in the hole part.Furthermore, it is possible to lower the temperature of heat treatment after forming the gate electrode.
Arrangement based on gate electrode material! a Reduce delay.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings together with a manufacturing method thereof.

FIG. 1 is an explanatory cross-sectional view of a semiconductor device showing one embodiment of the present invention.

In FIG. 1, the MOSFET is an n-channel type,
It is formed on the main surface of P-type semiconductor substrate 1. A field oxide film 2 is selectively formed in the P-type semiconductor substrate 1, and an n"ffi polycrystalline silicon FJ!I7 is provided from above the element formation region to the field oxide film 2, forming an n+ type packing. Due to the impurity diffusion in the crystal 9977 layer 7, an n" type source VI region 3 and an n" type drain region 4 are formed in a self-aligned manner, and the electrodes of these source-drain regions 3.4 are drawn out as n+ type. molded crystal 9
It is made of 977 layers 7. Additionally, a side wall spacer 6 made of phosphor glass (PSG) 113 is provided on the side wall of the n+ type polycrystalline silicon retainer 7. At the bottom of this side 1 spacer 6, there is an n'-type region 3 and an n? An n-type offset region 3as4a is formed adjacent to the type drain/region 4, and the conventional LDD
It has a structure similar to Ji-zukuri. Further, a channel region is defined in a self-aligned manner by the n+ type packed crystal 9977 layer 7 and the sidewall spacer 6, and a gate electrode 9 made of a high melting point metal or a metal is placed on the channel region via a gate film 5. is formed. Note that 8 in the figure is an oxide film, and the drawings of the electrodes of the n+ type packed crystal 9977 layer 7 are omitted.

According to the structure of the above embodiment, the n medium polycrystalline silicon layer 7
Due to impurity diffusion from the source/drain region 3.4
are formed in a self-aligned manner, and the source and drain electrodes are drawn out using this n+ type polycrystalline silicon layer 7, making it possible to reduce device dimensions without being subject to the limitations of the phosphorography technique described above. becomes. the result,
Parasitic elements such as the drain-substrate t11 capacitance can be significantly reduced, and higher performance and higher integration of the element can be achieved.

Furthermore, since the n+ type polycrystalline silicon b7 is inserted between the diffusion layer (source/drain region 3.4 and the wiring metal layer), the diffusion layer and the wiring metal layer do not come into direct contact with each other, so the contact hole area stable electrical contact is possible.

Additionally, according to this structure, it is possible to lower the temperature of heat treatment after forming the gate electrode, and a metal layer such as aluminum can be used as the gate electrode, reducing wiring delays caused by the gate electrode material and increasing the speed of the device. It has a calming effect.

Next, a method for manufacturing the semiconductor device of the above embodiment is shown in FIG.
) to (f) will be explained in order.

(1) Field oxide l122 and oxidized S i O* film 11 are formed on P-type semiconductor substrate 1 . Furthermore, C.V.
After the nitrided (S is N 4 ) a 12 and SiO film 13 are deposited by method D, the S 1 s Na film 1 is deposited in a region other than the region that will become the channel region of the MOSFET.
The film 13' is selectively etched with 2 and S i O,
By ion implanting phosphorus or arsenic (As), n-f
An f1 offset region 3as4a is formed. (See Figure 3(a)) (2) Next, a PSG film is deposited on the entire surface by CVD, and then etched by anisotropic etching (RIE) to selectively coat the sidewalls of the 5isN4a12 and SiO2 films 13. A sidewall spacer 14 made of a PSG film is then formed. (See Figure 3(b)) (3) Next, a polycrystalline silicon layer 7 is applied to the entire surface.
After doping the polycrystalline silicon layer 7 with arsenic or phosphorous by ion implantation or pre-deposition method, a resist film 15 is applied and formed by RI method.
The resist film 15 on the region that will become the channel region of the MOSFET is selectively removed by etchback using the E method. (See FIG. 3(c)) (4) Continuing, using the resist film 15 as a mask,
After selectively etching the polycrystalline silicon layer 7, the 5jOt film 13 is removed by RIE.

(See FIG. 3(d)) (5) Thermal oxidation of the polycrystalline silicon layer 7 is performed in a lower state with the S is Na film 12 remaining. At this time, n-type impurities are diffused from the polycrystalline silicon layer 7 and the n++ source region 3
and n++ drain region 4 are formed in a self-aligned manner.

(See FIG. 3(e)) (6) S is Na film 12
, and after removing the Sin film 11, oxidation is performed to form the gate film 5.

Further, after sputtering a metal such as aluminum, the gate electrode 9 is buttered by phosphorography. (See FIG. 3(f')) Hereinafter, by following the conventional semiconductor device manufacturing method, a semiconductor device having the above-described effects can be formed in a relatively small number of steps.

In this embodiment, an n-channel type MOSFET
Although the case described above has been described, if a P-type impurity such as boron (B) or 13F is used instead of the n-type impurity, a P-channel MO3FET having the same effect can be obtained.

In addition, a PSG film was used as a sidewall spacer, but in addition to this, an S>O* film and a borophosphorus glass (B
PSG) membrane, or 5hot crotch and nitrided (S js
A composite membrane such as a N a ) membrane may also be used. In addition, a polycide layer may be used instead of the polycrystalline silicon layer.

Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the spirit of the invention.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the source/drain regions are formed in a self-aligned manner by impurity diffusion from the polycrystalline silicon layer, and the source/drain electrodes are formed in this polycrystalline silicon layer. In order to bring out this, the device size can be reduced without being limited by phosphorography technology.

As a result, the influence of the parasitic region of the A, fO3FET can be significantly reduced, and higher performance and higher integration of the device can be achieved.

Furthermore, since the diffusion layer and the interconnection metal scrap layer do not come into direct contact with each other, electrically stable contact can be obtained at the contact hole portion, and a highly reliable device can be obtained.

Furthermore, since the heat treatment process after forming the gate electrode can be made less tedious, a metal layer can be used as the gate electrode, reducing speed delays caused by the gate electrode material and increasing the speed of the device. It has this effect.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention;
Figure 2 is a cross-sectional view of a conventional semiconductor device, and Figures 3 (a) to (
f) is a step-by-step sectional view showing a method for manufacturing the semiconductor device of FIG. 1; In the figure, 1 is a P-type semiconductor substrate, 2 is a field oxide film, 3 is an n+ type drain region, 4 is an n+ type drain region,
3 as 4 a is an n- type offset region, 5 is a gate film, 6.14 is a side wall spacer, 7 is an n + type polycrystalline silicon layer, 8.11 is an oxide film, and 9.1o is a gate ffl t! , 12 HaS i sN, IIQ, 13
CtCVDSiO*B, 15 is a resist film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Applicant: Seiko Epson Corporation No. 2

Claims (1)

[Claims] In a semiconductor device having a MOS structure, a polycrystalline silicon layer provided from a source or drain forming region to an element isolation region, and a polycrystalline silicon layer formed in a self-aligned manner by diffusion from the polycrystalline silicon layer. a source region and a drain region; a sidewall spacer provided on a sidewall of the polycrystalline silicon layer; and a source region or drain provided adjacent to the source region or drain region and below the sidewall spacer. a channel region defined in a self-aligned manner by the polycrystalline silicon layer and the sidewall spacer; and a channel region defined on the sidewall spacer and the polycrystalline silicon layer via a gate film on the channel region. A semiconductor device comprising: a gate electrode formed over an insulating film.