JPS64764A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS64764A JPS64764A JP15568287A JP15568287A JPS64764A JP S64764 A JPS64764 A JP S64764A JP 15568287 A JP15568287 A JP 15568287A JP 15568287 A JP15568287 A JP 15568287A JP S64764 A JPS64764 A JP S64764A
- Authority
- JP
- Japan
- Prior art keywords
- region
- self
- silicon layer
- polycrystalline silicon
- providing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To reduce the area of a parasitic region and to achieve high performance and high density in a MOSFET, in a semiconductor device having a MOS structure, by providing a source region and a drain region, which are formed in a self-aligning mode, providing a side wall spacer, which is provided at the side wall of a polycrystalline silicon layer, providing an offset region of the source region or the drain region, and providing a channel region and a gate electrode, which are determined by a self-aligning mode.
CONSTITUTION: A channel region is determined at an N+ type polycrystalline silicon layer 7 and a side wall spacer 6 in a self-aligning manner. A gate electrode 9 comprising high melting point metal is formed through a gate film 5 on the channel region. Therefore, source/drain regions 3 and 4 are formed in a self-aligning manner by the diffusion of impurities from the N+ type polycrystalline silicon layer 7. The leadout of the source/drain region electrodes is performed with the N+ type polycrystalline silicon layer 7. Therefore, the size of an element can be reduced without restriction on lithography technology. Parasitic elements such as a drain-substrate capacitor can be decreased to a large extent. The high performance and the high density are achieved in the element.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-155682A JPH01764A (en) | 1987-06-23 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-155682A JPH01764A (en) | 1987-06-23 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS64764A true JPS64764A (en) | 1989-01-05 |
JPH01764A JPH01764A (en) | 1989-01-05 |
Family
ID=
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5146291A (en) * | 1988-08-31 | 1992-09-08 | Mitsubishi Denki Kabushiki Kaisha | MIS device having lightly doped drain structure |
US5217913A (en) * | 1988-08-31 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers |
US5371024A (en) * | 1988-09-30 | 1994-12-06 | Kabushiki Kaisha Toshiba | Semiconductor device and process for manufacturing the same |
US5834816A (en) * | 1991-10-10 | 1998-11-10 | Goldstar Electron Co., Ltd. | MOSFET having tapered gate electrode |
US5949105A (en) * | 1991-06-26 | 1999-09-07 | Texas Instruments Incorporated | Insulated-gate field-effect transistor structure and method |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5146291A (en) * | 1988-08-31 | 1992-09-08 | Mitsubishi Denki Kabushiki Kaisha | MIS device having lightly doped drain structure |
US5217913A (en) * | 1988-08-31 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers |
US5371024A (en) * | 1988-09-30 | 1994-12-06 | Kabushiki Kaisha Toshiba | Semiconductor device and process for manufacturing the same |
US5949105A (en) * | 1991-06-26 | 1999-09-07 | Texas Instruments Incorporated | Insulated-gate field-effect transistor structure and method |
US5834816A (en) * | 1991-10-10 | 1998-11-10 | Goldstar Electron Co., Ltd. | MOSFET having tapered gate electrode |
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