JPS64762A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS64762A
JPS64762A JP15568387A JP15568387A JPS64762A JP S64762 A JPS64762 A JP S64762A JP 15568387 A JP15568387 A JP 15568387A JP 15568387 A JP15568387 A JP 15568387A JP S64762 A JPS64762 A JP S64762A
Authority
JP
Japan
Prior art keywords
silicon layer
polycrystalline silicon
region
source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15568387A
Other languages
Japanese (ja)
Other versions
JPH01762A (en
Inventor
Tomoyuki Furuhata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP15568387A priority Critical patent/JPS64762A/en
Publication of JPH01762A publication Critical patent/JPH01762A/en
Publication of JPS64762A publication Critical patent/JPS64762A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the area of a parasitic region and to achieve high performance and high density in a MOSFET, in a semiconductor device having a MIS structure, by providing a polycrystalline silicon layer, which is formed on a part from a source region to an element isolating region, providing the source region and a drain region, which are formed in a self-aligning mode, and providing a gate electrode, which is formed along an insulating film.
CONSTITUTION: A channel region is determined with an N+ type polycrystalline silicon layer 5 by a self-aligning mode. A gate electrode 8, which is selected from among a polycrystalline silicon layer, high melting point metal, metal and metal silicide, is formed on the channel region through a gate film 6. Source/drain regions 3 and 4 are formed in a self-aligning mode by the diffusion of impurities from the N+ type polycrystalline silicon layer 5. Lead-out of the source/drain electrodes is performed with said N+ type polycrystalline silicon layer 5. Therefore, the size of an element can be reduced without restriction on lithography technology. As a result, parasitic element such as a drain- substrate capacitance are decreased to a large extent. The high performance and the high density of the element can be achieved.
COPYRIGHT: (C)1989,JPO&Japio
JP15568387A 1987-06-23 1987-06-23 Semiconductor device Pending JPS64762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15568387A JPS64762A (en) 1987-06-23 1987-06-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15568387A JPS64762A (en) 1987-06-23 1987-06-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH01762A JPH01762A (en) 1989-01-05
JPS64762A true JPS64762A (en) 1989-01-05

Family

ID=15611281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15568387A Pending JPS64762A (en) 1987-06-23 1987-06-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS64762A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
US5006911A (en) * 1989-10-02 1991-04-09 Motorola, Inc. Transistor device with high density contacts

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
US5006911A (en) * 1989-10-02 1991-04-09 Motorola, Inc. Transistor device with high density contacts

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