JPS5696872A - Manufacture of insulated gate type semiconductor memory device - Google Patents
Manufacture of insulated gate type semiconductor memory deviceInfo
- Publication number
- JPS5696872A JPS5696872A JP17201380A JP17201380A JPS5696872A JP S5696872 A JPS5696872 A JP S5696872A JP 17201380 A JP17201380 A JP 17201380A JP 17201380 A JP17201380 A JP 17201380A JP S5696872 A JPS5696872 A JP S5696872A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- type
- covered
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 3
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To lower the wiring voltage of the insulated gate type semiconductor memory device and the reduce the size thereof by simultaneously forming high density layers at the peripheral edge of a layer arranged separately at least from a substrate and the channel peripheral edge between the layers in the MOS device. CONSTITUTION:The n type Si substrate 11 is covered with an SiO2 film, and an n<+> type layer 14 is formed n the periphery. Then, an SiO2 film is newly formed, the layer 14 is covered thereon, a gate oxide film and a polysilicon floating gate 16 are formed, and impurity is introduced to the gate 16. Further, a polysilicon gate electrode 15b is formed through the SiO2 film 15, is etched, and the substrate is exposed. B is diffused, p<+> type layers 12, 13 are formed with the gate 15b as a conductor, the SiO2 is covered thereon, a window is opened thereat, and aluminum electrodes 12b, 13b are formed thereon. According to this configuration a voltage causing avalanche breakdown is low and the n<+> type layer is formed at the periphery of the FET. Therefore, the expansion of the depletion layer from the drain becomes small. Consequently, it can be integrated, and the writing voltage is also low.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17201380A JPS5696872A (en) | 1980-12-08 | 1980-12-08 | Manufacture of insulated gate type semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17201380A JPS5696872A (en) | 1980-12-08 | 1980-12-08 | Manufacture of insulated gate type semiconductor memory device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3170872A Division JPS559834B2 (en) | 1972-03-31 | 1972-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5696872A true JPS5696872A (en) | 1981-08-05 |
Family
ID=15933904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17201380A Pending JPS5696872A (en) | 1980-12-08 | 1980-12-08 | Manufacture of insulated gate type semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5696872A (en) |
-
1980
- 1980-12-08 JP JP17201380A patent/JPS5696872A/en active Pending
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