JPS5696873A - Manufacture of insulated gate type semiconductor memory device - Google Patents
Manufacture of insulated gate type semiconductor memory deviceInfo
- Publication number
- JPS5696873A JPS5696873A JP17201480A JP17201480A JPS5696873A JP S5696873 A JPS5696873 A JP S5696873A JP 17201480 A JP17201480 A JP 17201480A JP 17201480 A JP17201480 A JP 17201480A JP S5696873 A JPS5696873 A JP S5696873A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- sio2
- substrate
- gate
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 239000010410 layer Substances 0.000 abstract 7
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 238000009792 diffusion process Methods 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To obtain the memory device by surrounding the layer provided on an Si substrate by separate diffusion and the periphery of the interlayer channels by a layer of high concentration, performing etching with a gate electrode as a mask, exposing the substrate, and providing a source and a drain on the exposed surface. CONSTITUTION:The n type Si substrate 11 is covered by SiO2 and an n<+> layer 14 is formed on the periphery. SiO2 is newly provided, the n<+> layer 14 is covered, a gate oxide film and a poly Si floating gate 16 are provided, and impurities are introduced into the gate 16. Then, a poly Si gate electrode 15b is provided via SiO2 15, etching is performed with the electrode as a mask, and the substrate is exposed. The electrode 15b is made to be a conductor by B diffusion, p<+> layers 12 and 13 are formed and covered by SiO2, windows are opened, and Al electrodes 12b and 13b are attached. In this constitution, the avalanche breakdown is generated at the low voltage, and the expansion of the depletion layer from the drain is small because of the n<+> layer around the FET. Therefore the integration can be accomplished and the writing voltage is small.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17201480A JPS5696873A (en) | 1980-12-08 | 1980-12-08 | Manufacture of insulated gate type semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17201480A JPS5696873A (en) | 1980-12-08 | 1980-12-08 | Manufacture of insulated gate type semiconductor memory device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3170872A Division JPS559834B2 (en) | 1972-03-31 | 1972-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5696873A true JPS5696873A (en) | 1981-08-05 |
Family
ID=15933922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17201480A Pending JPS5696873A (en) | 1980-12-08 | 1980-12-08 | Manufacture of insulated gate type semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5696873A (en) |
-
1980
- 1980-12-08 JP JP17201480A patent/JPS5696873A/en active Pending
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