JPH10144915A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which is compatible between a self-aligning contact formation and a salicide formation by a method wherein, in manufacturing a semiconductor circuit with a silicide film being used as an electrode material, an insulating film is formed, protecting a gate electrode part from an electric shorting without requiring considerable step increase and positioning with high precision. SOLUTION: After the formation of a gate electrode 13 composed of a laminated body of a first insulation film 12, a silicon film, a second insulating film 19 on a semiconductor substrate 10, and a side wall 16 enclosing this gate electrode, the second insulating film of the gate electrode 12 is removed to expose a silicon film, and a silicide layer 19 is formed therein. A cap insulating film is formed on the silicide layer 19 thus formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a salicide (Salicide: Self-aligned-type) which forms a silicide in a self-alignment manner with a gate electrode or a diffusion layer.
The present invention relates to a highly integrated semiconductor device having a self-aligned contact (SAC) and a self-aligned contact (SAC) for forming a contact in a self-aligned manner in a space between elements arranged in high density.

[0002]

2. Description of the Related Art As the density and performance of semiconductor integrated circuits increase, the width of wirings decreases, and the depth of source / drain diffusion layers decreases. For this reason, the electrical resistance of the wiring, the diffusion layer, and the like increases, which is one of the causes of an increase in signal transmission delay. One method of reducing such transmission delay is to use a low-resistance silicide as a wiring material or the like. In particular, a silicide formed in a self-aligned manner on a gate electrode or a diffusion layer is generally called a salicide. I have.

[0003] Further, due to the high integration of semiconductor integrated circuits,
Since the distance between adjacent transistors is getting smaller,
A wiring contact window shared between transistors is formed by a method of self-alignment (self-alignment) via a sidewall of a gate electrode. The contact thus formed is called a self-aligned contact.

[0004] Based on the process sectional views of FIGS. 12 and 13,
A conventionally used salicide process will be described.
First, as shown in FIG. 12A, an element isolation film 51 is formed on a silicon substrate 50 by a LOCOS method. Next, as shown in FIG. 12B, after forming a gate oxide film 54 by thermal oxidation, a polysilicon 52 serving as a gate electrode is formed, and the polysilicon gate electrode 52 is used as a mask.
Impurity ions are implanted into the surface of the silicon substrate 50 to form the source / drain diffusion layers 53.

[0005] Next, as shown in FIG. 12 (c), for example, an SiO ₂ layer is deposited on the entire surface and RIE (Reactive Ion Etching) is performed.
The SiO ₂ film is etched by anisotropic dry etching such as the
To form Next, as shown in FIG. 13A, for example, a cobalt film 56 which is a refractory metal is deposited on the entire surface.

Subsequently, when annealing is performed for a short time at a relatively low temperature of about 550 ° C. for about 30 seconds, as shown in FIG. 13 (b), the silicon is exposed on the gate electrode and the source / drain diffusion region is exposed. A silicidation reaction occurs on the layer, but no silicidation reaction occurs on the element isolation film 51 and the side wall 55 made of a silicon oxide film. Therefore, the silicide is selectively formed only on the gate electrode and the source / drain diffusion layers. Is formed.

Thereafter, unreacted cobalt is removed with a mixed solution of hydrogen peroxide and aqueous ammonia. This process leaves only the silicide film 57 formed only on the gate electrode and the source / drain diffusion layers. Next, high-temperature and short-time annealing is performed at a temperature of about 830 ° C. for about 30 seconds,
Reduce the resistance of CoSix film. The above is the conventional salicide process.

Next, a conventional method of forming a self-aligned contact will be described with reference to FIGS. First, as shown in FIG.
An element isolation film 61 is formed on the substrate 0 by the LOCOS method. Next, as shown in FIG. 14B, a polysilicon 62 serving as a gate electrode and an insulating film 63 are formed, and using this as a mask, impurities are ion-implanted into the surface of the silicon substrate 60 to form a source / drain diffusion layer 64. I do.

Next, as shown in FIG.
An O ₂ layer is deposited on the entire surface, the SiO ₂ film is etched by anisotropic dry etching such as RIE, and a sidewall 66 is formed on the side surface of the gate electrode to expose the source / drain diffusion layer 64. . Subsequently, as shown in FIG. 15A, an insulating film 67 is deposited by a CVD method, and as shown in FIG. 15B, the insulating film 67 is etched by an RIE method to form a contact hole 68. Form.

Next, as shown in FIG. 15C, a source / drain lead-out electrode 69 made of polysilicon is self-aligned using the side wall of the gate electrode.
Is formed at the position of the contact hole. The above is the conventional method of forming a self-aligned contact.

[0011]

However, it is not easy to combine the step of forming salicide on the gate electrode with the step of forming a self-aligned contact. This means that in the salicide formation step, the gate electrode must be exposed for silicidation, whereas in the self-aligned contact formation, the source / drain lead-out electrodes come into contact with the gate electrode to cause a short circuit. This is because an insulating film must be formed over the gate electrode in order to prevent this.

Therefore, after the silicide is formed on the gate electrode, it is necessary to selectively form an insulating film thereon. As a method of realizing this, for example, a method is considered in which, after forming silicide, an insulating film is deposited on the entire surface, and the insulating film is selectively etched using a mask to leave only the insulating film on the gate electrode. Can be However, such a method involves technical difficulties because accurate alignment accuracy is required for mask alignment.

As another method, an SiO ₂ film is formed on a substrate,
Polysilicon and a metal film are sequentially deposited, silicidation of the surface of the polysilicon film is performed, an insulating film is deposited thereon, and then a gate electrode is formed. Thereafter, silicidation of the source / drain diffusion layers is performed. There is a way. However, this method has a disadvantage that the silicidation step on the gate electrode and the silicidation step of the source / drain diffusion layers are separate steps, and the number of steps is increased.

The present invention provides a means for solving the above-mentioned problems. In the manufacture of a semiconductor circuit, the formation of an insulating film for protecting a gate electrode portion from an electrical short circuit can be performed by a large number of steps or by a high-precision position. It is an object of the present invention to provide a method capable of easily combining a salicide forming step and a self-aligned contact forming step by enabling the alignment without requiring the alignment.

[0015]

SUMMARY OF THE INVENTION The above problems are caused by the steps of sequentially forming a first insulating film, a silicon film, and a second insulating film on a semiconductor substrate, and forming the second insulating film and the silicon film on the semiconductor substrate. Forming a gate electrode composed of a stacked body of the silicon film and the second insulating film by selectively removing them sequentially;
Forming a source / drain diffusion layer in the semiconductor layer using the gate electrode as a mask; depositing a third insulating film on the semiconductor substrate including the gate electrode; Anisotropically etch the third
Forming a sidewall made of an insulating film, removing the second insulating film on the silicon film of the gate electrode to expose the silicon film, forming the gate electrode and the source / drain diffusion A step of depositing a metal film on the semiconductor substrate including the layer, and heat-treating the semiconductor substrate including the metal film to react the silicon film and the source / drain diffusion layers with the metal film;
Forming a silicide layer, selectively removing a non-silicidized portion of the metal film, and depositing a fourth insulating film on the semiconductor substrate including the silicide layer. Forming a cap film on the silicide layer on the gate electrode by etching an insulating film.

The principle of the present invention will be described with reference to FIGS. In FIG. 1A, 10 is a silicon substrate, 11 is an element isolation film, 12 is a gate oxide film, 13 is polysilicon doped with impurities to be a gate electrode, and 15 is a source / drain.
A drain diffusion layer, 16 is a side wall, and 18 and 19 are silicide layers. In the present invention, the coating film once deposited on the gate electrode is removed by utilizing the difference in the etching selectivity with the sidewall 16 to form the recess 70 where the gate electrode is exposed. Therefore, when a metal film is deposited on the entire surface, silicides 18 and 19 can be simultaneously formed on the gate electrode and the source / drain diffusion layer 15.

Next, as shown in FIG. 1B, a cap film 22 is formed on the silicide 19 on the gate electrode. This cap film protects the silicide 19 on the gate electrode,
Self-aligned source / drain extraction electrodes
Even in the case of forming by a contact, as shown in FIG. 1C, a short circuit between the silicide 19 on the gate electrode and the adjacent extraction electrode can be prevented.

Therefore, both a self-alignment contact forming step of forming a wiring contact at a high density by utilizing the side wall of the gate electrode and a salicide forming step on the gate electrode can be made compatible. Further, originally, a cap film for preventing a short circuit between the gate electrode and the wiring contact is formed. However, by forming this cap film so as to cover only a part of the salicide on the gate and to expose a part thereof, the gate film is formed. It is also possible to form a contact between a wiring and another wiring in a self-aligned manner.

That is, as shown in FIGS. 2 (a) and 2 (b), the width of the gate wiring is locally increased at a portion where electrical connection with the gate wiring is desired to be formed, and the cap film 29 is formed there. The cap film 29 cannot completely cover the gate, and the silicide 19 is exposed at the center. However, since the cap film 29 protects the silicide 19 at the edge, a self-alignment contact can be formed (FIG. 2A).

On the other hand, if the portion where the silicide 19 is exposed is used as a contact window and is connected to another wiring (FIG. 2 (b)), a window free from positional displacement without a window opening step can be formed. It is possible to form. in this case,
In other places where the gate wiring width is small, the cap film sufficiently covers the gate, so that even if another wiring passes right above, no short circuit occurs.

As described above, when the present invention is used, a contact between a gate wiring and another wiring can be formed in a self-aligned manner by adjusting the width of the gate wiring, thereby shortening the manufacturing process and reducing the cell area. It helps to reduce the size.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be specifically described below with reference to schematic sectional views shown in FIGS. First, an element isolation film 11 is formed on a silicon substrate 10 by a known LOCOS method (see FIG. 3A).

Referring to FIG. 3B, a gate oxide film 12 having a thickness of about 6 nm is formed by thermal oxidation. Then, polysilicon 13 doped with an impurity having a thickness of about 60 nm to be a gate electrode is formed by CVD.
To form Next, a SiN film 14 is deposited on the polysilicon by CVD. The deposited film thickness is about 70 nm.

The conditions for growing the SiN film are as follows: SiH ₄ / NH ₄ = 20 /
The film thickness is 60 SCCM, 1.5 Torr, RF Power 150 W, 350 ° C., and the optical constant of the formed SiN film 14 is n = 2.5 and k = 0.35 with respect to the light source of the exposure apparatus. . Here, n is a refractive index and k is an absorption constant. By setting the optical constants in such a manner, the SiN film 14 can have a wavelength of 2
It has an antireflection effect on light of 48 nm, and also plays a role as an antireflection film for preventing halation in a lithography process when processing a gate electrode.

Next, a resist is applied, the pattern of the gate electrode is transferred at a line width of 0.25 μm using a wavelength of 248 nm, and the gate electrode is formed by anisotropic etching such as reactive ion etching using the resist as a mask. Form. Next, an SiO ₂ film serving as a side wall is deposited and anisotropically etched by RIE to form a first side wall insulating layer 16 of a gate electrode.

Referring to FIG. 4A, an insulating film deposited on the polysilicon 13 in the gate electrode portion
The SiN 14 is selectively etched away with phosphoric acid. Although the insulating film SiN 14 is removed by this etching, the sidewall insulating layer 16 which is an oxide film is not etched. This leaves only the sidewalls,
A concave shape surrounded by the side wall is formed.

Next, using the gate electrode as a mask,
For example, As ⁺ has an acceleration energy of 30 KeV and a dose of 2 ×
Ion implantation is performed at 10 ¹⁵ / cm ² . RTA (Rapi
A thermal treatment at 1000 ° C. for 10 seconds is performed by the thermal annealing method to activate the ion-implanted As ⁺ ions, thereby forming the source / drain diffusion layers 15. Next, a cobalt (Co) film 17 having a thickness of 6 to 15 nm is deposited on the entire surface of the silicon substrate by, for example, a sputtering method.

Referring to FIG. 4C, as a first-step heat treatment for forming a silicide film, heat treatment is performed at 450 to 650 ° C. for 30 seconds by the RTA method. As a result, only the exposed portion of the cobalt layer in contact with the silicon substrate 10 and the cobalt layer on the gate electrode react to generate silicides 18 and 19 selectively on the element region.

Subsequently, the silicon substrate is immersed in a chemical solution containing, for example, a mixed solution of hydrogen peroxide and sulfuric acid, and wet-etched. At this time, the cobalt of the metal that has not been silicided is dissolved, but the silicides 18 and 19 are not dissolved. Therefore, the metal film in other portions is removed except for the silicide 18 on the source / drain diffusion layer 15 and the silicide 19 on the gate. After this, again,
A second-stage heat treatment for forming a silicide film is performed to reduce the resistance of the silicide film.

Next, referring to FIG. 5 (a), TEOS (Tetraethoxy
silan: Silicon oxide film 21 using Si (OC ₂ H ₅ ) ₄ ) and O ₂
Is deposited, for example, to about 100 nm. This silicon oxide film 2
Numeral 1 is also deposited in the depression surrounded by the side wall on the gate and serves as a cap film that covers silicide 19 on the gate electrode and prevents it from coming into contact with other conductors.

Referring to FIG. 5B, anisotropic etching such as a well-known RIE method is performed to remove the silicon oxide film 21. At this time, the cap film 22 on the gate electrode and the first side wall 16 are removed. The second sidewall 23 formed outside is left. The second side wall 23 has the advantage that the wiring arranged on the upper side becomes easy because the angle of the step portion of the side wall is made gentle.

Next, as shown in FIG. 5C, a BPSG film 24 is deposited to a thickness of 500 nm by the CVD method. Next, after applying a resist and performing an exposure process, the BPS
The G film 24 is anisotropically etched by RIE,
The resist is removed, and a contact hole 25 is formed on the diffusion layer.

Referring to FIG. 6B, a lead electrode 26 is formed at the position of the contact hole 25. Next, a second embodiment of the present invention will be described with reference to schematic sectional views of FIGS. 7 and 8. The semiconductor device according to the present embodiment is characterized in that a film for etching stop is formed after the formation of the cap film. 7 and 8
Parts corresponding to FIGS. 3 to 6 are denoted by the same reference numerals.

Referring to FIG. 7A, first, as in the first embodiment, an element isolation film 11, a gate oxide film 12, a polysilicon 1
3, a silicide 18, 19 on the gate electrode and the source / drain diffusion layer 15, a cap film 14 on the silicide on the gate electrode, a first sidewall 16 on the side of the gate electrode, and The second sidewall 23 is formed.

Next, a nitride film 28 is deposited on the entire surface to a thickness of about 10 nm. This film is formed in an oxide film etching step by RIE before forming a contact hole.
It functions as an etching stopper for protecting the lower oxide films 11, 14, and 23. Next, CV
A PSG film 27 is deposited to a thickness of about 500 nm by method D,
The surface is flattened by MP (Chemical Mechanical Polishing) method.

Next, referring to FIG. 7B, the PSG film 27 is etched by RIE using a resist film to form a contact hole 25. At this time, since the etching rate of the nitride film 28 is lower than that of the oxide film, the etching stops at the portion of the nitride film 28 and serves to protect the oxide films 11, 14, and 23 thereunder. After the etching, the resist mask is removed.

Referring to FIG. 7C, the exposed nitride film 28 is etched with phosphoric acid. A source / drain extraction electrode 26 is formed at the position of the contact hole formed with reference to FIG. 8 using the sidewall of the gate electrode.

As described above, by forming a film for etching stop on the cap film,
In the etching process performed to form holes,
The lower layer can be protected. Next, a third embodiment of the present invention will be described with reference to FIGS. The present embodiment is characterized in that the present invention is applied to an SRAM cell and a contact is formed by adjusting the width of a gate wiring. Note that the same reference numerals are given to portions corresponding to those in FIGS. 3 to 6 in the drawings.

FIG. 9A is a circuit diagram of an SRAM memory cell. In FIG. 9A, WL is a word line, BL and BL / (BL bar) are bit lines, and T1 to T6 are cells. Are transistors. In this cell, the transistor T
1 and T2, and transistors T3 and T
The outputs of the four inverters have a cross-coupled structure in which they are input to each other. T5,
T6 operates as a gate circuit.

In such a structure, in order to achieve high integration of the cell, it is necessary to narrow the interval between local wirings connecting the inside of the cell. FIG. 9B is a plan view of an SRAM cell portion corresponding to the circuit diagram of FIG. 9A. In this figure, 90 is a VDD contact, 91 is a VSS contact, 96 is a word line, 9
Numerals 2 and 93 indicate contact with the bit line, 80 and 81 indicate gate wirings, 82 and 83 indicate local wirings inside the cell, 8
6, 87, 88, 89 are contacts inside the cell, 84,
Reference numeral 85 denotes a contact between the local wiring and the gate wiring inside the cell.

Here, the gate wiring 8 having a width of L1
0 and 81 have a width L2 wider than L1 at a specific location.
The wirings 82 and 83 connecting the gate and the source / drain regions inside the cell pass over the gate wiring 81 having the width L1 and take the contacts 84 and 85 with the gate wiring 80 having the width L2. Next, a method of manufacturing the semiconductor device according to the third embodiment will be described with reference to the schematic sectional views of FIGS. FIG.
Reference numerals 0 and 11 correspond to the AA 'section in FIG. 9B.

Referring to FIG. 10A, first, an element isolation film 31 is formed on a silicon substrate 30 by a well-known LOCOS method. Next, as shown in FIG. 10B, a polysilicon 32 doped with an impurity and having a thickness of about 160 nm and a SiN film 33 serving as a gate wiring are sequentially formed on the element isolation film 31 by the CVD method. SiN film 3
The deposited film thickness of No. 3 is about 70 nm.

A resist is applied, a pattern of a gate wiring is transferred, and a gate wiring is formed by anisotropic etching such as reactive ion etching using the resist as a mask. The wiring width of the gate wiring 80 as the contact portion is L2, which is wider than the wiring width L1 of the gate wiring 81. Next, as shown in FIG. 10C, a SiO ₂ film serving as a side wall is deposited, and anisotropic etching is performed by RIE to form a side wall insulating layer 35 of a gate electrode.

Next, the SiN film 33 deposited on the polysilicon 32 of the gate wiring layer is selectively removed by etching. Although the SiN film 33 is removed by this etching, the sidewall insulating layer 35, which is an oxide film, is not etched due to a difference in selectivity, so that only the sidewall remains, and a concave shape surrounded by the side wall is formed. Next, ions of an impurity, for example, As ⁺ are implanted under the conditions that the acceleration energy is 30 KeV and the dose is 2 × 10 ¹⁵ / cm ² . Next, RTA (Rapid Thermal Anneal) method was performed at 980 ° C for 10 minutes.
A second heat treatment is performed to activate As ⁺ ions, and source / drain diffusion layers 34 are formed.

Next, a cobalt film having a thickness of 6 to 15 nm is deposited on the entire surface of the silicon substrate by, for example, a sputtering method.
Heat treatment is performed at 450 to 650 ° C. for 30 seconds by Method A. As a result, only the exposed portion of the cobalt layer in contact with the silicon substrate 30 and the cobalt layer on the gate wiring react to generate silicide. Subsequently, the silicon substrate is immersed in a chemical solution containing, for example, a mixed solution of hydrogen peroxide solution and sulfuric acid to leave only the silicide 36 on the source / drain diffusion layer and the silicide 36 on the gate wiring, and leave the other silicide 36 on the gate wiring. Portions of the metal film are removed. After this,
The heat treatment is performed again.

Next, a silicon oxide film 37 is deposited to a thickness of, for example, about 100 nm using TEOS by a plasma CVD method. This insulating film 37 is also deposited in the above-mentioned depression surrounded by the sidewall on the gate. Referring to FIG. 11B, a second sidewall 39 covering the existing sidewall 35 is formed by performing anisotropic etching such as the well-known RIE method.
And the insulating films other than the cap films 38 and 40 are removed. At this time, since the width is large above the wide gate wiring 80 having the wiring width L2, the insulating film 40 is
5 Fill the dent to some extent inward from both sides,
In the center, the silicide 36 is exposed without leaving any insulating film. On the other hand, the gate wiring 81 having a narrow wiring width L1
In the upper part, the width is narrow, so that the insulating film 38 can fill all the depressions.

Next, referring to FIG. 11C, Ti and Ti, which are local wirings connecting the inside of the cell,
N layer 83 is deposited. The deposited film thickness of the Ti layer is about 20 nm, and that of the TiN layer is about 50 nm. As shown in the figure, a local wiring 83 passes over the gate wiring 81 and makes contact with an adjacent gate wiring 80. Here, in the gate wiring 81, since the cap film 38 covers the entire surface of the silicide 36, it serves as a protective film for the cell internal wiring 83. However, in the gate wiring 80, since the wiring width is wide, the cap film 39 does not cover the entire surface of the silicide 36, and has a portion where the silicide 36 is exposed. For this reason, the cell internal wiring 83 is connected to the gate wiring 8
0 can be contacted.

As described above, by forming the cap film so as to cover only a part of the silicide on the gate and adjust the part so as to be exposed, the exposed part of the silicide can be used as a contact. . At this time, since the cap film covers the silicide at the edge,
Even if a self-alignment contact is formed in the vicinity, the problem of short circuit does not occur. In other places where the gate wiring width is narrow, the cap film sufficiently covers the gate, so that even if another wiring passes right above, no short circuit occurs. As described above, according to the present invention, it is possible to form a window free from a positional shift without a step of opening a window, which contributes to shortening of a manufacturing process and high integration.

In the formation of the diffusion layers according to the first to third embodiments, a simple example in which ion implantation is performed only once is taken as an example. For example, an LDD (Lightly Doped) in which ion implantation is performed twice.
The present invention can be applied to a transistor having a pedDrain structure or a MOD (Minimum Overlapped Drain) structure utilizing the existence of a sidewall. The present invention is particularly effective for a semiconductor device having a fine element spacing, for example, a device having a gate length of 0.35 μm or less, a sidewall width of 0.1 μm or less, and a diffusion layer having a depth of 0.1 μm or less. Is big.

Further, in the first to third embodiments, the nitride film is used as the first covering film on the gate electrode. However, any film having an etching characteristic with a selectivity different from that of the sidewall insulating film may be used. A metal film or a carbon film may be used. In this case, a TiN film can be selectively removed by hydrogen peroxide + ammonia, and a carbon film can be selectively removed by plasma ashing.

In the first to third embodiments, cobalt is used as a metal for forming silicide. However, any metal that can form silicide may be used. For example, titanium, nickel, tungsten, molybdenum, Platinum or the like may be used. However, for cobalt, Ti
Since the selectivity between N and etching is high, for example, when TiN is used as a local wiring, silicide is difficult to be etched, which is preferable.

[0052]

As described above, according to the present invention, the silicide on the gate electrode is protected by forming the cap film on the silicide on the gate electrode, and the source / drain lead-out electrode is formed by the self-alignment contact. Even when it is formed, short-circuiting between silicide on the gate electrode and an adjacent lead electrode can be prevented. Therefore,
It is possible to achieve both a self-alignment contact forming step of forming a wiring contact at a high density using the side wall of the gate electrode and a salicide forming step on the gate electrode.

[Brief description of the drawings]

FIG. 1 is a diagram (part 1) illustrating the principle of the present invention.

FIG. 2 is a diagram (part 2) illustrating the principle of the present invention.

FIG. 3 is a schematic process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device of the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 7 is a schematic process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 8 is a schematic process sectional view (part 2) illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 9 is a circuit diagram and a plan view of a cell part of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a schematic process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 12 is a sectional view (part 1) for explaining a salicide forming step;

FIG. 13 is a sectional view (part 2) for explaining a salicide forming step;

FIG. 14 is a cross-sectional view (part 1) illustrating a step of forming a self-alignment contact (SAC).

FIG. 15 is a cross-sectional view (part 2) illustrating a step of forming a self-alignment contact (SAC).

[Explanation of symbols]

 10, 30, 50, 60 ... silicon substrate 11, 31, 51, 61 ... element isolation film 12, 54, 65 ... gate oxide film 13, 32, 52, 62 ... gate electrode 15, 34, 53, 64 ... source / Drain diffusion layers 16, 35, 55, 66 Sidewalls 17, 56 Cobalt film 18 Silicide layers on source / drain diffusion layers 19 Silicide layers 36, 57 on gate electrodes 36, 57 Silicide layers 22, 38 Cap films 25, 68 contact holes 26, 69 source / drain lead electrodes 80, 81 gate wiring 82, 83 local wiring inside the cell

Claims (8)

[Claims] A step of sequentially forming a first insulating film, a silicon film, and a second insulating film on a semiconductor substrate; and selectively removing the second insulating film and the silicon film sequentially, Forming a gate electrode made of a laminate of a silicon film and the second insulating film; forming a source / drain diffusion layer in the semiconductor layer using the gate electrode as a mask; Depositing a third insulating film on a semiconductor substrate; anisotropically etching the third insulating film to form a sidewall made of the third insulating film; Removing the second insulating film on the film to expose the silicon film; depositing a metal film on the semiconductor substrate including the gate electrode and the source / drain diffusion layers; Heat-treating the semiconductor substrate including a film to react the silicon film and the source / drain diffusion layer with the metal film to form a silicide layer; and selectively forming a non-silicided portion of the metal film. And depositing a fourth insulating film on the semiconductor substrate including the silicide layer, and then etching the fourth insulating film to form a cap film on the silicide layer on the gate electrode And a method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the second insulating film can be selectively etched with respect to the silicon film and the third insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein an extraction electrode from a source or drain diffusion layer is formed in a self-alignment manner on a side surface of the sidewall of the gate electrode. 4. The second insulating film is a silicon nitride film having a refractive index of more than 2.0 and less than 2.8, and the light absorption coefficient of the silicon nitride film patterns the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the wavelength is larger than 0.4 and smaller than 0.8 with respect to the wavelength of a light source of an exposure apparatus used at that time. 5. The method according to claim 1, wherein said silicide is cobalt silicide. 6. A step of sequentially forming a first insulating film, a silicon film, and a second insulating film formed on a semiconductor substrate; and selectively removing the second insulating film and the silicon film sequentially. Forming a lamination pattern comprising a lamination of the silicon film and the second insulating film, the lamination pattern having a narrow width in the gate electrode region and a wide width in the contact region; and forming a lamination pattern in the semiconductor layer adjacent to the gate electrode region. Forming a source / drain diffusion layer on the substrate; forming a third insulating film on the semiconductor substrate including the stacked body; performing anisotropic etching to form a third insulating film on a side wall of the stacked body; Forming a sidewall made of a film, removing the second insulating film on the silicon film of the laminate to expose the silicon film, and forming the gate electrode and the source / drain diffusion layer Including Depositing a metal film on the semiconductor substrate, heat treating the semiconductor substrate including the metal film, and reacting the silicon film, the source / drain diffusion layer, and the metal film to form a silicide layer. Performing a step of selectively removing a non-silicidized portion of the metal film; and etching the fourth insulating film after depositing a fourth insulating film on the semiconductor substrate including the silicide layer. do it,
Forming a cap film on the silicide layer in the gate electrode portion, and exposing the metal silicide layer in the contact portion. 7. A gate electrode having a laminated structure of a silicon film and a first metal silicide layer formed in a device formation region on a semiconductor substrate via a gate insulating film, and a first metal silicide layer of the gate electrode A first insulating film formed thereon; a sidewall made of a second insulating film formed on a side surface of a stacked body of the silicon film, the first metal silicide layer, and the first insulating film; A diffusion layer formed on the semiconductor substrate in an element formation region on both sides of the electrode, the diffusion layer being a source and a drain; a second metal silicide layer formed on the diffusion layer being a source and a drain; And a conductive film contacting a second metal silicide layer formed on the diffusion layer serving as the source and the drain. 8. A conductive film which is in contact with a second metal silicide layer formed on a diffusion layer serving as a source and a drain, is in contact with the first insulating film. Semiconductor device.