JP2000077526A - Contact hole formation method for semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a contact hole for a semiconductor element, wherein the consistency tolerance for mismatching in photographic process is increased, for example, the exposure in a source/drain region of an MOS transistor is prevented so that a short circuit between the source/drain region and a gate electrode is prevented from occurring. SOLUTION: After first inter-layer insulating films 35 and 37 are formed around gate patterns 25 and 27 on a substrate 21, an etching-preventive film 39 and the second inter-layer insulating film 41 are formed over the entire surface, and the second inter-layer insulating film 41 is etched. Then the etching- preventive film 39 is etched to form a contact hole H'. Since the first inter-layer insulating films 35 and 37 and a spacer 31 are not etched at etching of the etchingpreventive film 39 even when a mismatching occurs, the exposure of a source/drain region 34 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.

[0002]

2. Description of the Related Art As the degree of integration of a semiconductor device increases, the size of a contact hole gradually decreases. Generally, a method of forming a contact hole includes a step of forming an interlayer insulating film on the entire surface of a semiconductor substrate on which a lower conductive layer is formed, and a step of patterning the interlayer insulating film to expose a predetermined region of the lower conductive layer. Become. The lower conductive layer is a region doped with an impurity or a wiring. The lower conductive layer is a gate electrode of the MOS transistor. At this time, the width of the gate electrode gradually decreases as the integration degree of the semiconductor device increases. Therefore, when performing a photolithography process for forming a contact hole directly on a gate electrode used for a highly integrated semiconductor device, an alignment margin (alignment margin) is required.
ment margin) is reduced.

FIGS. 1 and 2 are cross-sectional views for explaining a conventional method for forming a contact hole. First, as shown in FIG. 1, a gate insulating film 3 and a gate electrode 5 which are sequentially laminated on a predetermined region of a semiconductor substrate 1 are formed. Next, low concentration impurity regions are formed by implanting impurity ions into the surface of the semiconductor substrate 1 using the gate electrode 5 as an ion implantation mask. An insulating film is formed on the entire surface of the semiconductor substrate 1 on which the low-concentration impurity regions are formed, and the insulating film is anisotropically etched to form spacers 7 on the side walls of the gate electrode 5. Using the spacer 7 and the gate electrode 5 as an ion implantation mask, impurity ions are implanted into the surface of the semiconductor substrate 1 to form a high-concentration impurity region. The low-concentration impurity regions and the high-concentration impurity regions constitute source / drain regions 9 of the MOS transistor. An interlayer insulating film 11 is formed on the entire surface of the semiconductor substrate on which the source / drain regions 9 are formed.

Thereafter, as shown in FIG. 2, the interlayer insulating film 11 is patterned to form a contact hole H exposing the gate electrode 5. At this time, mis-alignment during a photo process for forming the contact hole H is performed.
When (nt) occurs, as shown in FIG. 2, the gate electrode 5 and the source / drain region 9 are simultaneously exposed by the contact hole H. Accordingly, if a conductive film (not shown) covering the contact hole H is formed in a subsequent process, a problem occurs in that the gate electrode 5 and the source / drain regions 9 are electrically connected to each other.

[0005]

As described above, according to the prior art, when a misalignment occurs during a photolithography process for defining a contact hole on a gate electrode, the gate electrode and the source / drain region are mutually connected. Has a problem of being electrically connected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a contact hole of a semiconductor device, which can increase a margin of misalignment in a photographic process, and more specifically, a method of forming a contact hole on a gate electrode of a MOS transistor. The present invention prevents the source / drain region adjacent to the gate electrode from being exposed even if a misalignment occurs during a photo process for forming a contact hole directly in the semiconductor device, and prevents a short circuit between the source / drain region and the gate electrode. To provide a method for manufacturing a semiconductor device.

[0007]

In the method of forming a contact hole in a semiconductor device according to the present invention, a lower pattern is first formed on a semiconductor substrate, and a first interlayer insulating film is formed on the entire surface of the semiconductor substrate on which the lower pattern is formed. Form a film. Here, the lower pattern is formed of a conductive film, for example, a metal film, a doped polysilicon film, or a polycide film. In addition, the lower pattern may be formed as a two-layer film pattern in which a conductive film pattern and a protective film pattern are sequentially stacked. The passivation layer pattern may be formed of an insulating layer having an etch selectivity with respect to the first interlayer insulating layer, for example, a silicon nitride layer or a silicon oxynitride layer. The first interlayer insulating film is an oxide film containing impurities or an undoped oxide film.
(USG; undoped silicate glass) and has an etching selectivity with respect to an etching prevention film described later. The impurity-containing oxide film may be a BPSG film flowed at a high temperature or a PSG film.
It is desirable to form with a film or a BSG film. Further, the first interlayer insulating film may be a two-layer insulating film in which a capping insulating film and an oxide film containing impurities are sequentially stacked. Here, the capping insulating layer is preferably formed of a plasma oxide layer or a high temperature oxide layer (HTO). The capping insulating layer prevents impurities in the oxide layer containing impurities from penetrating into the lower pattern, and deforms the lower pattern when the oxide layer containing impurities flows at a high temperature. It is formed for the purpose of preventing the occurrence. Also, a spacer may be formed on a sidewall of the lower pattern. At this time, the spacer can be formed of a silicon nitride film. In addition, the spacer may be formed of a material film such as the capping insulating film, that is, a silicon oxide film such as a plasma oxide film or a high-temperature oxide film.

Next, the entire surface of the first interlayer insulating film is etched until the upper surface of the lower pattern is exposed. Thereafter, an etch stop layer and a second interlayer insulating layer are sequentially formed on the entire surface of the semiconductor substrate where the upper surface of the lower pattern is exposed. Here, the second interlayer insulating film may be formed of an oxide film containing impurities or an undoped oxide film, or may be formed of a material film such as the first interlayer insulating film. On the other hand, the etch stop film is preferably formed of an insulator film having an etch selectivity with respect to the second interlayer insulating film, for example, a silicon nitride film.

Next, the second interlayer insulating layer is patterned in a photo / etching process to expose an etching stopper on the lower pattern. Thereafter, the exposed etch stop layer is etched to form a contact hole exposing a predetermined region of the lower pattern. At this time, even if a misalignment occurs during a photolithography process for patterning the second interlayer insulating film and the first interlayer insulating film and the spacer around the lower pattern are exposed, the exposed spacer and the first interlayer insulating film are exposed. The film is not etched because it has an etch selectivity to the etch stop film. In addition, even when the spacer is formed of the same material film as the etch stop layer, the semiconductor substrate is exposed by appropriately adjusting the over-etching time of the etch stop layer for forming a contact hole during etching. It can be adjusted so that it is not done. When the lower pattern is formed of a conductive film and a protective film pattern, the protective film pattern exposed after the etching of the exposed etching stopper film is continuously etched to form a predetermined region of the conductive film pattern. Expose.

In the above method, the lower pattern is specifically a wiring or a gate pattern of a MOS transistor. When the lower pattern is a gate pattern of a MOS transistor, after forming the gate pattern, a step of forming source / drain regions on the surface of the semiconductor substrate on both sides of the gate pattern is added. At this time, a spacer is formed on the side wall of the gate pattern, and impurity ions are implanted before and after the spacer, so that the source / drain region is formed by LDD.
Can be formed into a structure.

[0011]

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the embodiment, a contact hole is directly formed on a gate electrode of a MOS transistor using the lower pattern as a lower pattern. However, the present invention relates to a case where a contact hole is formed on the wiring using a general wiring as a lower pattern. It can also be applied to However, the present invention is suitable for forming a contact hole directly on the gate electrode of a short channel MOS transistor suitable for a highly integrated semiconductor device.

First, a gate insulating film 23 is formed on a semiconductor substrate 21 shown in FIG. 3, and a conductive film and a protective film are sequentially formed on the gate insulating film 23. Next, the protective film and the conductive film are successively patterned to form a conductive film pattern 25 and a protective film pattern 27 which are sequentially stacked on a predetermined region of the gate insulating film 23. Here, the conductive film pattern 25 serves as a gate electrode, and the conductive film pattern 25 and the protective film pattern 27.
Constitute a gate pattern. This gate pattern may be formed only by the conductive film pattern 25. However, in order to form a MOS transistor having a short channel suitable for a highly integrated semiconductor device, a fine gate electrode having a line width of 0.5 μm or less must be formed. An anti-reflection film is used to reduce irregular reflection during a photographic process for patterning the fine gate electrode. The passivation layer functions as an anti-reflection layer, and is formed of an insulating material having an etch selectivity with respect to a first interlayer insulating film formed in a subsequent process, for example, a silicon nitride film or a silicon oxynitride film. It is desirable. The conductive film is formed of a doped polysilicon film, a metal film, or a polycide film. Next, LDD regions 29 are formed on the surface of the semiconductor substrate 21 on both sides of the gate pattern by implanting impurity ions of a different conductivity type from the semiconductor substrate 21 using the gate pattern as an ion implantation mask.

Next, a spacer insulating film, for example, a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate 21 on which the LDD region 29 is formed. Then, the spacer insulating film is anisotropically etched to form spacers 31 on the side walls of the gate pattern as shown in FIG. Then
By using the spacer 31 and the gate pattern as an ion implantation mask, impurity ions of a conductivity type different from that of the semiconductor substrate 21 are implanted at a dose higher than that of the LDD region 29, thereby forming a semiconductor substrate on both sides of the gate pattern.
A high concentration impurity region 33 is formed on the surface of 21. At this time, the LDD region 29 remains below the spacer 31. The LDD region 29 and the high concentration impurity region 33 constitute a source / drain region 34.

As shown in FIG. 5, a first interlayer insulating film is formed on the entire surface of the semiconductor substrate 21 on which the source / drain regions 34 are formed. This first interlayer insulating film is preferably formed by sequentially laminating a capping insulating film 35 and an oxide film 37 containing impurities. Here, an undoped oxide film can be formed instead of the oxide film 37 containing impurities. The first interlayer insulating film is an oxide film containing impurities.
37 or an undoped oxide film alone. The oxide film containing the impurities is a BPSG film, a PSG film.
The film or BSG film is formed by flowing at a high temperature. On the other hand, the capping insulating film 35 is desirably formed of a plasma oxide film or a high temperature oxide film (HTO). This capping insulating film 35 prevents the impurity, that is, P or B, in the oxide film 37 containing the impurity from penetrating into the gate pattern, and the oxide film 37 containing the impurity, for example, a BPSG film. Is formed at a high temperature of 800 ° C. to 900 ° C. to prevent the gate pattern from moving and being deformed.

As shown in FIG. 6, the entire surface of the first interlayer insulating film is etched to expose an upper surface of the gate pattern.
At this time, when the gate pattern is formed only of the conductive film pattern 25, the conductive film pattern 25, that is, the upper surface of the gate electrode is exposed. On the other hand, when the gate pattern includes the conductive film pattern 25 and the protective film pattern 27, the upper surface of the protective film pattern 27 is exposed. The entire surface is etched by an etch-back process or chemical mechanical polishing (CMP).
nical polishing) process. An etch stop layer 39 and a second interlayer insulating layer 41 are sequentially formed on the entire surface of the semiconductor substrate 21 where the upper surface of the gate pattern is exposed. At this time, it is preferable that the etch stop film 39 is formed of an insulating material having an etch selectivity with respect to the second interlayer insulating film 41, for example, a silicon nitride film. On the other hand, the second interlayer insulating film 41 is preferably formed of a material film having excellent flattening characteristics, for example, a BPSG film flowed at a high temperature of 800 ° C. to 900 ° C. Also, the second
After forming the undoped oxide film, the interlayer insulating film 41 can also be formed by etching the entire undoped oxide film.

As shown in FIG. 7, the second interlayer insulating film 41 is formed.
Is patterned by a normal photo / etching process to expose the etch stop film 39 on the gate pattern. Subsequently, the exposed etch stop layer 39 is etched to form a contact hole H 'exposing a predetermined region of the gate pattern. At this time, when the gate pattern is formed only of the conductive film pattern 25, a predetermined region of the conductive film pattern 25 is exposed by the contact hole H '. On the other hand, when the gate pattern includes the conductive film pattern 25 and the protective film pattern 27, a predetermined region of the protective film pattern 27 is exposed by the contact hole H '. Therefore, the gate pattern is a conductive film pattern 25 and a protective film pattern.
27, the exposed protective film pattern
27 is continuously etched to expose the conductive film pattern 25, that is, a predetermined region of the gate electrode.

On the other hand, if a misalignment occurs during the photographic process for defining the contact hole H ', as shown in FIG. The interlayer insulating film and the spacer 31 are exposed. At this time, the first interlayer insulating film and the spacer 31 are formed of a material film having an etching selectivity with respect to the etching stopper film 39, that is, an oxide film, and are not etched. In addition, even when the spacer 31 is formed of a silicon nitride layer, the spacer 31 may be excessively etched by appropriately adjusting an over-etching time in etching the etch stop layer 39. Can be prevented. As a result, exposure of the source / drain region 34 can be prevented even if a misalignment occurs during a photo process for defining the contact hole H '.

Finally, a conductive film is formed on the entire surface of the semiconductor substrate 21 on which the contact hole H 'is formed, and the conductive film is patterned to form a wiring 43 covering the contact hole H' as shown in FIG. Form. This wiring 43
Is electrically connected to the conductive film pattern 25 through the contact hole H '.

As described above, according to the embodiment of the present invention, after forming the first interlayer insulating film around the gate pattern, the etching prevention film 39 and the second interlayer insulating film 41 are formed on the entire surface, This second interlayer insulating film 41 is etched, followed by an etching stopper film
Since the contact hole H 'is formed by etching the 39, even if a misalignment occurs when the contact hole H' is formed directly on the gate pattern, the source / drain region 34 adjacent to the gate pattern is formed. Can be prevented from being exposed, and the margin for matching against misalignment can be increased. As a result, a short circuit between the source / drain region 34 and the gate pattern (gate electrode) can be prevented, and a contact hole having a diameter larger than the width of the gate electrode can be formed when the width of the gate electrode is extremely narrow. Resistance can be improved. Therefore, a contact hole forming process suitable for a highly integrated semiconductor device requiring a fine line width can be realized.

It should be noted that the present invention is not limited to the above embodiment, and various modifications and improvements are possible.

[0021]

As described above in detail, according to the method for forming a contact hole in a semiconductor device of the present invention, the margin of matching against misalignment in the photolithography process can be increased. Exposure of the source / drain region can be prevented, and short circuit between the source / drain region and the gate electrode can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a conventional method for forming a contact hole.

FIG. 2 is a cross-sectional view for explaining a conventional method of forming a contact hole.

FIG. 3 is a cross-sectional view for describing an embodiment of a method for forming a contact hole in a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view for explaining an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention.

FIG. 5 is a sectional view for explaining an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view for explaining an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view for explaining an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view for explaining an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention.

[Explanation of symbols]

 Reference Signs List 21 semiconductor substrate 23 gate insulating film 25 conductive film pattern 27 protective film pattern 31 spacer 34 source / drain region 35 capping insulating film 37 oxide film 39 etching prevention film 41 second interlayer insulating film H 'contact hole

Claims (18)

[Claims] A step of forming a lower pattern on the semiconductor substrate; and forming a first pattern on an entire surface of the semiconductor substrate on which the lower pattern is formed.
Forming an interlayer insulating film; etching the entire first interlayer insulating film until the upper surface of the lower pattern is exposed; and preventing etching on the entire surface of the semiconductor substrate where the upper surface of the lower pattern is exposed. Forming a film and a second interlayer insulating film sequentially; patterning the second interlayer insulating film to expose an etching stopper on the lower pattern; and forming the exposed etching stopper on the lower pattern. Etching to expose a predetermined region of the lower pattern to form a contact hole. 2. The method according to claim 1, wherein the lower pattern is formed of a conductive film. 3. The contact hole according to claim 2, wherein the conductive film is one selected from a group consisting of a doped polysilicon film, a metal film, and a polycide film. Formation method. 4. The method of claim 1, wherein the lower pattern is a two-layer pattern in which a conductive layer pattern and a protective layer pattern are sequentially stacked. 5. The method according to claim 4, further comprising, after exposing a predetermined region of the lower pattern, exposing the predetermined region of the conductive film pattern by etching the protective film pattern. The method for forming a contact hole of a semiconductor device according to the above. 6. The method according to claim 4, wherein the protection film pattern comprises an insulating film having an etching selectivity with respect to the first interlayer insulating film. 7. The method according to claim 6, wherein the insulator film is one of a silicon nitride film and a silicon oxynitride film. 8. The method as claimed in claim 1, further comprising forming a spacer on a sidewall of the lower pattern. 9. The method as claimed in claim 8, wherein the spacer comprises one of a silicon oxide film and a silicon nitride film. 10. The method as claimed in claim 1, wherein the first interlayer insulating film comprises one of an oxide film containing impurities and an undoped oxide film. 11. The method according to claim 1, wherein the first interlayer insulating film is formed by sequentially stacking a capping insulating film and an oxide film containing impurities. 12. The method as claimed in claim 11, wherein the capping insulating film is one of a plasma oxide film and a high temperature oxide film. 13. The method of claim 1, wherein the etch stop film is an insulator film having an etch selectivity with respect to the second interlayer insulating film. . 14. The method according to claim 13, wherein the insulator film is a silicon nitride film. 15. The semiconductor device according to claim 1, wherein the second interlayer insulating film is made of the same material as the first interlayer insulating film.
3. The method for forming a contact hole in a semiconductor device according to item 1. 16. The method according to claim 16, wherein the lower pattern is a wiring or a MOS.
2. The method according to claim 1, wherein the contact hole is a gate pattern of a transistor. 17. When the lower pattern is a gate pattern of a MOS transistor, a step of forming source / drain regions on the surface of the semiconductor substrate on both sides of the gate pattern after forming the gate pattern is added. The method for forming a contact hole in a semiconductor device according to claim 16. 18. After forming a gate pattern, a spacer is formed on a side wall of the gate pattern, and impurity ions are implanted before and after the spacer to form a source / drain region.
The method according to claim 17, wherein the contact hole is formed in a D structure.