KR20000015140A - Contact hole formation method of semiconductor devices - Google Patents

Abstract

PURPOSE: A method for forming a contact hole is provided to improve a misalignment margin and a contact resistance by using an etching stopping layer. CONSTITUTION: The method comprises the steps of forming a lower wire pattern having a conductive layer (25) and a protection layer (27) on a semiconductor substrate (21); forming a first interlayer insulator having a capping insulator (35) and an oxide (37) on the resultant structure; etching the first interlayer insulator to expose the surface of the protection layer (27); sequentially forming an etch stopping layer (39) and a second interlayer insulator (41), wherein the etching selectivity of the etch stopping layer (39) is higher than that of the second interlayer insulator (41); exposing the etch stopping layer (39) by patterning the second interlayer insulator (41); and etching the exposed etch stopping layer (39), thereby forming a contact hole.

Description

Contact hole formation method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole for use in a semiconductor device.

As the degree of integration of semiconductor devices increases, the size of contact holes is becoming smaller. In general, a method of forming a contact hole includes forming an interlayer insulating film over an entire surface of a semiconductor substrate on which a lower conductive layer is formed and exposing a predetermined region of the lower conductive layer by patterning the interlayer insulating film. The lower conductive layer may be a region doped with impurities or a wiring. The wiring may correspond to the gate electrode of the MOS transistor. In this case, the width of the gate electrode gradually decreases as the degree of integration of the semiconductor device increases. Therefore, there is a problem in that alignment margin is reduced when performing a photolithography process for directly forming a contact hole on a gate electrode used in a highly integrated semiconductor device.

1 and 2 are cross-sectional views illustrating a method of forming a contact hole according to the prior art.

Referring to FIG. 1, a gate insulating film 3 and a gate electrode 5 that are sequentially stacked on a predetermined region of a semiconductor substrate 1 are formed. A low concentration impurity region is formed by implanting impurity ions into the surface of the semiconductor substrate 1 using the gate electrode 5 as an ion implantation mask. An insulating film is formed on the entire surface of the semiconductor substrate on which the low concentration impurity region is formed, and the insulating film is anisotropically etched to form spacers 7 on sidewalls of the gate electrode 5. A high concentration impurity region is formed by implanting impurity ions into the surface of the semiconductor substrate 1 using the spacer 7 and the gate electrode 5 as an ion implantation mask. The low concentration impurity region and the high concentration impurity region constitute a source / drain region 9 of the MOS transistor. An interlayer insulating film 11 is formed on the entire surface of the semiconductor substrate on which the source / drain regions 9 are formed.

Referring to FIG. 2, the interlayer insulating layer 11 is patterned to form a contact hole H exposing the gate electrode 5. In this case, when mis-alignment occurs in the photolithography process for forming the contact hole H, as shown in FIG. 2, the gate electrode 5 and the source / drain region are formed by the contact hole H. (9) is exposed at the same time. Accordingly, when a conductive film (not shown) covering the contact hole H is formed in a subsequent process, the gate electrode 5 and the source / drain region 9 are electrically connected to each other. .

As described above, according to the related art, there is a problem in that the gate electrode and the source / drain regions are electrically connected to each other when a misalignment occurs in the photolithography process for defining the contact hole on the gate electrode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of increasing a process margin for misalignment during a photolithography process.

Another object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent the source / drain region adjacent to the gate electrode from being exposed even when misalignment occurs in the photolithography process for directly forming a contact hole on the gate electrode of the MOS transistor. To provide.

1 and 2 are cross-sectional views illustrating a conventional method for forming a contact hole.

3 to 8 are cross-sectional views illustrating a method for forming a contact hole according to an embodiment of the present invention.

In order to achieve the above object, the present invention forms a lower wiring pattern on the semiconductor substrate and a first interlayer insulating film on the entire surface of the semiconductor substrate on which the lower wiring pattern is formed. The lower wiring pattern is formed of a conductor film, such as a metal film, a doped polysilicon film, or a polyside film. In addition, the lower wiring pattern may be formed as a double layered pattern in which a conductor film pattern and a protective film pattern are sequentially stacked. The protective film pattern may be formed of an insulator film having an etch selectivity with respect to the first interlayer insulating film, such as a silicon nitride film or a silicon oxynitride film. The first interlayer insulating film is formed of an oxide film containing an impurity or an undoped silicate glass (USG). The oxide film containing the impurity is preferably formed of a BPSG film, a PSG film or a BSG film flowed at a high temperature, and the undoped oxide film is preferably formed of a high temperature oxide (HTO). The first interlayer insulating film may be a double dielectric layer in which a capping dielectric layer and an oxide film containing impurities are sequentially stacked. The capping insulation layer may be formed of an undoped oxide layer such as a plasma oxide layer or a high temperature oxide (HTO) layer. The capping insulating layer is intended to prevent a phenomenon in which an impurity in an oxide film containing impurities penetrate into the lower wiring pattern and to prevent the lower wiring pattern from being deformed when the oxide film containing the impurities is flowed at a high temperature. Form. In addition, a spacer may be formed on sidewalls of the lower wiring pattern. In this case, the spacer may be formed of an insulator film having an etch selectivity with respect to the first interlayer insulating film, for example, a silicon nitride film. However, the spacer may be formed of the same material film as the capping insulating film, that is, a silicon oxide film such as a plasma oxide film or a high temperature oxide film.

The first interlayer insulating layer is etched entirely until the lower interconnection pattern is exposed. An etch stopper layer and a second interlayer insulating layer are sequentially formed on the entire surface of the semiconductor substrate to which the lower wiring pattern is exposed. The second interlayer insulating film is formed of an oxide film or an undoped oxide film containing impurities, or is formed of the same material film as the first interlayer insulating film. The etch stop layer is preferably formed of an insulator film having an etch selectivity with respect to the second interlayer insulating film, for example, a silicon nitride film.

The second interlayer insulating layer is patterned by a photo / etch process to expose an etch stop layer on the lower wiring pattern. Subsequently, the exposed etch stop layer is etched to form a contact hole exposing a predetermined region of the lower wiring pattern. In this case, even when misalignment occurs during the photolithography process for patterning the second interlayer insulating layer, the exposed first interlayer insulating layer may provide an etch selectivity with respect to the etch stop layer even if the first interlayer insulating layer around the lower wiring pattern is exposed. Visible and no longer etched. In addition, even when the spacer is formed of the same material layer as the etch stop layer, the semiconductor substrate may not be exposed by appropriately adjusting the overetch time when etching the etch stop layer for forming the contact hole. It is easy. When the lower interconnection pattern includes a conductive layer and a protective layer pattern, the exposed protective layer pattern is continuously etched after the exposed etch stop layer is etched to expose a predetermined region of the conductive layer pattern.

In order to achieve the above another object, the present invention forms a gate insulating film and a gate pattern sequentially stacked on a predetermined region of a semiconductor substrate. The gate pattern may be formed by patterning only a conductive layer, or by sequentially stacking a conductive layer and a protective layer, and then patterning the protective layer and the conductive layer continuously. The conductive film is formed of a doped polysilicon film, a metal film or a polyside film, and the protective film pattern is formed of an insulator film having an etching selectivity with respect to the first interlayer insulating film formed in a subsequent process. For example, the passivation layer pattern may be formed of a silicon nitride layer or a silicon oxynitride layer having an etching selectivity with respect to the first interlayer insulating layer formed of an oxide layer. Spacers are formed on sidewalls of the gate pattern. The spacer may be formed of a material film having an etching selectivity with respect to the passivation layer pattern, for example, a plasma oxide layer or a high temperature oxide layer (HTO), or may be formed of the same material layer as the passivation layer pattern. Source / drain regions are formed on the surface of the semiconductor substrate on both sides of the gate pattern. The source / drain region may include a lightly doped drain region (LDD). A first interlayer insulating film is formed on the entire surface of the semiconductor substrate on which the spacers and the source / drain regions are formed. The first interlayer insulating film is formed of an oxide film containing an impurity such as a BPSG film flowed at a high temperature, or a planarized undoped silicate glass (USG). The first interlayer insulating film may be a double dielectric layer in which a capping dielectric layer and an oxide film containing impurities are sequentially stacked. The capping insulation layer may be formed of an undoped oxide layer, for example, a plasma oxide layer or a high temperature oxide layer. The capping insulating layer may be configured to prevent the impurities in the oxide film containing impurities from penetrating into the conductive film pattern constituting the gate pattern and to prevent the gate pattern from moving and deforming when the BPSG film flows at a high temperature. Form for the purpose.

The first interlayer insulating layer is etched to expose the gate pattern. In this case, when the gate pattern includes a conductive layer pattern and a protective layer pattern, the protective layer pattern is exposed. An etch stop layer and a second interlayer insulating layer are sequentially formed on the entire surface of the semiconductor substrate to which the gate pattern is exposed. The etch stop layer may be formed of the same material layer as the passivation layer pattern, that is, a silicon nitride layer. The second interlayer insulating film is formed of the same material film as the first interlayer insulating film.

The second interlayer insulating layer is patterned by a photo / etch process to expose the etch stop layer on the gate pattern. Subsequently, the exposed etch stop layer is etched to form a contact hole exposing a predetermined region of the gate pattern. In this case, when the gate pattern includes a conductive layer pattern and a protective layer pattern, the exposed protective layer pattern is continuously etched after the exposed etch stop layer is etched to expose a predetermined region of the conductive layer pattern. Here, when misalignment occurs in the photolithography process for patterning the second interlayer insulating film, the first interlayer insulating film and the spacer around the conductive film pattern are simultaneously exposed. However, since the first interlayer insulating layer has a high etching selectivity with respect to the etch stop layer and the passivation layer pattern, the first interlayer insulating layer is not etched anymore. Therefore, even if misalignment occurs during the photolithography process for defining the contact hole, the source / drain regions adjacent to both sides of the gate pattern may be prevented from being exposed. In addition, when the spacer is formed of the same material film as the etch stop layer, the excessive etching time may be appropriately adjusted during the process of etching the etch stop layer, thereby preventing excessive etching of the spacer. Accordingly, even when misalignment occurs during the photolithography process of defining the contact hole, the source / drain region under the spacer may be exposed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, although the drawings introduced are examples of directly forming a contact hole on a gate electrode of a MOS transistor, the present invention may be applied to a case of forming a contact hole on a general wiring. In particular, the present invention is very effective in forming contact holes directly on the gate electrodes of short channel MOS transistors suitable for highly integrated semiconductor devices.

Referring to FIG. 3, a gate insulating film 23 is formed on a semiconductor substrate 21, and a conductor film and a protection layer are sequentially formed on the gate insulating film 23. The protective film and the conductive film are successively patterned to form a conductive film pattern 25 and a protective film pattern 27 that are sequentially stacked on a predetermined region of the gate insulating film 23. Here, the conductive layer pattern 25 serves as a gate electrode, and the conductive layer pattern 25 and the passivation layer pattern 27 constitute a gate pattern. The gate pattern may be formed of only the conductive layer pattern 25. However, in order to form a MOS transistor having a short channel suitable for a highly integrated semiconductor device, a fine gate electrode having a line width of 0.5 μm or less should be formed. Accordingly, an anti-reflective layer is widely used to reduce diffuse reflection in a photolithography process for patterning a fine gate electrode. As a result, the protective film is preferably formed of a material film, such as a silicon nitride film or a silicon oxynitride film, which serves as an antireflection film and has an etching selectivity with respect to the first interlayer insulating film formed in a subsequent process. The conductive film is formed of a doped polysilicon film, a metal film or a polyside film containing a refractory metal. Subsequently, lightly doped drain 29 (LDD) is formed on the surface of the semiconductor substrate 21 on both sides of the gate pattern by implanting impurity ions different from the semiconductor substrate 21 using the gate pattern as an ion implantation mask. Form an area.

Referring to FIG. 4, an insulator film for a spacer, such as a silicon oxide film or a silicon nitride film, is formed on the entire surface of the semiconductor substrate on which the LED region 29 is formed. The spacer insulator layer is anisotropically etched to form spacers 31 on the sidewalls of the gate pattern. By using the spacer 31 and the gate pattern as an ion implantation mask, implanting impurity ions of the semiconductor substrate 21 and other conductivity types into a higher dose than the LED region 29 to induce semiconductors on both sides of the gate pattern. A high concentration impurity region 34 is formed on the surface of the substrate 21. At this time, the LED region 23 remains under the spacer 31. The LED region 23 and the high concentration impurity region 34 constitute a source / drain region 34.

Referring to FIG. 5, a first interlayer insulating film is formed on an entire surface of the semiconductor substrate on which the source / drain regions 34 are formed. The first interlayer insulating film is preferably formed by laminating a capping insulating film 35 and an oxide film 37 containing impurities in sequence. The undoped oxide film may be formed instead of the oxide film 37 containing the impurity. In addition, the first interlayer insulating film may be formed of only an oxide film 37 or an undoped silicate glass containing impurities. The oxide film containing the impurity is formed by flowing a BPSG film, a BSG film or a BPSG film at a high temperature. The capping insulating layer 35 may be formed of a plasma oxide film or a high temperature oxide (HTO). The capping insulating layer 35 prevents impurities in the oxide film containing impurities, that is, phosphorus (P) or boron (B) from penetrating into the gate pattern, and forms an oxide film containing the impurities, such as a BPSG film, in 800. It is formed to prevent the phenomenon that the gate pattern is moved and deformed when flowing at a high temperature of ℃ to 900 ℃.

Referring to FIG. 6, an upper surface of the gate pattern is exposed by etching the entire first interlayer insulating layer. In this case, when the gate pattern is formed of only the conductive layer 25, the conductive layer pattern 25, that is, the upper surface of the gate electrode is exposed, and the gate pattern is formed of the conductive layer pattern 25 and the passivation layer pattern 27. In this case, the upper surface of the protective layer pattern 27 is exposed. The front surface etching may be performed by an etch-back process or a chemical mechanical polishing (CMP) process. An etch stop layer 39 and a second interlayer dielectric layer 41 are sequentially formed on the entire surface of the semiconductor substrate where the top surface of the gate pattern is exposed. The etch stop layer 39 may be formed of a material layer having an etch selectivity with respect to the second interlayer insulating layer 41, for example, a silicon nitride layer. The second interlayer insulating film 41 may be formed of a material film having excellent planarization characteristics, for example, a BPSG film flowed at a high temperature of 800 ° C to 900 ° C. In addition, the second interlayer insulating layer 41 may be formed by etching the entire undoped oxide layer after forming the undoped oxide layer.

Referring to FIG. 7, the second interlayer insulating layer 41 is patterned by a conventional photo / etch process to expose the etch stop layer 39 on the gate pattern. Subsequently, the exposed etch stop layer 39 is etched to form a contact hole H 'exposing a predetermined region of the gate pattern. In this case, when the gate pattern is formed of only the conductive layer pattern 25, a predetermined region of the conductive layer pattern 25 is exposed by the contact hole H ′, and the gate pattern is formed of the conductive layer pattern 25 and the passivation layer. When the pattern 27 is formed, a predetermined region of the passivation layer pattern 27 is exposed by the contact hole H '. Therefore, when the gate pattern includes the conductive layer pattern 25 and the protective layer pattern 27, the exposed protective layer pattern 27 is continuously etched to expose the conductive layer pattern 25, that is, a predetermined region of the gate electrode. Let's do it.

On the other hand, if misalignment occurs during the photolithography process for defining the contact hole H ', the first interlayer around the gate pattern after etching the etch stop layer 39 as shown in FIG. The insulating film and the spacer 31 are exposed. In this case, the first interlayer insulating layer and the spacer 31 are formed of a material layer having an etch selectivity with respect to the etch stop layer 39, that is, an oxide layer, and are not etched anymore. In addition, even when the spacer 31 is formed of a silicon nitride film, the spacer 31 is prevented from being excessively etched by appropriately adjusting an overetch time in the etching of the etch stop layer 39. Is easy. As a result, even if misalignment occurs during the photolithography process for defining the contact hole H ', the source / drain region 34 may be prevented from being exposed.

Referring to FIG. 8, a conductive film is formed on the entire surface of the semiconductor substrate on which the contact hole H 'is formed, and the conductive film is patterned to form a wiring 43 covering the contact hole H'. The wiring 43 is electrically connected to the conductive film pattern 25 through the contact hole H '.

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

According to the embodiment of the present invention described above, even when misalignment occurs when forming a contact hole directly on the gate electrode, it is possible to prevent the source / drain region adjacent to the gate electrode from being exposed. Therefore, the process margin for misalignment can be improved. In addition, when the width of the gate electrode is very narrow, it is possible to form a contact hole having a diameter larger than the width of the gate electrode, thereby improving contact resistance regardless of misalignment. Therefore, a contact process suitable for a highly integrated semiconductor device requiring a fine line width can be realized.

Claims (16)

Forming a lower wiring pattern on the semiconductor substrate; Forming a first interlayer insulating film on an entire surface of the semiconductor substrate on which the lower wiring pattern is formed; Etching the entire surface of the first interlayer insulating layer until the upper surface of the lower wiring pattern is exposed; Sequentially forming an etch stop layer and a second interlayer insulating layer on the entire surface of the semiconductor substrate where the upper surface of the lower wiring pattern is exposed; Patterning the second interlayer insulating layer to expose an etch stop layer on the lower interconnection pattern; And And etching the exposed etch stop layer to expose a predetermined region of the lower interconnection pattern. The method of claim 1, wherein the lower wiring pattern is formed of a conductive film. 3. The method of claim 2, wherein the conductive film is any one selected from a doped polysilicon film, a metal film, and a polyside film. The method of claim 1, wherein the lower wiring pattern is a double layered pattern in which a conductive layer pattern and a protective layer pattern are sequentially stacked. The method of claim 4, wherein after exposing a predetermined area of the lower wiring pattern, And etching the passivation layer pattern to expose a predetermined region of the conductive layer pattern. 5. The method of claim 4, wherein the conductive film is any one group consisting of a metal film, a doped polysilicon film, and a polyside film. The method of claim 4, wherein the protective layer pattern is formed of an insulator film having an etch selectivity with respect to the first interlayer insulating layer. 8. The method of claim 7, wherein the insulator film is any one of a silicon nitride film and a silicon oxynitride layer. The method of claim 1, further comprising forming spacers on sidewalls of the lower wiring pattern. 10. The method of claim 9, wherein the spacer is formed of any one of a silicon oxide film and a silicon nitride film. 2. The method of claim 1, wherein the first interlayer insulating film is formed of any one of an oxide film and an undoped oxide film containing impurities. The method of claim 1, wherein the first interlayer insulating film is formed by sequentially stacking a capping insulating film and an oxide film containing impurities. The method of claim 12, wherein the capping insulating layer is any one of a plasma oxide film and a high temperature oxide film. The method of claim 1, wherein the etch stop layer is an insulator film having an etch selectivity with respect to the second interlayer insulating film. 15. The method of claim 14, wherein the insulator film having an etch selectivity with respect to the second interlayer insulating film is a silicon nitride film. The method of claim 1, wherein the second interlayer dielectric layer is formed of the same material layer as the first interlayer dielectric layer.