JPS59169151A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of wirings in a through hole by accelerating the etching velocity of an insulating film of upper layer faster than that of an insulating film of lower layer, and etching the film, thereby eliminating an ultrafine groove in a hole. CONSTITUTION:An oxidized silicon film 14 is formed as the first insulating film between aluminum wiring patterns 13, a nitrided silicon film 15 is formed as the second insulating film, and an oxidized silicon film 16 is formed as the third insulating film. With photoresist 17 as a mask it is etched under the etching velocity of the film 16 faster than that of the film 15 until the surface of the film 15 is exposed by a reactive ion etching method, and the film 15 is etched under the condition faster than the film 14. Then, a fine and deep groove is not produced in the hole. The resist 17 is removed, and aluminum wiring pattern 18 is formed. The coating property in the hole is very good, and the disconnection does not occur, and the reliability of the element can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a wiring pattern without disconnection.

[Prior art and its problems]

Conventionally, as shown in FIG. 1, a processing method for creating an opening (through hole) in an insulating film between wiring layers for interconnection between wirings has been used to form an opening in an insulating film 4 deposited on an aluminum wiring 3, for example. When forming the opening, the opening is displaced from the aluminum wiring 3 due to a shift in the mask pattern, so a narrow and deep groove is formed in the insulating film 4 at the end of the opening for over-etching when forming the opening. Because of this groove, when the second aluminum wiring layer 5 is formed, its shape becomes thinner on one side wall of the opening as shown in FIG. This results in a decrease in yield and reliability.

In order to prevent this wiring breakage, it is necessary to take into consideration misalignment of patterns when forming a mask pattern corresponding to the opening, and to make the wiring width larger than the dimension of the opening. However, in this case, the wiring width becomes large, so that the degree of integration is initially reduced.

[Purpose of the invention]

The object of the present invention is to
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent wiring breakage in through holes and improve device reliability.

[Summary of the invention]

The feature of the present invention for achieving the above object is that after only the recesses between the wiring conductors are filled with the first insulating film, a second insulating film is placed on top of the first insulating film.
and a third insulating film, and when etching the opening, use an etching method in which the etching rate of the upper insulating film is faster than the etching rate of the -F layer insulating film,
The third and second insulating films are etched so that no fine grooves are formed in the openings.

〔Effect of the invention〕

According to the present invention, even if there is a misalignment of the mask pattern when etching the opening, fine grooves in the insulating film are not formed in the opening, so the second layer wiring can be disconnected at the opening.
i can be prevented and device reliability can be improved. Also 1
Since there is no need to increase the wiring width of each layer, there is no reduction in the degree of integration, and this method is extremely effective for forming through holes in the formation of multilayer wiring in high-density integrated circuits.

[Embodiments of the invention]

FIGS. 2(a) to 2(f) are process cross-sectional views showing −≠embodiments of the present invention. First, as shown in (a), after depositing, for example, a silicon oxide film 12 as an insulating film on a silicon substrate 11 on which an element is formed, necessary connection holes are opened, and the silicon oxide film including the holes is formed. A first wiring conductor is formed on 12 by, for example, magnetron sputtering to a thickness of ~0.8 μm.
After depositing an aluminum film of A silicon oxide film 14 is formed as a first insulating film on the entire surface including the surface of 13 by plasma vapor deposition using, for example, SiH4 and N20 gas at a temperature of ~300°C.
A thickness of 0.8 μm is formed.

Next, a method for planarizing the insulating layer using the reactive ion etching method previously proposed by the present inventors (1986-130) was proposed.
The silicon oxide film 14 is planarized using a silicon oxide film (No. 754, t￥f Application No. 55-150179). That is, a silicon nitride film is formed on the silicon oxide film 14, and a silicon nitride film is formed on the silicon oxide film 14.
Utilizing the flattening phenomenon when etching a silicon nitride film by the reactive ion etching method using 4 and Hz, the silicon oxide film 14 is flattened, and the upper surface of the aluminum wiring layer 13 is oxidized. (b) shows the state in which this etching has proceeded in the trench where the silicon film 14 is removed.

Next, as a second insulating film, silicon nitride @ 15f~0.2 μm (7) W is formed at a temperature of ~300°C by plasma vapor deposition using, for example, 8 iH4 and NHa gas, and then a As the third insulating film, for example, a silicon oxide film 16 formed by plasma vapor deposition using SiH4 and N20 gas, similar to the first insulating film, is
After forming the silicon oxide film 16 to a thickness of 8 μm, for example, a photoresist [7] is applied as a mask on the silicon oxide film 16, and buttering is performed to form the etching mask (C).
). In (C), one of the openings in the mask pattern has the same dimension as the wiring width of the aluminum pattern 13, but due to misalignment of the patterns, the state shown in (C) is obtained.

Next, as shown in (d), using the photoresist 17 as a mask, the silicon oxide film 1 in the opening is etched by reactive ion etching using, for example, a mixed gas of CF4 and Hz.
6 is etched in a trench where the surface of the underlying silicon nitride film 15 is exposed under conditions such that the etching rate of the silicon oxide film 16 is faster than the etching rate of the silicon nitride film 15. For example, if the CF4 flow rate is 24 cc/min, H
2 Flow rate: 15 cc/min, pressure: 1.33 Pa,
When the high frequency power is 150 W, the etching rate of the silicon nitride film is slower at ~20 A/min while the etching rate of the silicon oxide film is ~4oo5.7m1n, so after the surface of the silicon nitride film 150 is exposed, Since etching hardly progresses, the result is as shown in (d). - Next, as shown in (e), as before, the silicon nitride film 15 in the opening is etched using the photoresist 17 as a mask, using a reactive ion etching method using a mixed gas of CF4 and H2, for example. The silicon nitride film 1 is removed until the surface of the aluminum wiring pattern 130 is exposed.
Etching is performed under the conditions that the etching rate of No. 5 is faster than the etching rate of the silicon oxide film 14. For example, the CF4 flow rate is 24 cc/in, the H2 flow rate is 3 cc
/1 nin, pressure 1.33 Pa, high frequency power 15
When set to 0W, the etching rate of the silicon nitride film is ~
The etching rate of the silicon oxide film is as slow as ~450 A/min for 1000^/ml n, and since aluminum is not etched at all, the silicon oxide film is etched at the opening after the surface of the aluminum wiring pattern 13 is exposed. The film 14 is hardly etched, and as shown in FIG. Thin and deep grooves as shown in Figure 2 do not occur.

Next, after removing the photoresist 17, an aluminum film with a thickness of 1 μm to 1 μm is deposited as a second wiring conductor by, for example, magnetron sputtering, and an etching mask is formed to form, for example, CC4' 4 and C12. (f) shows the aluminum wiring pattern 18 formed by the reactive ion etching method using a mixed gas. As can be seen from (f), the thus formed aluminum wiring pattern 18 has very good coverage at the opening provided for connection with the aluminum wiring pattern 13, which is the first wiring conductor. There is no disconnection at the opening,
It was found that device reliability was improved.

[Other Embodiments of the Invention] In the above embodiments, silicon nitride is used as a method of filling the recesses of the first aluminum wiring pattern y and exposing the upper surface of the aluminum pattern to form the first insulating film. Although we have described the case where the flattening effect of the film is utilized by reactive ion etching, for example, it is also possible to apply an organic film such as a resist, organosilicate glass, or polymer resin film on the first insulating film. After smoothing the surface of the first insulating film, the first insulating film is etched using an etching method that makes the etching rate of the first insulating film and the organic film almost equal.
The surface of the insulating film may be removed by etching. Also, the first
Alternatively, a polyimide resin film, which is a fluid polymer film, may be used as the insulating film, and the entire flat surface thereof may be etched to expose the surface of the aluminum wiring pattern.

Further, in this embodiment, a case has been described in which a silicon oxide film is used as the first and third insulating films, and a silicon nitride film is used as the second insulating film. That is, in this case, there is an advantage that the capacitance between wirings can be lowered by reducing the thickness of the second insulating film.゛However, first. Second. The types and combinations of the third insulating film are not limited to the embodiments, but the present invention can be achieved by sequentially using an etching method in which the etching rate of the upper insulating film is faster than the etching rate of the lower insulating film. is effective, so it can be seen that the type and combination of insulating films can be arbitrarily selected depending on the etching method, etching gas, and etching conditions. In addition to the mixed gas of CF4 and H2, as the reactive gas for the reactive ion etching method,
A mixed gas of C2F6, CaFs, CF3Br, etc. and H2 can be used, and CHI can be used instead of H2.
``3 may be used.

Further, in this embodiment, an aluminum film is used as the wiring conductor, but it may also be a film of Mo, W, Pt, or a silicide alloy thereof.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device manufactured by a conventional manufacturing method, and FIGS. 2(a) to 2(f) are process sectional views showing an embodiment of the present invention. 1.11... Silicon substrate, 2.12... Seven silicon oxide film, 3.13... First wiring conductor (aluminum film), 4... Insulating film, 5, 18...・Second wiring conductor (aluminum film), 14...first insulating film (silicon oxide film), 15...second insulating film (silicone oxide film), 16...third insulating film Film (silicon oxide film), 1
7...Photoresist. Agent Patent attorney Kensuke Chika (and 1 other person)
Figure 1) Figure 2 (α) CI/) + Lt) View 2 Air (e)

Claims (3)

[Claims] (1) forming a first insulating film on the semiconductor substrate on which the first wiring conductor is formed, filling the recess of the first wiring conductor and exposing the upper surface of the first wiring conductor; After forming a second insulating film on this entire surface and further forming a third insulating film on this second insulating film, and selectively forming a mask on this third insulating film, etching the third insulating film using an etching method in which the etching rate of the third insulating film is faster than the etching rate of the second insulating film; etching the second insulating film using an etching method faster than the etching rate of the insulating film to form a connection window in a predetermined region, removing the mask, and then forming a second wiring conductor. A method of manufacturing a semiconductor device, comprising: (2) The semiconductor device according to claim 1, wherein a silicon oxide film is used as the first and third insulating films, and a silicon nitride film is used as the second insulating film. manufacturing method. (3) An etching method in which the etching rate of the third insulating film is faster than the etching rate of the second insulating film, and the etching rate of the second insulating film is faster than the etching rate of the first insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a reactive ion etching method is used as the fast etching method.