JP3781136B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly to a structure of a semiconductor device in which a through hole opened on a source / drain diffusion layer of a MOS transistor is formed in a gate electrode in a self-aligned manner and a manufacturing method thereof.
[0002]
[Prior art]
As LSIs become larger, device miniaturization is being pursued. In order to realize a semiconductor integrated circuit having gates, wirings, and through holes with finer dimensions, conventionally, the exposure wavelength in photolithography has been shortened to improve the resolution.
[0003]
Various device structures that reduce the alignment margin between lithography processes while reducing the minimum resolution size in this way have been studied, and the device size itself can be reduced without reducing the pattern size to be transferred. Has been tried. An example of such a device structure is self-aligned contact (hereinafter referred to as SAC).
[0004]
    Hereinafter, a conventional SAC will be described with reference to FIG.
  An element isolation film 12 that defines element regions 14 and 16 is formed on the silicon substrate 10. A gate electrode 26 is formed on the silicon substrate 10 in the element regions 14 and 16 via a gate oxide film 18. The gate electrode 26 has its sidewall and upper surface covered with an etching stopper film 36 made of a silicon nitride film.Here, the etching stopper film refers to an insulating film that stops etching of the insulating film formed thereon.Source / drain diffusion layers 28 are formed in the element regions 14 and 16 on both sides of the gate electrode 26. Thus, a MOS transistor composed of the gate electrode 26 and the source / drain diffusion layer 28 is formed.
[0005]
On the silicon substrate 10 on which the MOS transistor is formed, an interlayer insulating film 38 made of, for example, a BPSG (Boro-Phospho-Silicate Glass) film is formed. In the interlayer insulating film 38, through holes 42, 44, 48 opened on the source / drain diffusion layer 28 and a through hole 46 opened on the gate electrode 26 are formed. Among these, the through holes 42 and 44 are so-called SACs.
[0006]
Hereinafter, a method for forming a through hole by SAC will be described with reference to FIG.
After forming a MOS transistor having the gate electrode 26 covered with the etching stopper film 36 on the silicon substrate 10, an interlayer insulating film 38 made of a BPSG film is formed.
[0007]
Next, a resist pattern 40 having a through hole pattern to be opened is formed on the source / drain diffusion layer 28, and the interlayer insulating film 38 is etched using the resist pattern 40 as a mask.
At this time, the gate electrode 26 covered with the etching stopper film 36 exists in the region where the through holes 42 and 44 are formed. However, as a condition for etching the interlayer insulating film 38, the selection ratio is sufficient with respect to the silicon nitride film. If a large condition is used, the etching stopper film 36 is hardly etched, and the through holes 42 and 44 can be opened up to the source / drain diffusion layer 28 (FIG. 17A).
[0008]
Thus, since the through holes 42 and 44 opened on the source / drain diffusion layer 28 are formed in alignment with the position of the etching stopper film 36, these through holes are called SAC.
By using such a SAC structure, the pattern of the through holes 42 and 44 can be arranged so as to overlap the region where the gate electrode 26 is formed. Even if the opening position of the through hole is slightly shifted, the through hole can be opened in alignment with the etching stopper film, so that the alignment accuracy can be relaxed.
[0009]
Thus, a highly integrated semiconductor device using SAC has been manufactured.
[0010]
[Problems to be solved by the invention]
However, in the above-described conventional method of manufacturing a semiconductor device using SAC, the through hole 46 opened on the gate electrode 26 cannot be opened simultaneously with the through holes 42, 44, and 48.
In the conventional SAC method, a through-hole is formed by self-alignment using a silicon nitride film covering the periphery of the gate electrode 26 as an etching stopper film 36. Therefore, when trying to open the through-holes 42, 44, 46, 48 simultaneously, This is because the etching stopper film 36 covering the gate electrode 26 remains in the through hole 46 even after the through holes 42, 44, and 48 where the drain diffusion layer 28 is exposed are opened.
[0011]
Therefore, in order to open the through hole 46 on the gate electrode 26, it is necessary to remove the etching stopper film 36 separately. For example, as shown in FIG. 17B, the through hole 46 opened on the gate electrode 26 is formed. It was necessary to form a through hole 46 by adding one additional lithography process.
An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, in which a through hole opening on a gate electrode can be formed simultaneously with SAC without complicating the manufacturing process.
[0012]
[Means for Solving the Problems]
  The above object is formed on a semiconductor substrate and the semiconductor substrate.The firstElement areaAnd second element regionAn element isolation film definingFirstFormed in the element regionSource and drainA diffusion layer;Source and drainOn the semiconductor substrate between the diffusion layers, the firstGateFormed through an insulating filmFirstA gate electrode;FirstA side wall of the gate electrode;FirstThe distance from the gate electrode edge to the inside at an equal distanceFirstCovers the area on the top surface of the gate electrodeFirstEtching stopper film andA second gate electrode formed on the second element region via a second gate insulating film and extending to the element isolation film; a sidewall of the second gate electrode; A second etching stopper film covering a region of the upper surface of the second gate electrode from the periphery of the second gate electrode to the inner side of the same distance, and the first etching stopper film in a region where the first etching stopper film is not formed It is formed on the second gate electrode on the gate electrode and in the region where the second etching stopper film is not formed, and has different etching characteristics from the first etching stopper film and the second etching stopper film. A first insulating film formed on the entire surface of the semiconductor substrate on which the first etching stopper film and the second etching stopper film are formed; The topper film and the second etching stopper film have an interlayer insulating film having different etching characteristics, a pair of first through holes are formed in the interlayer insulating film on the source and drain diffusion layers, and the element A second through hole is formed in the first insulating film and the interlayer insulating film on the second gate electrode in a region on the separation film where the second etching stopper film is not formed.This is achieved by a semiconductor device. By configuring the semiconductor device in this way,The first through hole and the second through hole can be formed by only one lithography process. Thereby, compared with the conventional SAC process, the number of lithography processes can be reduced by one.
[0015]
  In the above semiconductor device, the element isolation film isFirstEtching stopper filmAnd the second etching stopper filmIt is desirable to be made of the same material. By configuring the semiconductor device in this manner, the through hole can be opened without being etched even when the through hole extends on the element isolation film. Therefore, the through hole can be formed in the etching stopper film and the element isolation film by self-alignment.
[0016]
  In the above semiconductor device, the element isolation filmThe first 1 Etching stopper filmAnd saidSecondThe etching stopper film is preferably composed of a silicon nitride film.
  Also,The above purpose isA plurality of word lines extending parallel to the first direction, a plurality of bit lines extending parallel to the second direction intersecting the first direction, and each intersection of the word line and the bit line In a semiconductor device in which a memory cell provided in a region is formed over a semiconductor substrate, the memory cell is formed over the semiconductor substrate,FirstElement areaAnd second element regionAn element isolation film definingFirstFormed in the element regionSource and drainA diffusion layer;Source and drainOn the semiconductor substrate between the diffusion layers,FirstGateIt is formed through an insulating film and doubles as the word lineFirstA gate electrode;FirstA side wall of the gate electrode;FirstThe distance from the gate electrode edge to the inside at an equal distanceFirstCovers the area on the top surface of the gate electrodeFirstEtching stopper film andA second gate electrode formed on the second element region via a second gate insulating film and extending to the element isolation film; and a sidewall of the second gate electrode; , A second etching stopper film covering a region of the upper surface of the second gate electrode from the periphery of the second gate electrode to the inner side of the same distance, and the region of the region where the first etching stopper film is not formed Formed on the first gate electrode and on the second gate electrode in a region where the second etching stopper film is not formed, and is etched with the first etching stopper film and the second etching stopper film Formed on the entire surface of the semiconductor substrate on which the first insulating film having different characteristics, the first etching stopper film, and the second etching stopper film are formed; And an interlayer insulating film having different etching characteristics from the second etching stopper film, and a pair of first through holes are formed in the interlayer insulating film on the source and drain diffusion layers, A second through hole is formed in the first insulating film and the interlayer insulating film on the second gate electrode in a region on the separation film where the second etching stopper film is not formed.This is also achieved by a semiconductor device characterized by the above. By configuring the semiconductor device in this way,The first through hole and the second through hole can be formed by only one lithography process. Thereby, compared with the conventional SAC process, the number of lithography processes can be reduced by one.
[0017]
  In the above semiconductor device,The first gate electrode is formed extending on the element isolation film,Formed on the element region.FirstThe gate electrode has a line width that is formed on the device isolation film.FirstIt is desirable that the width is wider than the line width of the gate electrode.
  Further, in the above semiconductor device, on the element isolation filmOn the first gate electrodeFormed in the aboveFirstThe etching stopper film isFirstIt is desirable to have a region covering the entire surface of the gate electrode. By configuring the semiconductor device in this manner, a through hole extending in a wide region including the gate electrode in that region can be opened. Thereby, for example, if the capacitor storage electrode is formed using the inner wall of the through hole, the capacitor area can be easily expanded.
[0018]
  Also,The above purpose isOn the semiconductor substrate,FirstElement areaAnd second element regionForming an isolation film for definingWorkAboutOf the semiconductor substrateSaidFirstelementOn areaFirstGateInsulating film is formedAnd forming a second gate insulating film on the second element region of the semiconductor substrate.YouWorkAboutA conductive film, a first insulating film, and a first insulating film are formed on the entire surface of the semiconductor substrate on which the first gate insulating film, the second gate insulating film, and the element isolation film are formed. Forming a second insulating film having different etching characteristics, processing the second insulating film, the first insulating film and the conductive film into the same pattern, and comprising the conductive film,The firstGateOn insulating filmFormed firstGate electrodeAnd a second gate electrode made of the conductive film, formed on the second gate insulating film and extending to the element isolation film,Forming a step;Forming a source and drain diffusion layer in the element region on both sides of the first gate electrode; and isotropically etching the first insulating film using the second insulating film as a mask; The step of retracting the first insulating film by an equal distance in the horizontal direction and the second insulating film have the same etching characteristics as the second insulating film so that the void formed by etching the first insulating film is buried. A step of depositing a third insulating film having an etching characteristic different from that of the first insulating film on the entire surface, and the second insulating film and the third insulating film in a vertical direction until the first insulating film is exposed. Etching into the third insulating film,SaidFirstA side wall of the gate electrode;FirstFrom the periphery of the gate electrodeSaidThe same distance to the insideFirstCovers the area on the top surface of the gate electrodeFirstEtching stopper filmAnd a second insulating layer that covers a side wall of the second gate electrode and a region of the upper surface of the second gate electrode from the periphery of the second gate electrode to the inside of the same distance. Etching stopper film andFormWorkAbout the aboveFirstEtching stopper filmAnd the second etching stopper filmOn the semiconductor substrate formed withThe whole surfaceAnd saidFirstEtching stopper filmAnd the second etching stopper filmEtching characteristics are different fromInterlayerForm an insulating filmWorkAbout the aboveInterlayerInsulating filmThe source and drain diffusion layers are formedTo be exposedA pair ofA first through hole;Formed on the first insulating film and the interlayer insulating film, on the element isolation film;SaidSecondThe region where the etching stopper film is not formedSecondOpen a second through hole that exposes the gate electrode at the same timeWorkIt is also achieved by a method of manufacturing a semiconductor device characterized by having By manufacturing the semiconductor device in this manner, the first through hole opened on the element region and the second through hole opened on the gate electrode can be formed by one lithography process. As a result, the number of lithography steps can be reduced by one compared with the conventional manufacturing process.
[0019]
  Further, in the above method for manufacturing a semiconductor device,In the step of forming the pair of first through holes and the second through holes, the etching of the first insulating film includes the element isolation film, the first etching stopper film, and the second etching stopper. It is desirable to carry out under conditions where the etching rate is higher than that of the film. By manufacturing the semiconductor device in this manner, the etching stopper film can be formed while suppressing the wear of the element isolation film and the second insulating film.
  Further, the object is to form a device isolation film for defining a first device region and a second device region on a semiconductor substrate, and a first gate on the first device region of the semiconductor substrate. Forming an insulating film and forming a second gate insulating film on the second element region of the semiconductor substrate; the first gate insulating film; the second gate insulating film; and the element isolation film. A step of forming a conductive film on the entire surface of the semiconductor substrate on which the film is formed, a step of depositing and patterning a first insulating film on the conductive film, and a step of forming the first insulating film. A second insulating film having a different etching characteristic from that of the first insulating film is deposited on the conductive film, etched in a vertical direction, and patterned on the side wall of the patterned first insulating film. Forming a first sidewall comprising: The conductive film is etched using the first insulating film and the first sidewall as a mask, the first gate electrode made of the conductive film and formed on the first gate insulating film, and the conductive film Forming a second gate electrode made of a film and formed on the second gate insulating film and extending to the element isolation film; and the element region on both sides of the first gate electrode Forming a source and drain diffusion layer therein, and on the semiconductor substrate on which the first insulating film and the first sidewall are formed, the second insulating film has the same etching characteristics as the second insulating film. A third insulating film having an etching characteristic different from that of the first insulating film is deposited and etched in a vertical direction, and the first gate electrode, the second gate electrode, and the first sidewall are side walls of the first insulating film. 3 Insulating film A second side wall formed of the first side wall and the second side wall, the side wall of the first gate electrode and the inner periphery of the first gate electrode from the periphery of the first gate electrode by an equal distance. A first etching stopper film covering a region of the upper surface of the first gate electrode; the first sidewall; and the second sidewall; a sidewall of the second gate electrode; A step of forming a second etching stopper film covering a region of the upper surface of the second gate electrode from the periphery of the gate electrode to an equal distance inside, and the first etching stopper film and the second etching stopper film On the entire surface of the formed semiconductor substrate, an interlayer insulation having different etching characteristics from the first etching stopper film and the second etching stopper film. Forming an edge film; a pair of first through holes formed in the interlayer insulating film, exposing the source and drain diffusion layers; and formed in the first insulating film and the interlayer insulating film, And a step of simultaneously opening a second through hole that exposes the second gate electrode in a region where the second etching stopper film is not formed on the element isolation film. This method can also be achieved. By manufacturing the semiconductor device in this manner, the first through hole opened on the element region and the second through hole opened on the gate electrode can be formed by one lithography process. As a result, the number of lithography processes can be reduced by one compared with the conventional manufacturing process.
[0020]
  In the method of manufacturing a semiconductor device,A pair of firstThrough holeAnd the second through holeThe openingDoIn the processFor the pair of first through holes,SaidFirstUsing the etching stopper film as an etching stopperInterlayerEtching insulation filmByThe aboveFirstShaped to match the etching stopper filmCompleteIt is desirable. By manufacturing the semiconductor device in this manner, a normal SAC technique can be used for opening the first through hole.
[0021]
  In the method of manufacturing a semiconductor device, the element isolationForm a filmIn the process,1Etching characteristics are different from other insulating filmsmaterialForming the element isolation film comprising:A pair of firstThrough holeAnd the second through holeThe openingDoIn the processOf the pair of first through holes, the first through hole that is in contact with the element isolation film,SaidFirstThe etching stopper film and the element isolation film as an etching stopperInterlayerEtching insulation filmByThe aboveFirstAligned with the etching stopper film and the element isolation filmCompleteIt is desirable. By manufacturing the semiconductor device in this manner, the first through hole can be opened without etching the element isolation film. As a result, the first through-hole can be extended and laid out on the element isolation film, so that the semiconductor device can be further integrated.
[0026]
  In the method of manufacturing a semiconductor device, the element isolationForm a filmIn the process,InterlayerThe etching characteristics differ from those of insulating films.4The insulating film is deposited and patterned, and the first4Made of insulating filmSaidIt is desirable to form an element isolation film. By manufacturing the semiconductor device in this way, it is possible to prevent the element isolation film from being etched when the through hole is opened. In addition, since the element isolation film can be used as an etching mask, a through hole can be opened in a self-aligned manner in the element isolation film.
[0027]
  In the method of manufacturing a semiconductor device, the element isolation filmThe first etching stopper filmAnd saidSecondThe etching stopper film is preferably a silicon nitride film.
  In the method of manufacturing a semiconductor device,InterlayerInsulating film and said first1The insulating film is preferably a silicon oxide film or a silicon oxide film containing impurities.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 2 and 3 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
[0029]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. An element isolation film 12 that defines element regions 14 and 16 is formed on the silicon substrate 10. A gate electrode 26 is formed in the element regions 14 and 16 via a gate oxide film 18. Source / drain diffusion layers 28 are formed in the element regions 14 and 16 on both sides of the gate electrode 26. Thus, a MOS transistor including the gate electrode 26 and the source / drain diffusion layer 28 is formed.
[0030]
An interlayer insulating film 38 is formed on the silicon substrate 10 on which the MOS transistor is formed. In the interlayer insulating film 38, through holes 42, 44, 46, 48 reaching the source / drain diffusion layer 28 and the gate electrode 26 are formed. Is formed.
Here, the semiconductor device according to the present embodiment is characterized in that it has the etching stopper film 36 covering the side wall of the gate electrode 26 and the region of the upper surface of the gate electrode 26 from the periphery of the gate electrode 26 to the inside of a predetermined distance.
[0031]
By configuring the etching stopper film 36 in this way, the manufacturing process of the semiconductor device can be simplified.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method to define element regions 14 and 16. Next, a gate oxide film 18 having a thickness of about 10 nm is formed in the element regions 14 and 16 by thermal oxidation.
[0032]
Subsequently, a PSG (Phospho-Silicate Glass) having a film thickness of about 100 nm is formed by a CVD (Chemical Vapor Deposition) method on the polycrystalline silicon film 20 containing a high concentration of P (phosphorus) having a film thickness of about 200 nm. A film 22 is continuously deposited by plasma CVD, and a silicon nitride film 24 having a thickness of about 20 nm is continuously deposited by thermal CVD.
Thereafter, the silicon nitride film 24, the PSG film 22, and the polycrystalline silicon film 20 are simultaneously patterned by using a normal lithography technique and an etching technique. Thus, the gate electrode 26 whose upper surface is covered with the PSG film 22 and the silicon nitride film 24 is formed.
[0033]
Next, using the gate electrode 26 as a mask, for example, P ions are accelerated at an energy of 30 keV, and the implantation amount is 2 × 10.¹³cm^-2Ions are implanted under the conditions described above to form a source / drain diffusion layer 28 (FIG. 2A).
Subsequently, the silicon substrate 10 is immersed in a solution such as HF (hydrofluoric acid), and the PSG film 22 is isotropically etched by about 150 nm. By this etching, the etching of the PSG film 22 proceeds in the horizontal direction, and the overhang portion 30 of the silicon nitride film 24 is formed (FIG. 2B).
[0034]
In this etching, the gate oxide film 28 and a part of the element isolation film 12 not covered by the gate electrode 26 are also etched, but the etching rate of the PSG film 22 deposited by the plasma CVD method is the same as that of the thermal oxide film. Since it is about 10 times faster than that, there is no particular problem caused by etching. If a method such as changing the composition of the etching solution or using HF vapor is used, it is possible to further reduce the film loss of the gate oxide film 18 and the element isolation film 12. The silicon nitride film 24 is hardly etched with the HF solution.
[0035]
Thereafter, the surface of the silicon substrate 10 is oxidized by a thermal oxidation method, and a silicon oxide film 32 having a thickness of about 5 nm is grown in a region not covered with the gate electrode 26.
Next, a silicon nitride film 34 having a thickness of about 100 nm is grown by thermal CVD. The height of the overhang formed by etching the PSG film 22 is determined by the thickness of the PSG film 22, and the film thickness is 100 nm. Therefore, by depositing a silicon nitride film 34 having a thickness of 100 nm, the overhang portion is formed. 30 is completely embedded (FIG. 2C).
[0036]
Subsequently, the silicon nitride films 34 and 24 are anisotropically etched to cover the side walls of the gate electrode 26 and to form an etching stopper film 36 formed on the end of the upper surface by about 150 nm. The length of the etching stopper film 36 that rides on the gate electrode 26 is the distance that the PSG film 22 recedes when the PSG film 22 is isotropically etched (FIG. 3A).
[0037]
Thereafter, a high concentration impurity layer (not shown) is formed in the source / drain diffusion layer 28 as necessary. Using the etching stopper film 36 and the gate electrode 26 as a mask, for example, As (arsenic) ions are accelerated at an energy of 30 keV and an injection amount is 4 × 10.¹⁵cm^-2Ion implantation is performed under the following conditions. In this way, the diffusion layer structure of the MOS transistor can be an LDD (Lightly Doped Drain) structure.
[0038]
Next, a silicon oxide film and a BPSG film are successively deposited by CVD, and the surface is flattened by reflow. Thus, an interlayer insulating film 38 made of a laminated film of a silicon oxide film and a BPSG film is formed.
Subsequently, a resist pattern 40 for opening a through hole is formed by a normal lithography technique.
[0039]
Thereafter, the interlayer insulating film 38 is anisotropically etched using the resist pattern 40 as a mask to form through holes 42, 44, 46, and 48 that expose the source / drain diffusion layer 28 and the gate electrode 26 (FIG. 3B). )).
At this time, the through holes 42 and 44 are formed to extend on the gate electrode 26. However, since the etching stopper film 36 made of a silicon nitride film covers the side wall and the shoulder of the gate electrode 26, a normal SAC is formed. Similar to the structure, the through hole can be opened by self-alignment.
[0040]
The through hole 48 has a conventional contact structure that does not use the etching stopper film 36, and can be opened to the surface of the silicon substrate 10 simultaneously with the SAC.
Further, although the through hole 46 is opened on the gate electrode 26, the etching stopper film 36 does not exist on the gate electrode 26 in the opening, and the PSG film 22 is formed instead. Therefore, since the underlying PSG film 22 can be etched simultaneously with the etching of the interlayer insulating film 38, the gate electrode 26 can be exposed simultaneously with the opening of other through holes.
[0041]
In this way, all the through holes including the SAC can be opened by only one lithography process.
If a thin silicon nitride film is formed under the interlayer insulating film 38, even when the through holes 42, 44, and 48 are opened on the element isolation film 12 due to misalignment in the lithography process, It is possible to prevent the element isolation film 12 from being excessively etched.
[0042]
That is, if the etching of the interlayer insulating film 38 is stopped by this silicon nitride film and then the through hole is opened by removing this silicon nitride film, the overetching required for opening the interlayer insulating film 38 is performed. Since the process is not performed in a state where the layer 12 is exposed, it is possible to reduce the film loss of the element isolation film 12 due to the etching of the interlayer insulating film 38.
[0043]
With respect to the through hole 46, it is necessary to further remove the PSG film 22 after the removal of the silicon nitride film, but the PSG film 22 is provided under a condition that a sufficiently high etching rate is obtained as compared with the thermal oxide film such as the element isolation film 12. Is etched, the PSG film 22 can be etched without a lithography process.
As described above, according to the present embodiment, the etching stopper film that covers the side wall of the gate electrode and the region of the upper surface of the gate electrode from the periphery of the gate electrode to the inside of the predetermined distance is formed. A through hole opened on the gate electrode can be opened by one lithography process.
[0044]
  Thereby, compared with the conventional SAC process, one lithography process can be reduced.
  In the above-described embodiment, an example in which a thin silicon nitride film is formed immediately below the interlayer insulating film 38 as a means for reducing the reduction of the element isolation film 12 has been described. However, it can also be achieved by other methods. For example, if the interlayer insulating film 38 is formed by laminating films having different etching characteristics and each layer is etched layer by layer, the amount of overetching required for etching each layer can be reduced. It is possible to reduce film thickness reduction.
[Reference example]
  Of the present inventionReference exampleA semiconductor device and a method for manufacturing the same will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0045]
  Figure 4 shows the bookReference exampleFIG. 5 is a schematic view showing the structure of a semiconductor device according to FIG.Reference exampleIt is process sectional drawing explaining the manufacturing method of the semiconductor device by this.
  BookReference exampleThe semiconductor device according to the first embodiment and the method for manufacturing the same will now be described with respect to the semiconductor device combined with the salicide process and the method for manufacturing the same.
  First, bookReference exampleThe structure of the semiconductor device according to FIG.TheoryLight up.
[0046]
  BookReference exampleThe basic structure of the semiconductor device is substantially the same as that of the semiconductor device according to the first embodiment shown in FIG. 1, but the gate electrode 26 and the source / drain diffusion layer 28 in the region where the etching stopper film 36 is not formed. It is characterized in that the silicide film 50 is formed on the self-alignment.
  By configuring the semiconductor device in this manner, the diffusion layer resistance of the source / drain diffusion layer 28 can be reduced, and the contact characteristics can be improved. Furthermore, since the etching stopper film 36 is formed, the reliability of the salicide process can be improved. This will be described in detail later.
[0047]
  Then bookReference exampleA method for manufacturing a semiconductor device will be described with reference to FIG.
  First, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A to 3A, the side wall of the gate electrode 26 and the gate electrode from the periphery of the gate electrode 26 to the inside of a predetermined distance. A MOS transistor having an etching stopper film 36 covering the region on the upper surface 26 is formed.
[0048]
Next, the substrate is immersed in a solution such as HF, and the PSG film 22 on the gate electrode 26 and the silicon oxide film 32 on the source / drain diffusion layer 28 are removed, and part of the gate electrode 26 and the source / drain diffusion layer 28 is removed. It is exposed on the surface (FIG. 5A).
Subsequently, a Ti (titanium) film is deposited on the entire surface by sputtering, and then heat treatment such as RTA (Rapid Thermal Annealing) is performed to expose the exposed region of the gate electrode 26 and the source / drain diffusion layer 28 and the Ti film. To form a titanium silicide film 50.
[0049]
Thereafter, when the unreacted Ti film not in contact with silicon is removed with aqua regia or the like, the titanium silicide film 50 remains only in predetermined regions on the gate electrode 26 and the source / drain diffusion layer 28 (FIG. 5 (b)).
Next, in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIG. 3B, an interlayer insulating film 38 in which through holes 42, 44, 46, and 48 are opened is formed (FIG. 5C). ).
[0050]
  The above process for selectively forming the titanium silicide film 50 in this way is a technique widely known as a salicide process. But bookReference exampleThe semiconductor device according to FIG. 1 has the etching stopper film 36 covering the side wall of the gate electrode 26 and the region of the upper surface of the gate electrode 26 from the periphery of the gate electrode 26 to the inside by a predetermined distance. Reduced compared to the process.
  In a normal salicide process, a titanium silicide film is selectively formed on the gate electrode and the source / drain diffusion layer using the sidewall formed only on the side wall of the gate electrode as a reaction mask. If the silicidation reaction proceeds in the lateral direction due to the abnormal reaction, the silicide film formed on the gate electrode 26 and the silicide film formed on the source / drain diffusion 28 layer are short-circuited, resulting in a high yield. There was a decline.
[0051]
  But bookReference exampleIn the method of manufacturing a semiconductor device according to the method, the etching stopper film 36 is formed so as to run from the side wall of the gate electrode 26 to the shoulder, and the distance between the region where the gate electrode 26 is exposed and the source / drain diffusion layer 28 is sufficiently set. Since it can be ensured, the silicidation reaction hardly proceeds in the lateral direction. As a result, the probability that the silicide film on the gate electrode 26 and the silicide film on the source / drain diffusion layer 28 are short-circuited can be greatly reduced.
[0052]
  Like thisReference exampleTherefore, an etching stopper film having a different etching characteristic from the interlayer insulating film is formed so as to cover the side wall of the gate electrode and the region of the upper surface of the gate electrode from the periphery of the gate electrode to a predetermined distance inside. The through hole having the SAC structure and the through hole opened on the gate electrode can be opened by a single lithography process.
[0053]
  In addition, since the silicide film is formed on the gate electrode and the source / drain diffusion layer by using the etching stopper film formed in this manner as a reaction mask, the manufacturing yield is improved as compared with the conventional salicide process. be able to.
  The aboveReference exampleAlthough an example using titanium salicide has been shown, a salicide process using another metal silicide may be applied. For example, refractory metal silicides such as tungsten silicide, molybdenum silicide, and cobalt silicide can be used.
[No.2Embodiment]
  First of the present invention2The semiconductor device and the manufacturing method thereof according to the embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0054]
FIG. 6 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIG. 7 is a process cross-sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.
In the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 3, the etching stopper film that covers the sidewall of the gate electrode 26 and the region of the upper surface of the gate electrode 26 from the periphery of the gate electrode 26 to the inside of a predetermined distance. By forming 36, the SACs 42 and 44 and the through hole 46 exposing the gate electrode 26 can be opened by a single lithography process.
[0055]
In order to obtain such an effect according to the first embodiment, it is important to form the structure shown in FIG. 3A. The manufacturing method for obtaining this structure is the semiconductor according to the first embodiment. It is not restricted to the manufacturing method of an apparatus.
In the present embodiment, a method for manufacturing a semiconductor device that realizes a structure equivalent to the semiconductor device according to the first embodiment will be described.
[0056]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.
On the gate electrode 26 of the MOS transistor, there is formed a silicon oxide film 52 formed in the central portion at a predetermined interval from the end portion. A sidewall 54 made of a silicon nitride film is formed on the side wall of the silicon oxide film 52. A side wall 56 made of a silicon nitride film is formed on the side wall of the gate electrode 26 whose upper surface is covered with the silicon oxide film 52 and the side wall 54. The upper part of the side wall 56 reaches the side wall of the side wall 54.
[0057]
Thus, a structure corresponding to the etching stopper film 36 according to the first embodiment shown in FIG. 3A is formed by the sidewall 54 and the sidewall 56 formed around the gate electrode 26.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0058]
First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method to define element regions 14 and 16. Next, a gate oxide film 18 having a thickness of about 10 nm is formed in the element regions 14 and 16 by thermal oxidation.
Next, a polycrystalline silicon film 20 containing a high concentration of P with a thickness of about 200 nm is deposited by CVD, and a silicon oxide film 52 with a thickness of about 100 nm is deposited by plasma CVD.
[0059]
Subsequently, the silicon oxide film 52 is patterned by using a normal lithography technique and an etching technique (FIG. 7A). The silicon oxide film 52 defines a pattern of a gate electrode to be formed in a later process, and is processed into a pattern narrower by a predetermined width than the pattern of the gate electrode to be formed. This width is set so as to be substantially equal to the width of the side wall 54 formed in a later step.
[0060]
Thereafter, a silicon nitride film having a thickness of about 100 nm is deposited by a thermal CVD method and etched vertically by the RIE method to form a sidewall 54 on the side wall of the silicon oxide film 52 (FIG. 7B).
Next, the polycrystalline silicon film 20 is patterned using the silicon oxide film 52 and the sidewalls 54 as a mask to form the gate electrode 26. Thus, since the line width of the gate electrode 26 is determined by the width of the silicon oxide film 52 and the side wall 54 formed on the side wall, the film thickness, pattern width, etc. of the silicon oxide film 52 should be set in advance. Is desirable.
[0061]
Subsequently, using the gate electrode 26 as a mask, for example, P ions are accelerated at an energy of 30 keV, and the implantation amount is 2 × 10¹³cm^-2Ions are implanted under the conditions described above to form the source / drain diffusion layer 28 (FIG. 7C).
Thereafter, a silicon nitride film having a thickness of about 100 nm is deposited by a thermal CVD method and etched in the vertical direction by an RIE method to form a sidewall 56 on the side walls of the gate electrode 26 and the sidewall 54 (FIG. 7D). ).
[0062]
  Thus, the etching stopper film 36 composed of the side wall 54 and the side wall 56 is formed.
  As described above, according to the present embodiment, the side wall 54 and the gate electrode 26 are formed in the silicon oxide film 52 by self-alignment, and the side wall 56 is formed in the gate electrode 26 and side wall 54 by self-alignment. An etching stopper film 36 covering the side wall of the electrode 26 and the region of the upper surface of the gate electrode 26 from the periphery of the gate electrode 26 to the inside by a predetermined distance can be formed.
[No.3Embodiment]
  First of the present invention3The semiconductor device and the manufacturing method thereof according to the embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0063]
FIG. 8 is a plan view showing the structure of the semiconductor device according to the present embodiment, FIG. 9 is a schematic view showing a cross section of the AA ′ portion of the semiconductor device of FIG. 8, and FIGS. It is process sectional drawing explaining a manufacturing method.
In the present embodiment, an example in which the semiconductor device according to the first embodiment and the structure thereof are applied to a DRAM (Random Access Memory) will be described.
[0064]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.
On the silicon substrate 10, element regions 14 and 16 defined by the element isolation film 12 are formed. A source / drain diffusion layer 26 is independently formed on the element regions 14 and 16. A gate electrode 26 is formed on the element region 14 between the source / drain diffusion layers 26 via a gate oxide film 18. Thus, a memory cell transistor composed of the gate electrode 26 and the source / drain diffusion layer 28 is formed.
[0065]
The gate electrode 26 formed on the element region 14 is formed extending in a direction perpendicular to the element region 14 and constitutes a word line in which a plurality of memory cell transistors are connected.
The gate electrode 26 constituting the word line has a different line width depending on its location, and has a line width of about 0.2 μm on the element region 14 (the gate electrode 26 in this region is represented as a gate electrode 26M). In this region, the thickness is about 0.15 μm (the gate electrode 26 in this region is represented as a gate electrode 26WL). The line width of the gate electrode 26 in the peripheral circuit portion is about 0.5 μm (the gate electrode 26 in this region is represented as a gate electrode 26P).
[0066]
An etching stopper film 36 is formed on the gate electrode 26 so as to cover the side wall and the region of the upper surface of the gate electrode 26 from the periphery to the inside by a predetermined distance. The upper surface of the gate electrode 26WL is entirely covered with the etching stopper film 36, and the gate electrodes 26M and 26P are covered with the etching stopper film 36 only at the end portions of the upper surface.
[0067]
On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 64 having through holes 58 and 60 opened on the source / drain diffusion layer 28 and a through hole 62 opened on the gate electrode 26P. Is formed. The through holes 58 and 60 are formed in the etching stopper film 36 in a self-alignment manner.
[0068]
A capacitor storage electrode 66 is formed on the inner wall of the through hole 60 and the source / drain diffusion layer 28, and is connected to the source / drain diffusion layer 28 at the bottom of the through hole 60. A capacitor dielectric film 68 is formed on the inner and upper surfaces of the capacitor storage electrode 66. A capacitor counter electrode 70 is formed in the through hole 60 in which the capacitor storage electrode 66 and the capacitor dielectric film 68 are formed and on the interlayer insulating film 64. Thus, a capacitor including the capacitor storage electrode 66, the capacitor dielectric 68, and the capacitor counter electrode 70 is formed.
[0069]
A contact conductive film 72 is formed on the inner wall of the through hole 58 and the source / drain diffusion layer 28, and is connected to the source / drain diffusion layer 28 at the bottom of the through hole 58. The contact conductive film 72 is also connected to a bit line 76 disposed in a direction intersecting the word line via an interlayer insulating film 74 formed on the capacitor counter electrode 70, and the source / drain diffusion layer 28 and the bit line 76 are connected.
[0070]
A contact conductive film 78 is formed on the inner wall of the through hole 62 and on the gate electrode 26, and is connected to the gate electrode 26 at the bottom of the through hole 62. The contact conductive film 78 is also connected to the bit line 76 formed on the interlayer insulating film 64, and plays a role of connecting the gate electrode 26 and the bit line 76.
[0071]
Thus, a DRAM composed of one transistor and one capacitor is constructed.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. If a semiconductor device is manufactured by such a manufacturing method, the above-described semiconductor device can be easily formed.
[0072]
First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method to define element regions 14 and 16. Next, a gate oxide film 18 having a thickness of about 10 nm is formed in the element regions 14 and 16 by thermal oxidation.
Next, a polycrystalline silicon film 20 having a film thickness of about 150 nm, a PSG film 22 having a film thickness of about 150 nm, and a silicon nitride film 24 having a film thickness of about 20 nm are successively formed by CVD, and then subjected to normal lithography technology and etching. The silicon nitride film 24, the PSG film 22, and the polycrystalline silicon film 20 are simultaneously patterned using a technique. Thus, the gate electrode 26 whose upper surface is covered with the PSG film 22 and the silicon nitride film 24 is formed.
[0073]
Here, patterning is performed so that the line width of the gate electrode 26WL is, for example, about 0.15 μm, the line width of the gate electrode M is, for example, about 0.2 μm, and the line width of the gate electrode 26P is, for example, about 0.5 μm. .
Subsequently, using the gate electrode 26 as a mask, for example, P ions are accelerated at an energy of 20 keV, and the injection amount is 2 × 10.¹³cm^-2The source / drain diffusion layer 28 is formed in the element region 14 and the low concentration diffusion layer 29 is formed in the element region 16. The low-concentration diffusion layer 29 is n in the peripheral circuit transistor having the LDD structure.^-Become a layer.
[0074]
Thereafter, the silicon substrate 10 is immersed in a diluted HF solution, and the PSG film 22 is isotropically etched by about 0.08 μm. By this etching, the etching of the PSG film 22 proceeds in the horizontal direction. Since the PSG film 22 immediately below the gate electrode 26WL has a width of about 0.15 μm, it is completely removed by this etching. On the other hand, since the line width of the PSG film 22 on the gate electrode 26M and the gate electrode 26P is larger than the film thickness (0.08 × 2 μm) to be etched, a part of the PSG film 22 remains on the gate electrodes 26M and 26P. (FIG. 10 (a)).
[0075]
In FIG. 10A, the silicon nitride film 24 on the gate electrode 26WL is drawn in a state of floating from the gate electrode 26WL, but the remaining PSG film in the region of the gate electrode 26M existing in the direction perpendicular to the paper surface. 22 is supported. The reason why the PSG film 22 is left on the gate electrode 26P in this manner is that it is preferable when the through hole 62 is opened in a subsequent process, as shown in the method of manufacturing the semiconductor device according to the first embodiment.
[0076]
Considering the memory cell region from this point of view, it is not necessary to leave the PSG film 22 on the gate electrodes 26WL and 26M, but the silicon nitride film 24 scatters unless a part of the remaining region is left. Therefore, it is desirable to form a region where the PSG film 22 remains.
Next, a silicon nitride film 34 having a thickness of about 100 nm is grown by thermal CVD. Thereby, the side etch portion formed by etching the PSG film 22 is completely filled with the silicon nitride film 34 (FIG. 10B).
[0077]
Subsequently, the silicon nitride films 34 and 24 are anisotropically etched to cover the side walls of the gate electrode 26 and to form an etching stopper film 36 formed on the end portion of the upper surface by about 0.08 μm. The gate electrode 26WL is completely covered with the etching stopper film 36.
Thereafter, using the etching stopper film 36 as a mask, for example, As ions are accelerated in the element region 16 with an acceleration energy of 15 keV and an implantation amount of 4 × 10.¹⁵cm^-2The low concentration diffusion layer 29 is n-implanted under the conditions of^-A source / drain diffusion layer 28 having an LDD structure as a layer is formed (FIG. 10C).
[0078]
Next, a silicon oxide film with a film thickness of about 50 nm and a BPSG film with a film thickness of about 2 μm are successively deposited by CVD, and the surface is flattened by reflow or polishing. Thus, an interlayer insulating film 38 made of a laminated film of a silicon oxide film and a BPSG film is formed.
Subsequently, through holes 58 and 60 opened on the source / drain diffusion layer 28 and a through hole 62 opened on the gate electrode 26 are opened in the interlayer insulating film 38 by a normal lithography technique and etching technique. (FIG. 11 (a)).
[0079]
At this time, since the etching stopper film 36 is not formed on the gate electrode 26P, the gate electrode 26P is exposed in the through hole 62. On the other hand, the through holes 58 and 60 extend to the gate electrodes 26M and 26WL. Since the etching stopper film 36 is formed on the gate electrodes 26M and 26WL in this region, 26WL is never exposed.
[0080]
In particular, since the gate electrode 26WL is completely covered with the etching stopper film 36, the gate electrode 26WL is not exposed even if the through hole 60 is opened in the region including the gate electrode 26WL. Therefore, the through hole 60 can be extended on the gate electrode 26WL, and a large-area capacitor can be formed in the through hole 60.
[0081]
When etching the interlayer insulating film 38, it is desirable to set the etching conditions so that the etching rate of the silicon nitride film is sufficiently low. By doing this, the etching of the etching stopper film 36 at the bottom of the through holes 58 and 60 is effectively suppressed, and the through holes 58 and 60 can be opened in a self-aligned manner without exposing the gate electrode 26.
[0082]
Thereafter, a titanium nitride (TiN) film having a thickness of about 50 nm is deposited by CVD, and only the TiN film formed on the interlayer insulating film 38 is removed by polishing or the like. Thus, the contact conductive film 72 formed on the inner wall and bottom of the through hole 58, the capacitor storage electrode 66 formed on the inner wall and bottom of the through hole 60, and the contact conductive film formed on the inner wall and bottom of the through hole 62. 78 is formed.
[0083]
Contact conductive film 72 and capacitor storage electrode 66 are connected to source / drain diffusion layer 28 at the bottom of through holes 58 and 60, and contact conductive film 78 is connected to gate electrode 26P at the bottom of through hole 62 (FIG. 11). (B)).
Next, Ta having a film thickness of about 150 nm is formed by CVD.₂O_FiveA film (tantalum oxide film) is formed by continuously forming a TiN film having a film thickness of about 100 nm by a CVD method and a silicon oxide film having a film thickness of about 100 nm by a plasma CVD method. These films are formed by a normal lithography technique and an etching technique. Process the membrane into the same pattern.
[0084]
Thus, Ta₂O_FiveA capacitor dielectric film 68 made of a film, a capacitor counter electrode 70 made of a TiN film, and an interlayer insulating film 74 made of a silicon oxide film are formed.
Subsequently, a silicon oxide film having a thickness of about 100 nm is deposited by plasma CVD and then anisotropically etched to form sidewall insulating films 80 on the sidewalls of the capacitor counter electrode 70 and the interlayer insulating film 74 (FIG. 12A). )).
[0085]
Thereafter, a TiN film having a thickness of about 100 nm is deposited by the CVD method, and is patterned by a normal lithography technique and an etching technique to form the bit line 76. The bit line 76 is connected to the source / drain diffusion layer 28 via the contact conductive film 72 and to the gate electrode 26P via the contact conductive film 78.
In this way, a DRAM composed of one transistor and one capacitor can be formed (FIG. 12B).
[0086]
As described above, according to the present embodiment, by applying the semiconductor device and the manufacturing method thereof according to the first embodiment to a DRAM manufacturing method, the SAC structure through hole and the through hole opened on the gate electrode are combined. Since the opening can be performed by one lithography process, the through hole can be easily opened while simplifying the DRAM manufacturing process.
[0087]
Further, by changing the line width of the gate electrode 26 constituting the word line depending on the region, the gate electrode 26WL completely covered with the etching stopper film 36 and only the end portion thereof are formed by the etching stopper film 36. A covered gate electrode 26M can be formed.
Thereby, even if a through hole extending on the gate electrode 26WL is opened, the gate electrode 26WL is not exposed, so that a large-area capacitor extending on the gate electrode 26M can be configured.
[0088]
  In the above-described embodiment, the case where the through holes 58 and 60 opened on the source / drain diffusion layer 28 having the SAC structure and the through hole 62 opened on the gate electrode 26P are formed. It is also possible to open normal through-holes not simultaneously.
  In the above embodiment, the etching stopper film is formed by the method for manufacturing the semiconductor device according to the first embodiment.2The semiconductor device according to the embodiment may be applied.
[0089]
  Also,Reference exampleAs shown in Fig. 5, a salicide process may be added.
[No.4Embodiment]
  First of the present invention4The semiconductor device and the manufacturing method thereof according to the embodiment will be described with reference to FIGS. 1st to 1st3EmbodimentAnd reference examplesThe same components as those of the semiconductor device and the method for manufacturing the same according to the present invention are denoted by the same reference numerals, and description thereof will be omitted or simplified.
[0090]
  FIG. 13 shows the first through3EmbodimentAnd reference examplesFIG. 14 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 15 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.
  1st to 1st above3EmbodimentAnd reference examplesIn the semiconductor device and the method for manufacturing the same according to the above, an example in which a typical LOCOS method is used as a method for forming an element isolation film is shown. However, since the element isolation film 12 is formed by oxidizing the underlying silicon substrate 10 in the LOCOS method, there is no room for selecting an insulating film other than the oxide film.
[0091]
On the other hand, since a silicon oxide film having good consistency with a silicon process or a silicon oxide film containing impurities is often used for the interlayer insulating film 38, silicon is often used in the through-hole etching opening in the interlayer insulating film 38. The etching is performed under an etching condition in which the etching rate of the oxide film or the silicon oxide film containing impurities is high and the etching rate of the silicon nitride film is low.
[0092]
In such a case, when a through hole is opened on the element isolation film 12 due to misalignment of lithography or the like, the element isolation exposed in the through hole 44 when the interlayer insulating film 38 is etched as shown in FIG. There is a possibility that the silicon substrate 10 in the region where the source / drain diffusion layer 28 is not formed is exposed until the film 12 is etched.
[0093]
Thereafter, if a wiring layer (not shown) such as Al is formed in the region where the element isolation film 12 is etched, the wiring layer and the silicon substrate 10 are short-circuited, so that the etching control of the interlayer insulating film 38 is more strictly controlled. It is necessary to compensate the contact by implanting impurity ions into the exposed silicon substrate 10.
Such inconvenience that the element isolation film 12 is etched can be solved, for example, by forming a thin silicon nitride film immediately below the interlayer insulating film 38 as shown in the first embodiment. Is not desirable because it increases.
[0094]
In the present embodiment, a semiconductor device and a method for manufacturing the semiconductor device that can solve the above disadvantages without complicating the manufacturing process are provided.
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.
The semiconductor device according to the present embodiment is characterized in that the element isolation film 12 is constituted by the silicon nitride film 82 formed on the silicon substrate 10 with the silicon oxide film 81 interposed therebetween. By configuring the semiconductor device in this manner, the etching can be stopped with high selectivity with respect to the base during the etching of the through hole.
[0095]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, the silicon substrate 10 is thermally oxidized to grow a silicon oxide film 81 having a film thickness of about 15 nm on the entire surface.
Next, a silicon nitride film 82 having a thickness of about 200 nm is deposited by CVD and processed into a desired pattern. The silicon nitride film 82 is patterned so as to remain in the element isolation region (FIG. 15A).
[0096]
Subsequently, after a silicon nitride film having a thickness of about 100 nm is deposited by CVD, the silicon nitride film is anisotropically etched to form a sidewall nitride film 84 on the sidewall of the silicon nitride film 82 (FIG. 15B). )). The side wall nitride film 84 is not always necessary, but it is desirable to form the side wall nitride film 84 in order to alleviate the step at the edge of the silicon nitride film 82.
[0097]
The silicon nitride film 82 and the side wall nitride film 84 thus formed constitute the element isolation film 12.
Thereafter, for example, B (boron) ions are accelerated at an energy of 180 keV, and the implantation amount is 5 × 10.¹²cm^-2The channel stop impurity layer 86 is formed immediately below the element isolation film 12 by ion implantation under the conditions described above. The channel stop impurity layer 86 formed in this manner can sufficiently increase the threshold voltage of the parasitic transistor formed in the element isolation region (FIG. 15C).
[0098]
Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A to 3B, MOS transistors are formed in the element regions 14 and 16, and through holes 42, 44, An interlayer insulating film 38 having an opening 46 is formed.
At this time, in the semiconductor device according to the present embodiment, since the element isolation film 12 is composed of the silicon nitride film 82, even when the element isolation film 12 is exposed in the through hole 44, the through hole etching is performed. In addition, the element isolation film 12 is not etched (FIG. 15D).
[0099]
Therefore, the silicon substrate 10 directly under the element isolation film 12 is not exposed during the through-hole etching, and it is possible to prevent a wiring layer formed in a later process and the silicon substrate 10 from being short-circuited.
As described above, according to the present embodiment, since the element isolation film is constituted by the silicon nitride film formed on the silicon substrate, the through hole is opened even when the through hole and the element isolation film overlap. At this time, the element isolation film can be prevented from being etched.
[0100]
As a result, the silicon substrate in the region where the diffusion layer is not formed can be prevented from being exposed in the through hole. Therefore, even when the wiring layer is formed in the through hole in a later process, the silicon substrate, the wiring layer, Can be prevented.
The device isolation film manufacturing method described above has almost the same number of manufacturing steps as the LOCOS method, and the above-described effects can be obtained without increasing the total number of manufacturing steps.
[0101]
In the above embodiment, a silicon nitride film is used as the element isolation film 12, but the element isolation film 12 is preferably made of the same insulating material as the etching stopper film 36. In this way, even when the element isolation film 12 is exposed in the through hole, the through hole can be opened in a self-aligned manner with the etching stopper film 36 and the element isolation film 12.
[0102]
In this embodiment, the case where the interlayer insulating film 38 is formed of a silicon oxide film has been described. However, the interlayer insulating film 38 may be formed using another insulating material having high etching selectivity with respect to the silicon oxide film. If possible, an oxide film formed by the LOCOS method can be used as the element isolation film 12. In this case, if the etching stopper film 36 is formed of a silicon oxide film, a through hole can be opened in the interlayer insulating film 38 by self-alignment using the element isolation film 12 and the etching stopper film 36 as a mask.
[0103]
【The invention's effect】
  As described above, according to the present invention, a semiconductor substrate is formed on the semiconductor substrate.The firstElement areaAnd second element regionAn element isolation film that defines:FirstFormed in the element regionSource and drainA diffusion layer;Source and drainOn the semiconductor substrate between the diffusion layers, the firstGateFormed through an insulating filmFirstA gate electrode;FirstA side wall of the gate electrode;FirstFrom the edge of the gate electrode to the same distance insideFirstCovers the area on the top surface of the gate electrodeFirstEtching stopper film andA second gate electrode formed on the second element region via a second gate insulating film and extending to the element isolation film; a sidewall of the second gate electrode; and a second gate electrode A second etching stopper film covering a region on the upper surface of the second gate electrode from the periphery to an equal distance inside, a first etching on the first gate electrode and a second etching in a region where the first etching stopper film is not formed A first insulating film formed on the second gate electrode in a region where the stopper film is not formed and having different etching characteristics from the first etching stopper film and the second etching stopper film, and the first etching stopper Formed on the entire surface of the semiconductor substrate on which the film and the second etching stopper film are formed and having different etching characteristics from the first etching stopper film and the second etching stopper film. A pair of first through holes is formed in the interlayer insulating film on the source and drain diffusion layers, and the second etching stopper film is not formed on the element isolation film. Second through holes are formed in the first insulating film and the interlayer insulating film on the two gate electrodes.By configuring the semiconductor device, the first lithography can be performed only by one lithography process.Through holeAnd secondThrough holeCan be formed. Thereby, compared with the conventional SAC process, the number of lithography processes can be reduced by one.
[0105]
  In the above semiconductor device, the element isolation film isFirstEtching stopper filmAnd second etching stopper filmIf the through hole extends on the element isolation film, the through hole can be opened without etching the element isolation film. Therefore, the through hole can be formed in the etching stopper film and the element isolation film by self-alignment.
[0106]
  In the above semiconductor device, the element isolation filmThe second 1 Etching stopper filmas well asSecondA silicon nitride film can be applied as the etching stopper film.
  In addition, a plurality of word lines extending in parallel to the first direction, a plurality of bit lines extending in parallel to the second direction intersecting the first direction, and each intersection region of the word lines and the bit lines In the semiconductor device in which the memory cell provided on the semiconductor substrate is formed on the semiconductor substrate, the memory cell is formed on the semiconductor substrate,FirstElement areaAnd second element regionAn element isolation film that defines:FirstFormed in the element regionSource and drainA diffusion layer;Source and drainOn the semiconductor substrate between the diffusion layers,FirstGateIt is formed through an insulating film and doubles as a word lineFirstA gate electrode;FirstA side wall of the gate electrode;FirstFrom the edge of the gate electrode to the same distance insideFirstCovers the area on the top surface of the gate electrodeFirstEtching stopper film andA second gate electrode formed on the second element region via the second gate insulating film and extending to the element isolation film; a sidewall of the second gate electrode; A second etching stopper film covering a region of the upper surface of the second gate electrode from the periphery of the gate electrode to an equal distance inside, and on the first gate electrode and in the region where the first etching stopper film is not formed A first insulating film formed on the second gate electrode in a region where the etching stopper film is not formed and having different etching characteristics from the first etching stopper film and the second etching stopper film; The etching stopper film and the second etching stopper film are formed on the entire surface of the semiconductor substrate, and the first etching stopper film and the second etching stopper film have etching characteristics. A region having a different interlayer insulating film, a pair of first through holes formed in the interlayer insulating film on the source and drain diffusion layers, and a region where the second etching stopper film is not formed on the element isolation film A second through hole is formed in the first insulating film and the interlayer insulating film on the second gate electrode.By configuring the semiconductor device,The first through hole and the second through hole can be formed by only one lithography process. Thereby, compared with the conventional SAC process, the number of lithography processes can be reduced by one.
[0107]
  In the above semiconductor device,Forming a first gate electrode on the device isolation film;Formed on the device regionFirstThe line width of the gate electrode is formed on the element isolation filmFirstIt can be made wider than the line width of the gate electrode.
  In the above semiconductor device, on the element isolation filmOn the first gate electrode ofFormed inFirstEtching stopper filmFirstIf a region covering the entire surface of the gate electrode is provided, a through hole extending in a wide region including the gate electrode in that region can be opened. Thereby, for example, if the capacitor storage electrode is formed using the inner wall of the through hole, the capacitor area can be easily expanded.
[0108]
  In addition, on the semiconductor substrate,FirstElement areaAnd second element regionForming an isolation film for definingWorkAboutSemiconductor substrate firstelementOn areaFirstGateInsulating film is formedAnd forming a second gate insulating film on the second element region of the semiconductor substrate.YouWorkAboutThe conductive film, the first insulating film, and the first insulating film have different etching characteristics over the entire surface of the semiconductor substrate on which the first gate insulating film, the second gate insulating film, and the element isolation film are formed. The step of forming the second insulating film, the second insulating film, the first insulating film, and the conductive film are processed into the same pattern, and the conductive film is formed.FirstGateOn insulating filmFormed firstGate electrodeA second gate electrode made of a conductive film and formed on the second gate insulating film and extending to the element isolation film;Forming a step;A step of forming source and drain diffusion layers in the element regions on both sides of the first gate electrode, and isotropically etching the first insulating film using the second insulating film as a mask, The step of retracting the film by an equal distance in the horizontal direction and the etching characteristics of the first insulating film are the same as those of the second insulating film so that the gap formed by the etching of the first insulating film is buried. A third insulating film having a different thickness and a second insulating film and a third insulating film are etched in a vertical direction until the first insulating film is exposed to form a third insulating film. The firstA side wall of the gate electrode;FirstFrom the edge of the gate electrode to the same distance insideFirstCovers the area on the top surface of the gate electrodeFirstEtching stopper filmAnd a second etching stopper film covering the side wall of the second gate electrode and the region of the upper surface of the second gate electrode from the periphery of the second gate electrode to the same distance inside from the periphery of the second gate electrode,FormWorkAboutFirstEtching stopper filmAnd second etching stopper filmOn a semiconductor substrate on which is formedThe whole surfaceIn addition,FirstEtching stopper filmAnd second etching stopper filmEtching characteristics are different fromInterlayerForm an insulating filmWorkAboutInterlayerInsulating filmFormed source and drain diffusion layersTo be exposedA pair ofA first through hole;A second insulating film formed on the first insulating film and the interlayer insulating film;In the region where the etching stopper film is not formed.SecondOpen a second through hole that exposes the gate electrode at the same timeWorkBy manufacturing the semiconductor device as described above, the first through hole opened on the element region and the second through hole opened on the gate electrode can be opened by one lithography process. Thereby, the lithography process can be reduced by one process as compared with the conventional manufacturing process.
[0109]
  In the above method for manufacturing a semiconductor memory device,In the step of forming the pair of first through holes and second through holes, the first insulating film is etched at a higher etching rate than the element isolation film, the first etching stopper film, and the second etching stopper film. If performed under large conditions, the etching stopper film can be formed while suppressing the wear of the element isolation film and the second insulating film.
  A step of forming an element isolation film for defining the first element region and the second element region on the semiconductor substrate; and forming a first gate insulating film on the first element region of the semiconductor substrate; Forming a second gate insulating film on the second element region of the semiconductor substrate, and an entire surface of the semiconductor substrate on which the first gate insulating film, the second gate insulating film, and the element isolation film are formed, Etching characteristics of the step of forming a conductive film, the step of depositing and patterning a first insulating film on the conductive film, and the first insulating film on the conductive film on which the first insulating film is formed Depositing a second insulating film having a different thickness and etching in the vertical direction to form a first side wall made of the second insulating film on the side wall of the patterned first insulating film, and the first insulating film Etching the conductive film using the first sidewall as a mask A first gate electrode made of a conductive film and formed on the first gate insulating film; and a first gate electrode made of the conductive film, formed on the second gate insulating film and extending to the element isolation film. Forming the second gate electrode, forming the source and drain diffusion layers in the element regions on both sides of the first gate electrode, and forming the first insulating film and the first sidewall. A third insulating film having the same etching characteristics as that of the second insulating film and having a different etching characteristic from that of the first insulating film is deposited on the semiconductor substrate and etched in the vertical direction, so that the first gate electrode, the second gate electrode, A second sidewall made of a third insulating film is formed on the side wall of the first gate electrode and the first sidewall, the first sidewall and the second sidewall are formed, and the side wall of the first gate electrode , The edge of the first gate electrode A first etching stopper film covering a region of the upper surface of the first gate electrode up to an equal distance inside, a first sidewall and a second sidewall, and a sidewall of the second gate electrode; Forming a second etching stopper film covering a region of the upper surface of the second gate electrode from the periphery of the gate electrode to an equal distance inside, and forming the first etching stopper film and the second etching stopper film Forming an interlayer insulating film having different etching characteristics from the first etching stopper film and the second etching stopper film on the entire surface of the semiconductor substrate; and exposing the source and drain diffusion layers formed on the interlayer insulating film. A pair of first through holes, a first insulating film and an interlayer insulating film are formed, and a second etching stopper film is formed on the element isolation film. The semiconductor device is manufactured by simultaneously opening the second through hole exposing the second gate electrode in the unexposed region, thereby opening the first through hole opened on the element region and the gate electrode. The second through hole can be opened by one lithography process. Thereby, compared with the conventional manufacturing process, the lithography process can be reduced by one process.
[0110]
  Also,A pair of firstThrough holeAnd second through holeThe openingDoIn the processFor the pair of first through holes, the firstUsing the etching stopper film as an etching stopperInterlayerEtching insulation filmBy,FirstShaped to match the etching stopper filmCompleteThen, a normal SAC technique can be used for opening the first through hole.
  Also, element isolationForm a filmIn the process1Etching characteristics are different from other insulating filmsmaterialForming an element isolation film consisting ofA pair of firstThrough holeAnd second through holeThe openingDoIn the processOf the pair of first through holes, the first through hole in contact with the element isolation film is the firstEtching stopper film and element isolation film as etching stopperInterlayerEtching insulation filmBy,FirstShaped to match the etching stopper film and element isolation filmCompleteThen, the first through hole can be opened without etching the element isolation film. As a result, the first through-hole can be extended and laid out on the element isolation film, so that the semiconductor device can be further integrated.
[0114]
  Also, element isolationForm a filmIn the processInterlayerThe etching characteristics differ from those of insulating films.4An insulating film is deposited and patterned, and the first4If the element isolation film made of the insulating film is formed, the element isolation film can be prevented from being etched when the through hole is opened. In addition, since the element isolation film can be used as an etching mask, a through hole can be opened in a self-aligned manner in the element isolation film.
[0115]
  Further, in the above method for manufacturing a semiconductor device, an element isolation film, First etching stopper filmas well asSecondA silicon nitride film can be applied to the etching stopper film.
  Further, in the above method for manufacturing a semiconductor device,InterlayerInsulating film and second1As the insulating film, a silicon oxide film or a silicon oxide film containing impurities can be used.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 4 of the present inventionReference exampleIt is a schematic sectional drawing which shows the structure of the semiconductor device by.
FIG. 5 shows the present invention.Reference exampleCross section showing the method of manufacturing a semiconductor deviceIn the figureis there.
FIG. 6 shows the first of the present invention.2It is a schematic sectional drawing which shows the structure of the semiconductor device by embodiment.
FIG. 7 shows the first of the present invention.2It is process sectional drawing which shows the manufacturing method of the semiconductor device by embodiment.
FIG. 8 shows the first of the present invention.3It is a top view which shows the structure of the semiconductor device by embodiment.
FIG. 9 shows a first embodiment of the present invention shown in FIG.3It is the schematic which shows the cross section of the AA 'part of the semiconductor device by embodiment.
FIG. 10 shows the first of the present invention.3It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by embodiment.
FIG. 11 shows the first of the present invention.3It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by embodiment.
FIG. 12 shows the first of the present invention.3It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by embodiment.
FIG. 13 shows the first to the first3EmbodimentAnd reference examplesIt is a figure explaining the subject of the manufacturing method of the semiconductor device by this.
FIG. 14 shows the first of the present invention.4It is a schematic sectional drawing which shows the structure of the semiconductor device by embodiment.
FIG. 15 shows the first of the present invention.4It is process sectional drawing which shows the manufacturing method of the semiconductor device by embodiment.
FIG. 16 is a schematic cross-sectional view showing the structure of a conventional semiconductor device.
FIG. 17 is a process sectional view showing a conventional method of manufacturing a semiconductor device.
[Explanation of symbols]
10 ... Silicon substrate
12 ... element isolation film
14: Element region
16: Element region
18 ... Gate oxide film
20 ... polycrystalline silicon film
22 ... PSG film
24. Silicon nitride film
26 ... Gate electrode
28 ... Source / drain diffusion layer
29 ... Low concentration diffusion layer
30 ... Overhang part
32 ... Silicon oxide film
34 ... Silicon nitride film
36 ... Etching stopper film
38. Interlayer insulating film
40 ... resist pattern
42 ... Through hole
44 ... Through hole
46 ... Through hole
48 ... Through hole
50. Titanium silicide film
52. Silicon oxide film
54 ... sidewall
56 ... Sidewall
58 ... Through hole
60 ... Through hole
62 ... Through hole
64 ... interlayer insulating film
66. Capacitor storage electrode
68. Capacitor dielectric film
70: Capacitor counter electrode
72. Conductive conductive film
74. Interlayer insulating film
76: Bit line
78. Contact conductive film
80. Side wall insulating film
81 ... Silicon oxide film
82. Silicon nitride film
84 ... Sidewall nitride film
86 ... Channel stop impurity layer

Claims (16)

A semiconductor substrate;
An element isolation film formed on the semiconductor substrate and defining a first element region and a second element region ;
A source and drain diffusion layer formed in the first element region;
A first gate electrode formed on the semiconductor substrate between the source and drain diffusion layers via a first gate insulating film;
A side wall of said first gate electrode, the first etching stopper film covering said first of said first gate electrode upper surface of the gate electrode periphery to equal distances inner region,
A second gate electrode formed on the second element region via a second gate insulating film and extending to the element isolation film;
A second etching stopper film covering a side wall of the second gate electrode and a region of the upper surface of the second gate electrode from the periphery of the second gate electrode to the inside of the equal distance;
Formed on the first gate electrode in a region where the first etching stopper film is not formed and on the second gate electrode in a region where the second etching stopper film is not formed; A first insulating film having etching characteristics different from those of the etching stopper film and the second etching stopper film;
The first etching stopper film and the second etching stopper film are formed on the entire surface of the semiconductor substrate, and have different etching characteristics from the first etching stopper film and the second etching stopper film. An interlayer insulating film,
A pair of first through holes are formed in the interlayer insulating film on the source and drain diffusion layers, and the second gate in a region on the element isolation film where the second etching stopper film is not formed. A semiconductor device, wherein a second through hole is formed in the first insulating film and the interlayer insulating film on the electrode . The semiconductor device according to claim 1 Symbol placement,
The device isolation film is made of the same material as the first etching stopper film and the second etching stopper film . A semiconductor device, wherein: The semiconductor device according to claim 2 ,
The element isolation film , the first etching stopper film, and the second etching stopper film are formed of a silicon nitride film. A plurality of word lines extending parallel to the first direction, a plurality of bit lines extending parallel to the second direction intersecting the first direction, and each intersection of the word line and the bit line In a semiconductor device in which a memory cell provided in a region is formed on a semiconductor substrate,
The memory cell is
An element isolation film formed on the semiconductor substrate and defining a first element region and a second element region ;
A source and drain diffusion layer formed in the first element region;
On said semiconductor substrate between said source and drain diffusion layers are formed through a first gate insulating film, a first gate electrode which also serves as the word line,
Has the a sidewall of the first gate electrode, and a first etching stopper film covering said first of said first gate electrode upper surface of the gate electrode periphery to equal distances inner region,
A second gate electrode formed on the second element region via a second gate insulating film and extending to the element isolation film;
A second etching stopper film covering a side wall of the second gate electrode and a region of the upper surface of the second gate electrode from the periphery of the second gate electrode to the inside of the equal distance;
Is formed on the first etching stopper film is not formed region of the first on the gate electrode及 beauty the second etching stopper film is not formed on the second gate electrode region, the second A first insulating film having etching characteristics different from those of the first etching stopper film and the second etching stopper film;
The first etching stopper film and the second etching stopper film are formed on the entire surface of the semiconductor substrate, and have different etching characteristics from the first etching stopper film and the second etching stopper film. An interlayer insulating film,
A pair of first through holes are formed in the interlayer insulating film on the source and drain diffusion layers, and the second gate in a region on the element isolation film where the second etching stopper film is not formed. A semiconductor device, wherein a second through hole is formed in the first insulating film and the interlayer insulating film on the electrode . The semiconductor device according to claim 4 .
The first gate electrode is formed to extend on the element isolation film, and a line width of the first gate electrode formed on the element region is formed on the element isolation film. semiconductor equipment, characterized in that wider than the line width of the first gate electrode. The semiconductor device according to claim 5 .
The semiconductor device, wherein the first etching stopper film formed on the first gate electrode on the element isolation film has a region covering the entire surface of the first gate electrode. On a semiconductor substrate, as engineering you forming an isolation layer defining a first element region and the second element region and,
And wherein the first gate insulating film formed on a semiconductor substrate of said first element region, as engineering that form a second gate insulating film on the second element region of said semiconductor substrate,
A conductive film, a first insulating film, and a first insulating film are formed on the entire surface of the semiconductor substrate on which the first gate insulating film, the second gate insulating film, and the element isolation film are formed. Forming a second insulating film having different etching characteristics;
The second insulating film, said first insulating film and then processed into the conductive film of the same pattern, the conductive film made of a first gate electrode formed on the first gate insulating film, Forming a second gate electrode made of the conductive film and formed on the second gate insulating film and extending to the element isolation film;
Forming source and drain diffusion layers in the element region on both sides of the first gate electrode;
Etching the first insulating film isotropically using the second insulating film as a mask, and retracting the first insulating film by an equal distance in the horizontal direction;
A third insulating film having the same etching characteristics as the second insulating film and different etching characteristics from the first insulating film is formed on the entire surface so as to fill a gap formed by etching the first insulating film. Depositing, and
Etching the second insulating film and the third insulating film in a vertical direction until the first insulating film is exposed, and comprising the third insulating film, the sidewall of the first gate electrode, a first etching stopper film covering the region of the first gate electrode upper surface from said first gate electrode periphery to said equal distance inside, made of the third insulating film, the second gate electrode and the side wall, and from the second gate electrode margins as the second second factory you form the etching stopper film covering the region of the gate electrode upper surface to the same distance inward,
Over the entire surface of said first of said semiconductor substrate etching stopper film and the second etching stopper film is formed, different interlayer insulating etching characteristics from the first etching stopper film and the second etching stopper film and as factories that form a film,
Wherein formed in the interlayer insulating film, wherein a pair of first through-hole exposing the source and drain diffusion layers, are formed on the first insulating film and the interlayer insulating film, on the isolation layer, the second the method of manufacturing a semiconductor device characterized by having a degree second factory you simultaneously opening a through hole exposing a 2 of said second gate electrode regions etching stopper film is not formed. The method of manufacturing a semiconductor device according to claim 7 .
In the step of forming the pair of first through holes and the second through holes, the etching of the first insulating film includes the element isolation film , the first etching stopper film, and the second etching stopper. A method for manufacturing a semiconductor device, characterized in that the etching is performed at a higher etching rate than the film . On a semiconductor substrate, as engineering you forming an isolation layer defining a first element region and the second element region and,
And wherein the first gate insulating film formed on a semiconductor substrate of the first device area on, as engineering that form a second gate insulating film on the second element region of said semiconductor substrate,
Forming a conductive film on the entire surface of the semiconductor substrate on which the first gate insulating film, the second gate insulating film, and the element isolation film are formed;
Depositing and patterning a first insulating film on the conductive film;
On the conductive film on which the first insulating film is formed, a second insulating film having etching characteristics different from that of the first insulating film is deposited, etched in the vertical direction, and patterned, the first insulating film Forming a first sidewall made of the second insulating film on the sidewall of the film;
The conductive film is etched using the first insulating film and the first sidewall as a mask, the first gate electrode made of the conductive film and formed on the first gate insulating film, and the conductive film Forming a second gate electrode made of a film and formed on the second gate insulating film and extending to the element isolation film;
Forming source and drain diffusion layers in the element region on both sides of the first gate electrode;
On the semiconductor substrate on which the first insulating film and the first sidewall are formed, a third insulating film having the same etching characteristics as the second insulating film and different in etching characteristics from the first insulating film. A film is deposited and etched in the vertical direction to form a second sidewall made of the third insulating film on the sidewalls of the first gate electrode, the second gate electrode, and the first sidewall. A side wall of the first gate electrode, and a region of the upper surface of the first gate electrode from the peripheral edge of the first gate electrode to an equal distance inside. a first etching stopper film that covers the made from the first sidewall and the second sidewall, and the sidewall of the second gate electrode, etc. from the second gate electrode margins A second etching stopper film had covering said second gate electrode upper surface region of the distance to the inner side as engineering you form,
Over the entire surface of said first of said semiconductor substrate etching stopper film and the second etching stopper film is formed, different interlayer insulating etching characteristics from the first etching stopper film and the second etching stopper film and as factories that form a film,
Wherein formed in the interlayer insulating film, wherein a pair of first through-hole exposing the source and drain diffusion layers, are formed on the first insulating film and the interlayer insulating film, on the isolation layer, the second the method of manufacturing a semiconductor device characterized by having a degree second factory you simultaneously opening a through hole exposing a 2 of said second gate electrode regions etching stopper film is not formed. In the manufacturing method of the semiconductor device according to any one of claims 7 to 9 ,
In the step of opening the pair of first through holes and the second through hole , the interlayer insulating film is etched using the first etching stopper film as an etching stopper for the pair of first through holes. it the method of manufacturing a semiconductor device, characterized in that that form the shape in alignment with the first etching stopper film. In the manufacturing method of the semiconductor device of any one of Claims 7 thru / or 10 ,
In the step of forming the element isolation film, the element isolation film made of a material having etching characteristics different from that of the first insulating film is formed,
In the step of opening the pair of first through holes and the second through hole , the first through hole that is in contact with the element isolation film among the pair of first through holes, by etching the interlayer insulating film using the first etching stopper film and the isolation layer as an etching stopper, characterized in that that form the first etching stopper film and form in alignment with the isolation layer A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to any one of claims 7 to 1 1,
In the step of forming the isolation layer, wherein the interlayer insulating film is patterned by depositing a different fourth insulating film etching characteristics to form the isolation layer made of the fourth insulating film A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to any one of claims 7 to 1 2,
The method of manufacturing a semiconductor device, wherein the first insulating film is a silicon oxide film or a silicon oxide film containing impurities. The method of manufacturing a semiconductor device according to any one of claims 7 to 1 3,
The method for manufacturing a semiconductor device, wherein the interlayer insulating film is a silicon oxide film or a silicon oxide film containing impurities. Keep method of manufacturing a semiconductor device according to any one of claims 7 to 1 4,
The method for manufacturing a semiconductor device, wherein the first etching stopper film and the second etching stopper film are silicon nitride films. In the manufacturing method of the semiconductor device of any one of Claims 7 thru | or 15,
The element isolation film is a silicon nitride film.
A method of manufacturing a semiconductor device.

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