JP5688605B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a structure of a semiconductor memory device capable of realizing a highly integrated DRAM (Dynamic Random Access Memory) with a small number of steps and a fine cell area, and a manufacturing method thereof.

  A DRAM is a semiconductor memory device that can be configured with one transistor and one capacitor. Conventionally, various structures and manufacturing methods for manufacturing a semiconductor memory device with higher density and higher integration have been studied.

  FIG. 59 shows a cross-sectional view of a semiconductor memory device described in Japanese Patent Laid-Open No. 61-176148.

  A source diffusion layer 24 and a drain diffusion layer 26 are independently formed in the semiconductor substrate 10. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. Thus, a memory cell transistor including the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is configured.

  On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed. Is formed.

  A cylindrical capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall of the through hole 40, and is connected to the source diffusion layer 24 at the bottom of the through hole 40.

  A capacitor dielectric film 48 is formed on the inner wall and upper surface of the capacitor storage electrode 46 and on the upper surface of the source diffusion layer 24 exposed inside the through hole 40.

  A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor including the capacitor storage electrode 46, the capacitor dielectric film 48, and the capacitor counter electrode 54 is configured.

  On the other hand, polycrystalline silicon is embedded in the through hole 38 and connected to a bit line 62 formed through an interlayer insulating film 53 formed on the capacitor counter electrode 54.

  Further, a metal wiring layer (not shown) is formed above the bit line via an interlayer insulating film (not shown), and a DRAM composed of one transistor and one capacitor is formed.

  FIG. 60 shows a cross-sectional view of another semiconductor memory device.

  A source diffusion layer 24 and a drain diffusion layer 26 are independently formed in the semiconductor substrate 10. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. Thus, a memory cell transistor including the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is configured.

  On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 102 in which a through hole 98 opened on the drain diffusion layer 26 and a through hole 100 opened on the source diffusion layer is formed. Has been. An insulating film 42 is formed on the gate electrode so as to surround the gate electrode, and exposed portions of the semiconductor substrate 10 in the through holes 98 and 100 are defined by the insulating film 42.

  An interlayer insulating film 36 is further formed on the interlayer insulating film 102, and a capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall and the bottom of the through hole 40 provided in the interlayer insulating film 36. The capacitor storage electrode 46 is connected to the source diffusion layer through the polycrystalline silicon film 104 embedded in the through hole 100.

  A capacitor dielectric film 48 is formed on the inner and upper surfaces of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed and on the interlayer insulating film 36. In this way, a capacitor including the capacitor storage electrode 46, the capacitor dielectric film 48, and the capacitor counter electrode 54 is configured.

  On the other hand, a polycrystalline silicon film 106 is embedded in the through hole 98 and is connected to a bit line 62 formed through an interlayer insulating film 53 formed on the capacitor counter electrode 54.

  Further, a metal wiring layer (not shown) is formed above the bit line via an interlayer insulating film (not shown), and a DRAM composed of one transistor and one capacitor is formed.

  Usually, in order to construct a DRAM cell, LOCOS isolation, gate electrode (word line), bit line contact hole, bit line, capacitor storage electrode through hole, capacitor storage electrode, capacitor counter electrode, metal wiring through hole, At least nine lithography steps for forming metal wiring are required.

  Further, in the lithography process, an alignment margin between the gate electrode and the bit line contact hole, an alignment margin between the gate electrode and the through hole, and an alignment margin between the through hole and the bit line are required.

  In order to improve these points, in the semiconductor memory device described in Japanese Patent Application Laid-Open No. 61-176148, by adopting the above structure, the capacitor storage electrode is formed in a self-aligned manner with respect to the through hole, so that lithography is possible. The process is reduced by one process.

  In addition, in the semiconductor memory device shown in FIG. 60, since the capacitor storage electrode is formed in a self-alignment manner, the through holes 98 and 100 are formed in a self-alignment with respect to the gate electrode. The memory cell area can be reduced to the extent that there is no need for an alignment margin for the line contact through-hole and an alignment margin for the gate electrode and the capacitor storage electrode through-hole.

  In this way, an attempt has been made to manufacture a semiconductor memory device that can be highly integrated with a small alignment margin and a small number of lithography processes.

  In the semiconductor memory device described in Japanese Patent Application Laid-Open No. 61-176148, the above structure is formed by depositing a polycrystalline silicon film to form the capacitor storage electrode 46 and simultaneously embedding polycrystalline silicon in the through hole 38. ing. The reason why the through hole 38 is completely buried is as follows.

  That is, as disclosed in the above publication, the bit line 62 is made of aluminum (Al), the bit line 62 is the uppermost wiring layer, and the source / drain or In order for Al to contact the gate electrode, it is necessary to etch an insulating film that is much thicker than the bit line contact portion, but since there is no evidence of etching in the interlayer insulating film 36 in the bit line contact portion, It is considered that the through hole of the circuit is completely filled with polycrystalline silicon like the through hole 38.

  In this way, the through hole of the peripheral circuit is completely embedded. The contact resistance in the peripheral circuit greatly affects the performance such as the operation speed of the circuit, and the contact resistance is lowered as much as possible by completely embedding the through hole. This is because it is desirable. Therefore, it is necessary to completely bury the bit line contact hole buried simultaneously with the through hole of the peripheral circuit.

  However, in the semiconductor memory device described in Japanese Patent Application Laid-Open No. 61-176148, the polycrystalline silicon film embedded in the through hole of the peripheral circuit needs to be formed thicker than the radius of the through hole. Since the capacitor storage electrode 46 is also formed at the same time, if the polycrystalline silicon film is too thick, the area of the inner wall of the through hole 40 is reduced and the cell capacity is lowered.

  Further, when the through holes 38 and 40 are formed, there is a problem that the cell area is increased correspondingly and the capacitor capacitance forming portion is reduced because the alignment margin with respect to the gate electrode 20 must be taken into consideration.

  In the semiconductor memory device shown in FIG. 60, since the self-aligned contact is formed as described above, it is not necessary to consider the alignment margin for the gate electrode 20 when the through holes 98 and 100 are formed. In addition, since the through hole 40 and the bit line contact hole 58 are formed separately, and the bit line contact hole 58 is not filled with a polycrystalline silicon film, a capacitor as in the semiconductor memory device described in Japanese Patent Application Laid-Open No. 61-176148 is used. Capacity does not decrease.

  However, in the semiconductor memory device of FIG. 60, polycrystalline silicon is embedded in the through holes 98 and 100 in order to connect the source diffusion layer 24 and the capacitor storage electrode 46, and the drain diffusion layer 26 and the bit line 62. Further, a lithography process for opening the through-holes 98 and 100 in the embedded portion is separately required. Therefore, there has been a problem that the number of lithography processes is increased by one process as compared with the semiconductor memory device described in JP-A-61-176148.

  An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which can reduce the memory cell area by reducing the alignment margin in the lithography process and reduce the number of lithography processes.

  Another object of the present invention is to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can easily etch a contact hole for a capacitor storage electrode and reduce the number of manufacturing steps.

  The object is to provide a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film. A memory cell transistor, an insulating film covering an upper surface and a side surface of the gate electrode, a first through hole covering the memory cell transistor and opening on the source diffusion layer, and on the drain diffusion layer A first interlayer insulating film formed with an open second through hole; a capacitor storage electrode formed on the inner wall and bottom of the first through hole and connected to the source diffusion layer; and the capacitor storage A capacitor having a capacitor dielectric film formed to cover the electrode and a capacitor counter electrode formed to cover the capacitor dielectric film A memory cell formed on the inner wall and bottom of the second through hole and having a first contact conductive film connected to the drain diffusion layer; and a bit line contact hole formed on the memory cell. And a bit line formed on the second interlayer insulating film and connected to the first contact conductive film of the memory cell through the bit line contact hole. This is achieved by a semiconductor memory device characterized by having. By configuring the semiconductor memory device in this way, when the first through hole opened on the source diffusion layer and the second through hole opened on the drain diffusion layer are formed, an alignment margin with the gate electrode is formed. Therefore, a semiconductor memory device having a small memory cell area can be configured. In addition, since the first contact conductive film does not need to be completely embedded in the second through hole, it is not necessary to increase the film thickness of the capacitor storage electrode formed at the same time more than necessary. Can be prevented.

  A source diffusion layer and a drain diffusion layer formed on the semiconductor substrate; and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer with a gate insulating film interposed therebetween. A memory cell transistor having an insulating film covering an upper surface and a side surface of the gate electrode, a first through hole covering the memory cell transistor and opening on the source diffusion layer, and opening on the drain diffusion layer A first interlayer insulating film in which the formed second through hole is formed, a first buried conductor buried in the bottom of the first through hole and connected to the source diffusion layer, and A second buried conductor buried in the bottom of the second through hole and connected to the drain diffusion layer, an inner wall of the first through hole, and the first buried conductor A capacitor storage electrode formed on a surface and connected to the source diffusion layer via the first buried conductor, a capacitor dielectric film formed to cover the capacitor storage electrode, and the capacitor dielectric A capacitor having a capacitor counter electrode formed so as to cover the film, an inner wall of the second through-hole, and an upper surface of the second embedded conductor are formed via the second embedded conductor. A memory cell having a first contact conductive film connected to the drain diffusion layer, a second interlayer insulating film formed on the memory cell and having a bit line contact hole, and the second interlayer insulating film. And a bit line connected to the first contact conductive film of the memory cell through the bit line contact hole. Also achieved by a semiconductor memory device according to claim and. By configuring the semiconductor memory device in this way, when forming a through hole or the like having a large aspect ratio, an ohmic contact is formed by previously forming a buried conductor having a low resistance in a region in contact with the semiconductor substrate substrate. Even when element integration progresses and the aspect ratio of the through hole increases, contact characteristics at the bottom of the through hole can be ensured.

  A source diffusion layer and a drain diffusion layer formed on the semiconductor substrate; and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer with a gate insulating film interposed therebetween. A memory cell transistor having a first through hole covering the memory cell transistor and opening on the source diffusion layer; a second through hole opening on the drain diffusion layer; and spaced apart from the semiconductor substrate A first interlayer insulating film formed so as to surround the first through hole in the region and having an opening diameter wider than that of the first through hole; an inner wall and a bottom of the opening; A capacitor storage electrode formed on the inner wall and bottom of one through hole and connected to the source diffusion layer; and a capacitor formed to cover the capacitor storage electrode A capacitor having a dielectric film and a capacitor counter electrode formed so as to cover the capacitor dielectric film; and a first dielectric layer formed on the inner wall and bottom of the second through hole and connected to the drain diffusion layer. A memory cell having a contact conductive film, a second interlayer insulating film formed on the memory cell and having a bit line contact hole formed thereon, and formed on the second interlayer insulating film, the bit It is also achieved by a semiconductor memory device having a bit line connected to the first contact conductive film of the memory cell through a line contact hole. By configuring the semiconductor memory device in this manner, the opening diameter of the through hole can be made extremely small without reducing the capacitor capacity. Thereby, it is possible to prevent a short circuit between the bit line and the word line due to adhesion of dust or the like.

  In the semiconductor memory device, the capacitor storage electrode includes a first columnar conductor formed inside the first through hole and spaced from the inner wall of the first through hole. The contact conductive film preferably includes a second columnar conductor formed inside the second through hole and spaced from the inner wall of the second through hole. By doing so, the first columnar conductor also functions as a capacitor storage electrode, so that the capacitor capacity can be greatly increased. Moreover, since the wiring between the drain diffusion layer and the bit line can be formed by the first contact conductive film and the second columnar conductor, the wiring resistance between the drain diffusion layer and the bit line can be reduced. .

  In the semiconductor memory device, it is preferable that the first interlayer insulating film in a region in contact with the insulating film is made of a material having etching characteristics different from those of the insulating film. By configuring the semiconductor memory device in this manner, the insulating film can be used as an etching stopper when the through hole is opened, and the substrate opening can be formed by self-alignment. Accordingly, since it is not necessary to secure a margin for alignment with the gate electrode when forming the through hole, a semiconductor memory device having a small memory cell area can be configured.

  In the semiconductor memory device, the insulating film is preferably a silicon nitride film, and the material having etching characteristics different from that of the insulating film is preferably a silicon oxide film or a silicon oxide film to which an impurity is added.

  In the semiconductor memory device, the capacitor storage electrode preferably further includes a columnar conductor protruding in a columnar shape from the first through hole into the opening. By doing so, the surface area of the capacitor storage electrode is increased by the amount of the columnar conductor, so that the capacitor capacity can be increased.

  The semiconductor memory device may further include a sidewall insulating film formed on an inner wall of the bit line contact hole, and the bit line is insulated from the capacitor counter electrode by the sidewall insulating film. Is desirable. By configuring the semiconductor memory device in this manner, the lithography process for forming the capacitor counter electrode and the lithography process for forming the bit line contact hole can be performed at a time.

  In the above semiconductor memory device, the peripheral circuit transistor formed on the semiconductor substrate in the periphery of the memory cell region where the memory cell is formed, the first interlayer insulating film, the bit Preferably, the wiring layer further includes a wiring layer made of the same conductive layer, and the wiring layer is directly connected to the gate electrode, the source diffusion layer, or the drain diffusion layer of the peripheral circuit transistor. By configuring the semiconductor memory device in this way, the semiconductor memory device can be configured without sacrificing the operation speed of the peripheral circuit.

  In the above semiconductor memory device, a peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed, a third interlayer insulating film formed on the bit line, and And a wiring layer formed on the third interlayer insulating film, wherein the wiring layer is directly connected to a gate electrode, a source diffusion layer, or a drain diffusion layer of the peripheral circuit transistor. desirable. By configuring the semiconductor memory device in this way, the semiconductor memory device can be configured without increasing the number of manufacturing steps and without sacrificing the operation speed of the peripheral circuit.

  In the semiconductor memory device, it is preferable that the wiring layer is directly connected to a gate electrode, a source diffusion layer or a drain diffusion layer of the peripheral circuit transistor, the capacitor counter electrode, or the bit line. Thus, the semiconductor memory device can be configured without increasing the number of manufacturing steps and without sacrificing the operation speed of the peripheral circuit.

  In the semiconductor memory device, the same structure as the stacked film of the capacitor counter electrode and the second interlayer insulating film is provided immediately below the bit line in the region connecting the bit line and the wiring layer. It is desirable to further have an etching protection pattern. By doing this, it is possible to simultaneously open a deep through hole formed in the peripheral circuit region and a shallow through hole formed on the bit line or the capacitor counter electrode without causing a short circuit between the bit line and the semiconductor substrate. it can.

  In the above semiconductor memory device, the bit is formed on the peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed, on the second interlayer insulating film, and on the bit A wiring layer made of the same conductive layer as the line, and the capacitor counter electrode and the second interlayer insulating film are formed to extend to a region where the peripheral circuit transistor is formed, The wiring layer is preferably directly connected to the gate electrode, source diffusion layer or drain diffusion layer of the peripheral circuit transistor. By configuring the semiconductor memory device in this way, the wiring layer of the peripheral circuit can be formed without increasing the number of manufacturing steps.

  In the semiconductor memory device, a peripheral circuit transistor formed on the semiconductor substrate around a memory cell region in which the memory cell is formed, and a gate electrode, a source diffusion layer of the peripheral circuit transistor, or A gate electrode of the peripheral circuit transistor, further comprising: a second contact conductive film formed on an inner wall and a bottom of a third through hole formed in the first interlayer insulating film on the drain diffusion layer. The source diffusion layer or the drain diffusion layer is preferably connected to a wiring layer formed on the first interlayer insulating film via the second contact conductive film. By configuring the semiconductor memory device in this way, the semiconductor memory device can be configured without increasing the number of manufacturing steps.

  The semiconductor memory device may further include a third embedded conductor formed at a bottom of the third through hole, and the second contact conductive film may include the third embedded conductor. It is desirable to be connected to the gate electrode, source diffusion layer, or drain diffusion layer of the peripheral circuit transistor via By configuring the semiconductor memory device in this way, when forming a through hole or the like having a large aspect ratio, an ohmic contact is formed by previously forming a buried conductor having a low resistance in a region in contact with the semiconductor substrate substrate. Even when element integration progresses and the aspect ratio of the through hole increases, contact characteristics at the bottom of the through hole can be ensured.

  In the semiconductor memory device, the first interlayer insulating film is preferably a stacked film in which a plurality of insulating materials having different etching characteristics are stacked. If the semiconductor memory device is configured in this manner, it can be easily performed when a through hole having a large aspect ratio is opened.

  In the semiconductor memory device, it is preferable that the stacked film is stacked with a silicon nitride film sandwiched between silicon oxide films.

  In the semiconductor memory device, the stacked film is preferably a film in which a silicon nitride film is stacked on a silicon oxide film.

  A source diffusion layer and a drain diffusion layer formed on the semiconductor substrate; and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer with a gate insulating film interposed therebetween. A memory cell transistor, an insulating film covering an upper surface and a side surface of the gate electrode, and a first interlayer insulating film covering the memory cell transistor and having a first through hole opened on the source diffusion layer And a contact portion formed on the inner wall and bottom of the first through hole and connected to the source diffusion layer, and a protrusion connected to the contact portion and protruding on the first interlayer insulating film A capacitor storage electrode having a portion, a capacitor dielectric film formed to cover the capacitor storage electrode, and a capacitor dielectric film formed to cover the capacitor dielectric film. A capacitor counter electrode also achieved by a semiconductor memory device characterized by having a memory cell having a capacitor having a. By doing so, the capacitor can be configured by using the front and back of the protruding portion, so that the capacitance of the capacitor can be increased.

  In the above semiconductor memory device, a second interlayer insulating film formed on the memory cell and having a bit line contact hole reaching the drain diffusion layer via the first interlayer insulating film; Preferably, the semiconductor device further includes a bit line formed on the second interlayer insulating film and connected to the drain diffusion layer of the memory cell through the bit line contact hole.

  In the semiconductor memory device, a second through hole opened on the drain diffusion layer is formed in the first interlayer insulating film, and is formed on an inner wall and a bottom of the second through hole. And a contact conductive film connected to the drain diffusion layer and a bit line formed on the memory cell via a second interlayer insulating film and connected to the contact conductive film. desirable.

  In the semiconductor memory device, the first interlayer insulating film includes a silicon nitride film and a silicon oxide film, and the silicon nitride film is formed on the gate electrode, and the silicon oxide film Is preferably formed on the silicon nitride film, and the second interlayer insulating film is preferably formed of a silicon oxide film. By doing so, the protruding portion can be easily formed. In addition, variation in capacitor capacity can be reduced.

  In the semiconductor memory device described above, the first contact conductive film, the second contact conductive film, or the capacitor storage electrode is preferably a conductive material that contacts N-type silicon and P-type silicon. . By configuring the semiconductor memory device in this way, contact characteristics with the silicon substrate can be improved.

  In the semiconductor memory device, the bit line contact hole preferably has a shape extending long in a direction in which the bit line extends. By configuring the semiconductor memory device in this manner, the bit line and the word line can be arranged with the minimum processing size, so that the memory cell area can be greatly reduced.

  In the semiconductor memory device, it is desirable that the bit line has a film thickness that is not more than half of an interval between the bit lines. By configuring the semiconductor memory device in this manner, capacitive coupling between bit lines can be suppressed.

  In addition, a plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel in a direction intersecting the plurality of bit lines, a sense amplifier provided at one end of each of the bit lines, and A decoder provided at one end of the word line, and the memory cell according to any one of the above provided at each intersection of the bit line and the word line, and the plurality of sense amplifiers are 2 Each set is provided on opposite side portions of the memory cell region where the memory cells are formed, and the plurality of decoders are divided into two sets, and the other opposing portions of the memory cell region. It is also achieved by a semiconductor memory device characterized in that each set is provided on the side portion. By configuring the semiconductor memory device in this way, it is possible to configure a peripheral circuit connected to the bit line and the word line arranged with the minimum processing size.

  A source diffusion layer and a drain diffusion layer formed on the semiconductor substrate; and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer with a gate insulating film interposed therebetween. A first through hole that covers the memory cell transistor and opens on the source diffusion layer, and a second through hole that opens on the drain diffusion layer. An interlayer insulating film, a buried conductor embedded in the first through-hole, and a capacitor storage formed on the first interlayer insulating film and connected to the source diffusion layer via the buried conductor An electrode, a capacitor dielectric film formed to cover the capacitor storage electrode, and a capacitor counter electrode formed to cover the capacitor dielectric film; A memory cell having a capacitor, and a bit line formed on the first interlayer insulating film and connected to the drain diffusion layer through the second through hole, and the embedded conductor; The bit line is also achieved by a semiconductor memory device characterized by being formed of the same conductive layer. By doing so, it is possible to reduce the etching time required to open the through hole for the contact of the capacitor storage electrode in the manufacturing process, so that the bit line can be prevented from being exposed during this etching.

  In the semiconductor memory device, the embedded conductor is preferably formed on a side wall and a bottom portion of the first through hole.

  In the semiconductor memory device, it is preferable that the first through hole and the second through hole are formed apart from the gate electrode.

  In the semiconductor memory device described above, it is preferable that the upper surface and the side surface of the bit line are covered with an insulating film that functions as an etching stopper for the second interlayer insulating film formed on the bit line. By doing so, it is possible to reduce damage to the bit line when opening the through hole for contact of the capacitor storage electrode.

  In the above semiconductor memory device, the second interlayer insulating film has a third through hole in which the embedded conductor is exposed, and the capacitor dielectric film includes the third dielectric hole. It is desirable to be formed on the side wall and bottom surface of the through hole. By doing so, the difference in height between the peripheral circuit region and the memory cell region can be reduced, so that the rule of the wiring layer formed on the upper layer can be reduced.

  In addition, after the first conductive film and the first insulating film are stacked and deposited on the semiconductor substrate, the first conductive film and the first insulating film are patterned, and the upper surface is the first insulating film. A gate electrode forming step of forming a gate electrode made of the first conductive film covered with a film; and a diffusion for introducing an impurity into the semiconductor substrate using the gate electrode as a mask to form a source diffusion layer and a drain diffusion layer A layer forming step, a first sidewall insulating film forming step of forming a first sidewall insulating film on a side wall of the gate electrode, a first through hole opened on the source diffusion layer, and the drain A first interlayer insulating film forming step of forming a first interlayer insulating film in which a second through hole opened on the diffusion layer is formed; and on the semiconductor substrate on which the first interlayer insulating film is formed To the second conductive film A second conductive film deposition step to be stacked; and the second through-hole on the first interlayer insulating film so as to leave the second conductive film in the first through hole and the second through hole. And the capacitor storage electrode made of the second conductive film formed in the first through hole and the second conductive film made of the second conductive film formed in the second through hole. A second insulating film serving as a capacitor dielectric film on the semiconductor substrate on which the conductive film removing step for forming one contact conductive film, the capacitor storage electrode, and the first contact conductive film are formed; And a capacitor counter electrode forming step of forming the capacitor counter electrode by depositing a film and a third conductive film to be a capacitor counter electrode and then patterning the third conductive film. Record Also achieved by the manufacturing method of the device. By manufacturing the semiconductor memory device in this manner, a semiconductor memory device having a small memory cell area can be formed without increasing the electric resistance between the bit line and the drain diffusion layer and without decreasing the capacitor capacity. .

  In the method for manufacturing a semiconductor memory device, in the capacitor counter electrode forming step, the third insulating film deposited on the third conductive film and the third conductive film are patterned, and the capacitor counter electrode is formed. And forming a bit line contact hole opened on the second through hole, depositing a fourth insulating film after the capacitor counter electrode forming step, and anisotropically etching the fourth insulating film. Forming a second sidewall insulating film on the inner wall of the bit line contact hole, and simultaneously removing the second insulating film at the bottom of the bit line contact hole; and A bit line is formed on the third insulating film and connected to the first contact conductive film exposed in the bit line contact hole. It is desirable to further include a bit line forming step. If the semiconductor memory device is manufactured in this manner, the lithography process for forming the capacitor counter electrode and the lithography process for forming the bit line contact hole can be performed at a time.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. The first gate electrode made of the first conductive film whose upper surface is covered with the first insulating film is formed in one region, the second region in which the peripheral circuit transistor is formed, and the upper surface is formed in the first region. Forming a second gate electrode made of the first conductive film covered with an insulating film, and introducing impurities into the semiconductor substrate using the gate electrode as a mask, A diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer of the memory cell transistor and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a sidewall of the gate electrode First A first sidewall insulating film forming step of forming a sidewall insulating film; a first through hole opened on the source diffusion layer of the memory cell transistor; and a drain diffusion layer of the memory cell transistor A first interlayer insulating film forming step of forming a first interlayer insulating film formed with the opened second through hole; and a second interlayer insulating film formed on the semiconductor substrate on which the first interlayer insulating film is formed. A second conductive film deposition step for depositing the conductive film, and the first interlayer insulation so as to leave the second conductive film in the first through hole and the second through hole. The second conductive film on the film is removed, a capacitor storage electrode made of the second conductive film formed in the first through hole, and a second formed in the second through hole. The conductive film A conductive film removing step for forming the first contact conductive film, the capacitor storage electrode, a second insulating film serving as a capacitor dielectric film on the first contact conductive film, and a capacitor counter electrode A third conductive film and a third insulating film are deposited, and then the third insulating film and the third conductive film are patterned to form the capacitor counter electrode and the second through hole. A bit line contact hole forming step for forming a bit line contact hole opened in the first electrode; and after depositing a fourth insulating film on the third insulating film in which the bit line contact hole is formed, The insulating film is anisotropically etched to form a second sidewall insulating film on the inner wall of the bit line contact hole, and at the same time, the second insulating film at the bottom of the bit line contact hole is formed. A second sidewall insulating film forming step for removing the second insulating film, a third through hole opened in the third insulating film on the capacitor counter electrode, and the source diffusion of the peripheral circuit transistor A second through hole forming step for forming a layer, a drain diffusion layer, or a fourth through hole opened in the first interlayer insulating film on the second gate electrode; and the bit line contact hole A bit line connected to the first conductive film exposed inside, a first wiring layer connected to the capacitor counter electrode via the third through hole, and the fourth through hole And a wiring layer forming step for forming a second wiring layer connected to the peripheral circuit transistor through the semiconductor device. . If the semiconductor memory device is manufactured as described above, the semiconductor memory device can be configured without sacrificing the operation speed of the peripheral circuit.

  In the method for manufacturing a semiconductor memory device, a bit line for forming a bit line connected to the contact conductive film exposed in the bit line contact hole after the second sidewall insulating film forming step And a second interlayer insulating film forming step of forming a second interlayer insulating film on the semiconductor substrate on which the bit line is formed, and in the second through-hole forming step, In the second interlayer insulating film and the third insulating film, a third through hole reaching the capacitor counter electrode is formed, and in the second interlayer insulating film and the first interlayer insulating film, A fourth through hole reaching the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor is formed. In the wiring layer formation step, the third scan hole is formed. A first wiring layer connected to the capacitor counter electrode via the Horu, it is preferable to form the second wiring layer connected to the peripheral circuit transistor through said fourth through hole. If the semiconductor memory device is manufactured in this way, the semiconductor memory device can be configured without increasing the number of manufacturing steps and without sacrificing the operation speed of the peripheral circuit.

  In the method of manufacturing a semiconductor memory device, in the second through hole forming step, when the fifth through hole that connects the bit line and the wiring layer is formed, the bit line contact hole is formed. In the forming step, a laminated film of the third conductive film and the third insulating film is formed on the first interlayer insulating film in a region where a contact hole connecting the bit line and the wiring layer is formed. It is desirable to form an etching protection pattern. By manufacturing the semiconductor memory device in this way, the first interlayer insulating film immediately below the bit line can be prevented from being etched even when a deep through hole formed in the peripheral circuit region is opened. Short circuit with the semiconductor substrate can be prevented.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. The first gate electrode made of the first conductive film whose upper surface is covered with the first insulating film is formed in one region, the second region in which the peripheral circuit transistor is formed, and the upper surface is formed in the first region. Forming a second gate electrode made of the first conductive film covered with an insulating film, and introducing impurities into the semiconductor substrate using the gate electrode as a mask, A diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer of the memory cell transistor and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a sidewall of the gate electrode First A first sidewall insulating film forming step of forming a sidewall insulating film; a first through hole opened on the source diffusion layer of the memory cell transistor; and a drain diffusion layer of the memory cell transistor A first interlayer insulating film forming step of forming a first interlayer insulating film formed with the opened second through hole; and a second interlayer insulating film formed on the semiconductor substrate on which the first interlayer insulating film is formed. A second conductive film deposition step for depositing the conductive film, and the first interlayer insulation so as to leave the second conductive film in the first through hole and the second through hole. The second conductive film on the film is removed, a capacitor storage electrode made of the second conductive film formed in the first through hole, and a second formed in the second through hole. The conductive film A conductive film removing step for forming the first contact conductive film, the capacitor storage electrode, a second insulating film serving as a capacitor dielectric film on the first contact conductive film, and a capacitor counter electrode A third conductive film and a third insulating film are deposited, and then the third insulating film and the third conductive film are patterned to form the capacitor counter electrode and the second through hole. And a third through hole opened on the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor. A step of forming a bit line contact hole that opens to the top of the insulating film; and a photoresist that selectively covers the bit line contact hole, and then the second through hole in the third through hole. The third through hole reaching the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor is etched by etching the first insulating film and the first interlayer insulating film. It is also achieved by a method for manufacturing a semiconductor memory device, comprising a second through hole forming step to be formed. If the semiconductor memory device is manufactured in this way, it is not necessary to perform fine alignment when opening a through hole in the peripheral circuit portion, so that the lithography process can be simplified.

  In the method for manufacturing a semiconductor memory device, in the bit line contact hole forming step, the capacitor storage electrode, the second insulating film serving as a capacitor dielectric film on the second conductive film, After successively depositing the third conductive film serving as a capacitor counter electrode, the third insulating film, and a mask film functioning as an etching stopper, the mask film, the third insulating film, and the third insulating film are deposited. Patterning the conductive film, forming a capacitor counter electrode and a bit line contact hole opened on the second through hole, and forming the source diffusion layer, the drain diffusion layer, or the peripheral circuit transistor, or The third through hole opened on the second gate electrode is opened to the second insulating film, and in the second through hole forming step, After selectively forming a photoresist covering the bit line contact hole, the second insulating film in the third through hole and the first interlayer insulating film using the mask film and the photoresist as an etching mask Are preferably etched to form the third through hole reaching the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor. If the semiconductor memory device is manufactured in this way, the lithography process can be simplified.

  In the method for manufacturing a semiconductor memory device, the mask film is preferably a silicon film.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. The first gate electrode made of the first conductive film whose upper surface is covered with the first insulating film is formed in one region, the second region in which the peripheral circuit transistor is formed, and the upper surface is formed in the first region. Forming a second gate electrode made of the first conductive film covered with an insulating film, and introducing impurities into the semiconductor substrate using the gate electrode as a mask, A diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer of the memory cell transistor and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a sidewall of the gate electrode First A first sidewall insulating film forming step of forming a sidewall insulating film; a first through hole opened on the source diffusion layer of the memory cell transistor; and a drain diffusion layer of the memory cell transistor A first interlayer in which an opened second through hole and a third through hole opened on the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor are formed. A first interlayer insulating film forming step for forming an insulating film; a second conductive film depositing step for depositing a second conductive film on the semiconductor substrate on which the first interlayer insulating film is formed; The second conductive film on the first interlayer insulating film so that the second conductive film remains inside the first through hole, the second through hole, and the third through hole. A capacitor storage electrode made of the second conductive film formed in the first through hole is removed, and a first conductive film made of the second conductive film formed in the second through hole. A conductive film removing step for forming a conductive film for contact, a second conductive film for contact made of the second conductive film formed in the third through hole, the capacitor storage electrode, A second insulating film serving as a capacitor dielectric film and a third conductive film serving as a capacitor counter electrode are formed on the semiconductor substrate on which the first conductive film for contact and the second conductive film for contact are formed. And the third insulating film are deposited, and then the third insulating film and the third conductive film are patterned, and the capacitor counter electrode and the bit line contact opened on the second through hole are formed. Forming a hole Forming a bit line contact hole, and depositing a fourth insulating film on the third insulating film in which the bit line contact hole is formed, and then anisotropically etching the fourth insulating film Forming a second sidewall insulating film on the inner wall of the bit line contact hole, and simultaneously removing the second insulating film at the bottom of the bit line contact hole; and the bit line A bit line connected to the first contact conductive film exposed in the contact hole and a wiring layer connected to the second contact conductive film formed in the third through hole are formed. It is also achieved by a method for manufacturing a semiconductor memory device comprising a wiring layer forming step. If the semiconductor memory device is manufactured in this way, the semiconductor memory device can be configured without increasing the number of manufacturing steps.

  In the method for manufacturing a semiconductor memory device, in the capacitor counter electrode forming step, the third conductive film is formed on the first through hole or the first so that the surface of the third conductive film becomes flat. It is desirable to embed in the two through holes. If the semiconductor memory device is manufactured in this manner, the lithography process for forming the capacitor counter electrode and the lithography process for forming the bit line contact hole can be performed at a time.

  In the method of manufacturing a semiconductor memory device, the second insulating film is anisotropically etched by depositing a fifth insulating film after the second conductive film deposition step. A third sidewall insulating film forming step for forming a third sidewall insulating film on inner walls of the first through hole and the second through hole in which the conductive film is formed, and the third sidewall A fourth conductive film deposition step of depositing a fourth conductive film filling the first through hole and the second through hole in which an insulating film is formed, and the third conductive film deposition step after the conductive film removal step. By removing the sidewall insulating film, the first columnar conductor made of the fourth conductive film is formed in the first through hole, and the fourth conductive film is formed in the second through hole. Second columnar conductive And in the conductive film removing step, the fourth conductive film, the second conductive film, and the like until the third sidewall insulating film is exposed on the surface. It is desirable to remove the first interlayer insulating film. If the semiconductor memory device is manufactured as described above, the capacitor storage electrode having the first columnar conductor formed away from the first through-hole inner wall and the second through-hole inner wall are formed apart from each other. Since the first contact conductive film having the second columnar conductor formed can be formed, the capacitance of the capacitor can be greatly increased and the wiring resistance between the drain diffusion layer and the bit line can be decreased. . Further, in the above method for manufacturing a semiconductor memory device, since the inside of the through hole is buried when the second conductive film is removed, it is possible to prevent an abrasive or the like from entering the through hole. Thereby, the fall of the yield by an abrasive | polishing agent etc. can be prevented.

  In the method of manufacturing a semiconductor memory device, in the first interlayer insulating film forming step, the surface of the first interlayer insulating film is formed after the first interlayer insulating film is deposited and before the through hole is formed. It is desirable to flatten the surface by polishing. If the semiconductor memory device is manufactured in this way, the global flatness on the interlayer insulating film is improved, so that the depth of focus when opening the through hole can be reduced and fine patterning can be performed.

  In the method for manufacturing a semiconductor memory device, it is preferable that in the conductive film removing step, the surface of the semiconductor substrate is polished to remove the second conductive film on the first interlayer insulating film. By manufacturing the semiconductor memory device in this way, it is possible to easily form the capacitor storage electrode and the contact conductive film in which the shape of the through hole is matched.

  In the method for manufacturing a semiconductor memory device, in the first interlayer insulating film forming step, the first interlayer insulating film is formed of a stacked film in which a plurality of insulating materials having different etching characteristics are stacked, and the insulating layer is formed. It is desirable to open the through hole by etching the material one layer at a time. If a semiconductor memory device is manufactured in this way, it can be easily performed when a through hole having a large aspect ratio is opened.

  In the method for manufacturing a semiconductor memory device, a photoresist is applied on the second conductive film after the second conductive film deposition step, and the first through hole and the second through hole are applied. Alternatively, a photoresist coating process embedded in the third through hole is embedded in the first through hole, the second through hole, or the third through hole after the conductive film removing process. And a photoresist stripping step for stripping the photoresist, and in the conductive film removing step, the second through hole, the second through hole, or the third through hole has the second through hole. Preferably, the second conductive film and the photoresist on the first interlayer insulating film are removed so that the conductive film and the photoresist remain. If the semiconductor memory device is manufactured in this way, the polishing agent and the like do not enter the through hole when the second conductive film is removed by polishing, so that it is possible to prevent a decrease in yield due to this.

  In the method for manufacturing a semiconductor memory device, a sixth insulating film having an etching characteristic different from that of the first interlayer insulating film is deposited after the second conductive film deposition step, and the first through-hole is formed. An insulating film deposition step for filling the hole, the second through hole, or the third through hole is performed after the conductive film removing step, after the first through hole, the second through hole, or the second through hole. A sixth insulating film removing step of removing the sixth insulating film embedded in the through hole of the first through hole, wherein the first through hole and the second through hole are removed in the conductive film removing step. Or the second conductive film and the sixth insulation on the first interlayer insulating film so that the second conductive film and the sixth insulating film remain inside the third through hole. It is desirable to remove the membrane . If the semiconductor memory device is manufactured in this way, the polishing agent and the like do not enter the through hole when the second conductive film is removed by polishing, so that it is possible to prevent a decrease in yield due to this.

  In the method for manufacturing a semiconductor memory device, the first interlayer insulating film is preferably a laminated film having an insulating film having an etching characteristic different from that of the sixth insulating film on the surface. By doing so, only the insulating film embedded in the through hole can be selectively removed after polishing.

  In the method of manufacturing a semiconductor memory device, a sixth insulating film having substantially the same etching characteristics as the first interlayer insulating film is deposited after the second conductive film deposition step, and the first through An insulating film deposition step for filling the hole, the second through hole, or the third through hole is performed after the conductive film removing step, after the first through hole, the second through hole, or the second through hole. 3 further includes an insulating film removing step of removing the sixth insulating film and the first interlayer insulating film buried in the through hole of the first through hole. In the conductive film removing step, the first through hole, The second conductive film on the first interlayer insulating film and the second through hole or the third through hole so that the second conductive film and the sixth insulating film remain inside the third through hole; The sixth insulating film It is desirable that support. If the semiconductor memory device is manufactured in this way, the polishing agent and the like do not enter the through hole when the second conductive film is removed by polishing, so that it is possible to prevent a decrease in yield due to this.

  In the method for manufacturing a semiconductor memory device, the first interlayer insulating film is substantially the same in etching characteristics as the sixth insulating film on an insulating film having etching characteristics different from those of the sixth insulating film. In the insulating film removing step, it is desirable to remove the sixth insulating film and the insulating film having substantially the same etching characteristics as the sixth insulating film. Thus, in the insulating film removing step, the sixth insulating film and the insulating film having substantially the same etching characteristics as those of the sixth insulating film can be selectively removed.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. The first gate electrode made of the first conductive film whose upper surface is covered with the first insulating film is formed in one region, the second region in which the peripheral circuit transistor is formed, and the upper surface is formed in the first region. Forming a second gate electrode made of the first conductive film covered with an insulating film, and introducing impurities into the semiconductor substrate using the gate electrode as a mask, A diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer of the memory cell transistor and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a sidewall of the gate electrode First A first sidewall insulating film forming step for forming a sidewall insulating film; and a first interlayer insulating film is deposited on the semiconductor substrate on which the first sidewall is formed, and then the first interlayer insulating film is formed. A first interlayer insulating film forming step for planarizing the surface of the film, and a second insulating film having a different etching characteristic from the first interlayer insulating film is formed on the planarized first interlayer insulating film A second insulating film forming step, patterning the first interlayer insulating film and the second insulating film, forming a first through hole opened on the source diffusion layer, and on the drain diffusion layer A through hole forming step for forming the opened second through hole and the third through hole opened on the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor When, A second conductive film deposition step of depositing a second conductive film on the semiconductor substrate having the through-holes opened, and the surface of the second conductive film is exposed to the second insulating film. The first embedded conductor embedded in the first through hole, the second embedded conductor embedded in the second through hole, and embedded in the third through hole. A buried conductor forming step for forming a third buried conductor; a fourth through hole opened on the first buried conductor; and a fifth through hole opened on the second buried conductor. A second interlayer insulating film forming step of forming a second interlayer insulating film, in which a through-hole and a sixth through-hole opened on the third buried conductor are formed; On the semiconductor substrate on which the interlayer insulating film is formed A third conductive film deposition step for depositing a third conductive film, the fourth through-hole, the fifth through-hole, and the sixth through-hole with the second conductive film The third conductive film on the second interlayer insulating film is removed so as to remain, a capacitor storage electrode made of the third conductive film formed in the fourth through hole, and the fifth A first contact conductive film made of the third conductive film formed in the through hole and a second contact conductive film made of the third conductive film formed in the sixth through hole. The present invention is also achieved by a method for manufacturing a semiconductor memory device comprising a conductive film removing step for forming a film. If the semiconductor memory device is manufactured in this way, contact characteristics at the bottom of the through hole can be ensured even when the integration of the elements progresses and the aspect ratio of the through hole increases.

  In the method for manufacturing a semiconductor memory device, it is preferable that in the conductive film removing step, the surface of the semiconductor substrate is polished to remove the third conductive film on the surface of the second interlayer insulating film. If the semiconductor memory device is manufactured in this way, the buried conductor can be formed at the same time that the interlayer insulating film is planarized.

  In the method of manufacturing a semiconductor memory device, the first insulating film and the first sidewall function as an etching stopper when the through hole is formed, and the through hole is formed by the first hole. Desirably, the insulating film and the first sidewall insulating film are formed in a self-aligned manner. If the semiconductor memory device is manufactured in this manner, the source diffusion layer and the drain diffusion layer can be easily exposed at the bottom of the through hole.

  In addition, a first conductive film is deposited on the semiconductor substrate and patterned to form a gate electrode made of the first conductive film, and an impurity is added to the semiconductor substrate using the gate electrode as a mask. Introducing a diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer; a first through hole opened on the source diffusion layer; and a second through hole opened on the drain diffusion layer. An interlayer insulating film forming step for forming the formed interlayer insulating film; and an opening having a diameter larger than that of the first through hole and not reaching the semiconductor substrate so as to surround the first through hole. An opening forming step for forming an insulating film; a second conductive film depositing step for depositing a second conductive film on the semiconductor substrate on which the interlayer insulating film is formed; Removing the second conductive film on the interlayer insulating film so as to leave the second conductive film inside the opening; and a capacitor storage electrode made of the second conductive film formed in the opening; , A conductive film removing step of forming a first contact conductive film formed of the second conductive film formed in the second through hole, the capacitor storage electrode, and the first contact conductive film An insulating film to be a capacitor dielectric film and a third conductive film to be a capacitor counter electrode are deposited on the semiconductor substrate on which is formed, and then the third conductive film is patterned to face the capacitor. It is also achieved by a method for manufacturing a semiconductor memory device comprising a capacitor counter electrode forming step for forming an electrode. If the semiconductor memory device is manufactured in this way, the gap between the gate electrode and the through hole can be increased, so that it is possible to prevent the bit line and the word line from being short-circuited due to the influence of dust generated in the manufacturing process. it can. In addition to the through hole having a small opening diameter, an opening for forming the capacitor dielectric film is provided, so that the capacitor capacity is not lowered.

  In the method for manufacturing a semiconductor memory device, a fourth conductive film is deposited after the interlayer insulating film forming step to fill the first through hole and the second through hole by depositing a fourth conductive film. A deposition step, wherein in the opening formation step, the columnar conductor made of the fourth conductive film embedded in the first through hole remains in a state of protruding in the opening. It is desirable to form an opening. By manufacturing the semiconductor memory device in this way, it is possible to prevent damage to the semiconductor substrate exposed in the first through hole when the opening is formed. In addition, since the capacitor storage electrode is formed so as to cover the columnar conductor, the capacitor capacity can be increased.

  In the method for manufacturing a semiconductor memory device, it is preferable that the first through hole and the second through hole are formed simultaneously in the interlayer insulating film forming step.

  In the method for manufacturing a semiconductor memory device, in the interlayer insulating film forming step, the interlayer insulating film is formed by a laminated film including two or more insulating films having different etching characteristics, and in the opening forming step, It is desirable that the opening be opened to an interface between the insulating films having different etching characteristics. By doing this, the depth of the opening can be controlled with good reproducibility, so that variations in capacitor capacitance can be reduced.

  In addition, a first conductive film is deposited on the semiconductor substrate and patterned to form a gate electrode made of the first conductive film, and an impurity is added to the semiconductor substrate using the gate electrode as a mask. Introducing a diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer; a first through hole opened on the source diffusion layer; and a second through hole opened on the drain diffusion layer. An interlayer insulating film forming step for forming the formed interlayer insulating film; a second conductive film depositing step for depositing a second conductive film on the semiconductor substrate on which the interlayer insulating film is formed; and the second A conductive film is patterned to form a second conductor that forms a bit line connected to the drain diffusion layer through the first through hole and a buried conductor buried in the second through hole. A film patterning step, a capacitor storage electrode connected to the source diffusion layer via the buried conductor on the interlayer insulating film, a capacitor dielectric film covering the capacitor storage electrode, and the capacitor dielectric film It is also achieved by a method for manufacturing a semiconductor memory device, comprising a capacitor forming step of forming a capacitor having a capacitor counter electrode to be covered. When the semiconductor memory device is manufactured in this way, the capacitor storage electrode is embedded in the second through hole formed at the same time as the first through hole for the bit line contact, and the embedded conductor embedded at the same time as the bit line is formed. To the source diffusion layer. Accordingly, the etching time for forming the through hole for the capacitor storage electrode contact can be reduced without adding a new process. Therefore, the insulating film on the bit line is etched during this etching, and the bit line Can be prevented from being exposed.

  In the method for manufacturing a semiconductor memory device, the first insulating film deposition step for depositing a first insulating film on the second conductive film after the second conductive film deposition step may include the first insulating film deposition step. After the second conductive film patterning step, the method further includes a side wall insulating film forming step for forming a side wall insulating film on the side wall of the bit line. In the second conductive film patterning step, the first insulating film and It is desirable to process the second conductive film into the same pattern. If the semiconductor memory device is manufactured in this way, the embedded conductor is exposed to the surface at the same time, so there is no need to form a through hole for capacitor storage electrode contact using a mask process as in the prior art. That is, the mask process can be reduced by one process.

  In the method of manufacturing a semiconductor memory device, a second insulating film forming step of forming a second insulating film having an opening formed on the buried conductor after the second conductive film patterning step. In addition, in the capacitor forming step, it is preferable that the capacitor storage electrode is selectively formed on a side wall and a bottom of the opening. By doing so, the difference in height between the memory cell region and the peripheral circuit region is reduced, so that the wiring rule of the wiring layer formed in the upper layer can be designed strictly.

  In the method of manufacturing a semiconductor memory device, the interlayer insulating film forming step includes an interlayer insulating film forming step of depositing an interlayer insulating film on the semiconductor substrate, and the first insulating layer on the interlayer insulating film. An etching stopper film forming step in which an opening is formed in a region where the through hole and the second through hole are to be formed, and an etching stopper film having different etching characteristics from the interlayer insulating film; and a sidewall portion of the etching stopper film In addition, a sidewall forming step for forming a sidewall having different etching characteristics from the interlayer insulating film, and the second interlayer insulating film is etched using the etching stopper film and the sidewall as a mask, and the first through-hole is formed. And a through hole opening process for forming the interlayer insulating film in which the second through hole is formed. It is desirable to. By manufacturing the semiconductor memory device in this way, it is possible to open a through hole having an opening diameter equal to or smaller than the resolution limit of the exposure apparatus.

  In the method of manufacturing a semiconductor memory device, in the interlayer insulating film forming step, the interlayer insulating film is deposited on the semiconductor substrate and then patterned using an electron beam lithography method as a mask. It is preferable that the interlayer insulating film is etched to open the first through hole and the second through hole. By manufacturing the semiconductor memory device in this way, it is possible to open the first through hole and the second through hole having an opening diameter equal to or smaller than the resolution limit of a normal exposure apparatus.

  As described above, according to the present invention, the source diffusion layer and the drain diffusion layer formed on the semiconductor substrate are formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via the gate insulating film. Memory cell transistor having a gate electrode, an insulating film covering the top and side surfaces of the gate electrode, a first through hole covering the memory cell transistor and opening on the source diffusion layer, and opening on the drain diffusion layer The first interlayer insulating film in which the second through hole is formed, the capacitor storage electrode formed on the inner wall and the bottom of the first through hole, connected to the source diffusion layer, and covering the capacitor storage electrode A capacitor having a capacitor dielectric film formed on the capacitor, a capacitor counter electrode formed to cover the capacitor dielectric film, an inner wall of the second through hole, A memory cell having a first contact conductive film formed at the bottom and connected to the drain diffusion layer; a second interlayer insulating film formed on the memory cell and having a bit line contact hole; Since the semiconductor memory device is formed by the bit line formed on the two interlayer insulating films and connected to the first contact conductive film of the memory cell via the bit line contact hole, the semiconductor memory device is opened on the source diffusion layer. When forming the first through hole and the second through hole opened on the drain diffusion layer, it is not necessary to secure an alignment margin with the gate electrode, and the memory cell area can be reduced. In addition, since the first contact conductive film does not need to be completely embedded in the second through hole, it is not necessary to increase the film thickness of the capacitor storage electrode formed at the same time more than necessary. Can be prevented.

  A memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film A transistor, an insulating film covering the top and side surfaces of the gate electrode, a first through hole covering the memory cell transistor and opened on the source diffusion layer, and a second through hole opened on the drain diffusion layer Embedded in the bottom portion of the first through hole, the first buried conductor connected to the source diffusion layer, and the bottom portion of the second through hole, The second buried conductor connected to the drain diffusion layer, the inner wall of the first through hole, and the upper surface of the first buried conductor, and the source through the first buried conductor A capacitor having a capacitor storage electrode connected to the diffusion layer, a capacitor dielectric film formed to cover the capacitor storage electrode, and a capacitor counter electrode formed to cover the capacitor dielectric film; A memory cell having a first contact conductive film formed on the inner wall of the through hole and the upper surface of the second embedded conductor and connected to the drain diffusion layer via the second embedded conductor; A second interlayer insulating film formed on the cell and having a bit line contact hole formed thereon, and a first contact conductive film of the memory cell formed on the second interlayer insulating film through the bit line contact hole Since the semiconductor memory device is constituted by the bit line connected to the capacitor, the region where the capacitor storage electrode or the contact conductive film is in contact with the semiconductor substrate Low Override by embedding conductors ohmic contact is formed. As a result, even when element integration is advanced and the aspect ratio of the through hole is increased, the contact characteristics at the bottom of the through hole can be ensured.

  A memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film A first through hole covering the transistor, the memory cell transistor, and opening on the source diffusion layer; a second through hole opening on the drain diffusion layer; and a first through hole in a region separated from the semiconductor substrate Formed on the inner wall and bottom of the opening, the inner wall and bottom of the first through hole, and formed on the inner wall and bottom of the first through hole. A capacitor storage electrode connected to the source diffusion layer, a capacitor dielectric film formed to cover the capacitor storage electrode, and a capacitor dielectric film A memory cell having a capacitor having a capacitor counter electrode, a first contact conductive film formed on the inner wall and bottom of the second through hole and connected to the drain diffusion layer, and formed on the memory cell; A second interlayer insulating film in which a bit line contact hole is formed, and a bit line formed on the second interlayer insulating film and connected to the first contact conductive film of the memory cell through the bit line contact hole Since the semiconductor memory device is configured as described above, the opening diameter of the through hole can be made extremely small without reducing the capacitor capacity. Thereby, it is possible to prevent a short circuit between the bit line and the word line due to adhesion of dust or the like.

  In the above semiconductor memory device, the first columnar conductor formed in the first through hole and spaced apart from the inner wall of the first through hole is provided in the capacitor electrode, and the second through hole If a second columnar conductor formed inside the second through-hole inner wall is provided in the first contact conductive film, the first columnar conductor also functions as a capacitor storage electrode. Therefore, the capacitor capacity can be greatly increased. Moreover, since the wiring between the drain diffusion layer and the bit line can be formed by the first contact conductive film and the second columnar conductor, the wiring resistance between the drain diffusion layer and the bit line can be reduced. .

  In the above semiconductor memory device, if the first interlayer insulating film in the region in contact with the insulating film covering the gate electrode is made of a material having etching characteristics different from those of the insulating film covering the gate electrode, a through hole is opened. In this case, the insulating film can be used as an etching stopper, and the substrate opening can be formed by self-alignment. Therefore, it is not necessary to secure an alignment margin with the gate electrode when forming the through hole, so that the memory cell area can be reduced.

  In the above semiconductor memory device, a silicon nitride film is applied to the insulating film covering the gate electrode, and a silicon oxide film or a silicon oxide film doped with impurities is applied to a material having etching characteristics different from those of the insulating film covering the gate electrode. can do.

  In the semiconductor memory device described above, if the capacitor storage electrode is further provided with a columnar conductor that protrudes in a columnar shape from the first through hole, the surface area of the capacitor storage electrode increases by the amount of the columnar conductor. Therefore, the capacitor capacity can be increased.

  If the bit line and the capacitor counter electrode are insulated by providing a sidewall insulating film on the inner wall of the bit line contact hole, a lithography process for forming the capacitor counter electrode and a lithography process for forming the bit line contact hole are performed. Can be done at once.

  Further, a peripheral circuit transistor formed on a semiconductor substrate in the periphery of the memory cell region where the memory cell is formed, and a wiring layer formed on the first interlayer insulating film and made of the same conductive layer as the bit line. If the wiring layer is directly connected to the gate electrode, the source diffusion layer, or the drain diffusion layer of the peripheral circuit transistor, the semiconductor memory device can be configured without sacrificing the operation speed of the peripheral circuit.

  Also, a peripheral circuit transistor formed on a semiconductor substrate in the periphery of the memory cell region in which the memory cell is formed, a third interlayer insulating film formed on the bit line, and a third interlayer insulating film are formed. If the wiring layer is directly connected to the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor, the number of manufacturing steps is not increased and the operation speed of the peripheral circuit is sacrificed. The above-described semiconductor memory device can be configured without doing so.

  In the above semiconductor memory device, if the wiring layer is directly connected to the gate electrode, source diffusion layer or drain diffusion layer of the peripheral circuit transistor, the capacitor counter electrode, or the bit line, the number of manufacturing steps can be increased. In addition, the semiconductor memory device can be configured without sacrificing the operation speed of the peripheral circuit.

  Further, if an etching protection pattern having the same structure as the stacked film of the capacitor counter electrode and the second interlayer insulating film is provided immediately below the bit line in the region connecting the bit line and the wiring layer, the peripheral circuit region The deep through hole formed in the first layer and the shallow through hole formed on the bit line or the capacitor counter electrode can be simultaneously opened without causing a short circuit between the bit line and the semiconductor substrate.

  Further, a peripheral circuit transistor formed on a semiconductor substrate in the periphery of the memory cell region where the memory cell is formed, and a wiring layer formed on the second interlayer insulating film and made of the same conductive layer as the bit line. The capacitor counter electrode and the second interlayer insulating film are formed to extend to the region where the peripheral circuit transistor is formed, and the wiring layer is formed on the gate electrode, the source diffusion layer, or the drain diffusion layer of the peripheral circuit transistor. When directly connected, the wiring layer of the peripheral circuit can be formed without increasing the number of manufacturing steps.

  Also, a peripheral circuit transistor formed on a semiconductor substrate in the periphery of the memory cell region where the memory cell is formed, and a first interlayer insulation on the gate electrode, source diffusion layer, or drain diffusion layer of the peripheral circuit transistor A second contact conductive film formed on the inner wall and bottom of the third through-hole formed in the film, and the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor as the second contact By connecting to the wiring layer formed on the first interlayer insulating film via the conductive film, the semiconductor memory device can be configured without increasing the number of manufacturing steps.

  Also, a third embedded conductor formed at the bottom of the third through hole is provided, and the second contact conductive film is connected to the gate electrode and the source diffusion of the peripheral circuit transistor via the third embedded conductor. If connected to the layer or the drain diffusion layer, an ohmic contact is formed by a third buried conductor having a low resistance in a region where the second contact conductive film and the semiconductor substrate are in contact with each other. As a result, even when element integration is advanced and the aspect ratio of the through hole is increased, the contact characteristics at the bottom of the through hole can be ensured.

  In addition, if an interlayer insulating film is formed of a laminate in which a plurality of insulating materials having different etching characteristics are stacked, it can be easily performed with good controllability even when a through hole having a large aspect ratio is opened.

  In addition, a stacked body in which a silicon nitride film is sandwiched between silicon oxide films can be applied to the above-described stacked film.

  In addition, a stacked body in which a silicon nitride film is stacked on a silicon oxide film can be applied to the above-described stacked film.

  A memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film A transistor; an insulating film covering the top and side surfaces of the gate electrode; a first interlayer insulating film covering the memory cell transistor and having a first through hole opened on the source diffusion layer; and a first through A capacitor storage electrode formed on the inner wall and bottom of the hole and having a contact portion connected to the source diffusion layer, and a protrusion connected to the contact portion and protruding on the first interlayer insulating film; A capacitor having a capacitor dielectric film formed to cover the storage electrode and a capacitor counter electrode formed to cover the capacitor dielectric film; By configuring the semiconductor memory device by the memory cell having, since it constitutes a capacitor with the front and back of the protruding portion, it is possible to increase the capacitor capacitance.

  The semiconductor memory device includes a second interlayer insulating film formed on the memory cell and having a bit line contact hole reaching the drain diffusion layer via the first interlayer insulating film, and a second interlayer insulating film. A bit line formed on the interlayer insulating film and connected to the drain diffusion layer of the memory cell through the bit line contact hole can be provided.

  Further, in the above semiconductor memory device, the first interlayer insulating film has a second through hole opened on the drain diffusion layer, formed on the inner wall and bottom of the second through hole, A contact conductive film connected to the drain diffusion layer and a bit line formed on the memory cell via the second interlayer insulating film and connected to the contact conductive film can be provided.

  In the above semiconductor memory device, the first interlayer insulating film is composed of a silicon nitride film and a silicon oxide film, the silicon nitride film is formed on the gate electrode, and the silicon oxide film is formed on the silicon nitride film. If it does, a protrusion part can be formed easily. Thereby, the dispersion | variation in a capacitor capacity can be made small.

  Further, if a conductive material that contacts N-type silicon and P-type silicon is used as the first contact conductive film, the second contact conductive film, or the capacitor storage electrode, the contact characteristics with the silicon substrate can be improved. it can.

  Further, in the above semiconductor memory device, if the bit line contact hole is elongated in the extending direction of the bit line, the bit line and the word line can be arranged with the minimum processing dimension, so that the memory cell area is greatly increased. Can be reduced.

  In addition, if the bit line has a film thickness that is half or less of the interval between the bit lines, capacitive coupling between the bit lines can be suppressed.

  In addition, a plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel in a direction crossing the plurality of bit lines, a sense amplifier provided at one end of each bit line, and each word A semiconductor memory device is constituted by a decoder provided at one end of a line and the memory cell according to any one of the above provided at each intersection of a bit line and a word line, and two sets of a plurality of sense amplifiers. Each set is provided on the opposite side of the memory cell region where the memory cells are formed, the plurality of decoders are divided into two sets, and each set is provided on the other opposite side of the memory cell region. For example, a peripheral circuit connected to the bit line and the word line arranged with the minimum processing dimension can be configured.

  A memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film A first interlayer insulating film covering the transistor, the first through hole opening on the source diffusion layer, and the second through hole opening on the drain diffusion layer; A buried conductor embedded in one through hole, a capacitor storage electrode formed on the first interlayer insulating film and connected to the source diffusion layer via the buried conductor, and so as to cover the capacitor storage electrode A memory cell having a capacitor dielectric film formed and a capacitor having a capacitor counter electrode formed to cover the capacitor dielectric film; In the manufacturing process, a bit line formed on the interlayer insulating film and connected to the drain diffusion layer through the second through hole is provided, and the embedded conductor and the bit line are formed of the same conductive layer. Since the etching time required to open the through hole for the contact of the capacitor storage electrode can be reduced, it is possible to prevent the bit line from being exposed during this etching.

  In the above semiconductor memory device, the embedded conductor may be formed only on the side wall and the bottom of the first through hole.

  In the semiconductor memory device, the first through hole and the second through hole can be formed apart from the gate electrode.

  Further, if the upper and side surfaces of the bit line are covered with an insulating film that functions as an etching stopper with respect to the second interlayer insulating film formed on the bit line, the bit line is opened when the through hole for the contact of the capacitor storage electrode is opened. Damage to the line can be reduced.

  Further, if a third through hole in which the embedded conductor is exposed is formed in the second interlayer insulating film, and the capacitor dielectric film is formed on the side wall and the bottom surface of the third through hole, the peripheral circuit can be obtained. Since the height difference between the region and the memory cell region can be reduced, the rule of the wiring layer formed on the upper layer can be reduced.

  In addition, after the first conductive film and the first insulating film are stacked and deposited over the semiconductor substrate, the first conductive film and the first insulating film are patterned, and the upper surface is covered with the first insulating film. A gate electrode forming step of forming a gate electrode made of the first conductive film; a diffusion layer forming step of introducing impurities into the semiconductor substrate using the gate electrode as a mask to form a source diffusion layer and a drain diffusion layer; A first sidewall insulating film forming step for forming a first sidewall insulating film on the side wall of the electrode; a first through hole opened on the source diffusion layer; and a second opening opened on the drain diffusion layer. A first interlayer insulating film forming step for forming a first interlayer insulating film in which a through hole is formed, and a second conductive film is deposited on the semiconductor substrate on which the first interlayer insulating film is formed. Conductive film deposition step and first through The second conductive film on the first interlayer insulating film is removed so that the second conductive film remains inside the first through hole and the second through hole, and the second conductive film formed in the first through hole is removed. A capacitor storage electrode made of a conductive film, a conductive film removal step of forming a first contact conductive film made of a second conductive film formed in the second through hole, a capacitor storage electrode, A second insulating film to be a capacitor dielectric film and a third conductive film to be a capacitor counter electrode are deposited on the semiconductor substrate on which the contact conductive film is formed; Since the semiconductor memory device is manufactured by patterning and forming a capacitor counter electrode, a capacitor counter electrode forming step, a semiconductor memory device having a small memory cell area can be increased in electrical resistance between the bit line and drain diffusion layers, and It can be formed without reducing the capacitance of the capacitor.

  Further, in the capacitor counter electrode forming step, the third insulating film and the third conductive film deposited on the third conductive film are patterned, and the capacitor counter electrode and the bit line opened on the second through hole are formed. A contact hole is formed, and after the capacitor counter electrode forming step, a fourth insulating film is deposited, and the fourth insulating film is anisotropically etched to form a second sidewall insulating film on the inner wall of the bit line contact hole. And a second sidewall insulating film forming step for removing the second insulating film at the bottom of the bit line contact hole, and a first insulating film formed on the third insulating film and exposed in the bit line contact hole. A bit line forming step for forming a bit line connected to the contact conductive film, a lithography step for forming a capacitor counter electrode, and a bit line It is possible to perform a lithography process of forming a contact hole at a time. Thereby, the number of manufacturing processes can be reduced.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. A first gate electrode made of a first conductive film whose upper surface is covered with a first insulating film is formed in a region, a second region in which a peripheral circuit transistor is formed, and an upper surface is covered with a first insulating film. Forming a second gate electrode made of the first conductive film, introducing a impurity into the semiconductor substrate using the gate electrode as a mask, and forming a source diffusion layer and a drain of the memory cell transistor in the first region; A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a first sidewall insulating film on the sidewall of the gate electrode Side wall An edge film forming step, a first through hole opened on the source diffusion layer of the memory cell transistor, and a second through hole opened on the drain diffusion layer of the memory cell transistor are formed. A first interlayer insulating film forming step for forming an interlayer insulating film; a second conductive film depositing step for depositing a second conductive film on the semiconductor substrate on which the first interlayer insulating film is formed; The second conductive film on the first interlayer insulating film was removed so as to leave the second conductive film inside the through hole and the second through hole, and was formed in the first through hole. A capacitor storage electrode made of a second conductive film; a conductive film removing step for forming a first contact conductive film made of a second conductive film formed in the second through hole; a capacitor storage electrode; On the first conductive film for contact After depositing a second insulating film to be a capacitor dielectric film, a third conductive film to be a capacitor counter electrode, and a third insulating film, the third insulating film and the third conductive film are patterned. A bit line contact hole forming step for forming a capacitor counter electrode and a bit line contact hole opened on the second through hole; and a fourth insulating film on the third insulating film on which the bit line contact hole is formed. After the insulating film is deposited, the fourth insulating film is anisotropically etched to form the second sidewall insulating film on the inner wall of the bit line contact hole, and at the same time, the second insulating film at the bottom of the bit line contact hole A second sidewall insulating film forming step for removing the semiconductor substrate, a third through hole opened in the third insulating film on the capacitor counter electrode, and a source of the peripheral circuit transistor A second through hole forming step for forming a diffusion layer, a drain diffusion layer, or a fourth through hole opened in the first interlayer insulating film on the second gate electrode; and exposure in the bit line contact hole The bit line connected to the first contact conductive film, the first wiring layer connected to the capacitor counter electrode via the third through hole, and the peripheral circuit transistor via the fourth through hole Since the semiconductor memory device is manufactured by the wiring layer forming process for forming the second wiring layer connected to the semiconductor memory device, the semiconductor memory device can be configured without sacrificing the operation speed of the peripheral circuit. .

  In addition, after the second sidewall insulating film forming step, a bit line forming step for forming a bit line connected to the contact conductive film exposed in the bit line contact hole, and on the semiconductor substrate on which the bit line is formed And a second interlayer insulating film forming step for forming a second interlayer insulating film. In the second through-hole forming step, the second interlayer insulating film and the third insulating film reach the capacitor counter electrode. A fourth through hole that forms a third through hole and reaches the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor in the second interlayer insulating film and the first interlayer insulating film. Forming a hole, and in the wiring layer forming step, the first wiring layer connected to the capacitor counter electrode via the third through hole, and the peripheral circuit transistor via the fourth through hole By forming the second wiring layer is continued, without increasing the number of manufacturing steps, it is possible to configure the semiconductor memory device without sacrificing the operation speed of the peripheral circuit.

  Further, when forming the fifth through hole for connecting the bit line and the wiring layer in the second through hole forming step, the contact hole for connecting the bit line and the wiring layer in the bit line contact hole forming step. If an etching protection pattern made of a laminated film of the third conductive film and the third insulating film is formed on the first interlayer insulating film in the region where the film is to be formed, a deep through hole formed in the peripheral circuit region is opened. Also in this case, since the first interlayer insulating film immediately below the bit line can be prevented from being etched, a short circuit between the bit line and the semiconductor substrate can be prevented.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. A first gate electrode made of a first conductive film whose upper surface is covered with a first insulating film is formed in a region, a second region in which a peripheral circuit transistor is formed, and an upper surface is covered with a first insulating film. Forming a second gate electrode made of the first conductive film, introducing a impurity into the semiconductor substrate using the gate electrode as a mask, and forming a source diffusion layer and a drain of the memory cell transistor in the first region; A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a first sidewall insulating film on the sidewall of the gate electrode Side wall An edge film forming step, a first through hole opened on the source diffusion layer of the memory cell transistor, and a second through hole opened on the drain diffusion layer of the memory cell transistor are formed. A first interlayer insulating film forming step for forming an interlayer insulating film; a second conductive film depositing step for depositing a second conductive film on the semiconductor substrate on which the first interlayer insulating film is formed; The second conductive film on the first interlayer insulating film was removed so as to leave the second conductive film inside the through hole and the second through hole, and was formed in the first through hole. A capacitor storage electrode made of a second conductive film; a conductive film removing step for forming a first contact conductive film made of a second conductive film formed in the second through hole; a capacitor storage electrode; On the first conductive film for contact After depositing a second insulating film to be a capacitor dielectric film, a third conductive film to be a capacitor counter electrode, and a third insulating film, the third insulating film and the third conductive film are patterned. Forming a capacitor counter electrode and a bit line contact hole opened on the second through-hole, and opening a third diffusion hole on the source diffusion layer, drain diffusion layer, or second gate electrode of the peripheral circuit transistor; A bit line contact hole forming step of opening the through hole to the second insulating film, and a photoresist covering the bit line contact hole is selectively formed, and then the second insulating film in the third through hole is formed. The second interlayer insulating film is etched to form a third through hole that reaches the source diffusion layer, drain diffusion layer, or second gate electrode of the peripheral circuit transistor. Since the semiconductor memory device is manufactured through the through-hole forming step, there is no need for fine alignment when opening the through-hole in the peripheral circuit portion, and the lithography process can be simplified.

  In the method for manufacturing a semiconductor memory device, in the bit line contact hole forming step, a capacitor storage electrode, a second insulating film serving as a capacitor dielectric film on the second conductive film, a capacitor counter electrode, A third conductive film, a third insulating film, and a mask film functioning as an etching stopper are successively deposited, and then the mask film, the third insulating film, and the third conductive film are patterned to face the capacitor. A third through hole formed on the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor by forming an electrode and a bit line contact hole opened on the second through hole; In the second through-hole forming step, after selectively forming a photoresist covering the bit line contact hole, a mask film is formed. The second insulating film in the third through hole and the first interlayer insulating film are etched using the photoresist as an etching mask, and the source diffusion layer, drain diffusion layer, or second gate electrode of the peripheral circuit transistor is etched. The lithography process can also be simplified by forming the third through hole reaching up.

  In the above method for manufacturing a semiconductor memory device, a silicon film can be applied to the mask film.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. A first gate electrode made of a first conductive film whose upper surface is covered with a first insulating film is formed in a region, a second region in which a peripheral circuit transistor is formed, and an upper surface is covered with a first insulating film. Forming a second gate electrode made of the first conductive film, introducing a impurity into the semiconductor substrate using the gate electrode as a mask, and forming a source diffusion layer and a drain of the memory cell transistor in the first region; A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a first sidewall insulating film on the sidewall of the gate electrode Side wall Edge film forming step, first through hole opened on source diffusion layer of memory cell transistor, second through hole opened on drain diffusion layer of memory cell transistor, and source of peripheral circuit transistor A first interlayer insulating film forming step of forming a first interlayer insulating film in which a third through hole opened on the diffusion layer, the drain diffusion layer or the second gate electrode is formed; and a first interlayer insulation A second conductive film deposition step of depositing a second conductive film on the semiconductor substrate on which the film is formed; a first through hole; a second through hole; and a second through hole inside the third through hole. The second conductive film on the first interlayer insulating film is removed so as to leave the conductive film of the capacitor, the capacitor storage electrode made of the second conductive film formed in the first through hole, and the second Formed in the through hole A conductive film removing step of forming a first contact conductive film made of the second conductive film and a second contact conductive film made of the second conductive film formed in the third through hole; On the semiconductor substrate on which the capacitor storage electrode, the first contact conductive film, and the second contact conductive film are formed, a second insulating film serving as a capacitor dielectric film and a capacitor counter electrode are formed. After depositing the third conductive film and the third insulating film, the third insulating film and the third conductive film are patterned, and the capacitor counter electrode and the bit line opened over the second through hole are formed. A bit line contact hole forming step for forming a contact hole, and depositing a fourth insulating film on the third insulating film in which the bit line contact hole is formed, and then anisotropically etching the fourth insulating film By bit line A second sidewall insulating film is formed on the inner wall of the contact hole, and at the same time, a second sidewall insulating film forming step for removing the second insulating film at the bottom of the bit line contact hole is exposed in the bit line contact hole. A semiconductor memory device comprising: a bit line connected to the first contact conductive film; and a wiring layer forming step for forming a wiring layer connected to the second contact conductive film formed in the third through hole. Since the conductive film directly connected to the peripheral circuit transistor is made to have the same structure as that of the capacitor storage electrode or the contact conductive film of the bit line contact portion, the contact of the peripheral circuit can be achieved without increasing the number of manufacturing steps. Can be formed.

  In addition, when depositing the conductive film to be the capacitor counter electrode, if the conductive film surface is embedded in the through hole so that the conductive film surface becomes flat, it is possible to prevent an unexpected step from occurring in the bit line contact portion, and contact characteristics Reliability can be improved.

  In the method for manufacturing the semiconductor memory device, the second conductive film is deposited by depositing a fifth insulating film and anisotropically etching the fifth insulating film after the second conductive film deposition step. A third sidewall insulating film forming step for forming a third sidewall insulating film on the inner wall of the first through hole and the second through hole formed with the third sidewall insulating film; and a third sidewall insulating film formed A fourth conductive film deposition step of depositing a fourth conductive film filling the first through hole and the second through hole by removing the third sidewall insulating film after the conductive film removal step; A columnar conductor forming step of forming a first columnar conductor made of the fourth conductive film in the first through hole and a second columnar conductor made of the fourth conductive film in the second through hole. In the conductive film removal process If the fourth conductive film, the second conductive film, and the first interlayer insulating film are removed until the third sidewall insulating film is exposed on the surface, the first through hole inner wall is separated. Forming a first contact conductive film having a second columnar conductor formed away from the capacitor storage electrode having the formed first columnar conductor and the inner wall of the second through hole is formed. As a result, the capacitance of the capacitor can be greatly increased, and the wiring resistance between the drain diffusion layer and the bit line can be reduced. Further, in the above method for manufacturing a semiconductor memory device, since the inside of the through hole is buried when the second conductive film is removed, it is possible to prevent an abrasive or the like from entering the through hole. Thereby, the fall of the yield by an abrasive | polishing agent etc. can be prevented.

  Further, in the above method of manufacturing a semiconductor memory device, if the surface of the first interlayer insulating film is flattened by polishing after the first interlayer insulating film is deposited and before the through hole is formed, the global flatness on the interlayer insulating film is obtained. Therefore, the depth of focus when opening a through hole can be reduced, and fine patterning can be performed.

  Further, in the above method of manufacturing a semiconductor memory device, if the second conductive film on the first interlayer insulating film is removed by polishing the surface of the semiconductor substrate, a capacitor storage electrode having a matched through-hole shape, A conductive film for contact can be easily formed.

  In addition, if a first interlayer insulating film is formed by a laminated film in which a plurality of insulating materials having different etching characteristics are stacked and a through hole is opened by etching the insulating material one by one, a through hole having a large aspect ratio is opened. This can be done easily.

  In the above method for manufacturing a semiconductor memory device, after the second conductive film deposition step, a photoresist is applied on the second conductive film, and the first through hole, the second through hole, or the third The photoresist coating process for embedding in the through-holes is performed by removing the photoresist embedded in the first through-hole, the second through-hole, or the third through-hole after the conductive film removing process. In the conductive film removing step, the first interlayer insulating film is formed so that the second conductive film and the photoresist remain in the first through hole, the second through hole, or the third through hole. If the second conductive film and the photoresist are removed, the polishing agent will not enter the through hole when the second conductive film is removed by polishing. It is possible to prevent a decrease in yield that.

  In the method for manufacturing a semiconductor memory device, after the second conductive film deposition step, a sixth insulating film having etching characteristics different from those of the first interlayer insulating film is deposited, and the first through hole, the first The insulating film deposition step embedded in the second through hole or the third through hole was embedded in the first through hole, the second through hole, or the third through hole after the conductive film removing step. A sixth insulating film removing step for removing the sixth insulating film is performed. In the conductive film removing step, the second conductive film and the second through hole, or the third through hole are provided in the first through hole, the third through hole, and the third through hole. If the second conductive film and the sixth insulating film on the first interlayer insulating film are removed so that the sixth insulating film remains, an abrasive or the like when the second conductive film is removed by polishing. Will not enter the through hole. It is possible to prevent a reduction in yield due to.

  Further, in the above method for manufacturing a semiconductor memory device, if an insulating film having an etching characteristic different from that of the sixth insulating film is provided on the surface of the first interlayer insulating film, it is embedded in the through hole after polishing. Only the insulating film can be selectively removed.

  In the method for manufacturing a semiconductor memory device, a sixth insulating film having substantially the same etching characteristics as the first interlayer insulating film is deposited after the second conductive film deposition step, and the first through hole, the first The insulating film deposition step embedded in the second through hole or the third through hole was embedded in the first through hole, the second through hole, or the third through hole after the conductive film removing step. An insulating film removing step for removing the sixth insulating film and the first interlayer insulating film is performed, and in the conductive film removing step, the second through hole, the second through hole, or the third through hole is second. When the second conductive film and the sixth insulating film on the first interlayer insulating film are removed so as to leave the conductive film and the sixth insulating film, the second conductive film is removed by polishing. Abrasives etc. can get into the through hole. Since there is no, it is possible to prevent a reduction in yield caused by this.

  Further, in the above method for manufacturing a semiconductor memory device, the first interlayer insulating film includes an insulating film having etching characteristics substantially equal to those of the sixth insulating film on an insulating film having etching characteristics different from those of the sixth insulating film. In the insulating film removing step, the sixth insulating film and the insulating film having substantially the same etching characteristics as the sixth insulating film can be selectively removed in the insulating film removing step.

  A first conductive film and a first insulating film are stacked and deposited on a semiconductor substrate, and then the first conductive film and the first insulating film are patterned to form a memory cell transistor. A first gate electrode made of a first conductive film whose upper surface is covered with a first insulating film is formed in a region, a second region in which a peripheral circuit transistor is formed, and an upper surface is covered with a first insulating film. Forming a second gate electrode made of the first conductive film, introducing a impurity into the semiconductor substrate using the gate electrode as a mask, and forming a source diffusion layer and a drain of the memory cell transistor in the first region; A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of the peripheral circuit transistor in the second region; and a first sidewall insulating film on the sidewall of the gate electrode Side wall Edge film forming step, and first interlayer insulating film forming step of planarizing the surface of the first interlayer insulating film after depositing the first interlayer insulating film on the semiconductor substrate on which the first sidewall is formed A second insulating film forming step of forming a second insulating film having etching characteristics different from those of the first interlayer insulating film on the planarized first interlayer insulating film; The second insulating film is patterned, and the first through hole opened on the source diffusion layer, the second through hole opened on the drain diffusion layer, the source diffusion layer of the peripheral circuit transistor, and the drain diffusion A through hole forming step for forming a layer or a third through hole opened on the second gate electrode, and a second conductive film for depositing the second conductive film on the semiconductor substrate having the through hole opened The deposition step and the surface of the second conductive film; Polishing until the second insulating film is exposed on the surface, a first embedded conductor embedded in the first through hole, a second embedded conductor embedded in the second through hole, and a third An embedded conductor forming step for forming a third embedded conductor embedded in the through-hole, a fourth through-hole opened on the first embedded conductor, and a second embedded conductor on the second embedded conductor A second interlayer insulating film forming step of forming a second interlayer insulating film in which a fifth through hole opened and a sixth through hole opened on the third buried conductor are formed; A third conductive film deposition step of depositing a third conductive film on the semiconductor substrate on which the second interlayer insulating film is formed; a fourth through hole; a fifth through hole; and a sixth through hole. So that the second conductive film remains inside the second conductive film. The third conductive film on the interlayer insulating film is removed, the capacitor storage electrode made of the third conductive film formed in the fourth through hole, and the third conductive film formed in the fifth through hole. Through the conductive film removing step of forming a first conductive film for contact made of a conductive film and a second conductive film for contact made of a third conductive film formed in the sixth through hole, Since the buried conductor is provided at the bottom, contact characteristics at the bottom of the through hole can be ensured even when the integration of the device is advanced and the aspect ratio of the through hole is increased.

  Further, in the above method of manufacturing a semiconductor memory device, when forming the buried conductor, the surface of the semiconductor substrate is polished, and the third conductive film on the surface of the second interlayer insulating film is removed. A buried conductor can be formed simultaneously with planarization.

  Further, if the first insulating film and the first sidewall covering the gate electrode are used as an etching stopper when forming a through hole opened on the semiconductor substrate, a source diffusion layer and a drain are formed at the bottom of the through hole. The diffusion layer can be easily exposed by self-alignment.

  A gate electrode forming step of depositing and patterning a first conductive film on the semiconductor substrate to form a gate electrode made of the first conductive film; and introducing impurities into the semiconductor substrate using the gate electrode as a mask; Diffusion layer forming step for forming source diffusion layer and drain diffusion layer, first through hole opened on source diffusion layer, and interlayer insulation formed with second through hole opened on drain diffusion layer An interlayer insulating film forming step of forming a film, and an opening forming step of forming an opening having a larger opening diameter than the first through hole and not reaching the semiconductor substrate in the interlayer insulating film so as to surround the first through hole; A second conductive film deposition step of depositing a second conductive film on the semiconductor substrate on which the interlayer insulating film is formed, and the interlayer so as to leave the second conductive film inside the second through hole and the opening. Insulation The upper second conductive film is removed, and the capacitor storage electrode made of the second conductive film formed in the opening, and the first contact made of the second conductive film formed in the second through hole A conductive film removing step for forming a conductive film, a capacitor storage electrode, a first contact conductive film, a semiconductor substrate on which an insulating film to be a capacitor dielectric film and a capacitor counter electrode are formed. After the third conductive film is deposited, the third conductive film is patterned, and a semiconductor memory device is manufactured by a capacitor counter electrode forming step for forming a capacitor counter electrode, thereby opening a gap between the gate electrode and the through hole. Therefore, it is possible to prevent the bit line and the word line from being short-circuited due to the influence of dust generated in the manufacturing process. In addition to the through hole having a small opening diameter, an opening for forming the capacitor dielectric film is provided, so that the capacitor capacity is not lowered.

  In the method for manufacturing a semiconductor memory device, a fourth conductive film deposition step of depositing a fourth conductive film and filling the first through hole and the second through hole after the interlayer insulating film formation step. In the opening forming step, the opening is formed if the opening is formed so that the columnar conductor made of the fourth conductive film embedded in the first through hole remains in a state of protruding into the opening. At this time, it is possible to prevent damage to the semiconductor substrate exposed in the first through hole. In addition, since the capacitor storage electrode is formed so as to cover the columnar conductor, the capacitor capacity can be increased.

  In the method for manufacturing the semiconductor memory device, the first through hole and the second through hole can be simultaneously formed in the interlayer insulating film forming step.

  Further, in the above method for manufacturing a semiconductor memory device, in the interlayer insulating film forming step, the interlayer insulating film is formed by a laminated film composed of two or more insulating films having different etching characteristics, and in the opening forming step, the opening is formed. Opening up to the interface between insulating films having different etching characteristics can control the depth of the opening with good reproducibility, thereby reducing variations in capacitor capacitance.

  A gate electrode forming step of depositing and patterning a first conductive film on the semiconductor substrate to form a gate electrode made of the first conductive film; and introducing impurities into the semiconductor substrate using the gate electrode as a mask; Diffusion layer forming step for forming source diffusion layer and drain diffusion layer, first through hole opened on source diffusion layer, and interlayer insulation formed with second through hole opened on drain diffusion layer An interlayer insulating film forming step of forming a film; a second conductive film depositing step of depositing a second conductive film on the semiconductor substrate on which the interlayer insulating film is formed; and patterning the second conductive film, A second conductive film patterning step for forming a bit line connected to the drain diffusion layer through the through-hole and a buried conductor buried in the second through-hole, and filling the interlayer insulating film on the interlayer insulating film A capacitor forming step of forming a capacitor having a capacitor storage electrode connected to the source diffusion layer through the only conductor, a capacitor dielectric film covering the capacitor storage electrode, and a capacitor counter electrode covering the capacitor dielectric film; If a semiconductor memory device is manufactured, a capacitor storage electrode is sourced via a buried conductor buried simultaneously with the bit line formation in a second through hole formed simultaneously with the first through hole for bit line contact. Can be connected to a diffusion layer. Accordingly, the etching time for forming the through hole for the capacitor storage electrode contact can be reduced without adding a new process. Therefore, the insulating film on the bit line is etched during this etching, and the bit line Can be prevented from being exposed.

  In the above method for manufacturing a semiconductor memory device, the first insulating film deposition step for depositing the first insulating film on the second conductive film is performed after the second conductive film deposition step. After the film patterning step, a sidewall insulating film forming step for forming a sidewall insulating film on the side wall of the bit line is performed, and the first insulating film and the second conductive film are formed in the same pattern in the second conductive film patterning step. If the upper and side walls of the bit line are covered with an insulating film by processing, the embedded conductor is exposed to the surface at the same time, so a through hole for capacitor storage electrode contact is formed using a mask process as in the past. There is no need to do. That is, the mask process can be reduced by one process.

  Further, in the above method for manufacturing a semiconductor memory device, after the second conductive film patterning step, a second insulating film forming step for forming a second insulating film having an opening formed on the buried conductor is performed. In the capacitor formation process, if the capacitor storage electrode is selectively formed on the side wall and bottom of the opening, the difference in height between the memory cell region and the peripheral circuit region is reduced. Can be designed.

  In addition, an interlayer insulating film forming step for depositing an interlayer insulating film on the semiconductor substrate, and an opening is formed in the region where the first through hole and the second through hole are to be formed on the interlayer insulating film. An etching stopper film forming step for forming an etching stopper film having a different etching characteristic from the film; a sidewall forming step for forming a sidewall having an etching characteristic different from that of the interlayer insulating film on the side wall of the etching stopper film; and an etching stopper. Etching the second interlayer insulating film using the film and the sidewall as a mask to form an interlayer insulating film through a first through hole and a through hole opening process for forming an interlayer insulating film in which the second through hole is formed If the interlayer insulating film having the first through hole and the second through hole is formed, the exposure apparatus can be resolved. It can be opened through holes having the opening diameter field.

  Further, in the interlayer insulating film forming step, after depositing an interlayer insulating film on the semiconductor substrate, the interlayer insulating film is etched using a photoresist patterned by electron beam lithography as a mask. The first through hole and the second through hole having an opening diameter equal to or smaller than the image limit can be opened.

[First Embodiment]
The semiconductor memory device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a plan view showing the structure of the semiconductor memory device according to the present embodiment. FIG. 2 is a schematic view showing a cross section of the semiconductor memory device of FIG. FIG. 7 is a schematic cross-sectional view of a semiconductor memory device according to a modification of the present embodiment.

  First, the structure of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

  Element regions 14 and 15 defined by the element isolation film 12 are formed on the silicon substrate 10. A source diffusion layer 24 and a drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. Thus, a memory cell transistor composed of the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is formed.

  Note that the gate electrode 20 is arranged in a direction perpendicular to the element region 14 and constitutes a word line that also functions as a gate electrode of a memory cell transistor in other memory cells.

  On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed. Is formed. The gate electrode 20 has an insulating film 42 formed in a self-aligned manner so as to surround the gate electrode 20, and the through holes 38 and 40 are formed in the insulating film 42 in a self-aligned manner.

  A capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner and upper surfaces of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed and on the interlayer insulating film 36. Thus, a capacitor including the capacitor storage electrode 46, the capacitor dielectric 48, and the capacitor counter electrode 54 is formed.

  A contact conductive film 44 made of polycrystalline silicon is formed on the inner wall of the through hole 38, and a bit arranged in a direction perpendicular to the word line via an interlayer insulating film 53 formed on the capacitor counter electrode 54. A line 62 is connected.

  Further, a wiring layer 70 is formed on the bit line 62 via an interlayer insulating film 64, and a DRAM including one transistor and one capacitor is formed.

  On the other hand, a source diffusion layer (not shown) and a drain diffusion layer 34 are independently formed in the element region 15 in the peripheral circuit region adjacent to the memory cell region. A gate electrode 22 is formed on the semiconductor substrate 10 between the source diffusion layer and the drain diffusion layer 34 with a gate oxide film 16 interposed therebetween. Thus, a peripheral circuit transistor including the gate electrode 22, the source diffusion layer, and the drain diffusion layer 34 is formed.

  A through hole 60 is formed in the interlayer insulating film 36 on the drain diffusion layer 34 and is connected to the wiring layer 70 formed on the interlayer insulating film 64 via the wiring layer 68 embedded in the through hole 60. Has been.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, an ordinary LOCOS method to define element regions 14 and 15. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element regions 14 and 15 by thermal oxidation (FIG. 3A).

Subsequently, a polycrystalline silicon film containing phosphorus (P) having a thickness of about 150 nm and a silicon nitride film having a thickness of about 200 nm are successively formed by chemical vapor deposition (CVD). After the film formation, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using a normal lithography technique and an etching technique.
Thus, the gate electrodes 20 and 22 whose upper surfaces are covered with the silicon nitride film 18 are formed.

Thereafter, using the silicon nitride film 18 and the gate electrodes 20 and 22 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 40 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , and the source diffusion layer 24 and drain of the memory cell transistor A diffusion layer 26 and a low concentration diffusion layer 28 of a peripheral circuit transistor are formed. The low-concentration diffusion layer 28 is an n ⁻ layer having an LDD (Lightly Doped Drain) structure (FIG. 3B).

Next, a silicon nitride film having a film thickness of about 100 nm is formed by CVD, and then anisotropic etching using CHF ₃ / H ₂ gas is performed to form sidewalls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22. A sidewall nitride film 30 made of a silicon nitride film is formed by self-alignment. As a result, the sidewalls and upper surfaces of the gate electrodes 20 and 22 are covered with the silicon nitride film 18 and the sidewall nitride film 30. Hereinafter, for convenience of explanation, the silicon nitride film 18 and the sidewall nitride film 30 covering the gate electrodes 20 and 22 are collectively referred to as an insulating film 42.

Subsequently, using normal lithography technology, for example, arsenic (As) ions are selectively ion-implanted into the N-type transistor region of the peripheral circuit under the conditions of an acceleration energy of 40 keV and an implantation amount of 4 × 10 ¹⁵ cm ^−2. A source diffusion layer and a drain diffusion layer 34 of the N-type transistor of the circuit are formed. Thus, a peripheral circuit transistor having an LDD structure is formed (FIG. 3C).

  Thereafter, a silicon oxide film of about 2 μm is deposited by the CVD method, and the surface thereof is polished and flattened by a chemical mechanical polishing (CMP) method. Here, the amount of polishing by the CMP method is sufficient if the steps due to the gate electrodes 20 and 22 and the element isolation film 12 can be removed, and in this embodiment, it is 500 nm.

  The surface may be flattened by depositing a laminated film of a silicon oxide film and a BPSG film instead of the silicon oxide film and reflowing the BPSG film. However, in consideration of global flatness, flattening by the CMP method is possible. desirable.

Next, after patterning the photoresist by a normal lithography process, the silicon oxide film is etched using an etching gas such as C ₂ F ₆ . Thereafter, the photoresist is removed, and an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor and a through hole 40 opened on the source diffusion layer 24 of the memory cell transistor are formed. (FIG. 3D).

  In this etching, the etching selectivity between the silicon oxide film and the silicon nitride film can be sufficiently secured, and the etching of the interlayer insulating film 36 can be stopped by the insulating film 42.

  The drain diffusion layer 26 and the source diffusion layer 24 are exposed at the bottoms of the through holes 38 and 40 formed in this manner, respectively, and the regions where the drain diffusion layer 26 and the source diffusion layer 24 are exposed are as follows. Since it is formed in a self-aligned manner with respect to the insulating film 42, it is not necessary to consider an alignment margin with respect to the gate electrode 20 when patterning the through holes 38 and 40. Accordingly, the area of the memory cell can be reduced by the amount of alignment margin.

The depth of the through hole 40 is an important parameter for determining the cell capacity. In this embodiment, the depth of the through hole 40 is about 1.5 μm. If the size is 0.3 × 0.6 μm, the sum of the bottom area and the side wall area of the through hole 40 is [0.3 × 0.6 + 1.5 × (0.3 + 0.6) × 2] μm ² , That is, about 2.88 μm ² can be secured. Accordingly, if the thickness of the capacitor dielectric is 4.5 nm in terms of oxide film, a sufficient capacitor having a capacity of about 22 fF can be formed.

  Subsequently, after a polycrystalline silicon film containing P in a high concentration is formed by a CVD method to a thickness of about 50 nm, the polycrystalline silicon film on the interlayer insulating film 36 is completely removed by a CMP method. Thus, the contact conductive film 44 is formed in the through hole 38 and the capacitor storage electrode 46 is formed in the through hole 40 in a self-aligned manner (FIG. 4A).

  Immediately after the deposition of the interlayer insulating film 36, planarization by CMP may not be performed, and the contact conductive film 44 and the capacitor storage electrode 46 may be planarized simultaneously with the self-alignment. In this way, the polishing process by the CMP method can be reduced by one process.

  Further, the capacitor storage electrode 46 and the contact conductive film 44 may be formed of a polycrystalline silicon film having surface irregularities (for example, H. Watanabe, Ext. Abstract of 22nd SSDM, p869 (1990)). In this way, the surface area of the capacitor storage electrode 46 is increased to about twice that when formed by a normal method, so that the depth of the through hole 40 is reduced to about half of 0.8 μm. The same capacitor capacity can be secured.

  Thereafter, a silicon nitride film having a thickness of about 5 nm is formed by CVD, and then the surface of the silicon nitride film is oxidized in a wet atmosphere at 800 ° C., and a capacitor dielectric film having a thickness of about 4.5 nm in terms of oxide film 48 is formed.

  Next, a polycrystalline silicon film 50 containing a high concentration of P having a thickness of about 150 nm and a BPSG film 52 having a thickness of about 200 nm are successively formed by CVD, and then the BPSG film is formed by reflow or CMP. The surface of 52 is flattened. At this time, the inside of the through hole 38 is completely filled with the polycrystalline silicon film 50 (FIG. 4B).

  Subsequently, the BPSG film 52 and the polycrystalline silicon film 50 are simultaneously patterned by a normal lithography process and etching process to form a capacitor counter electrode 54.

  Thereafter, a silicon oxide film having a thickness of about 100 nm is deposited by CVD, and then the entire surface is anisotropically etched to form a sidewall oxide film 56 on the side wall of the capacitor counter electrode 46. The body membrane 48 is removed.

As a result, the capacitor counter electrode 54 is covered by the interlayer insulating film 53 made of the sidewall oxide film 56 and the BPSG film, so that the opening formed on the through hole 38 can be used as the bit line contact hole 58. That is, the bit line contact hole 58 can be formed by self-alignment simultaneously with the formation of the sidewall oxide film 56 (FIG. 5A).
Next, a contact hole 59 of the capacitor counter electrode 54 and a through hole 60 such as a peripheral circuit transistor are opened by a normal lithography process and etching process (FIG. 5B).

  Subsequently, a titanium (Ti) film having a film thickness of about 50 nm is continuously formed by sputtering using a collimator, a TiN film having a film thickness of about 50 nm, and a tungsten (W) film having a film thickness of about 200 nm are formed by CVD. Thereafter, the laminated film composed of the W film / TiN film / Ti film is patterned by the normal lithography process and etching process, and the bit line 62 and the wiring layer 68 are formed.

  Next, an interlayer insulating film 64 made of a silicon oxide film having a film thickness of about 1 μm is deposited by CVD, and the surface is planarized by CMP or the like as necessary, and then a via hole 66 is opened.

  Subsequently, a W film is deposited by CVD and then patterned to form a wiring layer 70. The wiring layer 70 may be an aluminum (Al) film deposited by sputtering.

  In this way, a DRAM composed of one transistor and one capacitor can be formed (FIG. 6).

  As described above, according to this embodiment, the lithography process that requires precise pattern formation includes element isolation region definition, gate electrode, capacitor storage electrode through-hole and bit line contact through-hole opening, counter electrode, and periphery. There are a total of 8 steps: circuit through-hole opening, bit line, via hole, and wiring layer. Therefore, compared with the conventional example shown in FIG. 60, the lithography process can be reduced by one process.

  On the other hand, when compared with the conventional example shown in FIG. 59, the number of lithography processes is the same, but in this embodiment, the capacitor storage electrode through hole and the bit line contact through hole are self-aligned with the gate electrode. Since it is formed, the alignment margin can be reduced.

  Further, the through hole for the bit line contact and the through hole for the capacitor storage electrode are formed in a self-aligned manner on the insulating film formed in a self-aligned manner around the gate electrode. There is no need for an alignment margin when forming the through-hole for use, and the memory cell area can be reduced accordingly.

  The capacitor storage electrode and the bit line contact conductive film are formed simultaneously, but the wiring layer embedded in the through hole of the peripheral circuit and the contact conductive film are formed separately, so that the through hole of the peripheral circuit is completely formed. For embedding, the capacitance of the capacitor storage electrode is not sacrificed.

  In the peripheral circuit portion in the above embodiment, since the wiring layer 70 embedded in the via hole 66 is formed via the wiring layer 68 embedded in the through hole 60, the through hole 60 of the peripheral circuit is formed. However, the lithography process can be reduced by using the structure shown in FIG.

In this case, the contact hole 59 for the capacitor counter electrode 54 and the through hole 60 for the peripheral circuit are opened after the interlayer insulating film 64 is formed, and the wiring layer 70 is the source of the capacitor counter electrode 54 and the peripheral circuit transistor. / The drain diffusion layer 34 may be directly contacted.
[Second Embodiment]
Next, a semiconductor memory device and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. The same components as those in the method of manufacturing the semiconductor memory device of the first embodiment shown in FIGS. 3 to 6 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  8 is a plan view showing the structure of the semiconductor memory device according to the present embodiment, FIG. 9 is a schematic diagram showing a cross section of the semiconductor memory device of FIG. 8 taken along the line AA ′, and FIGS. FIG. 14 is a process cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to a modification of the present embodiment.

  In the semiconductor memory device according to the modification of the first embodiment shown in FIG. 7, the process is simplified by embedding the through hole 60 of the peripheral circuit with the wiring layer 70. However, in this case, since the depth of the through hole 60 may reach about 3 μm, it may be difficult to completely fill the through hole.

  The present embodiment provides a structure of a semiconductor memory device and a method for manufacturing the semiconductor memory device that can simplify the manufacturing process in consideration of this point.

  First, the structure of the semiconductor memory device according to the present embodiment will be explained.

  Element regions 14 and 15 defined by the element isolation film 12 are formed on the silicon substrate 10. A source diffusion layer 24 and a drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. Thus, a memory cell transistor composed of the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is formed.

  On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed. Is formed. The gate electrode 20 is formed with an insulating film 42 formed by self-alignment so as to surround the gate electrode 20, and the through hole 38 and the through hole 40 are formed in the insulating film 42 by self-alignment. Yes.

  A capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner and upper surfaces of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed and on the interlayer insulating film 36. Thus, a capacitor including the capacitor storage electrode 46, the capacitor dielectric 48, and the capacitor counter electrode 54 is formed.

  A contact conductive film 44 made of polycrystalline silicon is formed on the inner wall of the through hole 38, and a bit arranged in a direction perpendicular to the word line via an interlayer insulating film 53 formed on the capacitor counter electrode 54. A line 62 is connected.

  Further, a wiring layer 70 is formed on the bit line 62 via an interlayer insulating film 64, and a DRAM including one transistor and one capacitor is formed.

  On the other hand, a source diffusion layer (not shown) and a drain diffusion layer 34 are independently formed in the element region 15 in the peripheral circuit region adjacent to the memory cell region. A gate electrode 22 is formed on the semiconductor substrate 10 between the source diffusion layer and the drain diffusion layer 34 via a gate oxide film 16. Thus, a peripheral circuit transistor including the gate electrode 22, the source diffusion layer 32, and the drain diffusion layer 34 is configured.

  A through hole 60 is formed in the interlayer insulating film 36 on the drain diffusion layer 34 and is connected to the wiring layer 70 formed on the interlayer insulating film 64 via the wiring layer 68 embedded in the through hole 60. Has been.

  The semiconductor memory device according to the present embodiment is different from the semiconductor memory device according to the first embodiment in that the polycrystalline silicon film 50 constituting the capacitor counter electrode 54 and the interlayer insulating film 53 thereabove are formed in the peripheral circuit region. Is that it extends to.

  The advantage of configuring the capacitor counter electrode 54 and the interlayer insulating film 53 in this way is mainly that the manufacturing process can be simplified. The method for manufacturing the semiconductor memory device according to the present embodiment will be described below in detail.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, an ordinary LOCOS method to define element regions 14 and 15. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element regions 14 and 15 by thermal oxidation (FIG. 10A).

  Subsequently, a polycrystalline silicon film containing P at a high concentration is continuously formed by a CVD method to a film thickness of about 150 nm and a silicon nitride film is formed to a film thickness of about 200 nm, and then a normal lithography technique and an etching technique are used. The silicon nitride film and the polycrystalline silicon film are patterned at the same time. Thus, the gate electrodes 20 and 22 whose upper surfaces are covered with the silicon nitride film 18 are formed.

Thereafter, using the silicon nitride film 18 and the gate electrodes 20 and 22 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 40 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , and the source diffusion layer 24 and drain of the memory cell transistor A diffusion layer 26 and a low-concentration diffusion layer 28 for peripheral circuit transistors are formed (FIG. 10B).

Next, a silicon nitride film having a film thickness of about 100 nm is formed by CVD, and then anisotropic etching using CHF ₃ / H ₂ gas is performed to form sidewalls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22. A sidewall nitride film 30 made of a silicon nitride film is formed by self-alignment. As a result, the sidewalls and upper surfaces of the gate electrodes 20 and 22 are covered with the silicon nitride film 18 and the sidewall nitride film 30. Subsequently, using normal lithography technology, for example, As ions are selectively ion-implanted into the N-type transistor region of the peripheral circuit under the conditions of an acceleration energy of 40 keV and an implantation amount of 4 × 10 ¹⁵ cm ^−2. A source diffusion layer and a drain diffusion layer 34 of the transistor are formed. Thus, a peripheral circuit transistor having an LDD structure is formed (FIG. 10C).

  Thereafter, a silicon oxide film of about 2 μm is deposited by the CVD method, and its surface is polished and planarized by the CMP method. Here, the amount of polishing by the CMP method is sufficient if the steps due to the gate electrodes 20 and 22 and the element isolation film 12 can be removed, and in this embodiment, it is 500 nm.

Next, after patterning the photoresist by a normal lithography process, the silicon oxide film is etched using an etching gas such as C ₂ F ₆ . Thereafter, the photoresist is removed, and an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor and a through hole 40 opened on the source diffusion layer 24 of the memory cell transistor are formed. Is formed (FIG. 10D).

  Subsequently, after a polycrystalline silicon film containing P in a high concentration is formed by a CVD method to a thickness of about 50 nm, the polycrystalline silicon film on the interlayer insulating film 36 is completely removed by a CMP method. Thus, the contact conductive film 44 is formed in the through hole 38, and the capacitor storage electrode 46 is formed in the through hole 40 in a self-aligned manner (FIG. 11A).

  Thereafter, a silicon nitride film having a thickness of about 5 nm is formed by CVD, and then the surface of the silicon nitride film is oxidized in a wet atmosphere at 800 ° C., and a capacitor dielectric film having a thickness of about 4.5 nm in terms of oxide film 48 is formed.

  Next, a polycrystalline silicon film 50 containing a high concentration of P having a thickness of about 150 nm and a BPSG film 52 having a thickness of about 200 nm are successively formed by CVD, and then the BPSG film is formed by reflow or CMP. The surface of 52 is flattened. At this time, the through hole 38 is completely filled with the polycrystalline silicon film 50 (FIG. 11B).

  Subsequently, after patterning the photoresist 72 using a positive photoresist by a normal lithography process, the BPSG film 52 and the polycrystalline silicon film 50 are continuously etched to form the capacitor counter electrode 54. . At this time, the polycrystalline silicon film 50 and the BPSG film 52 in the peripheral circuit region open up to the capacitor dielectric film 48 only in the region where the peripheral circuit through hole 60 is formed, and the other regions are not removed (FIG. 12A )).

  Thereafter, without removing the photoresist 72, resist patterning using a negative photoresist is performed to form a photoresist 74 covering the memory cell region. In the patterning of the photoresist 74, it is only necessary to cover the memory cell region, so that a fine alignment accuracy is not required, and the lithography process can be remarkably simplified.

  The reason why the photoresist 74 is formed using a negative photoresist is to prevent inconveniences such as simultaneous peeling of the underlying photoresist 72 when the photoresist 74 is developed. Therefore, immediately after patterning the photoresist 72, UV curing or the like may be performed to cure the photoresist 72, and then patterning may be performed using a positive resist.

  Subsequently, etching is performed using the photoresists 72 and 74 as a mask to completely open the through hole 60 for the peripheral circuit (FIG. 12B).

  After removing the photoresists 72 and 74, a silicon oxide film having a film thickness of about 100 nm is deposited by CVD, and the entire surface is anisotropically etched. As a result, a sidewall oxide film 56 is formed on the sidewall of the capacitor counter electrode 46, and a sidewall oxide film 76 is formed on the inner wall of the through hole 60. At the same time, the capacitor dielectric film 48 on the through hole 38 is removed.

Thereby, the capacitor counter electrode 54 is covered with the interlayer insulating film 53 made of the sidewall oxide film 56 and the BPSG film, so that the opening formed on the through hole 38 can be used as the bit line contact hole 58. That is, the bit line contact hole 58 can be formed by self-alignment simultaneously with the formation of the sidewall oxide film 56 (FIG. 13A).
Subsequently, a Ti film having a film thickness of about 50 nm is successively formed by sputtering using a collimator, a TiN film having a film thickness of about 50 nm, and a W film having a film thickness of about 200 nm are formed by CVD. Thereafter, the laminated film composed of the W film / TiN film / Ti film is patterned by the normal lithography process and etching process, and the bit line 62 and the wiring layer 68 are formed.

  Next, an interlayer insulating film 64 made of a silicon oxide film having a film thickness of about 1 μm is deposited by CVD, and the surface is planarized by CMP or the like as necessary, and then a via hole 66 is opened.

  Subsequently, a W film is deposited by CVD and then patterned to form a wiring layer 70.

  In this way, a DRAM composed of one transistor and one capacitor can be formed (FIG. 13B).

  As described above, according to the present embodiment, when manufacturing a semiconductor memory device, the lithography process that requires precise pattern formation includes element isolation region definition, gate electrode, capacitor storage electrode through hole, and bit line contact. There are a total of 7 steps: through-hole opening, counter electrode, bit line, via hole, and wiring layer. A lithography process that can be simplified by the present embodiment is a through-hole opening process for peripheral circuits. Therefore, compared with the conventional example shown in FIG. 60, the lithography process can be reduced by one process and simplified by one process.

  On the other hand, when compared with the conventional example shown in FIG. 59, as in the first embodiment, it is possible to reduce the alignment margin of the capacitor storage electrode through hole and the bit line contact through hole with respect to the gate electrode.

  In the above embodiment, when opening the through hole in the peripheral circuit region, after forming the photoresist 72 and opening it to the capacitor dielectric film 48, the photoresist 74 is formed without removing the photoresist 72. The through hole 60 is completely opened, but the through hole 60 may be opened by the manufacturing method described below.

  First, as shown in FIG. 11B, after a BPSG film is deposited, a polycrystalline silicon film 78 having a thickness of about 100 nm is deposited by a CVD method.

  Next, after patterning the photoresist 72 by a normal lithography process, the polycrystalline silicon film 78, the BPSG film 52, and the polycrystalline silicon film 50 are successively etched to form the capacitor counter electrode. At this time, the polycrystalline silicon film 50 and the BPSG film 52 in the peripheral circuit region are not removed, and only the peripheral circuit through-hole 60 formation region is opened to the capacitor dielectric film 48 (FIG. 14A).

  After removing the photoresist 72, the photoresist 74 is patterned again by a normal lithography process, and the memory cell region is covered with the photoresist 74.

  Subsequently, the capacitor dielectric film 48 and the interlayer insulating film 36 are etched using the photoresist 74 as a mask, and the through hole 60 is completely opened. At this time, since the polycrystalline silicon film 78 is formed on the interlayer insulating film 53, the interlayer insulating film 53 is not etched when the through hole 60 is etched. Therefore, the patterning of the photoresist 74 does not require fine alignment accuracy, and the lithographic process can be simplified (FIG. 14B).

Although the polycrystalline silicon film 78 remains even after the through hole is opened, there is no inconvenience if it is patterned simultaneously with the bit line 62 formed in the upper layer.
[Third Embodiment]
A semiconductor memory device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 14 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 15 is a schematic cross-sectional view of the semiconductor memory device according to the present embodiment, and FIGS. 16 to 18 are process cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the present embodiment, by using the same structure for the bit line contact portion and the contact portion in the peripheral circuit region, the semiconductor memory device that can further simplify the method of manufacturing the semiconductor memory device according to the first and second embodiments, and A manufacturing method thereof is provided.

  First, the structure of the semiconductor memory device according to the present embodiment will be explained.

  Element regions 14 and 15 defined by the element isolation film 12 are formed on the silicon substrate 10. A source diffusion layer 24 and a drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. Thus, a memory cell transistor composed of the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is formed.

  Note that the gate electrode 20 forms a word line that also functions as a gate electrode of a memory cell transistor in another plurality of memory cells.

  On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed. Is formed. The gate electrode 20 has an insulating film 42 formed in a self-aligned manner so as to surround the gate electrode 20, and the through hole 38 and the through hole 40 are formed in the insulating film 42 in a self-aligned manner. Yes.

  A capacitor storage electrode 46 made of a TiN film is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner and upper surfaces of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. Thus, a capacitor including the capacitor storage electrode 46, the capacitor dielectric 48, and the capacitor counter electrode 54 is formed.

  A contact conductive film 44 made of a TiN film is formed on the inner wall of the through hole 38, and a bit line arranged in a direction perpendicular to the word line via an interlayer insulating film 53 formed on the capacitor counter electrode 54. 62 is connected.

  Further, a wiring layer 70 is formed on the bit line 62 via an interlayer insulating film 64, and a DRAM including one transistor and one capacitor is formed.

  On the other hand, a source diffusion layer (not shown) and a drain diffusion layer 34 are independently formed in the element region 15 in the peripheral circuit region adjacent to the memory cell region. A gate electrode 22 is formed on the semiconductor substrate 10 between the source diffusion layer 32 and the drain diffusion layer 34 with a gate oxide film 16 interposed therebetween. Thus, a peripheral circuit transistor including the gate electrode 22, the source diffusion layer 32, and the drain diffusion layer 34 is configured.

  A through hole 60 is formed in the interlayer insulating film 36 on the drain diffusion layer 34 and the gate electrode 22. A conductive film 80 made of a TiN film is formed on the inner wall and bottom surface of the through hole 60, and the drain diffusion layer 34 and the gate electrode 22 are connected to the wiring layer 68 through the conductive film 80. Yes.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, an ordinary LOCOS method to define element regions 14 and 15. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element regions 14 and 15 by thermal oxidation.

  Subsequently, a polycrystalline silicon film containing P at a high concentration is continuously formed by a CVD method to a film thickness of about 150 nm and a silicon nitride film is formed to a film thickness of about 200 nm, and then a normal lithography technique and an etching technique are used. Then, a part of the silicon nitride film in the peripheral circuit region is removed. This region becomes the gate contact portion 82 when the wiring is later drawn out from the gate electrode 22.

  Next, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using a normal lithography technique and an etching technique to form the gate electrode 20 of the memory cell transistor and the gate electrode 22 of the peripheral circuit.

  The upper surfaces of the gate electrodes 20 and 22 thus formed are covered with the silicon nitride film 18 except for the gate contact portion 82 of the peripheral circuit portion.

Thereafter, using the silicon nitride film 18 and the gate electrodes 20 and 22 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 40 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , and the source diffusion layer 24 and drain of the memory cell transistor A diffusion layer 26 and a low concentration diffusion layer 28 of a peripheral circuit transistor are formed. The low concentration diffusion layer 28 becomes an n ⁻ layer having an LDD structure (FIG. 16A).

Next, a silicon nitride film having a film thickness of about 100 nm is formed by CVD, and then anisotropic etching using CHF ₃ / H ₂ gas is performed to form sidewalls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22. A sidewall nitride film 30 made of a silicon nitride film is formed by self-alignment. As a result, the sidewalls and upper surfaces of the gate electrodes 20 and 22 are covered with the silicon nitride film 18 and the sidewall nitride film 30. Hereinafter, for convenience of explanation, the silicon nitride film 18 and the sidewall nitride film 30 covering the gate electrodes 20 and 22 are collectively referred to as an insulating film 42.

Subsequently, using normal lithography technology, for example, As ions are selectively ion-implanted into the N-type transistor region of the peripheral circuit under the conditions of an acceleration energy of 40 keV and an implantation amount of 4 × 10 ¹⁵ cm ^−2. A source diffusion layer 32 and a drain diffusion layer 34 of the transistor are formed. Thus, a peripheral circuit transistor having an LDD structure is formed (FIG. 16B).

  Thereafter, a silicon oxide film is deposited by about 2.5 μm by the CVD method, and the surface is polished and planarized by about 0.5 μm by the CMP method.

  Instead of the 2.5 μm silicon oxide film, for example, a laminated film of a silicon oxide film of 50 nm and a BPSG film of 2 μm is deposited and the surface is flattened by reflowing the BPSG film in a nitrogen atmosphere at 850 ° C. for about 15 minutes. May be used.

Next, after patterning the photoresist by a normal lithography process, the silicon oxide film is etched using an etching gas such as C ₂ F ₆ .

  Thereafter, the photoresist is removed, and a through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor, a through hole 40 opened on the source diffusion layer 24 of the memory cell transistor, and a through hole 60 in the peripheral circuit region are formed. The formed interlayer insulating film 36 is formed (FIG. 16C).

  The drain diffusion layer 26 and the source diffusion layer 24 are exposed at the bottom portions of the through hole 38 and the through hole 40 formed in this way, respectively, but the regions where the drain diffusion layer 26 and the source diffusion layer 24 are exposed are as follows. Since it is formed in a self-aligned manner with respect to the insulating film 42, it is not necessary to consider an alignment margin with respect to the gate electrode 20 when patterning the through holes 38 and 40. Accordingly, the area of the memory cell can be reduced by the amount of alignment margin.

  On the other hand, the gate electrode 22 of the peripheral circuit transistor and the drain diffusion layer 34 are exposed at the bottom of the through hole 60. In the gate contact portion 82 that opens the through hole 60, since the insulating film 42 on the gate electrode 22 is removed in advance, the through hole 60 is opened at the same time as the through hole 38 and the through hole 40. The gate electrode 22 can be exposed in the hole 60.

  Subsequently, after a Ti film having a thickness of about 10 nm and a TiN film having a thickness of about 20 nm are successively formed by the CVD method, the TiN film and the Ti film on the interlayer insulating film 36 are completely removed by the CMP method. As a result, the contact conductive film 44 is formed in the through hole 38, the capacitor storage electrode 46 is formed in the through hole 40, and the conductive film 80 is formed in the through hole 60 in the peripheral circuit portion in a self-aligned manner (FIG. 17). (A)).

  When the conductive film 80 is formed, a TiN film may be grown by a CVD method after depositing a Ti film mainly at the bottom of the through hole by a collimated sputtering method with many sputter components in the vertical direction.

  Further, when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80, the photoresist is left in the through hole 38, the through hole 40, and the through hole 60 by using a lithography technique instead of the CMP method. Thereafter, the Ti film and the TiN film may be removed by etching using this photoresist as a mask.

  The electrical resistance of the conductive film 80 embedded in the through hole 60 in the peripheral circuit portion is very important because it affects the operation speed of the peripheral circuit. However, the conductive film 80 thus formed has a sheet resistance of about 30Ω / □, the depth of the through hole 60 is about 2 μm, and the peripheral length of the through hole 60 is about 0.8 μm. The resistance is about 75Ω, which is a sufficiently low value.

  Next, a silicon nitride film having a thickness of about 5 nm is formed at a low temperature of about 650 ° C. by CVD, and then heat-treated in a wet atmosphere at 700 ° C. and 4 atm for 10 minutes to oxidize the surface of the silicon nitride film, thereby A body film 48 is formed.

  By this heat treatment, the Ti film at the bottom of the through hole 38, the through hole 40, and the through hole 60 undergoes a silicidation reaction with the underlying source / drain diffusion layers 24, 26, 32, 34 or the gate electrode 22, so Is reduced.

  The heat treatment for forming the capacitor dielectric film 48 used high-pressure oxidation at a low temperature as described above. This is because, when the TiN film and the silicon nitride film react with each other by the high temperature heat treatment, the dielectric breakdown voltage of the capacitor dielectric film 48 may be deteriorated, so that high pressure oxidation that can lower the heat treatment temperature is desirable.

  Next, a polycrystalline silicon film 50 containing P at a high concentration and a silicon oxide film 52 of about 200 nm in thickness are continuously formed by CVD. Thus, the through hole 38, the through hole 40, and the through hole 60 are filled.

  Subsequently, the silicon oxide film 52 and the polycrystalline silicon film 50 are simultaneously patterned by a normal lithography process and etching process to form a capacitor counter electrode 54 (FIG. 17B).

  Although the silicon oxide film 52 and the polycrystalline silicon film 50 remain embedded in the through holes 38 and 60, these films only contribute to flattening and do not cause any adverse effects.

  Further, as the material of the capacitor counter electrode 54, a TiN film deposited by a CVD method may be used. However, in this embodiment, the dielectric film is damaged during the growth of the TiN film using a chlorine-based reaction gas. Since there is a concern, the polycrystalline silicon film 50 was used.

  Thereafter, a silicon oxide film having a thickness of about 100 nm is deposited by CVD, and the entire surface is anisotropically etched to form a sidewall oxide film 56 on the side wall of the capacitor counter electrode 54. At the same time, a capacitor dielectric on the through hole 38 is formed. The film 48 is removed.

As a result, the capacitor counter electrode 54 is covered with the sidewall oxide film 56 and the interlayer insulating film 53, so that the opening formed on the through hole 38 can be used as the bit line contact hole 58. That is, the bit line contact hole 58 can be formed by self-alignment simultaneously with the formation of the sidewall oxide film 56 (FIG. 18A).
Subsequently, a titanium Ti film having a film thickness of about 50 nm is continuously formed by sputtering using a collimator, a TiN film having a film thickness of about 50 nm, and a W film having a film thickness of about 200 nm are formed by CVD. Thereafter, the laminated film composed of the W film / TiN film / Ti film is patterned by the normal lithography process and etching process, and the bit line 62 and the wiring layer 68 are formed.

  Next, an interlayer insulating film 64 made of a silicon oxide film having a film thickness of about 1 μm is deposited by CVD, and the surface is planarized by CMP or the like as necessary, and then a via hole 66 is opened.

  Subsequently, a W film is deposited by CVD and then patterned to form a wiring layer 70.

  In this way, a DRAM composed of one transistor and one capacitor can be formed (FIG. 18B).

  As described above, according to the present embodiment, by using a low-resistance material for the conductive film that fills the through-hole connecting the bit line and the memory cell transistor, the through-hole in the peripheral circuit and the through-hole in the memory cell region are formed. Since the structure can be made the same, the number of lithography processes can be reduced by one.

  Therefore, the lithography process that requires precise pattern formation is a total of seven processes: element isolation region definition, gate electrode, through hole opening, counter electrode, bit line, via hole, and wiring layer. Therefore, compared with the conventional example shown in FIG. 60, the number of lithography processes can be reduced by two.

  On the other hand, in comparison with the conventional example shown in FIG. 59, the number of lithography processes can be reduced by one process, and in this embodiment, the capacitor storage electrode through hole and the bit line contact through hole are self-aligned with the gate electrode. As a result, the margin for alignment can be reduced. Moreover, since the thickness of the capacitor storage electrode can be reduced, it is possible to prevent a decrease in the capacitor capacity.

In the above embodiment, the semiconductor memory device is configured using a TiN film as a capacitor storage electrode, a SiN film as a capacitor dielectric film, and a polycrystalline silicon film as a capacitor counter electrode. For example, K. Koyama (Technical Digest IEDM 1992, p. 823 (1992)), H. Shinriki (IEEE Trans., Electron Devices, Vol. 38 No. 3, p. 455 (1991)), Ta ₂ O ₅ film and A high-ferroelectric film such as a (Ba _x Sr _1-x ) TiO ₃ film is used as a capacitor dielectric film, and the capacitor storage electrode and the capacitor are opposed to each other by W or Pt which are electrode materials that can be used for the dielectric film. You may comprise a capacitor using an electrode.

  If a capacitor is formed of a high-ferroelectric film in this way, a sufficient capacitor capacity can be secured even if the surface area of the capacitor electrode is reduced. Therefore, the above dielectric material having the highest dielectric constant is used. In this case, the depth of the through hole can be reduced to about 0.2 μm, which is extremely effective.

In the above embodiment, a laminated film of a Ti film and a TiN film is used as the capacitor storage electrode and the capacitor counter electrode. However, other materials may be used as long as the conductive film can sufficiently reduce the contact resistance.
[Fourth Embodiment]
A semiconductor memory device and a manufacturing method thereof according to the fourth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device and the manufacturing method thereof according to the third embodiment shown in FIGS. 15 to 18 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 19 is a schematic cross-sectional view of the semiconductor memory device according to the present embodiment, and FIGS. 20 and 21 are process cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the first to third embodiments, when the through hole 38, the through hole 40, and the like are opened, the interlayer insulating film 36 having a film thickness of about 2 μm is performed by a single etching process. In an actual manufacturing process, it is normal to perform over-etching corresponding to the film thickness of the interlayer insulating film in consideration of film thickness variations at the time of film formation. Therefore, considerable over-etching is required to etch the interlayer insulating film 36 having a thickness of about 2 μm.

  On the other hand, when opening the through hole 38, the through hole 40, etc., the insulating film 42 is used as an etching stopper to form a self-aligned contact. However, the silicon nitride film formed in the stepped portion like the insulating film 42 has a lower etching selectivity with respect to the silicon oxide film than the silicon nitride film formed in the flat portion. In particular, the etching of the insulating film 42 easily proceeds at the edge portions of the gate electrodes 20 and 22.

  Therefore, when the through hole 38, the through hole 40, etc. are opened in the thick interlayer insulating film, the insulating film 42 is etched by excessive over-etching, and the gate electrodes 20, 22 are exposed, for example, embedded in the through hole 38. The contact conductive film and the gate electrode 20 may be short-circuited.

  Thus, the formation of the through hole 38 and the through hole 40 is one of the most difficult manufacturing steps in the present invention.

  In the present embodiment, a semiconductor memory device that can easily form the through hole 38 and the through hole 40 and a manufacturing method thereof will be described in consideration of the above-described problems.

  The semiconductor memory device according to the present embodiment is characterized in that the interlayer insulating film formed between the bit line 62 and the silicon substrate 10 is an insulating film having a three-layer structure.

  That is, a silicon oxide film 84, a silicon nitride film 86, and a silicon oxide film 88 are sequentially stacked on the semiconductor substrate 10 on which the memory cell transistor including the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is formed. An interlayer insulating film 36 is formed.

  A through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed in the interlayer insulating film 36.

  A capacitor storage electrode 46 made of a TiN film is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner and upper surfaces of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed and on the interlayer insulating film 36. Thus, a capacitor including the capacitor storage electrode 46, the capacitor dielectric 48, and the capacitor counter electrode 54 is formed.

  A contact conductive film 44 made of a TiN film is formed on the inner wall of the through hole 38, and a bit line arranged in a direction perpendicular to the word line via an interlayer insulating film 53 formed on the capacitor counter electrode 54. 62 is connected.

  Further, a wiring layer 70 is formed on the bit line 62 via an interlayer insulating film 64, and a DRAM including one transistor and one capacitor is formed.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method to define an element region 14. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element region 14 by thermal oxidation.

  Subsequently, a polycrystalline silicon film containing a high concentration of P having a thickness of about 150 nm and a silicon nitride film having a thickness of about 200 nm are successively formed by CVD, and then a normal lithography technique and an etching technique are used. A part of the silicon nitride film in the peripheral circuit region is removed. This region becomes the gate contact portion 82 when the wiring is later drawn out from the gate electrode 22.

  Next, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using a normal lithography technique and an etching technique to form the gate electrode 20 of the memory cell transistor and the gate electrode 22 of the peripheral circuit.

Thereafter, using the silicon nitride film 18 and the gate electrodes 20 and 22 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 40 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , and the source diffusion layer 24 and drain of the memory cell transistor A diffusion layer 26 and a low-concentration diffusion layer 28 for peripheral circuit transistors are formed (FIG. 20A).

Next, a silicon nitride film having a film thickness of about 100 nm is formed by CVD, and then anisotropic etching using CHF ₃ / H ₂ gas is performed to form sidewalls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22. A sidewall nitride film 30 made of a silicon nitride film is formed by self-alignment.

Subsequently, using normal lithography technology, for example, As ions are selectively ion-implanted into the N-type transistor region of the peripheral circuit under the conditions of an acceleration energy of 40 keV and an implantation amount of 4 × 10 ¹⁵ cm ^−2. A source diffusion layer 32 and a drain diffusion layer 34 of the transistor are formed (FIG. 20B).

  Thereafter, a silicon oxide film 84 is deposited by about 1 .mu.m by the CVD method, and the surface is polished and planarized by about 0.7 .mu.m by the CMP method. Next, a silicon nitride film 86 and a silicon oxide film 88 are continuously grown by CVD using a thickness of 20 nm and 1.8 μm, respectively.

Next, after patterning the photoresist 90 by a normal lithography process, the silicon oxide film 88 is etched using an etching gas such as C ₂ F ₆ . Here, since the silicon nitride film 86 is deposited on the flattened silicon oxide film 84 and a selection ratio of about 100 with respect to the silicon oxide film can be secured, it is sufficient as an etching stopper when the silicon oxide film 88 is etched. It can be used (FIG. 20 (c)).

Subsequently, using the same photoresist 90 as a mask, the silicon nitride film 86 is etched using CHF ₃ / CF ₄ / Ar as an etching gas, and then the silicon oxide film 84 is etched using C ₂ F ₆ as an etching gas.

  Thereafter, the photoresist is removed, and a through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor, a through hole 40 opened on the source diffusion layer 24 of the memory cell transistor, and a through hole 60 in the peripheral circuit region are formed. The formed interlayer insulating film 36 is formed (FIG. 21A).

  Thereafter, for example, capacitors, bit lines, wiring layers, etc. are formed by the manufacturing process shown in FIG. 17A and subsequent drawings of the third embodiment, and a DRAM comprising one transistor and one capacitor shown in FIG. To do.

As described above, according to the present embodiment, etching of a very deep opening is divided into two stages, so that each etching can be performed relatively easily. In particular, since the film thickness of the silicon oxide film 84 etched in the etching process of the silicon oxide film 84 that diffuses the source diffusion layers 24 and 32 and the drain diffusion layers 26 and 34 can be remarkably reduced, the side surfaces of the gate electrodes 20 and 22 are insulated. The film loss of the element isolation film 12 when the element isolation film 12 is exposed in the opening due to misalignment or the like in the lithography process can be suppressed.
[Fifth Embodiment]
A semiconductor memory device and a manufacturing method thereof according to the fifth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device and the manufacturing method thereof according to the third embodiment shown in FIGS. 15 to 18 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 22 is a schematic cross-sectional view of the semiconductor memory device according to the present embodiment. FIGS. 23 and 24 are process cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the third embodiment, the through hole 38, the through hole 40, and the through hole 60 are opened in the interlayer insulating film 36, and then a Ti film and a TiN film are deposited by the CVD method or the collimated sputtering method, and the capacitor storage electrode 54 is formed. Etc. formed.

  Here, since the deposited Ti film reacts with the underlying silicon substrate 10 by a subsequent heat treatment to form a titanium silicide film, it is indispensable to enable ohmic contact, and the through-hole 38, It must be deposited on the bottom of the through hole 40 and the through hole 60.

  However, when the integration of elements progresses and these through holes become fine and deep, it is difficult to bury the Ti film in this way.

  In the present embodiment, a semiconductor memory device that can solve the above problems and a method for manufacturing the same will be described.

  The semiconductor memory device according to the present embodiment is characterized in that a buried conductor 92 is formed at the bottom of the through hole 38, the through hole 40, and the through hole 60 through hole.

  That is, a silicon oxide film 84, a silicon nitride film 86, and a silicon oxide film 88 are sequentially stacked on the semiconductor substrate 10 on which the memory cell transistor including the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is formed. An interlayer insulating film 36 is formed.

  A through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed in the interlayer insulating film 36.

  A buried conductor 92 made of Ti and TiN is formed at the bottom of the through hole 38 and the through hole 40.

  A capacitor storage electrode 46 made of a TiN film is formed on the inner wall of the through hole 40 and the embedded conductor 92, and is connected to the source diffusion layer 24 through the embedded conductor 92. A capacitor dielectric film 48 is formed on the inner and upper surfaces of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed and on the interlayer insulating film 36. Thus, a capacitor including the capacitor storage electrode 46, the capacitor dielectric 48, and the capacitor counter electrode 54 is formed.

  A contact conductive film 44 made of a TiN film is formed on the inner wall of the through hole 38 and the embedded conductor 92, and the drain diffusion layer 26 and the bit line 62 are connected via the embedded conductor 92.

  Further, a wiring layer 70 is formed on the bit line 62 via an interlayer insulating film 64, and a DRAM including one transistor and one capacitor is formed.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method to define an element region 14. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element region 14 by thermal oxidation.

  Subsequently, a polycrystalline silicon film containing a high concentration of P having a thickness of about 150 nm and a silicon nitride film having a thickness of about 200 nm are successively formed by CVD, and then a normal lithography technique and an etching technique are used. A part of the silicon nitride film in the peripheral circuit region is removed. This region becomes the gate contact portion 82 when the wiring is later drawn out from the gate electrode 22.

  Next, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using a normal lithography technique and an etching technique to form the gate electrode 20 of the memory cell transistor and the gate electrode 22 of the peripheral circuit.

Thereafter, using the silicon nitride film 18 and the gate electrodes 20 and 22 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 40 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , and the source diffusion layer 24 and drain of the memory cell transistor The diffusion layer 26 and the low-concentration diffusion layer 28 of the peripheral circuit transistor are formed (FIG. 23A).

Next, a silicon nitride film having a film thickness of about 100 nm is formed by CVD, and then anisotropic etching using CHF ₃ / H ₂ gas is performed to form sidewalls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22. A sidewall nitride film 30 made of a silicon nitride film is formed by self-alignment.

Subsequently, using normal lithography technology, for example, As ions are selectively ion-implanted into the N-type transistor region of the peripheral circuit under the conditions of an acceleration energy of 40 keV and an implantation amount of 4 × 10 ¹⁵ cm ^−2. A source diffusion layer 32 and a drain diffusion layer 34 of the transistor are formed (FIG. 23B).

  Thereafter, a silicon oxide film 84 is deposited by about 1 .mu.m by the CVD method, and the surface is polished and planarized by about 0.7 .mu.m by the CMP method. Next, a silicon nitride film 86 is grown to a thickness of about 100 nm by CVD.

Next, after patterning a photoresist (not shown) by a normal lithography process, the silicon nitride film 86 is etched using CHF ₃ / CF ₄ / Ar as an etching gas, and then C ₂ F ₆ is used as an etching gas. The silicon oxide film 84 is etched. As a result, the source diffusion layers 24 and 32 and the drain diffusion layers 26 and 34 are exposed.

  Subsequently, a Ti film of 10 nm is continuously formed by collimated sputtering and a TiN film of 200 nm is continuously formed by CVD, and is embedded on the source diffusion layers 24 and 32 and the drain diffusion layers 26 and 34. Thereafter, the Ti film and the TiN film on the silicon nitride film 86 are removed by CMP to form a buried conductor 92 (FIG. 23C).

Next, a silicon oxide film 88 having a thickness of about 2 μm is grown by the CVD method, and after patterning the photoresist by a normal lithography process, the silicon oxide film 88 is etched using an etching gas such as C ₂ F _6. . At this time, if C ₂ F ₆ gas is used as the etching gas, the etching can be automatically stopped at the buried conductor 92 or the silicon nitride film 86.

  Subsequently, the photoresist is removed, and a through hole 38 opened on the buried conductor 92 on the drain diffusion layer 26 of the memory cell transistor and an opening on the buried conductor 92 on the source diffusion layer 24 of the memory cell transistor are opened. The interlayer insulating film 36 in which the through hole 40 and the through hole 60 in the peripheral circuit region in which the buried conductor 92 is formed at the bottom is formed is formed (FIG. 24A).

  Thereafter, capacitors, bit lines, wiring layers, etc. are formed in the same manner as in the manufacturing process shown in FIG. 17A and subsequent figures of the third embodiment, and a DRAM comprising one transistor and one capacitor shown in FIG. Configure.

  As described above, according to the present embodiment, when forming a through hole having a large aspect ratio or the like, an ohmic contact is formed by previously forming a buried conductor in a region in contact with the silicon substrate. The contact characteristics at the bottom of the through hole can be ensured even when these through holes become fine and deep.

  In the above-described embodiment, the buried conductor 92 is formed by adding one lithography process. For example, the salicide process (SALICIDE: Self-ALIgned siliCIDE; (1990)), a contact conductor can be formed at the bottom of the through hole without adding a lithography process.

  That is, after forming the insulating film 42 covering the gate electrodes 20 and 22, a Ti film, for example, is deposited on the entire surface of the semiconductor substrate 10 by sputtering. Thereafter, when heat treatment is performed, a silicidation reaction occurs only in a region where the silicon of the semiconductor substrate 10 and the deposited Ti film are in direct contact, for example, on the source diffusion layer 24 and the drain diffusion layers 26 and 34.

  Next, if the unreacted Ti film is removed by aqua regia, for example, a titanium silicide film can be formed on the source diffusion layer 24 and the drain diffusion layers 26 and 34 in a self-aligning manner.

  After the titanium silicide film is formed on the source / drain diffusion layer in this manner, a semiconductor substrate device is manufactured in the same manner as the semiconductor memory device manufacturing method described in any of the first to fourth embodiments. When forming a through hole having a large aspect ratio, contact characteristics at the bottom of the through hole can be ensured.

As another metal film applicable to the salicide process, for example, Ta (tantalum), W (tungsten), Mo (molybdenum), or the like can be used.
[Sixth Embodiment]
A semiconductor memory device and a manufacturing method thereof according to the sixth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 25 is a schematic sectional view showing the structure of the semiconductor memory device according to the present embodiment, and FIGS. 26 to 28 are process sectional views showing the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the method of manufacturing the semiconductor memory device according to the first embodiment, as shown in FIG. 4A, when forming the contact conductive film 44 and the capacitor storage electrode 46, polycrystalline silicon containing P at a high concentration is formed. After forming the film, the polycrystalline silicon film on the interlayer insulating film 36 was removed by CMP.

  However, if the polishing is simply performed, the dust generated during the polishing may enter the through holes 38 and 40, which may reduce the yield.

  In the semiconductor memory device according to the first embodiment, the contact conductive film 44 and the capacitor storage electrode 46 are formed of the same film. Therefore, if the contact conductive film 44 is thickened, the inner surface of the through hole 40 of the capacitor storage electrode 46 is increased. The surface area is reduced. For this reason, in order to reduce the resistance value of the contact conductive film 44, the capacitor capacity is sacrificed.

  If the depth is about 256 MDRAM, the depth of the through hole 40 can be set to 2 μm or less, so the resistance of the conductive film for contact 44 does not matter, but the degree of integration is further improved and the through hole 40 is deepened. When the thickness of the contact conductive film 44 is reduced, the accompanying increase in resistance of the contact conductive film 44 becomes a serious problem.

  In the present embodiment, in the polishing step when forming the contact conductive film 44 and the capacitor storage electrode 46, it is possible to prevent the powdery matter from remaining in the through holes 38 and 40 and to sacrifice the capacitor capacity. Provided are a semiconductor memory device and a method for manufacturing the semiconductor memory device that can reduce the resistance of the contact conductive film 44 without any problem.

  The semiconductor memory device according to the present embodiment is characterized in that the columnar conductors 112 and 114 are formed in the through holes 38 and 40, respectively.

  That is, in the through hole 38, a columnar conductor 112 is formed which is connected to the contact conductive film 44 at the bottom and has a capacitor dielectric film 48 formed on the side wall thereof. A columnar conductor 114 is formed which is connected to the capacitor storage electrode 46 at the bottom and has a capacitor dielectric film 48 formed on the side wall thereof.

  By providing the columnar conductor in this way, in the through hole 38, the electrical path connecting the drain diffusion layer 26 and the bit line 62 is configured by the contact conductive film 44 and the columnar conductor 112. The electric resistance in the bit line contact portion can be greatly reduced.

  Further, by providing the columnar conductor 114 in the through hole 40, the capacitor dielectric film 48 is also formed on the side wall portion thereof, so that the area of the capacitor is increased and the capacitor capacity can be greatly increased.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, in the same manner as in the method of manufacturing the semiconductor memory device according to the first embodiment shown in FIGS. 3A to 3D, a through hole 38 is formed on the drain diffusion layer 26, and the source diffusion layer 24 is formed. Then, an interlayer insulating film 36 in which a through hole 40 is formed is formed (FIG. 26A). The size of the through hole 38 is, for example, 0.3 × 0.3 μm, and the size of the through hole 40 is, for example, 0.3 × 0.6 μm.

  Next, a polycrystalline silicon film 106 containing P at a high concentration is formed by a CVD method to a thickness of about 30 nm.

  Subsequently, for example, a silicon oxide film is grown to a thickness of about 80 nm by a CVD method using TEOS (tetraethoxysilane: ethyl orthosilicate) as a main raw material gas, and then the entire surface is etched in the vertical direction by the RIE method to form the sidewall 108. It forms (FIG.26 (b)).

  As a result, a gap of [300-2 × (30 + 80)] × [300-2 × (30 + 80)] nm, that is, 80 × 80 nm remains in the through hole 38, and [300] −2 × (30 + 80)] × [600−2 × (30 + 80)] nm, that is, a gap of 80 × 380 nm remains.

  Thereafter, a polycrystalline silicon film 110 having a thickness of about 200 nm is deposited by the CVD method (FIG. 27A). The film thickness of the deposited polycrystalline silicon film 110 is preferably set so that the gaps in the through holes 38 and 40 are completely filled and the whole becomes substantially flat.

  Next, the entire surface is polished by a CMP method. At this time, some over-polishing is performed so that the upper surface of the sidewall 108 is completely exposed. As a result, the contact conductive film 44 made of the polycrystalline silicon film 106, the columnar conductor 112 made of the polycrystalline silicon film 110, and the sidewall 108 are completely embedded in the through hole 38. Inside, the capacitor storage electrode 46 made of the polycrystalline silicon film 106, the columnar conductor 114 made of the polycrystalline silicon film 110, and the sidewall 108 are completely buried, and the surface is flattened ( FIG. 27 (b)).

Subsequently, the sidewall 108 is selectively removed by immersing the substrate in a solution of HF: NH ₄ F = 1: 5, for example. As a result, a gap 116 is formed in the through holes 38 and 40 (FIG. 28A).

  Thereafter, the capacitor dielectric film 48, the capacitor counter electrode 54, the bit line 62, and the like are performed by the same procedure as that of the method for manufacturing the semiconductor memory device according to the first embodiment shown in FIG. 4B to FIG. Wiring 70 and the like are formed (FIG. 28B).

  Thus, according to the present embodiment, by forming the columnar conductor 114 in the through hole 40, the columnar conductor 114 also functions as the capacitor storage electrode in addition to the capacitor storage electrode 46. Therefore, the columnar conductor The capacitor surface area can be increased by the 114 surface area. Therefore, even when the same capacitance value as that of the semiconductor memory device shown in FIG. 1 is obtained, the depth of the through hole 40 can be reduced.

  In addition, since the lead electrode of the bit line contact portion is formed by the contact conductive film 44 and the columnar conductor 112, the resistance of the lead electrode can be reduced. Further, since the capacitor capacity can be increased as described above, the through hole 38 can be shallowed, and the resistance of the extraction electrode can be further reduced.

In the semiconductor memory device according to the present embodiment, the peripheral circuit contact hole 60 is formed by the same structure as that of the semiconductor memory device according to the modification of the first embodiment shown in FIG. May be. For example, as in the semiconductor memory device according to the first embodiment shown in FIG. 2, the via hole 66 may be opened on the wiring layer 68 to form the wiring layer 70.
[Seventh Embodiment]
A semiconductor memory device and a manufacturing method thereof according to the seventh embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  29 is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment, and FIGS. 30 and 31 are process cross-sectional views showing the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the semiconductor memory device according to the modification of the first embodiment shown in FIG. 7, the through hole 60 of the peripheral circuit is opened after the interlayer insulating film 64 is formed, and the wiring layer 70 is the capacitor counter electrode 54 and the source of the peripheral circuit transistor. The lithography process is reduced by the configuration in which the / drain diffusion layer 34 is in direct contact.

  However, since the wiring layer 70 needs to be simultaneously connected to the source / drain diffusion layer 34 of the peripheral circuit transistor, the capacitor counter electrode 54, the bit line 62, etc., the depth of the through hole 60, the contact hole 59, etc. is extremely high. They range from deep to shallow.

  In such hole etching with remarkably different depths, it takes a long time until the source / drain diffusion layer 34 of the peripheral circuit transistor is exposed after the surface of the bit line 62 and the counter electrode 54 is exposed. The bit line 62 and the counter electrode surface continue to be exposed to the etching gas. In particular, when the bit line 62 is formed of a columnar crystal metal thin film such as tungsten, damage such as etching of the underlying insulating film enters through the gap between the crystals, resulting in a short circuit between the bit line 62 and the silicon substrate 10. There is a risk of it.

  The present embodiment provides a semiconductor memory device and a method for manufacturing the semiconductor memory device that can simultaneously form through holes of various depths.

  In the semiconductor memory device according to the present embodiment, the interlayer insulating film 53 made of a film having different etching characteristics from the interlayer insulating films 64 and 36 is formed on the capacitor counter electrode 54, and the bit line 62 and the upper wiring layer 70 are formed. An etching stopper made of a laminated film 118 of a conductive film 124 and an insulating film 126 having different etching characteristics from that of the interlayer insulating films 64 and 36 is disposed below the bit line 62 in a region where the contact hole 120 is connected. It is characterized by being.

  That is, the wiring layer 70 formed on the interlayer insulating film 64 is connected to the gate electrode 22 of the peripheral circuit transistor through the through hole 122 and is connected to the source / drain diffusion layer of the peripheral circuit transistor through the through hole 60. 34, is connected to the capacitor counter electrode 54 via the contact hole 59, and is connected to the bit line 62 via the contact hole 120. An interlayer insulating film 53 made of a silicon nitride film is formed on the capacitor counter electrode 54. A laminated film 118 composed of a conductive film 124 and an insulating film 126 made of a silicon nitride film is disposed below the contact hole 120 opened on the bit line 62.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

  First, the capacitor counter electrode 54 is formed by a procedure similar to the method of manufacturing the semiconductor memory device according to the first embodiment shown in FIGS. 3A to 5A. At this time, the conductive film 124 formed of the same film as the capacitor counter electrode 54 and the insulating film formed of the same film as the interlayer insulating film 53 are formed in the region where the contact between the bit line and the upper wiring layer is to be formed. A laminated film 118 made of 126 is disposed in advance (FIG. 30A). The interlayer insulating film 53 is formed of a material having a different etching characteristic from the interlayer insulating film 36 and the interlayer insulating film 64 deposited on the upper layer, for example, a silicon nitride film.

  Next, after an interlayer insulating film 64 is deposited on the entire surface to planarize the surface, a photoresist 72 in which a pattern of through holes and contact holes is formed is formed by a normal lithography technique.

  Subsequently, the interlayer insulating film 64 and the interlayer insulating film 36 are etched using the photoresist 72 as a mask. The etching of the interlayer insulating films 64 and 36 is performed under a condition that allows a sufficient selection ratio with respect to the interlayer insulating film 53.

  At this time, the contact hole 59 formed on the capacitor counter electrode 54 and the contact hole 120 formed on the bit line 62 include the through-hole 60 opened on the source / drain diffusion layer 36 of the peripheral circuit transistor and the peripheral circuit. Since it is shallower than the through hole 122 opened on the gate electrode 22 of the transistor, the interlayer insulating film 64 on the bit line 62 is completely removed before the through holes 60 and 122 are completely opened, and the surface of the bit line 62 is removed. Are exposed to an etching gas. Although the interlayer insulating film 53 is exposed on the capacitor counter electrode 54, the interlayer insulating film 53 is formed of a silicon nitride film having etching characteristics different from that of the interlayer insulating film 64 made of a silicon oxide film, and is hardly etched. (FIG. 30 (b)).

  Further, by continuing the etching, the source / drain diffusion layer 36 of the peripheral circuit transistor is exposed (FIG. 31A). At this time, if the bit line 62 is formed of a columnar crystal material, for example, a tungsten film, the etching may reach the lower layer film at the crystal boundary. In FIG. 31A, this is emphasized and expressed so that the bit line 62 itself disappears. However, since an insulating film 126 made of a silicon nitride film is formed below the bit line 62, The interlayer insulating film 36 is not damaged.

Next, the silicon nitride film is removed by etching using, for example, CF ₄ / CHF ₃ / He gas. As a result, the interlayer insulating film 53 on the capacitor counter electrode 54 and the insulating film 42 on the gate electrode 22 of the peripheral circuit transistor are removed, and the through holes 60 and 122 and the contact holes 59 and 120 are completely opened (see FIG. 31 (b)). At this time, the insulating film 126 under the bit line 62 is also removed, but the etching is stopped by the conductive film 124 thereunder.

  Note that the etching gas used here has a slow etching rate of silicon and the remaining silicon nitride film is not thick, so that the etching time can be set short. Therefore, the etching of the already exposed source / drain diffusion layer 36 of the peripheral circuit transistor is negligible.

  In this way, all through holes and contact holes can be formed without inconvenience.

As described above, according to the present embodiment, the laminated film 118 is formed in advance in the region where the contact between the bit line 62 and the upper wiring layer is formed, whereby the deep through holes 60 and 120 in the peripheral circuit are formed. Also during the formation, the interlayer insulating film 36 under the bit line 62 is not etched, and a short circuit between the bit line 62 and the semiconductor substrate 10 or the like can be prevented.
[Eighth Embodiment]
A semiconductor memory device and a method for manufacturing the same according to an eighth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 32 is a diagram for explaining the problems in the method of manufacturing the semiconductor memory device according to the first embodiment, FIG. 33 is a plan view showing the structure of the semiconductor memory device according to the present embodiment, and FIG. 34 is the structure of the semiconductor memory device according to the present embodiment. FIG. 35 to FIG. 38 are process cross-sectional views illustrating the method of manufacturing the semiconductor memory device according to the present embodiment.

  In the method of manufacturing the semiconductor memory device according to the first embodiment shown in FIGS. 3 to 6, the contact conductive film 44 and the capacitor storage electrode 46 are formed in self-alignment with the gate electrode 20 of the memory cell transistor. According to this method, there is no need to consider the alignment margin between the gate electrode 20 and the through hole 38, and there is an advantage that the memory cell area can be reduced.

  However, when the memory cell is miniaturized, the depth of the through hole 38 increases rapidly, and etching of the through hole becomes difficult rapidly. The problems in the semiconductor memory device according to the first embodiment will be described below.

  When the silicon nitride film 18 is deposited on the polycrystalline silicon film 128 to be the gate electrode 20 in the process of manufacturing the semiconductor memory device shown in FIGS. If the dust 130 is attached, the silicon nitride film 18 grown thereon is swollen in a region where the dust 130 is attached (FIG. 32A).

  When the silicon nitride film 18 is etched using the photoresist 72 processed into the pattern of the gate electrode 20 as a mask, the film around the dust 130 swells, and a part thereof remains as a residue 132 (FIG. 32B). .

  If the underlying polycrystalline silicon film 128 is etched in this state, the residue 132 acts as a mask, and a part of the polycrystalline silicon film 128 remains as the residue 134 (FIG. 32C).

  Thereafter, when the through holes 38 and 40 are formed in the same manner as in the method of manufacturing the semiconductor memory device shown in FIGS. 3B to 3D, the residue 134 is exposed in the through holes 38, and finally This causes a short circuit with the contact conductive film 44 (FIG. 32D).

  As described above, the structure of the semiconductor memory device according to the first embodiment is very sensitive to dust, which may cause a decrease in yield. If the yield is simply reduced, it can be remedied by a method such as redundancy, but a short circuit between the bit line 62 and the word line 20 becomes a serious problem. That is, during standby, the potential of the bit line 62 is set to half of the power supply voltage, and the potential of the word line 20 is set to zero, so that a constant current flows from the bit line 62 to the word line 20. Become. As a result, the current consumption during standby increases, and repair cannot be performed with normal redundancy.

  In the present embodiment, a semiconductor memory device and a manufacturing method capable of solving the problems of the first embodiment as described above are provided.

  As shown in the plan view of FIG. 33 and the cross-sectional view of FIG. 34, the semiconductor memory device according to the present embodiment has a fine through hole 38 connecting the bit line 62 and the drain diffusion layer 26 and a contact between the capacitor storage electrode 46. The capacitor storage electrode 36 is characterized by being formed in a large opening 142 opened on the through hole 40.

  With this configuration, the contact conductive film 44 embedded in the through hole 38 can be formed sufficiently away from the gate electrode 20, so that the short circuit between the gate electrode 20 and the bit line 62 is greatly reduced. Can be reduced.

  Further, since the polycrystalline silicon film 140 buried in the through hole 40 exists as a columnar protrusion in the opening 142, the capacitance of the capacitor can be increased.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method to define an element region 14. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element region 14 by thermal oxidation.

  Subsequently, a polycrystalline silicon film having a film thickness of about 150 nm containing P at a high concentration is formed by a CVD method. Then, the polycrystalline silicon film is patterned using a normal lithography technique and an etching technique, and the gate electrode 20 is formed. Form.

  In this embodiment, the gate electrode 20 is formed by patterning only a single layer of the polycrystalline silicon film. However, as shown in the first embodiment, the polycrystalline silicon film and the silicon nitride film are continuously formed. The laminated film may be patterned at the same time. In this case, when the through holes 38 and 40 are formed later, it is possible to prevent the gate electrode 20 from being exposed in the through holes 38 and 40 by mistake.

Thereafter, using the gate electrode 20 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 20 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² to form the source diffusion layer 24 and the drain diffusion layer 26 of the memory cell transistor. . Although not shown in the present embodiment, the diffusion layer formed in this manner is an n ⁻ layer having an LDD structure in the N-type transistor for the peripheral circuit (FIG. 35A).

  Next, a silicon nitride film having a thickness of about 100 nm is formed by CVD, and then anisotropic etching is performed to form a side wall nitride film 30 on the side wall of the gate electrode 20 in a self-aligned manner (FIG. 35B). Note that the sidewall to be formed may be a silicon oxide film.

Subsequently, for example, As ions are selectively ion-implanted into an N-type transistor region (not shown) of the peripheral circuit under the conditions of an acceleration energy of 40 keV and an injection amount of 4 × 10 ¹⁵ cm ⁻² , thereby Source / drain diffusion layers are formed. Thus, a peripheral circuit transistor having an LDD structure is formed.

  Thereafter, a BPSG film is deposited with a thickness of about 2 μm by the CVD method, and an interlayer insulating film 36 is formed.

  Next, after depositing a polycrystalline silicon film having a thickness of about 100 nm on the interlayer insulating film 36 by a CVD method. The polycrystalline silicon film is patterned by using a normal lithography technique and an etching technique to form a polycrystalline silicon pattern 136.

  Subsequently, a polycrystalline silicon film having a thickness of about 150 nm is deposited and then etched by the RIE method to form a polycrystalline silicon side wall 138 on the side wall of the patterned polycrystalline silicon pattern 136 (FIG. 35C).

  Thereafter, the interlayer insulating film 36 is etched using the thus formed polycrystalline silicon pattern 136 and the polycrystalline silicon side wall 138 as a mask, the through hole 40 opened on the source diffusion layer 24, and the drain diffusion layer 26. A through hole 38 opened upward is formed (FIG. 36A).

  Since the through holes 38 and 40 formed in this way are opened using the polycrystalline silicon pattern 136 and the polycrystalline silicon side wall 138 as a mask, a fine opening having a size smaller than the minimum resolution dimension of the exposure apparatus, for example, 0.1 μm. Can be formed.

  The above-described method for forming the through holes 38 and 40 requires a considerable number of steps. However, if the locations where such through holes 38 and 40 are used are limited to only memory cells, for example, an electron beam It can also be formed by a lithography technique using a drawing method. In general, lithography by electron beam lithography increases the throughput, but limiting the locations to be used cancels out the difference in the number of steps by the above method and may reduce the throughput.

  Next, a polycrystalline silicon film 140 having a thickness of about 100 nm is deposited by the CVD method to fill the through holes 38 and 40 (FIG. 36B). This step is not necessarily required, but is effective in increasing the capacitor capacity and protecting the base substrate from damage during etching. This will be described later.

  Subsequently, the polycrystalline silicon film 140, the polycrystalline silicon pattern 136, the polycrystalline silicon sidewall 138, and the interlayer insulating film 36 are patterned by a normal lithography technique and etching technique, and an opening 142 is formed in a region where a capacitor is formed ( FIG. 37 (a)). At this time, since the polycrystalline silicon film 140 buried in the through hole 40 remains as a columnar protrusion, the surface of the silicon substrate 10 under the through hole 40 is not directly subjected to etching damage.

  In the etching of the interlayer insulating film 36, it is necessary to stop the etching in the middle of the film. If sufficient etching accuracy cannot be obtained, the interlayer insulating film 36 may be a laminated film made of, for example, a silicon nitride film and a BPSG film, and the etching of the opening 142 may be stopped by the silicon nitride film. By doing this, the number of steps increases, but the depth control of the opening 142 is facilitated, variation in capacitor capacitance is reduced, and characteristics can be stabilized.

  Thereafter, a polycrystalline silicon film having a thickness of about 20 nm is deposited by the CVD method and polished by the CMP method until the interlayer insulating film 36 is exposed on the surface. As a result, the capacitor storage electrode 46 is formed in the opening 142, and the contact conductive film 44 is formed in the through hole 38 (FIG. 37B).

  Since the polycrystalline silicon film 140 remaining as columnar protrusions is present in the opening 142, the surface area of the capacitor storage electrode 46 increases. Thereby, the capacitor capacity can be increased.

  After the contact conductive film 44 and the capacitor storage electrode 46 are formed in this manner, the capacitor dielectric film is formed in the same manner as in the method for manufacturing the semiconductor memory device according to the first embodiment shown in FIGS. 48, capacitor counter electrode 54, bit line 62, wiring 70, etc. are formed (FIG. 38).

  As described above, according to the present embodiment, the opening diameters of the through hole 40 opened on the source diffusion layer 24 and the through hole 38 opened on the drain diffusion layer 26 can be made extremely small. Even when an etching residue is generated, a short circuit between the bit line 62 and the gate electrode 20 can be greatly reduced.

  Further, since the area of the capacitor storage electrode 54 is determined by the separately formed opening 142, the above-described effect can be obtained without reducing the area of the storage electrode 54.

  Further, by depositing the polycrystalline silicon film 140 before forming the opening 142, columnar protrusions remain in the opening 142, so that the capacitor capacity can be increased. As a result, the depth of the through hole for achieving a certain storage capacity can be reduced.

In the above embodiment, the polycrystalline silicon film is used as the conductive film embedded in the through holes 38 and 40. However, for example, various conductors as shown in the third embodiment may be used.
[Ninth Embodiment]
A method for fabricating a semiconductor memory device according to the ninth embodiment of the present invention will be explained with reference to FIGS. The same constituent elements as those of the semiconductor memory device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 7 or the third embodiment shown in FIGS. Keep it simple.

  39 and 40 are process cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the method of manufacturing the semiconductor memory device according to the first embodiment, as shown in FIG. 4A, when forming the contact conductive film 44 and the capacitor storage electrode 46, polycrystalline silicon containing P at a high concentration is formed. After forming the film, the polycrystalline silicon film on the interlayer insulating film 36 was removed by CMP.

  In the method of manufacturing the semiconductor memory device according to the third embodiment, as shown in FIG. 17A, when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80, a Ti film and a TiN film are formed. After the film was continuously formed, the TiN film and the Ti film on the interlayer insulating film 36 were removed by the CMP method.

  However, as shown in the sixth embodiment, when the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed in the through holes 38, 40, and 60 in this way, powders generated during polishing. Or the like may enter the through holes 38, 40, and 60, thereby reducing the yield.

  Further, if a powdery substance or the like enters the through hole 40, the through hole 40 is completely filled, and it becomes impossible to secure a capacity, and the pressure resistance deteriorates.

  Furthermore, a lithography technique is used instead of the CMP method, and after leaving the photoresist in the through hole 38, the through hole 40, and the through hole 60, the Ti film and the TiN film are removed by etching using the photoresist as a mask. As shown in the third embodiment, this method cannot control etching at the end point.

  Further, in the control by time, if a residue remains in a place other than in the through holes 38, 40, 60, for example, the bit line 62 and the capacitor storage electrode 46 are short-circuited. If this is done, even the capacitor storage electrode 46 on the side wall of the through hole 40 is etched, so that the capacitance of the capacitor is reduced.

  In the present embodiment, there is provided a method for manufacturing a semiconductor memory device in which the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 can be formed by a CMP method without entering dust or the like into the through holes 38, 40, and 60. provide.

  In the following description, an embodiment in which the present invention is applied to the method for manufacturing a semiconductor memory device according to the third embodiment will be described.

  First, through holes 38, 40, and 60 are formed in the interlayer insulating film 36 in the same manner as in the method of manufacturing the semiconductor memory device according to the third embodiment shown in FIGS. 16 (a) to 16 (c).

  Next, a Ti film having a thickness of about 10 nm and a TiN film having a thickness of about 30 nm are successively formed by a CVD method to form a conductive film 144 (FIG. 39A).

  Subsequently, a pigment-containing resist is applied on the surface to form a photoresist 72 having a thickness of about 2 μm. As a result, the through holes 38, 40, 60 are completely filled with the photoresist 72 (FIG. 39B). Note that photosensitive polyimide may be used instead of the photoresist 72.

  Thereafter, the entire surface of the photoresist 72 is exposed to leave the photoresist 72 only in the through holes 38, 40, and 60 (FIG. 40A).

  Next, the conductive film 144 on the interlayer insulating film 36 is removed by a CMP method. At this time, since the photoresist 72 is buried in the through holes 38, 40, 60, the dust generated by polishing does not enter the through holes 38, 40, 60. Thus, the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed.

  Note that the photoresist 72, the TiN film, and the Ti film may be removed by CMP without exposing the entire surface of the photoresist 72.

  Subsequently, the photoresist 72 remaining in the through holes 38, 40, 60 is removed with hydrogen peroxide (FIG. 40B).

  Thereafter, a semiconductor memory device is formed by the manufacturing method shown in FIGS.

  As described above, according to the present embodiment, the photoresist 72 is embedded in the through holes 38, 40, 60 before the polishing step when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80. Therefore, the powdery substance and abrasive | polishing agent which generate | occur | produce in the case of grinding | polishing do not enter into the through holes 38, 40, 60, and the yield fall resulting from this can be prevented.

  In the above embodiment, the bit line contact portion and the contact portion in the peripheral circuit region are formed in the same structure as in the semiconductor memory device according to the third embodiment, but the first embodiment or the second embodiment is used. A peripheral circuit region contact may be formed as in the semiconductor memory device according to FIG.

The structure of the semiconductor memory device according to the above embodiment can also be applied to other embodiments according to the present invention.
[Tenth embodiment]
A semiconductor memory device and a manufacturing method thereof according to the tenth embodiment of the present invention will be described with reference to FIGS. The same components as those in the semiconductor memory device and the manufacturing method thereof according to the ninth embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 41 is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment. FIGS. 42 and 43 are process cross-sectional views showing the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the present embodiment, as in the ninth embodiment, there is provided a method for manufacturing a semiconductor memory device in which a conductive film for contact, a capacitor storage electrode, and the like can be formed by a CMP method without entering dust or the like into a through hole. .

  The semiconductor memory device according to the present embodiment is characterized in that an insulating film having an etching characteristic different from that of the interlayer insulating film 36 is formed on the uppermost portion of the interlayer insulating film 36.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, memory cell transistors and peripheral circuit transistors are formed on the semiconductor substrate 10 in the same manner as in the method of manufacturing the semiconductor memory device according to the third embodiment shown in FIGS. 16A and 16B.

  Next, a silicon oxide film having a thickness of about 2 μm and a silicon nitride film having a thickness of about 50 nm are successively formed by a CVD method to form an interlayer insulating film 36 having a silicon nitride film 146 formed on the top.

  Subsequently, through holes 38, 40, and 60 are opened in the interlayer insulating film 36 having a two-layer structure composed of a silicon nitride film and a silicon oxide film (FIG. 42A).

  Thereafter, a Ti film having a thickness of about 10 nm, a conductive film 144 made of a TiN film having a thickness of about 30 nm, and a silicon oxide film 148 having a thickness of about 0.15 μm are deposited by CVD (FIG. 42B). The through holes 38, 40 and 60 are completely filled with the silicon oxide film 148.

  Next, the silicon oxide film 148 is removed onto the conductive film 144 by CMP, and then the conductive film 144 is removed onto the silicon nitride film 146 (FIG. 43A). Thus, the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed.

  If the conductive film for contact 44, the capacitor storage electrode 46, and the conductive film 80 are formed in this way, the powder and abrasives generated during polishing of the conductive film 144 will not enter the through holes 38, 40, and 60. .

  Subsequently, the silicon oxide film 148 is removed by wet etching using, for example, a hydrofluoric acid aqueous solution (FIG. 43B).

  Thereafter, a semiconductor memory device is formed by the manufacturing method shown in FIGS.

Thus, according to the present embodiment, the silicon oxide film 148 is embedded in the through holes 38, 40, 60 before the polishing step when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80. Therefore, the powdery substance and abrasive | polishing agent which generate | occur | produce in the case of grinding | polishing do not enter into the through holes 38, 40, 60, and the yield fall resulting from this can be prevented.
[Eleventh embodiment]
A semiconductor memory device and a manufacturing method thereof according to the eleventh embodiment of the present invention will be described with reference to FIGS.

  44 is a schematic sectional view showing the structure of the semiconductor memory device according to the present embodiment. FIGS. 45 to 47 are process sectional views showing the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the semiconductor memory device and the manufacturing method thereof according to the present embodiment, the manufacturing method of the semiconductor memory device according to the fourth and tenth embodiments is applied to a semiconductor memory device having a double-sided cylinder capacitor.

  That is, as shown in FIG. 44, the capacitor storage electrode 46 includes a contact portion 46a formed on the inner wall and bottom of the through hole 40 formed in the interlayer insulating film made of the silicon oxide film 84 and the silicon nitride film 86, and It is comprised by the protrusion part 46b formed continuously in the upper part. The capacitor dielectric film 48 is formed so as to cover the inside of the capacitor storage electrode 46 and the outer wall of the protrusion 46b. The capacitor counter electrode is formed so as to cover the capacitor dielectric film 48. In this way, a double-sided cylinder capacitor is formed.

  The interlayer insulating film 36 in which the through hole 40 is formed is formed of a laminated film made of films having different etching characteristics. That is, in the semiconductor memory device according to the present embodiment, the interlayer insulating film 36 is formed by the silicon oxide film 84 and the silicon nitride film 86.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, a three-layer structure of a silicon oxide film 84, a silicon nitride film 86, and a silicon oxide film 88 is performed in the same procedure as in the method of manufacturing the semiconductor memory device according to the fourth embodiment shown in FIGS. 20A to 21A. An interlayer insulating film is formed and a through hole 40 is opened. In the method of manufacturing the semiconductor memory device according to the fourth embodiment, the through hole 38 opened on the drain diffusion layer 26 is formed at the same time, but is not formed in this embodiment (FIG. 45A).

  Next, a conductive film 144 made of a polycrystalline silicon film doped with P at a high concentration with a thickness of about 50 nm and a silicon oxide film 148 with a thickness of about 0.15 μm are deposited by CVD (FIG. 45B). . As a result, the inside of the through hole 40 is completely filled with the silicon oxide film 148.

  Subsequently, the silicon oxide film 148 is removed up to the conductive film 144 by CMP, and then the conductive film 144 is removed up to the silicon oxide film 88 (FIG. 46A). In this way, the capacitor storage electrode 46 is formed.

  If the capacitor storage electrode 46 is formed in this way, powders and abrasives generated during polishing of the conductive film 144 will not enter the through hole 40.

  Thereafter, wet etching using, for example, a hydrofluoric acid aqueous solution is performed. As a result, the silicon oxide film 148 and the silicon oxide film 88 are etched, and the capacitor storage electrode 46 is exposed as a cylindrical projection (FIG. 46B).

  Next, a capacitor dielectric film 48 and a capacitor counter electrode 54 are formed to form a double-sided cylinder structure capacitor, and an interlayer insulating film 64 is deposited.

  Subsequently, a through hole 38 penetrating the interlayer insulating film 64, the silicon nitride film 86, and the silicon oxide film 84 is opened, and a bit line 62 is formed so as to fill the through hole 38 (FIG. 47).

  By manufacturing the semiconductor memory device in this manner, a DRAM cell having a double-sided cylinder structure capacitor can be formed.

  As described above, according to the present embodiment, before the polishing step for forming the capacitor storage electrode 46, the silicon oxide film 148 is embedded in the through hole 40, whereby powders and polishing generated during polishing are polished. Since the agent does not enter the through hole 40, the yield reduction due to this can be prevented even in the semiconductor memory device having the cylinder capacitor.

In the above embodiment, the bit line 62 formed on the interlayer insulating film 64 is directly connected to the drain diffusion layer 26. However, the bit line 62 is formed simultaneously with the capacitor storage electrode 46 in the same manner as the semiconductor memory device according to the first embodiment. You may connect via the conductive film 44 for a contact.
[Twelfth embodiment]
The structure of the semiconductor memory device according to the twelfth embodiment of the present invention will be explained with reference to FIGS. Note that the same components as those of the semiconductor memory devices of the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  48 is a plan view and a partial cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment. FIG. 49 is a diagram showing an example of the peripheral circuit configuration of the semiconductor memory device according to the present embodiment.

  In the first to third embodiments, various alignment margins are not required by making full use of the self-alignment process. Therefore, it is possible to arrange the word line and the bit line with a minimum processing dimension of line and space (L / S).

  However, if the word line or bit line is processed with the minimum processing dimension L / S, an overlap margin between the contact hole and the wiring layer cannot be secured, and the wiring cannot be bent. Therefore, in order to realize such a memory cell, it is necessary to perform a pattern layout in consideration of the arrangement of peripheral circuits in addition to those shown in the above embodiment.

  In the present embodiment, the structure of a semiconductor memory device capable of realizing the semiconductor memory device according to the first to third embodiments will be described in consideration of the layout of peripheral circuits.

  As shown in FIG. 48A, the semiconductor memory device according to the present embodiment is arranged so that the bit line 62 and the word line 20 patterned with the minimum processing dimension are orthogonal to each other. A problem in such an arrangement is an overlap margin between the bit line contact hole and the bit line.

  As shown in FIG. 48B, which is a cross-sectional view taken along the line XX ′ of FIG. 48A, the bit line 62 needs to be in contact with the contact conductive film 44. The line contact hole 58 needs to be exposed.

  However, if the pattern end of the bit line 62 is formed in the bit line contact hole 58 due to misalignment when the bit line 62 is patterned, the contact conductive film 44 and the like are etched by the etching when the bit line 62 is formed. This causes inconveniences such as an increase in level difference. Therefore, the width of the bit line contact hole 58 is required to be narrower than the width of the bit line 62 as shown in FIG. 48C, which is a cross-sectional view of the YY ′ portion of FIG.

  On the other hand, since the bit line 62 is connected to the polycrystalline silicon film 50 embedded in the through hole 38, the polycrystalline silicon film 50 embedded in the through hole 38 and the capacitor counter electrode 54 do not remain connected. Thus, when patterning the capacitor counter electrode 54, it is necessary to form it sufficiently away from the through hole 38. Therefore, it is desirable that the bit line contact hole 58 is wide.

  In order to satisfy these conflicting requirements for the bit line contact hole 58, it is necessary to optimize the thickness of the contact conductive film 44 and the width of the sidewall oxide film 56.

  For example, when the bit line 62 is patterned with an L / S of 0.3 μm and a through hole is opened with a 0.3 μm, the bit line 62 is aligned in consideration of misalignment of the bit line 62 with respect to the bit line contact hole 58. The overlap is set to 0.07 μm, for example, and the distance between the polycrystalline silicon film 50 and the capacitor counter electrode 54 is secured to 0.1 μm, for example.

  Next, the thickness of the contact conductor film 44 and the width of the sidewall oxide film 56 are optimized to satisfy the above parameters. For example, if the thickness of the contact conductive film 44 is 0.05 μm and the width of the sidewall oxide film 56 is 0.12 μm, the interval between the capacitor counter electrodes 54 in the word line 20 direction is 0.4 μm, and the bit line contact hole The width of 58 is 0.16 μm.

  The purpose of the bit line contact hole 58 described here is to prevent the contact conductive film 44 and the like from being etched during the formation of the bit line 62, and the etching is precisely controlled. For example, the width of the bit line contact hole 58 shown in FIG. 48C may be wider than the width of the bit line 62.

Thus, by forming the rectangular bit line contact hole 58 extending in the direction of the bit line 62 as shown in FIGS. 48B and 48C, a minimum cell area can be realized. The cell area at this time is 0.72 μm ² .

  Next, a configuration example of the peripheral circuit is shown.

  As shown in FIG. 49, a decoder 94 and a sense amplifier 96 are formed on both sides of the memory cell region. By arranging the decoder 94 and the sense amplifier 96 in this way, peripheral circuits can be arranged without any problem even when the memory cell area is reduced by eliminating any alignment margin.

  In the present embodiment, since the word line and the bit line are arranged with the minimum processing dimension L / S, the bit line 62 cannot be bent halfway. Therefore, it is not possible to employ a twisted bit line structure that suppresses interference between bit lines by twisting the paired bit lines halfway. Further, in order to employ a shield bit line structure in which a shield plate is provided on the bit line to suppress interference between the bit lines, an increase in the manufacturing process is inevitable.

  However, if the film thickness of the bit lines is made sufficiently thinner than the bit line interval, the capacitive coupling between the bit lines can be suppressed, so that interference between the bit lines can be suppressed. For example, if the bit line structure is W film (50 nm) / TiN film (50 nm) / Ti film (30 nm) and the total film thickness is 0.13 μm, the bit line spacing can be made smaller than half of 0.3 μm. Can cope with interference between bit lines.

  As described above, according to the present embodiment, by optimizing the structure of the bit line contact hole, even when the bit line is arranged with the minimum processing size, the overlap margin between the bit line contact hole and the bit line is provided. Since it could be ensured, a semiconductor memory device with a greatly reduced memory cell area can be configured.

Further, since the decoder and the sense amplifier are provided on both sides of the memory cell region, the peripheral circuit can be arranged without any problem even when the memory cell area is reduced by eliminating any alignment margin.
[Thirteenth embodiment]
A semiconductor memory device and a method for manufacturing the same according to a thirteenth embodiment of the present invention will be described with reference to FIGS.

  50 is a plan view showing the structure of the semiconductor memory device according to the present embodiment, FIG. 51 is a schematic diagram showing a cross section of the AA ′ portion of the semiconductor memory device of FIG. 50, and FIGS. 52 to 55 are semiconductors according to the present embodiment. FIG. 56 is a schematic cross-sectional view showing the structure of a semiconductor memory device according to a modification of the present embodiment.

  In the present embodiment, a semiconductor memory device and a method for manufacturing the semiconductor memory device in which another method for forming bit lines and capacitors is applied to the semiconductor memory device and the method for manufacturing the semiconductor memory device according to the eighth embodiment will be described.

  First, the structure of the semiconductor memory device according to the present embodiment will be explained with reference to the plan view of FIG. 50 and the sectional view of FIG. FIG. 51 basically shows a cross section taken along the line AA ′ of FIG. 50, but a part of the bit line 62 and the through hole 38 are virtually moved. That is, in FIG. 51, the cross section of the BB 'part of FIG. 50 and the cross sectional view of the AA' part are shown simultaneously.

  An element region 14 defined by the element isolation film 12 is formed on the silicon substrate 10. A source diffusion layer 24 and a drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. Thus, a memory cell transistor composed of the gate electrode 20, the source diffusion layer 24, and the drain diffusion layer 26 is formed.

  A bit line 62 is disposed in a direction crossing the gate electrode 20 and is connected to the drain diffusion layer 26 through the through hole 38. A capacitor storage electrode 46 is connected to the source diffusion layer 24 through a through hole 40, and a capacitor is formed by the capacitor dielectric film 48 and the capacitor counter electrode 54 formed on the capacitor storage electrode 46. Yes. A wiring layer 70 is formed on the capacitor via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

Here, the width of the gate electrode 20, that is, the word line is 0.2 μm, and is arranged at intervals of 0.3 μm. The through holes 38 and 40 have an opening diameter of 0.1 μm and are spaced from the gate electrode 20 by 0.1 μm. The width of the bit lines 62 is 0.2 μm and is arranged at intervals of 0.3 μm. The overlap with the through hole 38 is about 0.05 μm, and the distance with the through hole 40 is about 0.1 μm. Thus, a memory cell having a cell area of 0.5 μm ² is formed.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, an element isolation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method to define an element region 14. Next, a gate oxide film 16 having a thickness of about 10 nm is formed in the element region 14 by thermal oxidation.

  Subsequently, after growing a polycrystalline silicon film containing about 150 nm in thickness and containing P at a high concentration by CVD, the polycrystalline silicon film is patterned using a normal lithography technique and an etching technique, and a gate electrode 20 is formed.

Thereafter, using the device isolation film 12 and the gate electrode 20 as a mask, for example, P ions are ion-implanted under the conditions of an acceleration energy of 20 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , and the source diffusion layer 24 and drain diffusion of the memory cell transistor The layer 26 is formed (FIG. 52 (a)).

  Next, a silicon oxide film having a thickness of about 50 nm and a BPSG film having a thickness of about 200 nm are sequentially grown by CVD, and then the surface is planarized by reflow to form an interlayer insulating film 150.

  Subsequently, a polycrystalline silicon film 158 having a film thickness of about 50 nm is deposited by a CVD method and patterned to a width of about 0.3 μm by using a normal lithography technique and an etching technique (FIG. 52B).

  Thereafter, a polycrystalline silicon film having a thickness of about 100 nm is deposited by the CVD method and etched in the vertical direction by the RIE method to form the polycrystalline silicon side wall 160 on the side wall of the patterned polycrystalline silicon film 158. Due to the polycrystalline silicon side walls 160 formed at intervals of 0.3 μm in width, the width of the interlayer insulating film 150 exposed therebetween becomes about 0.1 μm (FIG. 52C).

  Next, the interlayer insulating film 150 is etched using the polycrystalline silicon film 158 and the polycrystalline silicon sidewall 160 as a mask, and a through hole 38 opened on the drain diffusion layer 26 and a through hole opened on the source diffusion layer 24. 40 (FIG. 52D).

  The opening diameter of the through holes 38 and 40 formed in this way is approximately equal to the interval between the polycrystalline silicon sidewalls 160, and is about 0.1 μm as described above.

  In this embodiment, the through-holes 38 and 40 are opened by using the polycrystalline silicon film 158 and the polycrystalline silicon sidewall 160 as a mask, thereby enabling processing below the resolution limit of the exposure apparatus. As shown in the method of manufacturing the semiconductor memory device according to the embodiment, the through holes 38 and 40 may be opened using an electron beam drawing method. By using either method, a through hole having a dimension that cannot be formed by ordinary lithography can be opened.

  Subsequently, a polycrystalline silicon film having a thickness of about 60 nm, a tungsten silicide film having a thickness of about 100 nm, and a silicon nitride film are deposited by a CVD method and patterned by a normal lithography technique and an etching technique. As a result, a bit line 62 having a tungsten polycide structure whose upper layer is covered with the silicon nitride film 156 is formed.

  When the bit line 62 is patterned, the polycrystalline silicon film 158 and the polycrystalline silicon sidewall 160 are patterned at the same time so that the buried conductor 162 made of the polycrystalline silicon film remains in the through hole 40 ( FIG. 53 (a)).

  The through hole 40 may not be filled with only polycrystalline silicon. For example, it may be filled with a polycrystalline silicon film and a tungsten silicide film, or may be filled with a polycrystalline silicon film, a tungsten silicide film, and a silicon nitride film as shown in FIG. In any structure, there is no problem because the contact can be made on the entire bottom of the through hole 40.

  The insulating film formed on the bit line 62 is preferably a silicon oxide film having a low dielectric constant in order to reduce the parasitic capacitance, but is not applicable when the insulating film on the bit line 62 is used as an etching stopper film. It becomes difficult. Therefore, when used as an etching stopper film, it is also effective to form a laminated film of a silicon oxide film and a silicon nitride film on the bit line 62.

  Thereafter, a silicon nitride film having a thickness of about 80 nm is deposited by the CVD method and etched in the vertical direction by the RIE method. As a result, a sidewall 164 is formed on the side wall of the bit line 62, and the bit line 62 is completely covered with the silicon nitride film 156 and the sidewall 164 (FIG. 53B).

  Next, a polycrystalline silicon film having a thickness of about 500 nm is deposited by the CVD method and patterned by a normal lithography technique and etching technique to form the capacitor storage electrode 46 (FIG. 54A). By forming the capacitor storage electrode 46 in this way, the capacitor storage electrode 46 can be connected to the source diffusion layer 24 without using a mask process, so that the mask process is reduced by one process compared to the conventional method. can do.

  Subsequently, a silicon nitride film having a thickness of about 5 nm is deposited by the CVD method, and then the surface thereof is oxidized to form a capacitor dielectric film 48.

  Thereafter, a polycrystalline silicon film having a thickness of about 100 nm is deposited by the CVD method and patterned by a normal lithography technique and an etching technique to form a capacitor counter electrode 54 (FIG. 54B).

  Next, a BPSG film having a thickness of about 300 nm is deposited by a CVD method and then reflowed to form an interlayer insulating film 154.

  Subsequently, after forming a through hole in a peripheral circuit region (not shown), a metal material such as tungsten is deposited and patterned to form a wiring layer 70 (FIG. 55).

  In this way, a DRAM comprising one transistor and one capacitor is constructed.

  In the above embodiment, since the height of the memory cell capacitor is large and the height difference between the peripheral circuit region and the memory cell region is large, the wiring layer 70 on the memory cell has a relaxed line width and spacing. It is said.

  Thus, according to the present embodiment, the capacitor storage electrode 46 is connected to the source diffusion layer 24 via the embedded conductor 162 embedded simultaneously with the formation of the bit line 62 in the through hole 40 formed simultaneously with the through hole 38. It is connected to the. Therefore, the time for which the silicon nitride film 156 on the bit line 62 is exposed to the etching atmosphere can be reduced without adding a new process to the formation of the through hole 40.

Further, since the embedded conductor 162 is exposed when the upper portion and the side wall of the bit line 62 are covered with an insulating film, the contact through hole of the capacitor storage electrode 46 is masked as in the conventional manufacturing method. There is no need to form it. Therefore, the mask process can be reduced by one process.
[Fourteenth embodiment]
A semiconductor memory device and a method for manufacturing the same according to a fourteenth embodiment of the present invention will be described with reference to FIGS.

  56 is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment. FIGS. 57 and 58 are process cross-sectional views showing the method for manufacturing the semiconductor memory device according to the present embodiment.

  In the semiconductor memory device according to the thirteenth embodiment, the height of the memory cell capacitor is large, and the height difference between the peripheral circuit region and the memory cell region is large. Must be designed with rules. In the present embodiment, a semiconductor memory device and a method for manufacturing the same are provided.

  The semiconductor memory device according to the present embodiment is characterized in that an interlayer insulating film is formed in the peripheral circuit region, and the difference in height between the memory cell region and the peripheral circuit region is small.

  That is, in the peripheral circuit region, an interlayer insulating film is configured by a three-layer structure including interlayer insulating films 150, 152, and 154, and in the memory cell region, an interlayer insulating film is configured by the interlayer insulating films 150 and 154. . Therefore, in the peripheral circuit region, the interlayer insulating film is thickened by the amount of the interlayer insulating film 152, and the difference in height between the memory cell region and the peripheral circuit region is small.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained.

  First, the bit line 62 and the buried conductor 162 are formed by the same procedure as the method of manufacturing the semiconductor memory device according to the thirteenth embodiment shown in FIGS. 52A to 53B (FIG. 57A). .

  Next, a BPSG film having a thickness of about 300 nm is deposited by a CVD method, and an interlayer insulating film 152 having a flat surface is formed by reflow or polishing.

  Subsequently, an opening 166 is formed in the interlayer insulating film 152 by using an ordinary lithography technique and an etching method that stops at the silicon nitride film, and the bit line 62 is covered with the silicon nitride film 156 and the sidewall 164 so as to be buried conductive. The body 162 is exposed (FIG. 57B).

  Thereafter, a polycrystalline silicon film having a film thickness of about 20 nm is grown by the CVD method and the surface is polished to form the capacitor storage electrode 46 in the opening 166. The capacitor storage electrode 46 is connected to the buried conductor 162 at the upper part of the through hole 40 (FIG. 58A).

  It should be noted that the semiconductor memory device manufacturing method according to the ninth to eleventh embodiments may be applied so that powders and abrasives do not enter the opening 166 during polishing.

  Next, the interlayer insulating film 152 is etched by 50 nm, for example, by wet etching using a hydrofluoric acid aqueous solution. When the upper portion of the interlayer insulating film 152 is thus increased, the exposed area of the capacitor storage electrode 46 increases, so that the capacitance of the capacitor increases, but the height difference between the memory cell region and the peripheral circuit region increases. Therefore, it is desirable not to perform etching when the height difference is a particular problem.

  Subsequently, a capacitor dielectric film 48, a capacitor counter electrode 54, an interlayer insulating film 154, and a wiring layer 70 are formed to constitute a DRAM consisting of one transistor and one capacitor (FIG. 58B).

  In the method for manufacturing the semiconductor memory device according to the present embodiment, the surface step of the interlayer insulating film 154 in the memory cell region and the peripheral circuit region can be reduced, so that the wiring layer 70 is provided in the semiconductor memory according to the thirteenth embodiment. It can be arranged with rules that are stricter than the device.

  As described above, according to the present embodiment, the height difference between the peripheral circuit region and the memory cell region can be reduced, so that the design rule of the wiring layer 70 can be made fine without increasing the number of manufacturing steps. it can.

1 is a plan view showing a structure of a semiconductor memory device according to a first embodiment of the present invention. 1 is a schematic cross-sectional view showing a structure of a semiconductor memory device according to a first embodiment of the present invention. FIG. 6 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the invention; FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention; FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention; FIG. 9 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention; It is a schematic sectional drawing which shows the structure of the semiconductor memory device by the modification of 1st Embodiment of this invention. FIG. 6 is a plan view showing a structure of a semiconductor memory device according to a second embodiment of the present invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 2nd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 2nd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 2nd Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by 2nd Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor memory device by 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor memory device by the modification of 2nd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 3rd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 3rd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 3rd Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by 3rd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 4th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 4th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 4th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 5th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 5th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 5th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 6th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 6th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 6th Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by 6th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 7th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 7th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 7th Embodiment of this invention. It is a figure explaining the subject in the manufacturing method of the semiconductor memory device by a 1st embodiment. It is a top view which shows the structure of the semiconductor memory device by 8th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 8th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 8th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 8th Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by 8th Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor memory device by 8th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 9th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 9th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 10th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 10th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 10th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 11th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 11th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 11th Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by 11th Embodiment of this invention. It is the top view and partial sectional view which show the structure of the semiconductor memory device by 12th Embodiment of this invention. It is a figure which shows the peripheral circuit structural example in the semiconductor memory device by 12th Embodiment of this invention. It is a top view which shows the structure of the semiconductor memory device by 13th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 13th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 13th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 13th Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by 13th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by the modification of 13th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by 14th Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor memory device by 14th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by 14th Embodiment of this invention. It is a schematic sectional drawing (the 1) which shows the structure of the conventional semiconductor memory device. It is a schematic sectional drawing (the 2) which shows the structure of the conventional semiconductor memory device.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... Element isolation film 14 ... Element region 15 ... Element region 16 ... Gate oxide film 18 ... Silicon nitride film 20 ... Gate electrode (word line)
DESCRIPTION OF SYMBOLS 22 ... Gate electrode 24 ... Source diffusion layer 26 ... Drain diffusion layer 28 ... Low concentration diffusion layer 30 ... Side wall nitride film 32 ... Source diffusion layer 34 ... Drain diffusion layer 36 ... Interlayer insulating film 38 ... Through hole 40 ... Through hole 42 ... Insulating film 44 ... Contact conductive film 46 ... Capacitor storage electrode 48 ... Capacitor dielectric film 50 ... Polycrystalline silicon film 52 ... BPSG film 53 ... Interlayer insulating film 54 ... Capacitor counter electrode 56 ... Side wall oxide film 58 ... Bit line Contact hole 59 ... Contact hole 60 ... Through hole 62 ... Bit line 64 ... Interlayer insulating film 66 ... Via hole 68 ... Wiring layer 70 ... Wiring layer 72 ... Photoresist 74 ... Photoresist 76 ... Side wall oxide film 78 ... Polycrystalline silicon film 80 ... conductive film 82 ... gate contact portion 84 ... silicon oxide film 86 ... Recon nitride film 88 ... BPSG film 90 ... Photoresist 92 ... Built-in conductor 94 ... Decoder 96 ... Sense amplifier 98 ... Through hole 100 ... Through hole 102 ... Interlayer insulating film 104 ... Polycrystalline silicon film 106 ... Polycrystalline silicon film 108 ... Side wall 110 ... polycrystalline silicon film 112 ... columnar conductor 114 ... columnar conductor 116 ... void 118 ... laminated film 120 ... contact hole 122 ... through hole 124 ... conductive film 126 ... insulating film 128 ... polycrystalline silicon film 130 ... dust 132 ... residue 134 ... residue 136 ... polycrystalline silicon pattern 138 ... polycrystalline silicon sidewall 140 ... polycrystalline silicon film 142 ... opening 144 ... conductive film 146 ... silicon nitride film 148 ... silicon oxide film 150 ... interlayer insulating film 152 ... interlayer Insulating film 154 ... interlayer insulating film 156 Silicon nitride film 158 ... polycrystalline silicon film 160 ... polycrystalline silicon sidewall 162 ... buried conductors 164 ... sidewall 166 ... opening

Claims (5)

Forming a conductor pattern on a semiconductor substrate;
Forming a first insulating film on the upper surface of the conductor pattern;
Introducing a impurity into the semiconductor substrate using the conductor pattern and the first insulating film as a mask to form a diffusion layer;
After the step of forming the diffusion layer and forming the first insulating film and the side wall film having a same material as the first insulating film on the sidewall of the conductive pattern,
Forming a second insulating film having a surface flattened by a CMP method on the first insulating film and the sidewall film and having etching characteristics different from those of the first insulating film;
Forming a third insulating film having etching characteristics different from those of the second insulating film on the second insulating film;
Forming a fourth insulating film having etching characteristics different from those of the third insulating film on the third insulating film;
Forming a mask layer on the fourth insulating film;
Forming an opening in the fourth insulating film under a first etching condition using the mask layer as a mask and the third insulating film as a stopper;
Etching the third insulating film under a second etching condition different from the first etching condition using the second insulating film as a stopper, and opening the opening to the second insulating film;
After the step of opening the opening to the second insulating film, the second insulating film and the sidewall film are used as stoppers, and the second etching condition is different from the second etching condition. Etching the insulating film and forming a through hole opened on the diffusion layer;
Forming a conductive pattern in electrical contact with the diffusion layer in the through hole formed in the second insulating film, the third insulating film, and the fourth insulating film. A method for manufacturing a semiconductor device. Forming a conductor pattern on a semiconductor substrate;
Forming a first insulating film on the upper surface of the conductor pattern;
Introducing a impurity into the semiconductor substrate using the conductor pattern and the first insulating film as a mask to form a diffusion layer;
After the step of forming the diffusion layer, forming a sidewall film having the same material as the first insulating film on the side walls of the first insulating film and the conductor pattern;
Forming a second insulating film having a planarized surface on the first insulating film and the sidewall film and having different etching characteristics from the first insulating film;
Forming a third insulating film having etching characteristics different from those of the second insulating film on the second insulating film;
Forming a fourth insulating film having etching characteristics different from those of the third insulating film on the third insulating film;
Forming a mask layer on the fourth insulating film;
Forming an opening in the fourth insulating film under a first etching condition using the mask layer as a mask and the third insulating film as a stopper;
Etching the third insulating film under a second etching condition different from the first etching condition using the second insulating film as a stopper, and opening the opening to the second insulating film;
After the step of opening the opening to the second insulating film, the second insulating film and the sidewall film are used as stoppers, and the second etching condition is different from the second etching condition. Etching the insulating film and forming a through hole opened on the diffusion layer;
Forming a conductive pattern in electrical contact with the diffusion layer in the through hole formed in the second insulating film, the third insulating film, and the fourth insulating film;
The method of manufacturing a semiconductor device, wherein the thickness of the third insulating film is one digit or more smaller than the thickness of the fourth insulating film. In the manufacturing method of the semiconductor device of Claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the second insulating film contains silicon oxide. In the manufacturing method of the semiconductor device of Claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the third insulating film contains silicon nitride. In the manufacturing method of the semiconductor device of Claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the fourth insulating film contains silicon oxide.

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