JP2004134586A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method of the same which realizes self aligned contact capable of preventing the deterioration of characteristics due to the increase of leakage current even when over-etching is contingently applied on a trench element separating film. <P>SOLUTION: In the semiconductor device formed on a semiconductor substrate having a trench element separating structure in which an insulating film 3 is embedded into a trench 2, a part of an inner wall of the trench 2 is covered with a refractory metal silicide film 9. This device is manufactured by a method wherein the insulating film 3 is embedded into the substrate 1 so as to be flush with the surface thereof, then an impurities diffusion layer 8 is formed on the substrate 1 and the insulating film 3 in the trench 2 is removed so that a part of inner wall of the trench 2 is exposed. Further, the refractory metal film is formed on the whole surface of the substrate 1, and heat treatment is applied thereon to form the refractory metal silicide film 9 on the impurities diffusion layer 8 and a part of inner wall of the trench 2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a contact structure in which a through-hole is formed across a trench element isolation region due to alignment deviation or the like, and a method of manufacturing the same.
[0002]
[Prior art]
Submicron and quarter micron devices that are widely used in recent years are usually manufactured using a large number of exposure masks. When overlaying each mask pattern, misalignment occurs inevitably between the patterns, but if this misalignment is not within a certain range, the device as designed cannot be obtained, Therefore, the device does not operate normally.
However, as the miniaturization of the semiconductor integrated circuit progresses, the allowable range of the misalignment, that is, the margin for alignment decreases.
[0003]
Various means have been studied in order to increase the alignment margin, and the following method of manufacturing a semiconductor device has been proposed (for example, Patent Document 1).
The semiconductor device according to this method realizes a self-aligned contact (SAC) and is configured as follows. That is, the MOS transistor is formed in the element formation region of the silicon substrate, and the gate electrode of the MOS transistor is covered with the cap oxide film and the sidewall. Further, a silicon nitride film is formed so as to cover the cap oxide film, the sidewalls, and the silicon substrate, and a silicon oxide-based interlayer insulating film is formed thereon. A wiring layer is formed on the interlayer insulating film, and the wiring layer is connected to the gate electrode and the silicon substrate in the element formation region through a connection hole provided in the interlayer insulating film.
[0004]
This semiconductor device is manufactured as follows.
First, a trench 2 is formed on the surface of a silicon substrate 1, a silicon oxide film is formed on the silicon substrate 1 including the trench 2, and then the silicon oxide film is etched back until the surface of the silicon substrate 1 is exposed. An element isolation film 3 (silicon oxide film) is buried in the trench to form an element isolation region. Subsequently, a gate electrode 5 is formed on the silicon substrate 1 with a gate oxide film 4 interposed therebetween. As shown in FIG. 2A, an n-type low-concentration impurity diffusion layer (LDD) 7 is formed on a side wall of the gate electrode 5. An n-type impurity diffusion layer 8 serving as a wall 6 and source / drain regions is formed.
Optionally, as shown in FIG. 2B, a titanium silicide film 9 is formed on the gate electrode 5 and the source / drain regions.
[0005]
Next, as shown in FIG. 2C, an interlayer insulating film including the silicon nitride film 10 and the silicon oxide film 11 is formed, and a mask pattern (not shown) is formed on the interlayer insulating film by a photolithography and etching process. Then, using the mask pattern as a mask, a through hole 12 reaching the source / drain region is formed by anisotropic etching.
Further, as shown in FIG. 2D, a wiring film 23 is formed by depositing a metal film in the through hole 12 and patterning it into a desired shape.
Therefore, even if the mask pattern for forming the through hole 12 is misaligned and a part of the through hole 12 overlaps the gate electrode 5, the silicon nitride film 10 as the interlayer insulating film functions as an etching stopper. Therefore, a short circuit between the wiring electrode 23 and the gate electrode 5 buried in the through hole in a later step can be prevented, and as a result, a margin for mask alignment is widened.
[0006]
[Patent Document 1]
JP-A-6-196499
[Problems to be solved by the invention]
However, when the trench element isolation method is used as described above, misalignment of the mask occurs in a photolithography process for forming a mask pattern, and the formation position of the through-hole 12 becomes, for example, the trench element isolation method. When the interlayer insulating film and the silicon oxide film in the trench 2 are overetched as they are over the region 3, the silicon substrate in the trench isolation region 3 is exposed. Since a PN junction is not necessarily formed on the exposed silicon substrate, a problem occurs in that a current leaks at the exposed portion due to contact between the wiring substrate 23 and the silicon substrate on which the PN junction is not formed.
The present invention has been made in view of the above problems, and even when unexpected overetching occurs in a trench element isolation film by a trench element isolation method, a self-aligned contact that can reliably prevent characteristic deterioration due to an increase in leakage current. It is an object to provide a semiconductor device that can be realized and a method for manufacturing the same.
[0008]
[Means for Solving the Problems]
According to the present invention, there is provided a semiconductor device formed on a semiconductor substrate having a trench element isolation structure in which an insulating film is buried in a trench, wherein a part of the inner wall of the trench is covered with a refractory metal silicide film. An apparatus is provided.
Further, according to the present invention, (i) an insulating film is buried in a trench formed in the semiconductor substrate almost flush with the surface of the semiconductor substrate,
(Ii) forming at least an impurity diffusion layer on the obtained semiconductor substrate;
(Iii) etching away a part of the insulating film in the trench such that a part of the inner wall of the trench is exposed;
(Iv) A semiconductor device comprising forming a refractory metal film on the entire surface of the obtained semiconductor substrate and heat-treating to form a refractory metal silicide film on at least the impurity diffusion layer and at least a part of the inner wall of the trench. Is provided.
[0009]
Further, according to the present invention, an insulating film is buried in a trench formed in a semiconductor substrate so that a part of the inner wall of the trench is exposed, and at least an impurity diffusion layer is formed in the obtained semiconductor substrate. Forming a refractory metal film over the entire surface of the semiconductor substrate, and heat-treating to form a refractory metal silicide film on at least the impurity diffusion layer and at least part of the trench inner wall. You.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
The semiconductor device of the present invention is formed on a semiconductor substrate having a trench element isolation structure in which an insulating film is embedded in a trench. The semiconductor substrate is not particularly limited as long as it is generally used for a semiconductor device, and examples thereof include elemental semiconductors such as silicon and germanium, and compound semiconductors such as GaAs, InGaAs, and ZnSe. Among them, a silicon substrate is preferable. The shape of the trench in the trench element isolation structure is not particularly limited, and may be a polygonal prism such as a rectangular parallelepiped or a cube, or a truncated polygonal pyramid having a tapered side surface. The insulating film is not particularly limited. For example, a silicon oxide film (thermal oxide film, low-temperature oxide film: LTO film or the like, high-temperature oxide film: HTO film), silicon nitride film, SOG film, PSG film, BSG A single-layer film such as a film, a BPSG film, or the like, a laminated film, or the like can be given. Among them, a silicon oxide film is preferable. If a part of the inner wall of the trench is covered with the refractory metal silicide film as described later, the insulating film may be buried in the trench, flush with the surface of the semiconductor substrate, Instead of being buried flush with the surface of the semiconductor substrate, it may be buried so that a part of the inner wall of the trench is exposed, in other words, a part of the inner wall of the trench is not in contact with the insulating film. The part of the inner wall of the trench that does not contact the insulating film is suitably a part of the upper part of the trench. In particular, it is preferable that a portion adjacent to an impurity diffusion layer functioning as a source / drain region, a bit line, or the like, which forms part of a semiconductor device formed over a semiconductor substrate, or its vicinity does not contact an insulating film.
[0011]
It is necessary that a part of the inner wall of the trench is covered with a refractory metal silicide film. Here, as the refractory metal silicide film is not particularly limited, for _example, CoSi _x, NiSi x, etc. TiSi _x and ZrSi _x and the like. The refractory metal silicide film is self-aligned with the trench inner wall where the insulating film is not buried or not in contact with the insulating film, in other words, covers the entire trench inner wall where the insulating film is not buried. It is preferable to form it.
[0012]
The semiconductor device according to the present invention includes all of the semiconductor elements constituting a memory, a logic device, a signal processing circuit, and the like, and includes not only MOS transistors but also all of bipolar transistors, resistance elements, capacitors, and the like.
In the method of manufacturing a semiconductor device according to the present invention, first, in step (i), an insulating film is buried in a trench formed in a semiconductor substrate so as to be substantially flush with the surface of the semiconductor substrate. The trench can be formed by forming a mask of a desired shape on the semiconductor substrate by a known method, for example, a photolithography and etching process, and etching the semiconductor substrate using the mask. For the etching, various methods such as wet etching and dry etching can be used, and among them, dry etching, in particular, RIE, which is anisotropic etching, is preferably used. The insulating film is formed on the semiconductor substrate including the trench by, for example, a CVD method, a sputtering method, coating, or the like, to have a predetermined thickness, for example, a trench thickness or more, preferably a thicker film than the trench depth, and etch back. Thus, the insulating film can be buried almost flush with the surface of the semiconductor substrate. The etch back can be selected from the above etching methods, but the CMP method is preferable.
[0013]
Next, in a step (ii), at least an impurity diffusion layer is formed on the obtained semiconductor substrate. The impurity diffusion layer generally functions as a source / drain region, a bit line, an electrode, or the like, and can be formed by introducing a p-type or n-type impurity into a semiconductor substrate so as to have a desired concentration. it can. Specifically, it can be formed by introducing impurities by various methods such as solid phase diffusion, gas phase diffusion, and ion implantation. At this time, if the semiconductor device constitutes a MOS transistor or the like, it is preferable to form a gate electrode and then perform ion implantation using the gate electrode as a mask to form an impurity diffusion layer. Here, the impurity diffusion layer may have an LDD or DDD structure.
[0014]
Further, in the step (iii), a part of the insulating film in the trench is removed by etching so that a part of the inner wall of the trench is exposed. Here, the etching removal of a part of the insulating film can be selected from the above etching methods, but is preferably performed by dry etching, particularly, anisotropic dry etching. The insulating film may be removed with a uniform thickness or may be removed only partially. The etching removal may be performed to any extent as long as the insulating film can function as a trench element isolation film in the trench. For example, the etching removal may be deeper than the depth of the impurity diffusion layer formed earlier, It can be performed to a degree or shallower than the impurity diffusion layer. In particular, it is preferable to perform the process so that the inner wall of the trench of about 20 to 50% of the depth of the impurity diffusion layer is exposed or does not contact the insulating film.
[0015]
Subsequently, in a step (iv), a refractory metal film is formed on the entire surface of the obtained semiconductor substrate, and heat treatment is performed. Examples of the high melting point metal film include Co, Ni, Ti, and Zr. These can be formed by various methods such as a sputtering method, a CVD method, and a vapor deposition method. The film thickness is, for example, about 10 to 200 nm. The heat treatment includes, for example, various methods such as lamp annealing, EB, and RTA, and is suitably performed at a temperature of about 650 to 750 ° C. for about 10 seconds to 1 minute. Thereafter, by removing the unreacted high-melting-point metal film, a high-melting-point metal silicide film can be formed in a self-aligning manner at least on the impurity diffusion layer and on the exposed inner wall surface of the trench. The removal of the unreacted high melting point metal film here can be performed by a method known in the art, for example, wet etching or the like.
[0016]
In the present invention, when the insulating film is buried in the trench formed in the semiconductor substrate, a part of the inner wall of the trench is exposed instead of burying the insulating film surface almost flush with the semiconductor substrate surface. An insulating film may be embedded. That is, the surface of the insulating film may be buried in the trench so as to be lower than the surface of the semiconductor substrate. Thus, in the above process, after forming the impurity diffusion layer in the semiconductor substrate, the step of etching and removing a part of the insulating film in the trench can be omitted. However, in this case, before forming the refractory metal silicide film on the exposed inner wall of the trench, the oxide film naturally formed on the inner wall of the trench or the film formed as the protective film when forming the impurity diffusion layer is removed. It is preferable to keep it.
[0017]
After the refractory metal silicide film is formed on a part of the inner wall of the trench, an insulating film may be further embedded so that the trench surface is flush with the semiconductor substrate surface. In this case, the same insulating film as described above can be used.
In the present invention, after forming the high-melting-point gold silicide film, an interlayer insulating film is further formed on the obtained semiconductor substrate in the step (v). The interlayer insulating film here is, for example, a silicon oxide film (thermal oxide film, low-temperature oxide film: LTO film, etc., high-temperature oxide film: HTO film), silicon nitride film, SOG film, PSG film, BSG film, BPSG film, etc. Can be formed by a single layer film or a laminated film. The thickness of the interlayer insulating film and the like are not particularly limited, and can be set arbitrarily. The interlayer insulating film is preferably formed in a laminated structure in which insulating films having different etching rates are formed, preferably such that the insulating film having a small etching rate is the lowermost layer. It functions as an etching stopper for the insulating film. Specifically, a silicon oxide film / silicon nitride film or the like is appropriate. In this case, the thickness of the silicon nitride film is, for example, about 10 to 200 nm.
[0018]
After that, a contact hole reaching the impurity diffusion layer is formed in the interlayer insulating film. In the contact hole, a mask pattern having an opening on a desired region of the interlayer insulating film, that is, an impurity diffusion layer is formed by a photolithography and an etching process using a predetermined mask, and the mask pattern is used as a mask. It is formed by wet etching, dry etching, or the like, but in the present invention, since the mask is misaligned and a part of the opening of the mask pattern straddles the trench element isolation, such a mask pattern is formed. By using such a contact hole, a contact hole at least partially extending over the trench element isolation is also included. The bottom of such a contact hole is connected to the inner wall of the trench, but since the refractory metal silicide film is disposed on the inner wall of the trench as described above, this refractory metal silicide film is As an etching stopper, it does not directly reach the semiconductor substrate forming the inner wall of the trench. The size and shape of the contact hole are not particularly limited, and can be set arbitrarily.
[0019]
A conductive film is buried in the contact hole. The conductive film here is suitably a metal or metal compound film usually used for contact plugs, barrier metals, wirings, electrodes, etc., for example, gold, platinum, silver, copper, aluminum, nickel , Chromium, tungsten, iron, molybdenum and other metals or alloys, and single-layer or laminated films of transparent conductive materials such as SnO ₂ , InO ₂ , ZnO, and ITO. Such a film can be formed by various methods such as a sputtering method, a CVD method, an EB method, and an evaporation method. Such a conductive film may be formed as a contact plug for embedding only the through hole by, for example, wet etching, dry etching, a CMP method, or the like, or may be formed on the interlayer insulating film in a desired shape with an electrode or a wiring. May also be arranged. Note that in the case where the conductive film is formed as a contact plug or the like, it is preferable to further form a wiring and / or an electrode connected thereto.
[0020]
As described above, even if the conductive film is buried in the contact hole, the refractory metal silicide film is disposed on a part of the inner wall of the trench by the above-described method. In addition, it is possible to prevent the conductive film from directly contacting the semiconductor substrate in the trench element isolation region.
Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.
[0021]
First, after a thermal oxide film having a thickness of about 20 nm is formed on the surface of the silicon substrate 1, a silicon nitride film having a thickness of about 150 nm is formed thereon by a low pressure CVD method. The silicon nitride film and the thermal oxide film are patterned by photolithography and anisotropic dry etching, and a region to be a field region later is opened. Thereafter, anisotropic dry etching is performed using the silicon nitride film and the thermal oxide film as an etching mask, and a trench 2 having a depth of about 400 nm is formed in a portion of the silicon substrate 1 to be a field region.
[0022]
Next, after a thermal oxide film having a thickness of about 10 nm is formed on the inner surface of the trench 2, a silicon oxide film having a thickness of about 600 nm is formed as a trench element isolation film 3 on the entire surface by a low pressure CVD method so as to fill the trench 2. Form. Using a silicon nitride film as a stopper, the trench isolation film 3 is polished by chemical mechanical polishing (CMP), and the trench isolation film 3 in a region other than the trench 2 is removed. Thereafter, the silicon nitride film is removed by wet etching using hot phosphoric acid, and the thermal oxide film is removed by etching to form a trench element isolation.
Subsequently, the obtained silicon substrate 1 is thermally oxidized to form a thermal oxide film having a thickness of about 10 nm as a gate oxide film 4 on the entire surface. A polysilicon film having a thickness of about 150 nm is formed thereon by a low pressure CVD method. The gate electrode 5 is formed by patterning the polysilicon film by photolithography and anisotropic dry etching.
[0023]
Next, a first ion implantation of a relatively low concentration is performed to form an n-type low concentration impurity diffusion layer (LDD) 7, and a silicon oxide film having a thickness of about 150 nm is formed on the entire surface by a low pressure CVD method. Then, the silicon oxide film is etched back by anisotropic dry etching to form sidewalls 6 on the side surfaces of the gate electrode. Thereafter, arsenic (As) ion implantation is performed at an acceleration energy of about 60 keV and a dose of about 3 × 10 ¹⁵ cm ⁻² , for example, using the gate electrode 5 having the sidewall 6 and the trench element isolation as a mask. In a region near the surface of the silicon substrate 1 on both sides of the electrode 5, a pair of n-type impurity diffusion layers 8 serving as a source and a drain of the MOS transistor are formed (FIG. 1A).
[0024]
Subsequently, as shown in FIG. 1B, the trench element isolation film 3 is removed by about 50 nm by an anisotropic dry etching method. At this time, the removal amount of the trench element isolation film 3 is set to be 30 to 50% of the depth of the n-type impurity diffusion layer 8 and shallower than the n-type impurity diffusion layer 8.
Next, a titanium film as a high melting point metal film is formed on the entire surface by sputtering at a thickness of about 50 nm, and is heat-treated at about 700 ° C. for about 30 seconds by an RTA method, and then the obtained silicon substrate 1 is treated with sulfuric acid and hydrogen peroxide. Immerse in a mixture of water. Thereafter, the silicon substrate 1 is immersed in a mixed solution of ammonium hydroxide and hydrogen peroxide solution, and is subjected to a heat treatment at about 850 ° C. for about 10 seconds by the RTA method, thereby forming the gate electrode 5 as shown in FIG. A titanium silicide film having a thickness of about 40 to 80 nm is formed as a high melting point metal silicide film 9 on the n-type impurity diffusion layer 8 and on the side wall thereof.
[0025]
Further, as shown in FIG. 1D, a silicon nitride film 10 having a thickness of about 30 nm is deposited on the entire surface by a low pressure CVD method, and then a silicon oxide film 11 having a thickness of about 900 nm is formed by a low pressure CVD method. Formed. Thereafter, the silicon oxide film 11 is polished to a thickness of about 200 nm by a chemical mechanical polishing (CMP) method to form an interlayer insulating film. By photolithography and anisotropic dry etching, a through hole 12 reaching the n-type impurity diffusion layer 8 is formed in the interlayer insulating film immediately above the n-type impurity diffusion layer 8 of each MOS transistor.
[0026]
Next, as shown in FIG. 1E, a laminated film 14 in which a titanium film and a titanium nitride film are laminated is formed to a thickness of about 150 nm by a sputtering method, and a tungsten film 15 is embedded in the through hole 12 by a blanket method. Thereafter, an aluminum metal film containing about 1% of copper is deposited, and the aluminum metal film is patterned on the wiring electrode 16 by photolithography and anisotropic dry etching.
In such a method of manufacturing a semiconductor device, even when a misalignment of an exposure mask occurs when a self-aligned contact (SAC) is formed in a silicon oxide-based interlayer insulating film by etching, a refractory metal silicide is formed on a trench sidewall portion. Since the film is formed and the refractory metal silicide film has a high etching selectivity with respect to the etching of the interlayer insulating film, the end of the silicon substrate in the trench is not exposed.
In the semiconductor device formed by the above method, the withstand voltage between the aluminum metal film 16 as the metal wiring and the silicon substrate 1 is about 5 to 10 V, a normal withstand voltage can be obtained, and the prevention of the leakage of the titanium silicide film can be prevented. Can be planned.
[0027]
【The invention's effect】
According to the present invention, when a self-aligned contact (SAC) is formed in an interlayer insulating film by etching, a trench element isolation is unexpectedly etched due to misalignment of an exposure mask, fluctuation of an interlayer insulating film thickness and an etching amount. In this case, the refractory metal silicide film is formed on the side wall of the trench, and the refractory metal silicide film has a high etching selectivity with respect to the interlayer insulating film, thereby avoiding exposing the semiconductor substrate. can do. Therefore, direct contact between the semiconductor substrate and the wiring electrode can be prevented, current leakage can be prevented, and a highly reliable semiconductor device can be manufactured.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional process drawing of a main part for describing an embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 2 is a schematic sectional view of a main part showing a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
1 Silicon substrate (semiconductor substrate)
2 trench 3 trench element isolation film 4 gate oxide film 5 gate electrode 6 sidewall 7 n-type low concentration impurity diffusion layer 8 n-type impurity diffusion layer 9 refractory metal silicide film 10 silicon nitride film 11 silicon oxide film 12 through-hole 13 nitridation Silicon film 14 Stacked film 15 Tungsten film 16, 23 Wiring electrode

Claims (8)

A semiconductor device formed on a semiconductor substrate having a trench element isolation structure in which an insulating film is buried in a trench, wherein a part of the inner wall of the trench is covered with a refractory metal silicide film. . 2. The semiconductor device according to claim 1, wherein an insulating film is buried in a part of the trench, and the refractory metal silicide film is formed in a self-aligned manner with respect to an inner wall of the trench where the insulating film is not buried. . Refractory metal silicide _film, CoSi _x, NiSi _x, semiconductor device according to claim 1 or 2 is either TiSi _x or ZrSi _x. (I) an insulating film is buried in a trench formed in the semiconductor substrate substantially flush with the surface of the semiconductor substrate;
(Ii) forming at least an impurity diffusion layer on the obtained semiconductor substrate;
(Iii) etching away a part of the insulating film in the trench such that a part of the inner wall of the trench is exposed;
(Iv) A semiconductor device comprising forming a refractory metal film over the entire surface of the obtained semiconductor substrate and heat-treating to form a refractory metal silicide film on at least the impurity diffusion layer and at least part of the inner wall of the trench. Manufacturing method. An insulating film is buried in a trench formed in the semiconductor substrate so that a part of the inner wall of the trench is exposed, at least an impurity diffusion layer is formed on the obtained semiconductor substrate, and a high melting point is formed on the entire surface of the obtained semiconductor substrate. A method of manufacturing a semiconductor device, comprising: forming a metal film and heat-treating to form a high-melting-point metal silicide film on at least the impurity diffusion layer and at least part of the inner wall of the trench. After forming the refractory metal silicide film, (v) further forming an interlayer insulating film on the obtained semiconductor substrate, forming a contact hole reaching the impurity diffusion layer in the interlayer insulating film, and forming a conductive film in the contact hole. The method according to claim 4 or 5, wherein the membrane is embedded. 7. The method according to claim 4, wherein the etching of the insulating film in the step (iii) is performed at about 20 to 50% of the depth of the impurity diffusion layer. The method according to any one of claims 4 to 7, wherein the refractory metal film is any one of Co, Ni, Ti and Zr.

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