JP2003133546A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents wires from being disconnected or deviated in alignment by planarizing its surface and which has high reliability and stable transistor characteristics, and to provide a method for manufacturing the same. SOLUTION: The semiconductor device comprises source/drain regions 38, 39 formed on the surface of a semiconductor substrate 31, and a gate electrode formed between the source and drain regions 38 and 39 via a gate insulating film 34. The gate electrode has a first gate electrode 35 and a second gate electrode 36. The electrode 35 is embedded in a groove formed on the surface of the substrate 31 so as to be disposed deeper at its bottom than each bottom of the source/drain region 38, 39, and the electrode 36 is connected to the electrode 35 on the upper surface of the electrode 35, and further connected to a metal wire 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a trench field effect transistor is flattened and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the progress of miniaturization in recent years, MOS transistors are miniaturized in accordance with the scaling rule. However, due to increase in parasitic resistance due to reduction of junction depth (Xj) and thinning of gate insulating film. There is a limit to miniaturization due to an increase in leak current of the gate insulating film itself.

As one of the methods for solving the miniaturization limit of such a MOS transistor, as shown in the sectional view in the channel direction of FIG. 9A and the sectional view in the gate direction of FIG. 9B, the gate insulating film 14 is contacted. The bottom surface of the gate electrode 15 is deeper than the bottom surfaces of the source / drain regions 17 and 18,
A device buried in a silicon substrate 11 has been proposed (see Japanese Patent Laid-Open No. 50-8483).

With the MOS transistor having such a structure, the depletion layer due to the drain voltage is unlikely to extend to the source region 17, so that the punch-through phenomenon can be suppressed and the channel length viewed from the top surface of the chip can be reduced. It will be possible. This MOS transistor can be manufactured by the following method.

First, as shown in FIGS. 10A and 10B, the silicon oxide film 12 is formed by using the silicon nitride film 12 having a predetermined shape formed on the silicon substrate 11 as a mask.
a, the silicon substrate 11 is etched to form a groove. Then, a silicon oxide film 13 having a thickness of 250 to 500 nm is deposited and flattened by the CMP method.

Next, as shown in FIGS. 11A and 11B, a part of the silicon oxide film 13 is removed to form a groove, and the remaining silicon oxide film 13 is used as an element isolation region 19. To do. By thermal oxidation, a new 15
A gate insulating film 14 having a thickness of about nm is formed, and a polysilicon film 15a is deposited thereon to a thickness of about 500 nm. A resist pattern 16 is formed thereon by patterning using a lithography technique.

Then, the polysilicon film 15a is removed by etching using the resist pattern 16 as a mask, and the resist pattern 16 is peeled off. As a result, FIG.
As shown in (a) and (b), the gate electrode 15 is formed.

Next, as shown in FIGS. 13A and 13B, the silicon nitride film 12 is removed by etching, and the source / drain regions 17 and 18 are formed by ion implantation.

After that, the interlayer insulating film 20, the contact plugs 21, the aluminum wirings, etc. are formed in accordance with the usual process to form the semiconductor device shown in FIGS. 9A and 9B.

[0010]

However, as described above, the buried gate electrode 15 and the contact connection portion (electrode lead-out portion) of the gate electrode 15 are simultaneously formed by using the single-layer polysilicon film 15a. Because
A high step 22 is formed on the surface of the polysilicon film 15a in the electrode lead portion with respect to the surface of the silicon substrate 11. Therefore, even if planarization is performed after depositing the interlayer insulating film 20, the step 23 still remains.

Further, in order to fill the high level difference 22, it is necessary to deposit the interlayer insulating film 20 thickly, resulting in a problem that the deposition time and the process cost increase.

Further, after depositing the interlayer insulating film 20,
Even if planarization is performed by a chemical mechanical polishing (CMP) method or the like, the surface is not perfectly flat and the step 23 remains, so that there is a problem of reducing the focal depth margin of exposure when patterning the upper wiring. .

On the other hand, in order to prevent the high step 22,
As shown in FIG. 4, when the thickness of the polysilicon film 25a itself is reduced, the polysilicon film 25 remains on the side wall of the groove only when the gate electrode is patterned, as shown in FIG. It becomes impossible to embed the gate electrode.

Further, as shown in FIG. 16, when the resist mask 26 corresponding to the shape of the gate electrode is formed and patterned on the polysilicon film 25a, the gate electrode can be formed in the groove. However, since the resist mask 26 wider than the width of the groove is formed in consideration of the misalignment in the photolithography process when forming the resist mask 26, the gate electrode 25 itself also becomes wider. As a result, as shown in FIG.
Source formed by ion implantation with a mask
The offset A occurs in the drain regions 17 and 18, the source / drain resistance increases, and the transistor characteristics are affected by the misalignment.

Moreover, since the semiconductor device has transistors having various gate lengths, the width L of the largest groove portion is large.
It is necessary to optimize the polysilicon film thickness for
The polysilicon film thickness requires L × 1/2 + safety factor α. Therefore, at present, it is impossible to reduce the thickness of the polysilicon film itself.

The present invention has been made in view of the above-mentioned problems, and provides a semiconductor device having a highly reliable and stable transistor characteristic and a flat surface to prevent disconnection and misalignment, and a method for manufacturing the same. The purpose is to do.

[0017]

According to the present invention, a semiconductor comprising a source / drain region formed on the surface of a semiconductor substrate and a gate electrode formed between the source / drain regions with a gate insulating film interposed therebetween. In the device, the gate electrode comprises a first gate electrode and a second gate electrode, and the first gate electrode is in a groove formed on the surface of the semiconductor substrate, and the bottom surface of the source / drain region is lower than the bottom surface of the source / drain region. Is buried deeply, the second gate electrode is connected to the first gate electrode on the upper surface of the first gate electrode, and
Further provided is a semiconductor device connected to the metal wiring.

According to the invention, the semiconductor substrate is etched to form a groove, a gate insulating film and a first electrode material film are formed at least in the groove, and the first electrode material film is etched. Forming a first gate electrode in the groove, depositing a second electrode material film on a semiconductor substrate including the first gate electrode, patterning it, and connecting to the first gate electrode;
There is provided a method of manufacturing a semiconductor device, which comprises forming a gate electrode and forming source / drain regions on the surface of the semiconductor substrate.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor device of the present invention generally comprises a semiconductor substrate, source / drain regions, a gate insulating film, and a gate electrode.

The semiconductor substrate used here is not particularly limited as long as it is usually used for a semiconductor memory device. For example, elemental semiconductors such as silicon and germanium, compounds such as GaAs, InGaAs and ZnSe. Semiconductors can be mentioned. Of these, silicon is preferable.

A groove is formed on the surface of the semiconductor substrate,
A gate electrode is embedded in the groove via a gate insulating film. The size and shape of the groove are not particularly limited, and it is preferable to correspond to the film thickness and shape of the gate electrode in consideration of the characteristics of the semiconductor device to be obtained.
Specific examples thereof include a cubic groove, a U-shaped groove, a V-shaped groove, and the like, but the cubic groove is preferable. The depth of the groove is
Depending on the junction depth of the source / drain region described later,
For example, a depth of about 100 to 500 nm and a bottom width of 1
For example, it is about 100 to 300 nm. The gate insulating film is
For example, it can be formed of a silicon oxide film, a silicon nitride film, or a laminated film thereof. The film thickness is not particularly limited and may be, for example, about 5 to 50 nm.

The gate electrode comprises a first gate electrode and a second gate electrode. These gate electrodes are not particularly limited as long as they are made of a conductive material usually used for electrodes, and examples thereof include polysilicon; metals such as copper and aluminum; and high-grade materials such as tungsten, tantalum and titanium. A metal having a melting point; a silicide with a metal having a high melting point; a polycide and the like can be mentioned, and among them, polysilicon is preferable. Note that the first gate electrode and the second gate electrode do not necessarily have to be made of the same conductive material. The first gate electrode and the second gate electrode have, for example, a film thickness of 50 to 50.
The second gate electrode can be formed with a thickness of about 0 nm.
It is preferably thinner than the film thickness of the first gate electrode.

The first gate electrode is formed by being buried in a groove formed on the surface of the semiconductor substrate, and the bottom surface thereof is
It is located deeper than the bottom surface of the source / drain regions formed on the surface of the semiconductor substrate. The upper surface may be flush with the surface of the semiconductor substrate or may be slightly convex.

The second gate electrode is formed so as to be connected to the first gate electrode on the upper surface of the first gate electrode. The shape and size are not particularly limited, but the first
On the gate electrode, it is suitable that it is connected to the first gate electrode with an appropriate contact resistance and, as will be described later, has a size and shape sufficient to connect with the metal wiring with an appropriate contact resistance. For example, it is preferable that it is drawn out from above the gate electrode to the semiconductor substrate side, and the drawn out part is more preferably wider than the first gate electrode. When it is drawn out to the semiconductor substrate side, it is preferable to dispose it on the semiconductor substrate via an insulating film. Examples of the insulating film in this case include a silicon oxide film, a silicon nitride film or a laminated film thereof, or an insulating film formed as an element isolation region. It is preferable that the thickness of the insulating film is equal to or greater than the degree of ensuring insulation between the semiconductor substrate and the gate electrode. Further, the second gate electrode is usually a metal wiring further formed on the second gate electrode via an interlayer insulating film formed thereon, a contact hole formed in the interlayer insulating film, and a contact formed therein. It is connected through a plug or a conductive film. The connection portion with the metal wiring may be any region of the second gate electrode, but it is preferable that the connection portion is connected to the portion extended to the semiconductor substrate side, that is, above the semiconductor substrate.

The position / junction depth, size, impurity concentration, etc. of the source / drain region can be appropriately adjusted in consideration of the size, performance, etc. of the semiconductor device to be obtained. For example, the junction depth of the source / drain region preferably overlaps only a part of the side wall of the gate electrode, that is, is smaller than the depth of the groove formed in the semiconductor substrate.

In the method of manufacturing a semiconductor device of the present invention, first, the semiconductor substrate is etched to form a groove.
In this case, the groove can be formed by using photolithography and etching processes. Specifically, a silicon nitride film and a resist film are formed on the entire surface of a semiconductor substrate, an opening having a shape corresponding to a groove is formed in the resist film by a photolithography and etching process, and the resist film is used as a mask. , The silicon nitride film, the silicon oxide film, and the semiconductor substrate are etched. Examples of the etching here include wet etching using an acid or alkali solution and dry etching such as RIE.

Next, a gate insulating film and a first electrode material film are formed at least in the groove, and the first electrode material film is etched to form a first gate electrode in the groove. The gate insulating film and the first electrode material film are formed, for example, by a thermal oxidation method, a CVD method,
Various methods such as a sputtering method can be appropriately selected and formed. These films can be embedded only in the groove by forming the entire surface of the semiconductor substrate including the groove and performing anisotropic etching. Alternatively, it may be removed by the CMP method. Further, when forming these films on the entire surface of the semiconductor substrate, it is preferable to leave the silicon nitride film formed in the previous step and use this silicon nitride film as an etching stopper in the CMP method.

A second layer is formed on the semiconductor substrate including the first gate electrode.
An electrode material film is deposited and patterned to form a second electrode connected to the first gate electrode, and the second electrode material film is the first electrode.
It can be formed similarly to the electrode material film, and is preferably formed on the entire surface of the semiconductor substrate including the first gate electrode.
Patterning can be performed by using photolithography and etching processes.

Further, source / drain regions are formed on the surface of the semiconductor substrate. In this case, the source / drain regions can be formed by introducing impurities into the semiconductor substrate, and examples thereof include ion implantation. Ion implantation can be formed in a self-aligned manner with respect to the gate electrode by using the first and second gate electrodes as a mask. The acceleration energy of ion implantation, the conditions such as dose, and the type of impurities can be appropriately selected.

A semiconductor device and a method of manufacturing the same according to the present invention are
It will be described in detail with reference to the drawings. The semiconductor device of the present invention has a gate electrode composed of a first gate electrode 35 and a second gate electrode 36, as shown in the channel direction sectional view of FIG. 1A and the gate direction sectional view of FIG. is doing. The first gate electrode 35 is embedded in the groove formed on the surface of the silicon substrate 31 via the gate insulating film 34,
The bottom surface is located deeper than the source / drain regions 38 and 39. The second gate electrode 36 is formed on the silicon substrate 31 and the element isolation film 1 from above the first gate electrode 35.
The silicon nitride film 32 is formed on the silicon nitride film 32 and is connected to the contact plug 41.

In this semiconductor device, the groove is 250
The first gate electrode 35 is formed to a depth of about nm.
Is about 350 nm, and the second gate electrode 36 is 50 n
It has a film thickness of about m. In addition, the silicon nitride film 32
Has a film thickness of 150 to 250 nm, and the junction depth of the source / drain regions 38 and 39 is about 100 nm.
This semiconductor device can be manufactured by the following method.

First, as shown in FIGS. 2A and 2B, a silicon oxide film 32a having a film thickness of about 10 to 30 nm and a silicon nitride film 32 are formed on a silicon substrate 31 which is a first conductivity type semiconductor substrate. A film thickness of about 150 to 250 nm is deposited,
A resist pattern (not shown) having a predetermined shape is formed by using the lithography technique. Using this resist pattern as a mask, the silicon nitride film 32 is etched to remove the resist pattern. As shown in FIGS. 3A and 3B, using the silicon nitride film 32 as a mask, the silicon oxide film 32a / silicon substrate 31 is formed.
Is etched to form a groove. Then, FIG. 4 (a)
As shown in FIGS. 5B and 5B, a silicon oxide film 13 having a thickness of about 250 to 500 nm is deposited, and as shown in FIGS. 5A and 5B, planarization is performed by the CMP method.

Next, a part of the silicon oxide film 13 is removed to form a groove portion, and the remaining silicon oxide film 1 is formed.
3 is an element isolation region 19.

Next, thermal oxidation is performed to form a film thickness of 10 n in the groove.
A gate insulating film 34 having a thickness of about m is formed, and a first polysilicon film 35a as a first gate electrode material is formed on the gate insulating film 34 to a thickness of 30.
The layers are stacked in the range of 0 to 400 nm. Here, in order to completely fill the trench with the gate electrode, the first polysilicon film 35a is formed.
Secures a film thickness of ½ or more of the width L of the groove bottom in the channel direction.

Subsequently, the first polysilicon film 35a is polished by the CMP method until the surface of the silicon nitride film 32 is exposed, and the first gate electrode 35 as a buried gate electrode is formed.
To form. The silicon nitride film 32 functions as an etching stopper. The first polysilicon film 35a may be removed by anisotropic etching.

Next, as shown in FIGS. 6A and 6B, the second gate electrode 3 is formed on the obtained silicon substrate 31.
A second polysilicon film is deposited as the 6th material to a film thickness of about 50 nm, and a resist pattern 37 processed into a predetermined shape is formed on the second polysilicon film by a lithography technique.

Next, as shown in FIGS. 7A and 7B, the second polysilicon film / silicon nitride film 32 is removed by etching using the resist pattern 37 as a mask to form a contact connecting portion. First gate electrode 35
A second gate electrode 36 is formed over a part of the surface of the semiconductor substrate 31. Then, the resist pattern 37 is peeled off.

Subsequently, as shown in FIGS. 8A and 8B, arsenic ions were implanted at an implantation energy of ¹⁵ keV and an implantation amount of about 3 × 10 ¹⁵ cm ^-2 , and then the crystallinity was restored and impurities were removed. Then, heat treatment is performed to activate the source region 38 and the drain region 39.

Then, as shown in FIGS. 1 (a) and 1 (b), BPSG (Boro) is formed on the obtained silicon substrate 31.
n Phosphorus Silicate Glass) 1000 protective film 40
Deposit about nm. Further, the contact plug 41 is formed and aluminum wiring or the like is formed in accordance with a usual process to complete the semiconductor device of the present invention.

In the prior art, it was necessary to leave the thick first gate electrode pattern optimized for filling the trench on the field oxide film wider than the trench width in consideration of the alignment margin of the contact. But,
In the above-described embodiment, since the wiring made of the second gate electrode material can be connected directly above the first gate electrode material embedded in the trench, the wiring made of the first gate electrode material can be formed at the contact portion with the metal wiring. It is not necessary to form a wiring portion wider than the trench width. Therefore,
Instead of extending the thick first gate electrode material on the field oxide film, the thin second gate electrode material can be arranged, and the step difference at the contact connection point between the gate electrode and the metal wiring can be reduced. You can

[0041]

According to the present invention, by forming the gate electrode as a two-layer structure of the first and second gate electrodes,
It is possible to reduce the step difference at the connection portion of the gate electrode with the contact only by adding a simple manufacturing process. Therefore, it is possible to secure a focus depth margin of exposure when patterning the metal wiring formed on the connection portion of the gate electrode with the contact, prevent a short circuit of the wiring pattern, and provide a highly reliable semiconductor device. It will be possible to obtain.

Further, the interlayer insulating film formed on the contact portion of the gate electrode can be made sufficiently thin, and the manufacturing cost can be reduced by shortening the deposition time of the interlayer insulating film. Become.

[Brief description of drawings]

FIG. 1 is a schematic plan view and a sectional view of a main part of a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional process diagram of a main part of the semiconductor device of FIG.

FIG. 3 is a schematic cross-sectional process diagram of a main part of the semiconductor device of FIG.

FIG. 4 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

5A to 5C are schematic cross-sectional process diagrams of a main part of the semiconductor device of FIG.

FIG. 6 is a schematic cross-sectional process diagram of a main part of the semiconductor device of FIG.

FIG. 7 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

FIG. 8 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

9A and 9B are a schematic plan view and a sectional view of a main part of a conventional semiconductor device.

10 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

FIG. 11 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

12 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

13 is a schematic cross-sectional process diagram of a main part of the semiconductor device in FIG.

FIG. 14 is a schematic cross-sectional process diagram of a main part for explaining a problem in a method for manufacturing a semiconductor device.

FIG. 15 is a schematic cross-sectional process diagram of a main part for explaining a problem in the method for manufacturing a semiconductor device.

FIG. 16 is a schematic cross-sectional process diagram of a main part for explaining a problem in another method for manufacturing a semiconductor device.

FIG. 17 is a schematic cross-sectional process diagram of a main part for explaining a problem in another method for manufacturing a semiconductor device.

[Explanation of symbols]

13 Silicon oxide film 19 Element isolation film 31 Silicon substrate (semiconductor substrate) 32 Silicon nitride film (insulating film) 32a Silicon oxide film 34 Gate insulating film 35 First Gate Electrode 35a First polysilicon film 36 Second gate electrode 37 resist pattern 38, 39 source / drain regions 40 Protective film 41 contact plug

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshimitsu Yamauchi             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F-term (reference) 4M104 AA01 AA02 AA05 AA06 BB01                       BB02 BB04 BB14 BB17 BB18                       BB24 CC05 DD19 DD37 DD43                       DD66 DD72 DD75 FF06 FF14                       FF26 GG09 GG10 GG14 HH12                       HH14 HH20                 5F033 GG00 GG01 GG02 HH04 HH08                       HH11 HH18 HH19 HH21 HH26                       JJ01 JJ04 JJ08 JJ11 JJ18                       JJ19 JJ21 JJ26 KK04 KK08                       KK11 KK18 KK19 KK21 KK26                       LL04 MM07 NN20 QQ08 QQ09                       QQ10 QQ16 QQ25 QQ31 QQ37                       QQ48 QQ49 QQ59 QQ73 RR04                       RR06 RR15 VV06 XX01 XX02                       XX03 XX31 XX34                 5F140 AA15 AA40 BA01 BA03 BA07                       BA09 BA10 BD05 BD07 BD10                       BE03 BE07 BE09 BE10 BF03                       BF04 BF05 BF07 BF08 BF11                       BF13 BF14 BF15 BF17 BF18                       BF43 BF58 BF60 BG28 BG30                       BG38 BG40 BG58 BJ27 BK13                       BK21 CA03 CC01 CC03 CC07                       CC08 CE07 CE08

Claims (3)

[Claims] 1. A semiconductor device comprising a source / drain region formed on a surface of a semiconductor substrate, and a gate electrode formed between the source / drain regions via a gate insulating film, wherein the gate electrode is A first gate electrode and a second gate electrode, wherein the first gate electrode is embedded in a groove formed on the surface of the semiconductor substrate such that the bottom surface of the source / drain region is deeper than the bottom surface of the source / drain region; The semiconductor device, wherein the two gate electrodes are connected to the first gate electrode on the upper surface of the first gate electrode and further connected to metal wiring. 2. The second gate electrode is drawn out from above the first gate electrode onto an insulating film formed on the surface of the semiconductor substrate, and the connection portion with the metal wiring is arranged above the semiconductor substrate. 1. The semiconductor device according to 1. 3. A semiconductor substrate is etched to form a groove, a gate insulating film and a first electrode material film are formed at least in the groove, and the first electrode material film is etched to form a first gate in the groove. An electrode is formed, a second electrode material film is deposited on the semiconductor substrate including the first gate electrode, and patterned to form a second gate electrode connected to the first gate electrode. A method of manufacturing a semiconductor device, which comprises forming a drain region.