JPH0334574A - Mos type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress the breakdown at source and drain diffusion layers effectively by thickening a gate insulating film at the region where source and drain diffusion layers and a gate electrode overlap each other than that above a channel region. CONSTITUTION:A gate electrode 3, consisting of a polycrystalline silicon film, is formed through a gate insulating film 2 on a p-type silicon substrate 1 where an element isolating insulating film is formed. N<+>-diffusion layers 4 and 5 to become a source and a drain in self-alignment are formed for a gate electrode 3. The n<+>-diffusion layers 4 and 5 overlap the gate electrode 3 partially, and the gate insulating film 22 at this overlapping part is made thicker than the gate insulating film 2 above a channel region. The topside of the substrate, where elements are formed, is covered with a CVD insulating film, and a contact hole is opened in this film, and Al wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a finely structured MOS type semiconductor device and a manufacturing method thereof.

(Prior Art) Various integrated circuits in which MOS transistors are integrally formed are becoming increasingly miniaturized and highly integrated due to advances in processing technology. As devices become smaller, gate insulating films are becoming extremely thin due to scaling laws. Recently, in such fine MO8 devices, an increase in leakage current generated in the diffusion layer near the gate electrode has been attracting attention as a major problem. This is because a deep depletion state occurs near the interface between the source and drain diffusion layers and the gate insulating film due to the strong electric field caused by the thinning of the gate insulating film, resulting in a shift from the valence band to the conduction band within the diffusion layer. This is caused by electron tunneling (Zener). Leakage current due to this new Zener phenomenon increases the power consumption of the integrated circuit and also reduces the reliability of the device.

(Problems to be Solved by the Invention) As described above, in the finely structured MOS transistor, breakdown occurring in the source and drain diffusion layers directly under the gate electrode is a major problem.

An object of the present invention is to provide a MOS type semiconductor device and a method for manufacturing the same that solves such problems.

[Structure of the Invention] (Means for Solving the Problems) A MOS semiconductor device according to the present invention has a gate insulating film thicker in the region where the gate electrode and the source and drain diffusion layers overlap than that on the channel region. It is characterized by

In manufacturing a MOS type semiconductor device having such a structure, the method of the present invention involves forming a gate electrode on a semiconductor substrate via a gate insulating film, and then etching the gate insulating film under the gate electrode by isotropic etching. A gap is formed by etching a predetermined distance laterally from the end of the gate electrode, and thermal oxidation is performed to embed an insulating film thicker than the original gate insulating film under the end of the gate electrode. .

(Function) In the device structure of the present invention, by making the gate insulating film in the region where the source and drain diffusion layers overlap with the gate electrode thicker than that on the channel region, the source and drain Breakdown in the diffusion layer can be prevented.

Further, according to the method of the present invention, after forming the gate electrode, a thick gate insulating film can be formed under the end of the gate electrode by isotropic etching and thermal oxidation. That is, a step can be formed in the gate insulating film in a self-aligned state with the gate electrode without requiring a PEP process or a mask alignment process.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of the MOS transistor according to one embodiment. A gate electrode 3 made of a polycrystalline silicon film is formed on a p-type silicon substrate 1 on which an element isolation insulating film is formed, with a gate insulating film 2 interposed therebetween.

n that becomes the source and drain in self-alignment with the gate electrode 3
+ Diffusion layers 4 and 5 are formed. The n+ diffusion layers 4 and 5 partially overlap the gate electrode 3, and the gate insulating film 2□ at this overlapping portion is formed thicker than the gate insulating film 21 on the channel region. The substrate on which the elements are formed is covered with a CVD insulating film, and contact holes are formed in this to form Aρ wiring.

2(a) to 2(d) are cross-sectional views of the manufacturing process of the device of FIG. 1. After forming an element isolation insulating film on a p-type silicon substrate 1, a gate insulating film 2I with a thickness of 50 to 200λ is formed by thermal oxidation, and a 3° polycrystalline silicon film is deposited on this by a low pressure plasma CVD method (second Figure (a)). Impurity ions are implanted into the polycrystalline silicon film 3° to impart conductivity.

Next, the polycrystalline silicon film 3° is patterned by PEP and reactive ion etching to form the gate electrode 3. Then, using the gate electrode 3 as a mask, impurity ions are implanted to form an n+ diffusion layer 4.5 (Fig. C'j52(b)).

Thereafter, the gate insulating film 21 is laterally etched by an etching method in which the etching rate for SiO2 is higher than that for St and is isotropic, such as solution etching using ammonium fluoride, and the edges of the gate electrode 3 are etched. at least a predetermined distance from the diffusion layer 4.5
Remove the upper part (Fig. 2(C)). Thereafter, the exposed bottom of the gate electrode 3 and the substrate 1 are oxidized by a thermal oxidation method, and a gate insulating film 2, which is thicker than the original gate insulating film 2I, is buried under the gate electrode 3 (
Figure 2(d)).

In the device of this example, by forming a thick gate insulating film 22 on top of the diffusion layers 4 and 5 in the region overlapping with the gate electrode 3, breakdown in the diffusion layer due to thinning of the gate insulating film in the fine structure is prevented. can be effectively suppressed.

Further, according to the process of this embodiment, the thickness of the gate insulating film is formed in such a manner that the change in thickness within a minute gate length is self-aligned with the gate electrode. This process is extremely simple compared to, for example, a method in which a thick gate insulating film is formed, a part of it is selectively etched to form a thinner gate insulating film, and a gate electrode is patterned on this. Controllability is also excellent.

Note that the present invention is not limited to the above embodiments. For example, in the method of the embodiment, after forming the gate electrode, a part of the gate insulating film was removed using lateral etching to form a new thick gate insulating film.

Instead of this method, it is also possible to first form a thick gate insulating film, and then etch the part above the channel region except for the position overlapping with the source and drain diffusion layers to form a thin gate insulating film there. Complex: 1 step is possible.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, the MOS semiconductor device according to the present invention has the following effects:
Flakdown in the source and drain diffusion layers, which is a problem specific to microstructures, can be effectively suppressed.

Further, according to the method of the present invention, MOS with such a fine structure
A type semiconductor device can be formed in a simple process with good controllability.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) show a MOS according to an embodiment of the present invention.
) A plan view showing a transistor and its AA' cross-sectional view, Figures 2 (a) to (d) are cross-sectional views showing the manufacturing process of the MOS transistor, and Figure 3 is a cross-sectional view showing the conventional MOS transistor structure. , FIG. 4 is a diagram showing the state of breakdown due to miniaturization in a conventional MOS transistor. 1...p-type silicon substrate, 2(2,,2□)...gate insulating film, 3...gate electrode, 4,5...n+ type scattered layer

Claims (2)

[Claims] (1) In a MOS semiconductor device in which a gate electrode is formed on a semiconductor substrate via a gate insulating film, and source and drain diffusion layers are formed partially overlapping the gate electrode, the source and drain diffusion layers and the gate A MOS type semiconductor device characterized in that a gate insulating film in a region where electrodes overlap is set to be thicker than that on a channel region. (2) Forming a gate electrode on a semiconductor substrate via a gate insulating film, and laterally etching the insulating film under the gate electrode from the end of the gate electrode using an isotropic etching method to form a part under the end of the gate electrode. forming a gap in a predetermined range; performing thermal oxidation to fill the gap under the end of the gate electrode with a gate insulating film thicker than the original gate insulating film thickness; using the gate electrode as a mask, impurities are added to the substrate. 1. A method for manufacturing a MOS type semiconductor device, comprising: forming source and drain diffusion layers by doping.