JPH0366166A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0366166A JPH0366166A JP1201362A JP20136289A JPH0366166A JP H0366166 A JPH0366166 A JP H0366166A JP 1201362 A JP1201362 A JP 1201362A JP 20136289 A JP20136289 A JP 20136289A JP H0366166 A JPH0366166 A JP H0366166A
- Authority
- JP
- Japan
- Prior art keywords
- buried layer
- groove
- semiconductor
- drain
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000001939 inductive effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 9
- 238000000605 extraction Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 2
- 239000003513 alkali Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 54
- 230000002093 peripheral effect Effects 0.000 description 5
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
この発明は、半導体装置、特に横形のパワーＭＯＳＦＥ
Ｔ （以下ＬＤＭＯＳという）に関し、そのドレイン抵
抗を低減させたものである。[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to semiconductor devices, particularly horizontal power MOSFETs.
Regarding T (hereinafter referred to as LDMOS), its drain resistance is reduced.
（従来の技術）
パワーＭＯＳＦＥＴは、その周辺回路となるＣＭｏ５ｓ
とともに１チツプ上に集積されてパワーＩＣとして構成
されることがある。このとき、パワーＭＯＳＦＥＴは、
そのドレイン電極を半導体基板の主面側からとる横形の
構造とすると、周辺回路との電気的分離が容易になり、
パワーＭＯＳＦＥＴのドレイン電圧の変動が基板を通し
て周辺回路に影響を及ぼすことがなくなる。このため、
パワーＩＣを構成するパワーＭＯＳＦＥＴは、ＬＤＭＯ
Ｓが多用される。(Prior art) Power MOSFET is a CMo5s peripheral circuit.
They may be integrated together on one chip to form a power IC. At this time, the power MOSFET is
If the drain electrode is formed into a horizontal structure from the main surface side of the semiconductor substrate, electrical isolation from peripheral circuits becomes easy.
Fluctuations in the drain voltage of the power MOSFET no longer affect peripheral circuits through the substrate. For this reason,
The power MOSFETs that make up the power IC are LDMO
S is often used.
第３図は、このようなＬＤＭＯＳの従来例を示している
。同図中、１はｐ形基板であり、ｐ形基板１の主面には
ｎ＋埋込層２が形成され、その上に第１導電形半導体と
してのｎ形エピタキシャル層３が形成されている。ｎ形
エピタキシャル層３は、ＬＤＭＯ５のドレイン領域とな
るものであり、その主面にはｐチャネル領域４が形成さ
れている。FIG. 3 shows a conventional example of such an LDMOS. In the figure, 1 is a p-type substrate, an n+ buried layer 2 is formed on the main surface of the p-type substrate 1, and an n-type epitaxial layer 3 as a first conductivity type semiconductor is formed thereon. . The n-type epitaxial layer 3 serves as a drain region of the LDMO 5, and has a p-channel region 4 formed on its main surface.
ｐチャネル領域４内の表面部にはｎ＋ソース領域５が形
成され、このｎ＋ソース領域５とｎ形エピタキシャル層
３との間におけるｐチャネル領域４上には、そのｐチャ
ネル領域４の表面層にチャネルを誘起させるためのゲー
ト電極７がゲート絶縁膜としてのゲート酸化膜６を介し
て形成されている。８は中間絶縁層、９はソース電極で
ある。An n+ source region 5 is formed in the surface portion of the p channel region 4, and an n+ source region 5 is formed on the p channel region 4 between the n+ source region 5 and the n type epitaxial layer 3 in the surface layer of the p channel region 4. A gate electrode 7 for inducing a channel is formed through a gate oxide film 6 as a gate insulating film. 8 is an intermediate insulating layer, and 9 is a source electrode.
また、ｐチャネル領域４側方のｎ形エピタキシャル層３
の部分にはドレイン引出し用のｎ形拡散領域２１がｎ＋
埋込層２に達するように形成され、このｎ形拡散領域２
１内の表面部に形成されたｎ＋ ドレインコンタクト領
域２２に接続されるようにドレイン電極２３が形成され
ている。ｎ形拡散領域２１は深く拡散するため、その横
幅も広く形成されている。Also, the n-type epitaxial layer 3 on the side of the p-channel region 4
An n-type diffusion region 21 for leading out the drain is located in the n+
This n-type diffusion region 2 is formed to reach the buried layer 2.
A drain electrode 23 is formed so as to be connected to an n+ drain contact region 22 formed on the surface of the semiconductor device 1 . Since the n-type diffusion region 21 is deeply diffused, its width is also wide.
なお、図示省略されているがＬＤＭＯ３と同一基板中に
ＣＭＯ３等を集積したパワーＩＣとする場合には、ｎ形
エピタキシャル層３には、上述のＬＤＭＯ８の形成領域
外の部位でｐ形基板１に達するｐ形分離領域が形成され
てＬＤＭＯ８の形成領域と周辺回路領域との接合分離が
行われ、その周辺回路領域にＣＭＯ８等が形成されてい
る。Although not shown in the drawings, in the case of a power IC in which a CMO3 and the like are integrated in the same substrate as the LDMO3, the n-type epitaxial layer 3 includes a portion of the p-type substrate 1 outside the above-mentioned LDMO8 formation region. A p-type isolation region is formed to separate the region where the LDMO 8 is formed and the peripheral circuit region, and the CMO 8 and the like are formed in the peripheral circuit region.
そして、ドレイン電極２３にドレイン電圧が加えられ、
ゲート電極７に閾値電圧以上のゲート電圧が加えられる
とチャネルが導通し、ドレイン電極２３から、ｎ＋ ド
レインコンタクト領域２２→ｎ形拡散領域２１→ｎ＋埋
込層２→ｎ形エピタキシャル層３をほぼ垂直に上に流れ
てチャネルからｎ＋ソース領域５→ソース電極９の経路
でドレイン電流が流れる。このように、ＬＤＭＯ５は、
ｎ＋埋込層２と表面から形成したｎ形拡散領域２１を通
る経路でドレイン電流を引出す構造となっている。Then, a drain voltage is applied to the drain electrode 23,
When a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 7, the channel becomes conductive, and from the drain electrode 23, the n+ drain contact region 22→n-type diffusion region 21→n+ buried layer 2→n-type epitaxial layer 3 is almost vertically connected. A drain current flows upward from the channel through a path from the n+ source region 5 to the source electrode 9. In this way, LDMO5 is
The structure is such that the drain current is drawn out through a path passing through the n+ buried layer 2 and the n-type diffusion region 21 formed from the surface.
（発明が解決しようとする課題）
従来のＬＤＭＯ８は、ｎ＋埋込層と、このｎ＋埋込層に
達するように深く形成され且つ横幅の店いｎ形拡散領域
でドレイン電流を引出す構造となっていたため、半導体
の主面に占める装置面積が広くなるとともにｎ＋埋込層
とｎ形拡散領域の抵抗（ドレイン引出し抵抗）がドレイ
ン抵抗に直列に入ってその抵抗値が大になり、オン抵抗
が大きいという問題があった。このオン抵抗は、縦形の
パワーＭＯＳＦＥＴ （ＶＤＭＯ３）と比べると約２倍
以上である。(Problems to be Solved by the Invention) The conventional LDMO 8 has a structure in which a drain current is drawn through an n+ buried layer and an n-type diffusion region that is formed deeply to reach the n+ buried layer and has a narrow width. Therefore, as the area occupied by the device on the main surface of the semiconductor increases, the resistance of the n+ buried layer and the n-type diffusion region (drain extraction resistance) enters in series with the drain resistance, increasing its resistance value and increasing the on-resistance. There was a problem. This on-resistance is approximately twice as high as that of a vertical power MOSFET (VDMO3).
そこで、この発明は、半導体の主面に占める装置面積を
縮小するとともにドレイン引出し抵抗を低減して単位面
積当りのオン抵抗を小さくすることのできる半導体装置
を提供することをＵ的とする。Therefore, an object of the present invention is to provide a semiconductor device that can reduce the area occupied by the device on the main surface of the semiconductor, reduce the drain extraction resistance, and reduce the on-resistance per unit area.
［発明の構成］
（課題を解決するための手段）
この発明は上記課題を解決するために、第１導電形半導
体の主面に形成された第２導電形のチャネル領域と、該
チャネル領域内の表面部に形成された第１導電形のソー
ス領域と、該ソース領域と前記第１導電形半導体との間
における前記チャネル領域上にゲート絶縁膜を介して設
けられ当該チャネル領域にチャネル２を誘起させるゲー
ト電極と、前記第１導電形半導体の主面から所要の深さ
に形成され第１導電形で且つ当該第１導電形半導体より
高濃度の埋込層と、前記第１導電形半導体の主面から前
記埋込層に達する構内で当該埋込層に接続され前記第１
導電形半導体の主面に引出された金属製のドレイン電極
とを有することを要旨とする。[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention includes a channel region of a second conductivity type formed on the main surface of a semiconductor of a first conductivity type, and a channel region within the channel region. a source region of a first conductivity type formed on the surface of the semiconductor; and a channel 2 provided in the channel region via a gate insulating film on the channel region between the source region and the first conductivity type semiconductor. a gate electrode to be induced; a buried layer formed at a predetermined depth from the main surface of the first conductivity type semiconductor and of a first conductivity type and having a higher concentration than the first conductivity type semiconductor; and the first conductivity type semiconductor. The first layer is connected to the buried layer in a section that reaches the buried layer from the main surface of the
The gist is that it has a metal drain electrode drawn out on the main surface of the conductive semiconductor.
また、前記溝は、前記埋込層の形成された深さ位置で横
方向に張出して形成してなることもこの発明の要旨とし
て包含する。The gist of the present invention also includes that the groove is formed to extend laterally at a depth position where the buried layer is formed.
（作用）
半導体装置は、ドレイン電極を第１導電形半導体の主面
側からとるＬＤＭＯ８として構成される。(Function) The semiconductor device is configured as an LDMO 8 in which the drain electrode is taken from the main surface side of the first conductivity type semiconductor.
このとき、金属製のドレイン電極を高濃度の埋込層に直
接接続させる溝は、この埋込層に達する拡散領域を形成
する場合と比べると、狭幅に形成することができる。し
たがって、半導体の主面に占める装置面積の縮小を図る
ことが可能となる。また、ドレイン電極は、高濃度の埋
込層に直接接続され、その間に拡散領域を形成すること
が不要となるため、ドレイン引出し抵抗が減少する。こ
の結果、単位面積当りのオン抵抗を小さくすることが可
能となる。At this time, the trench that directly connects the metal drain electrode to the highly doped buried layer can be formed narrower than the trench that connects the metal drain electrode directly to the buried layer. Therefore, it is possible to reduce the area occupied by the device on the main surface of the semiconductor. Further, the drain electrode is directly connected to the highly doped buried layer, and it is not necessary to form a diffusion region therebetween, so that the drain extraction resistance is reduced. As a result, it is possible to reduce the on-resistance per unit area.
上記の溝を、埋込層の形成された深さ位置で横方向に張
出すように形成したときは、ドレイン電流の経路上にお
ける埋込層の長さが減るため、ドレイン引出し抵抗が一
層減少する。したがって、単位面積当りのオン抵抗を一
層小さくすることが可能となる。When the above groove is formed so as to extend laterally at the depth position where the buried layer is formed, the length of the buried layer on the path of the drain current is reduced, so the drain extraction resistance is further reduced. do. Therefore, it is possible to further reduce the on-resistance per unit area.
（実施例）
以下、この発明の実施例を第１図及び第２図に基づいて
説明する。(Example) Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.
なお、第１図及び第２図において、前記第３図における
部材及び部位と同一ないし均等のものは、前記と同一符
号を以って示し、重複した説明を省略する。In FIGS. 1 and 2, the same or equivalent members and parts as in FIG. 3 are designated by the same reference numerals, and redundant explanation will be omitted.
まず、半導体装置としてのＬＤＭＯ３の構成を説明する
と、この実施例では、前記第３図におけるｎ形拡散領域
の代りに、その部分に溝１１が形成されている。溝１１
は、ｎ形エピタキシャル層３の表面から、成る所定の深
さ位置までは、はぼ均一の幅を持ち、その下方の部分で
断面菱形の空洞状に店かり、その断面菱形の側方突起部
がｎ＋埋込層２の中心深さとほぼ一致して、このｎ＋埋
込層２内に張出されるように形成されている。溝１１の
内面には、ドレインコンタクト領域となるｎ＋拡散層１
２が形成され、ドレイン電極１３を形成しているＡｉ等
の金属は、この溝１１の１ノ弓部まで埋込まれるように
形成されている。そして、ドレイン電極１３は、この溝
１１内でｎ＋拡散層１２を介して直接ｎ＋埋込層２に接
続されている。First, the structure of the LDMO 3 as a semiconductor device will be explained. In this embodiment, instead of the n-type diffusion region in FIG. 3, a groove 11 is formed in that portion. Groove 11
has a nearly uniform width from the surface of the n-type epitaxial layer 3 to a predetermined depth position, and forms a cavity with a rhombus cross section in the lower part, and has a lateral protrusion with a rhombus cross section. is formed so as to substantially coincide with the center depth of the n+ buried layer 2 and to extend into the n+ buried layer 2. On the inner surface of the groove 11, there is an n+ diffusion layer 1 which becomes a drain contact region.
2 is formed, and the metal such as Ai forming the drain electrode 13 is formed so as to be buried up to the first arch part of this groove 11. The drain electrode 13 is directly connected to the n+ buried layer 2 within this groove 11 via the n+ diffusion layer 12.
次いで、第２図を用いて、製造方法の一例を説明するこ
とにより、その構成をさらに詳述する。Next, the configuration will be further explained in detail by explaining an example of the manufacturing method using FIG. 2.
なお、以下の説明において、（ａ）〜（ｈ）の各項目記
号は、第２図の（ａ）〜（ｈ）のそれぞれに対応する。In the following description, the item symbols (a) to (h) correspond to (a) to (h) in FIG. 2, respectively.
（ａ） ｐ形基板１の主面にｎ＋埋込層２を形成し、
その上にｎ形エピタキシャル層３を成長させたエピタキ
シャル基板を準備する。ｐ形基板１は、例えば（１１０
）面を有する基板を使用することにより、ｎ形エピタキ
シャル層３の表面も（１１，０）面となっている。(a) forming an n+ buried layer 2 on the main surface of a p-type substrate 1;
An epitaxial substrate on which an n-type epitaxial layer 3 is grown is prepared. The p-type substrate 1 is, for example, (110
) plane, the surface of the n-type epitaxial layer 3 also has a (11,0) plane.
（ｂ） ｎ形エピタキシャル層３の表面にゲト酸化膜
６を形成したのち、ポリＳｔを堆積しパターニングして
ゲート電極７を形成する。(b) After forming a gate oxide film 6 on the surface of the n-type epitaxial layer 3, polySt is deposited and patterned to form a gate electrode 7.
（Ｃ） ゲート電極７等をマスクとしたｐ形不純物及
びｎ形不純物の拡散によりｐチャネル領域４及びｎ＋ソ
ース領域５を形成し、さらに表面には中間絶縁層８を形
成する。(C) A p-channel region 4 and an n+ source region 5 are formed by diffusion of p-type impurities and n-type impurities using the gate electrode 7 etc. as a mask, and an intermediate insulating layer 8 is further formed on the surface.
（ｄ） 中間絶縁層８における溝の形成部分を孔開け
したのち、反応性イオンエツチングにより、ｎ形エピタ
キシャル層３の領域に所要深さの垂直溝１４を掘る。(d) After drilling the groove formation portion in the intermediate insulating layer 8, a vertical groove 14 of a required depth is dug in the region of the n-type epitaxial layer 3 by reactive ion etching.
（ｅ） 垂直溝１４の内面及び中間絶縁層８の表面に
ＳｉＮ膜によるエツチングストップ膜１５を堆積後、再
び反応性イオンエツチングにより垂直溝１４ａを掘り下
げる。このとき、垂直溝１４．１４ａは、その側面に（
００１）面が出るように掘られる。(e) After depositing an etching stop film 15 made of a SiN film on the inner surface of the vertical groove 14 and the surface of the intermediate insulating layer 8, the vertical groove 14a is dug again by reactive ion etching. At this time, the vertical groove 14.14a has (
001) Digged so that the surface is exposed.
（ｆ） ヒドラジン、エチレンジアミン等のアルカリ
系異方性エツチング液を用いて、下部の垂直溝１４ａの
みを異方性エツチングする。アルカリ系異方性エツチン
グ液で８１をエツチングすると、（１１１）面で著しく
エッチレートが遅くなるため、（１１１）面が露出した
ところでエツチングが止り、ｎ＋埋込層２の深さ位置に
おいて、浅い角度で断面菱形状に横方向に広がった溝１
１が形成される。(f) Using an alkaline anisotropic etching solution such as hydrazine or ethylenediamine, only the lower vertical groove 14a is anisotropically etched. When etching 81 with an alkaline anisotropic etching solution, the etching rate becomes significantly slower on the (111) plane, so the etching stops when the (111) plane is exposed, and a shallow layer is formed at the depth of the n+ buried layer 2. Groove 1 that spreads laterally with a diamond-shaped cross section at an angle
1 is formed.
（ｇ） エツチングストップ膜１５を除去後、溝１１
の内面にｎ＋拡散層１２を形成する。(g) Groove 11 after removing etching stop film 15
An n+ diffusion layer 12 is formed on the inner surface.
（ｈ） 中間絶縁層８におけるソース電極のコンタク
ト部に孔開けを行った後、ＣＶＤ法により溝１１の内部
まで及ぶようにＡｌ膜を堆積し、パターニングを施して
ドレイン電極１３及びソース電極９を形成する。(h) After drilling a hole in the contact portion of the source electrode in the intermediate insulating layer 8, an Al film is deposited by CVD so as to extend into the groove 11, and patterned to form the drain electrode 13 and the source electrode 9. Form.
次に、作用を説明する。Next, the effect will be explained.
Ａ１等の金属からなるドレイン電極１３が、溝 ｎ
１１内でｎ＋埋込層２に直接接続されて、前記第３図に
おけるｎ形拡散領域が無い。また、溝１１は、（１１０
）面の基板を使用し、異方性エツチングにより（１１１
）面でエツチングｉｆｆ ＋ｌ−，さけて形成している
ので、基板内でほぼ３５℃の浅い角度で幅広く横方向に
広がり、ｐチャネル領域４下方部のｎ＋埋込層２まで食
込んで、おり、この食込んだ分だけドレイン電流経路上
のｎ＋埋込層２の長さが減る。したがって、従来例と比
べるとドレイン引出し抵抗が小さくなる。A drain electrode 13 made of a metal such as A1 is directly connected to the n+ buried layer 2 in the groove n11, and there is no n-type diffusion region in FIG. Moreover, the groove 11 is (110
) using a substrate with (111
), the etching is avoided on the surface, so it spreads widely in the lateral direction at a shallow angle of approximately 35° C. in the substrate, digs into the n+ buried layer 2 below the p channel region 4, and is etched. , the length of the n+ buried layer 2 on the drain current path is reduced by the amount of this encroachment. Therefore, compared to the conventional example, the drain extraction resistance becomes smaller.
溝１１は、ｎ形エピタキシャル層３の表面部では幅が狭
く、上述のように、基板内部のｐチャネル領域４の下方
部の部分で、横方向に広がっている。このため、横幅の
広いｎ形拡散領域を備えた従来例と比べると、基板主面
に占める装置面積が小さくなる。The groove 11 has a narrow width at the surface of the n-type epitaxial layer 3, and widens laterally at a portion below the p-channel region 4 inside the substrate, as described above. Therefore, compared to the conventional example including a wide n-type diffusion region, the device area occupied on the main surface of the substrate becomes smaller.
上述の結果から、単位面積当りのオン抵抗が減少する。From the above results, the on-resistance per unit area is reduced.
［発明の効果］
以上説明したように、この発明によれば、第１導電形半
導体の主面側から取出すようにした金属製のドレイン電
極を、その第１導電形半導体の主面から高濃度の埋込層
に達する溝内で当該埋込層に接続されるようにしたため
、ドレイン電極と高濃度の埋込層との間に拡散領域を形
成することが不要となってドレイン抵抗を低減すること
ができる。また、上記の溝は、埋込層に達する拡散領域
を形成する場合と比べると狭幅に形成することができて
半導体の主面に占める装置面積を縮小することができる
。したがって、単位面積当りのオン抵抗を小さくするこ
とができるという利点がある。[Effects of the Invention] As explained above, according to the present invention, the metal drain electrode, which is taken out from the main surface side of the first conductivity type semiconductor, is exposed to a high concentration from the main surface of the first conductivity type semiconductor. Since it is connected to the buried layer within the trench that reaches the buried layer, it is not necessary to form a diffusion region between the drain electrode and the highly doped buried layer, reducing drain resistance. be able to. Further, the trench can be formed narrower than the case where a diffusion region reaching the buried layer is formed, and the device area occupied on the main surface of the semiconductor can be reduced. Therefore, there is an advantage that the on-resistance per unit area can be reduced.
さらに、上記の溝を、埋込層の形成された深さ位置で横
方向に張出すようにした構成によれば、ドレイン電流の
経路上における埋込層の長さが減るため、ドレイン引出
し抵抗が一層減少し、単位面積当りのオン抵抗を一層小
さくすることができる。Furthermore, according to a configuration in which the above-mentioned groove is laterally extended at the depth position where the buried layer is formed, the length of the buried layer on the path of the drain current is reduced, so the drain extraction resistance is reduced. is further reduced, and the on-resistance per unit area can be further reduced.
第１図はこの発明に係る半導体装置の実施例を示す縦断
面図、第２図は同上実施例の製造方法の１
２
一例を示す工程図、第３図は従来の半導体装置を示す縦
断面図である。
２：ｎ＋埋込層、
３：ｎ形エピタキシャル層（第１導電形半導体）４：ｐ
チャネル領域、 ５：ｎ＋ソース領域、６：ゲート酸
化膜（ゲート絶縁膜）、
７：ゲート電極、 １１：溝、
１３ニドレイン電極。FIG. 1 is a longitudinal sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a process diagram showing one example of the manufacturing method of the same embodiment, and FIG. 3 is a longitudinal sectional view showing a conventional semiconductor device. It is a diagram. 2: n+ buried layer, 3: n-type epitaxial layer (first conductivity type semiconductor) 4: p
Channel region, 5: N+ source region, 6: Gate oxide film (gate insulating film), 7: Gate electrode, 11: Groove, 13 Nidrain electrode.
Claims (2)
のチャネル領域と、該チャネル領域内の表面部に形成さ
れた第１導電形のソース領域と、該ソース領域と前記第
１導電形半導体との間における前記チャネル領域上にゲ
ート絶縁膜を介して設けられ当該チャネル領域にチャネ
ルを誘起させるゲート電極と、前記第１導電形半導体の
主面から所要の深さに形成され第１導電形で且つ当該第
１導電形半導体より高濃度の埋込層と、前記第１導電形
半導体の主面から前記埋込層に達する溝内で当該埋込層
に接続され前記第１導電形半導体の主面に引出された金
属製のドレイン電極とを有することを特徴とする半導体
装置。(1) a channel region of a second conductivity type formed on the main surface of the semiconductor of the first conductivity type; a source region of the first conductivity type formed on the surface portion within the channel region; a gate electrode provided on the channel region between the first conductivity type semiconductor via a gate insulating film and inducing a channel in the channel region; and a gate electrode formed at a required depth from the main surface of the first conductivity type semiconductor. a buried layer that is of a first conductivity type and has a higher concentration than the first conductivity type semiconductor; A semiconductor device characterized by having a metal drain electrode drawn out on the main surface of a conductive semiconductor.
方向に張出して形成してなることを特徴とする請求項１
記載の半導体装置。(2) Claim 1, wherein the groove is formed so as to extend laterally at a depth position where the buried layer is formed.
The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1201362A JPH0366166A (en) | 1989-08-04 | 1989-08-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1201362A JPH0366166A (en) | 1989-08-04 | 1989-08-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0366166A true JPH0366166A (en) | 1991-03-20 |
Family
ID=16439797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1201362A Pending JPH0366166A (en) | 1989-08-04 | 1989-08-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0366166A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539238A (en) * | 1992-09-02 | 1996-07-23 | Texas Instruments Incorporated | Area efficient high voltage Mosfets with vertical resurf drift regions |
| JP2008166775A (en) * | 2006-12-27 | 2008-07-17 | Dongbu Hitek Co Ltd | Semiconductor element and manufacturing method thereof |
| DE19539541B4 (en) * | 1994-10-25 | 2017-06-01 | Fuji Electric Co., Ltd. | Lateral trench MISFET and process for its preparation |
-
1989
- 1989-08-04 JP JP1201362A patent/JPH0366166A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539238A (en) * | 1992-09-02 | 1996-07-23 | Texas Instruments Incorporated | Area efficient high voltage Mosfets with vertical resurf drift regions |
| US5569949A (en) * | 1992-09-02 | 1996-10-29 | Texas Instruments Incorporated | Area efficient high voltage MOSFETs with vertical RESURF drift regions |
| US5696010A (en) * | 1992-09-02 | 1997-12-09 | Texas Instruments Incorporated | Method of forming a semiconductor device including a trench |
| DE19539541B4 (en) * | 1994-10-25 | 2017-06-01 | Fuji Electric Co., Ltd. | Lateral trench MISFET and process for its preparation |
| JP2008166775A (en) * | 2006-12-27 | 2008-07-17 | Dongbu Hitek Co Ltd | Semiconductor element and manufacturing method thereof |
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