JPS5987872A - Insulated gate semiconductor device and manufacture thereof - Google Patents
Insulated gate semiconductor device and manufacture thereofInfo
- Publication number
- JPS5987872A JPS5987872A JP57197530A JP19753082A JPS5987872A JP S5987872 A JPS5987872 A JP S5987872A JP 57197530 A JP57197530 A JP 57197530A JP 19753082 A JP19753082 A JP 19753082A JP S5987872 A JPS5987872 A JP S5987872A
- Authority
- JP
- Japan
- Prior art keywords
- type region
- region
- type
- gate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims 5
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 150000002500 ions Chemical class 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は縦形の絶縁ゲート・電界効果トランジスタ（以
下ＭＯ８ＦＥＴと称する）における出力容量低減技術に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technology for reducing output capacitance in a vertical insulated gate field effect transistor (hereinafter referred to as MO8FET).
ビディオ出力用素子として用いられている高耐圧縦形Ｍ
Ｏ８ＦＥＴは、第１図に示すように、裏面にｎ＋＋層２
を有するｎ型Ｓｉ （シリコン）基体１をドレイン（Ｄ
）として、この基体１の一生表面に浅いｐ型領域３とこ
のｐ型領域３に囲まれその一部で重なる深いｐ型ウェル
領域４とな形成し、周辺の浅いｐ型頭域３０表面の一部
にさらに浅い高濃度のｎ＋型領領域５形成してソース（
Ｓ）となし、このｎ＋型領領域５形成されない浅いｐ型
頭域３０表面をチャネル部３ａとしてこの上に絶縁膜（
Ｓ Ｉ Ｏ＊ Ｈａ ） ６を介してポリＳｉ （シリ
コン）からなるゲート７ （Ｇ）を設け、このゲートＧ
への電圧印加によってその直下のチャネル部３ａにおい
てソース・ドレイン電流Ｉ８Ｄを制御する構成を有する
。High voltage vertical type M used as a video output element
As shown in Figure 1, O8FET has an n++ layer 2 on the back side.
An n-type Si (silicon) substrate 1 having a drain (D
), a shallow p-type region 3 and a deep p-type well region 4 surrounded by and partially overlapping with this p-type region 3 are formed on the surface of the substrate 1, and the surface of the peripheral shallow p-type head region 30 is formed. A shallower high concentration n+ type region 5 is formed in a part of the source (
S), and an insulating film (
A gate 7 (G) made of polySi (silicon) is provided via the SIO*Ha) 6, and this gate G
It has a configuration in which the source-drain current I8D is controlled in the channel portion 3a immediately below by applying a voltage to the channel portion 3a.
パワー縦形ＭＯ８ＦＥＴを高周波帯域で使用する場合、
出力容量Ｃ８８８は出力損失となるため、容量はできる
だけ小さい方が望ましい。又このＭＯＳＦＥＴをキャラ
クタディスプレイ等のビデビオ出力用トランジスタとし
て使用する場合、負荷となるブラウン管の容量が３〜５
ＰＦと小さく、ビディオ出力の周波数帯域を５０ＭＨｚ
以上必要とする高精細ディスプレイではＣ８８８はｌ０
ＰＦ以下であることを要しできれば、５ＰＦが理想的で
ある。When using power vertical MO8FET in high frequency band,
Since the output capacitance C888 causes output loss, it is desirable that the capacitance be as small as possible. Also, when using this MOSFET as a video output transistor for a character display, etc., the capacity of the cathode ray tube serving as the load is 3 to 5.
Small PF, video output frequency band 50MHz
For high-definition displays that require more than 10
If it is possible to require less than PF, 5PF is ideal.
しかし前記の高耐圧縦形ＭＯ８ＦＥＴの構造では第１図
を参照しドレイン・ソース間の出力容量Ｃｏ５５はチャ
ネル部を含む浅いｐ型領域３の接合容量Ｃ１と深いｐ型
ウェル値域４の接合容量Ｃ３で決定され、したがってＣ
８８８を小さくする手段としては接合面積を小さくする
かスはｐ型領域３，４の不純物濃度を薄くするかしなけ
ればならない。However, in the structure of the above-mentioned high voltage vertical MO8FET, referring to FIG. 1, the output capacitance Co55 between the drain and source is the junction capacitance C1 of the shallow p-type region 3 including the channel part and the junction capacitance C3 of the deep p-type well range 4. determined and therefore C
In order to reduce the size of 888, it is necessary to reduce the junction area or to reduce the impurity concentration of the p-type regions 3 and 4.
しかしチャネル部を含む浅いｐｉ領域３ではｎチャネル
ＭＯ８ＦＥＴの１ｍ特性や■１等から所要の濃度に限定
され、チャネル部拡散による接合容量Ｃ１は動かすこと
ができない。一方、ｐ型ウェル領域４の不純物濃度はチ
ャネル部に比して低く選ぶことができるが、ウニ；が深
くなるほどその側面部分の面積が増加し、又、浅いｐ型
領域３と深いｐ型ウェル領域４０重なる部分４ａは２度
の拡散によりチャネル部３ａの不純物濃度よりも濃くな
っており、したがって接合容量Ｃｔが大きくなり、全体
としてＣ８８８の低減は困難である。However, in the shallow pi region 3 including the channel part, the concentration is limited to a required value due to the 1m characteristic of the n-channel MO8FET and (1), and the junction capacitance C1 due to channel part diffusion cannot be changed. On the other hand, the impurity concentration of the p-type well region 4 can be selected to be lower than that of the channel region, but the deeper the region, the larger the area of the side surface. The region 40 overlapping portion 4a has an impurity concentration higher than that of the channel portion 3a due to the double diffusion, and therefore the junction capacitance Ct increases, making it difficult to reduce C888 as a whole.
次に低耐圧・低オン抵抗縦形ＭＯ８ＦＥＴとして、ｐ型
ウェルの浅い場合、あるいは第２図に示すようにチャネ
ル部を含む浅いｐ型領域のみで深いウェルを有しない構
造では、ゲート電圧印加時に空乏層がチャネル部拡散層
にぶつかることになり、同様に出力容量Ｃ８８８の低減
ができない。Next, as a vertical MO8FET with low breakdown voltage and low on-resistance, if the p-type well is shallow, or if the structure has only a shallow p-type region including the channel part and no deep well as shown in Figure 2, depletion occurs when the gate voltage is applied. The layer collides with the channel diffusion layer, and the output capacitance C888 cannot be similarly reduced.
本発明は上記の問題を解決するためになされたものであ
り、その目的とするところは、出力用縦形ＭＯ８ＦＥＴ
において出力容量を低減し、ビディオ出力の周波数帯域
特性を向上することにある。The present invention was made to solve the above problems, and its purpose is to provide a vertical MO8FET for output.
The objective is to reduce the output capacitance and improve the frequency band characteristics of video output.
上記目的を達成するための本発明の一実施態様は第３図
に示されるように裏面にｎ＋型ＳｉＪ脅２を有するｎ型
Ｓｉ基板１をドレインとして、このｎ型基板ｌの表面に
一部がチャネル部となるｐ型領域３を有し、ｐ型頭域３
０表面の一部にｎ＋型領領域５形成してソースとし、ｎ
＋型領領域形成されないｐ型頭域３表面に薄い絶縁膜６
を介してゲート（電極）７を設けたｎチャネ／Ｉ／ＭＯ
８ＦＥＴにおいて、チャネル部をゲート近傍下のｐ型頭
域３表面に限定し、このｐ型領域に囲まれたｐ−型領域
８の不純物濃度をチャネル部となるｐ型領域３のそれよ
りも低いものとしたものである。第４図は第３図に示し
たＭＯＳＦＥＴに対応する拡散パターンをあられす平面
図である。As shown in FIG. 3, one embodiment of the present invention for achieving the above object uses an n-type Si substrate 1 having an n+ type SiJ layer 2 on the back surface as a drain, and a part of the surface of this n-type substrate 1 is used as a drain. has a p-type region 3 which becomes a channel part, and a p-type head region 3
An n+ type region 5 is formed on a part of the surface of 0 to serve as a source.
A thin insulating film 6 is formed on the surface of the p-type head region 3 where the +-type region is not formed.
n-channel/I/MO with gate (electrode) 7 provided through
In the 8FET, the channel portion is limited to the surface of the p-type head region 3 below near the gate, and the impurity concentration of the p-type region 8 surrounded by this p-type region is lower than that of the p-type region 3 which becomes the channel portion. It was taken as a thing. FIG. 4 is a plan view showing a diffusion pattern corresponding to the MOSFET shown in FIG. 3.
このような構造とすることによって、チャネル部となる
ｐ型領域３とそれＫより囲まれたｐ−型領域８とを個別
に設計でき、特にｐ−型領域８の不純物濃度を低減させ
たことにより、ゲート電圧印加時に空乏層の拡がりを少
なくし、又、ｐ−型領域８を浅く形成して「ウェル」側
面部の面積を減少させることにより、このｐ−型領域８
にかかわるＣ１を小さくし、パワーＭＯ８ＦＥＴのＩＤ
・７ｍを低下させることなく出力容量Ｃ８８８を低減す
ることができる。By adopting such a structure, the p-type region 3 serving as the channel portion and the p-type region 8 surrounded by the p-type region 8 can be individually designed, and the impurity concentration of the p-type region 8 can be particularly reduced. By reducing the spread of the depletion layer when a gate voltage is applied, and by forming the p-type region 8 shallowly to reduce the area of the "well" side surface, this p-type region 8
By reducing C1, which is related to
- Output capacitance C888 can be reduced without reducing 7m.
第５図は本発明の他の実施形態を示し、この場合はチャ
ネル部を含むｐ型領域３とそれに囲まれたｐ−型領域些
との重なり部分をＣ型領域６の直下に形成した場合で、
第４図の場合よりチャネル部となるｐ型領域３の面積が
小さくなるため、その部分の接合容量Ｃ１が小さくなり
、したがって全体の出力容量Ｃ８，８をより低減できる
。FIG. 5 shows another embodiment of the present invention, in which the overlapping portion of the p-type region 3 including the channel portion and the p-type region surrounded by it is formed directly under the C-type region 6. in,
Since the area of the p-type region 3 serving as the channel portion is smaller than in the case of FIG. 4, the junction capacitance C1 of that portion becomes smaller, and therefore the overall output capacitance C8, 8 can be further reduced.
第６図はｐ型領域とｎ型基板とのｐｎ接合（０の位置）
よりの空乏層の拡がり（距離）Ｊと電界強度Ｅとの関係
がｐ型領域の不純物濃度によって変ることを示している
。同図において、曲線（１）はｐ型領域の濃度が高い場
合で、ｐ型層ｎ型層双方への拡がりの大きいことな示し
、曲線（２）はｐ型領域の濃度を低くｕｐ型層への拡が
りが小さく、ｎ型層へのそれが大きい場合、曲線（３１
ｐ型層へもｎ型層へも共に拡がりが小さい場合を示して
いる。Figure 6 shows the pn junction between the p-type region and the n-type substrate (position 0)
This shows that the relationship between the spread (distance) J of the depletion layer and the electric field strength E changes depending on the impurity concentration of the p-type region. In the same figure, curve (1) shows the case where the concentration of the p-type region is high, indicating a large spread to both the p-type layer and the n-type layer, and the curve (2) shows the case where the concentration of the p-type region is low and the up-type layer. If the spread to the n-type layer is small and that to the n-type layer is large, then the curve (31
This shows a case where the spread is small both to the p-type layer and to the n-type layer.
第７図乃至第１３図は本発明による出力用ｎチャネルＭ
Ｏ８ＦＥＴの製造法をそのプロセスの工程断面図により
示すもので各工程は下記の通り。7 to 13 show n-channel M for output according to the present invention.
The O8FET manufacturing method is shown in cross-sectional diagrams of the process, and each step is as follows.
（１） 第７図に示すようにｎ＋＋層２な有するｎ型
単結晶Ｓｉ基板１又はｎ＋＋基板（２１の上にｎ型層（
１）をエピタキシャル成長させたｎ” ｎ型基板（１゜
２）を用意し、そのｎ型層（基板）１０表面に絶縁膜（
ＳｉＯｘ膜）９をマスクとしてＢ（ポロン）イオン打込
み（不純物オーダＮ：１０１２／ＩＪ２）拡散（１２０
０°ＣＸ１．３ｈｒ程度）してｐ−型領域８を形成する
。(1) As shown in FIG. 7, an n-type single crystal Si substrate 1 having an n++ layer 2 or an n-type layer (
An "n" n-type substrate (1°2) on which 1) was epitaxially grown is prepared, and an insulating film (
Using SiOx film) 9 as a mask, implant B (poron) ions (impurity order N: 1012/IJ2) diffusion (120
0° C. for about 1.3 hr) to form a p-type region 8.
（２） 第８図に示すようにｐ−型領域８上の厚い酸
化膜１０をフィールド酸化膜（４〜５０００Ａ ）の一
部として残して他をエッチ除去する。(2) As shown in FIG. 8, the thick oxide film 10 on the p-type region 8 is left as part of the field oxide film (4 to 5000 Å) and the rest is removed by etching.
（３）第９図に示すようにゲート酸化を行ないゲート酸
化膜６を１２５０Ａ程度に形成する。(3) As shown in FIG. 9, gate oxidation is performed to form a gate oxide film 6 having a thickness of about 1250A.
（４）全面にポリＳｉをデポジットし、所定のホトレジ
スト処理で第１０図に示すようにポリＳｉゲート７をパ
ターニングにより残す。(4) Deposit poly-Si over the entire surface, and pattern it to leave a poly-Si gate 7 as shown in FIG. 10 using a predetermined photoresist process.
（５）ポリＳｉゲート７及びフィールド酸化膜１０をマ
スクとしてＢ（ボロン）及びＡｓ （ヒ素）をイオン打
込みしそれぞれ拡散することにより第１０図に示すチャ
ネル部となるｐ型領域３及びソースとなるｎ＋型領領域
５形成する。この場合、ｐ型領域３の濃度は８ Ｘ １
０１３１０ｔｎ２、拡散時間１２００℃Ｘ１ｈｒ程度で
あり、ｎ＋型領領域５濃度は５Ｘ１０”１０１Ｒ２、拡
散時間は９００℃×％ｈｒ程度とする。(5) Using the poly-Si gate 7 and field oxide film 10 as a mask, B (boron) and As (arsenic) are ion-implanted and diffused to form the p-type region 3 which becomes the channel portion and the source shown in FIG. 10. An n+ type region 5 is formed. In this case, the concentration of p-type region 3 is 8×1
01310tn2, the diffusion time is about 1200° C. x 1 hr, the concentration of the n+ type region 5 is 5×10”101R2, and the diffusion time is about 900° C.×% hr.
（６）この後ＰＳＧ（リンシリケートガラス）膜１１を
０．９μｍデポジットし、第１２図に示すようにコンタ
クトホトエッチを行なってｎ＋型領領域５一部と内側の
ｐ−型頭ｗ、８の全部が露出するようにＳ ｉｏ、膜を
エッチ窓開する。(6) After this, a PSG (phosphosilicate glass) film 11 of 0.9 μm is deposited, and contact photoetching is performed as shown in FIG. The film is etched to expose the entire Sio layer.
（７）最後に第１３図に示すようにＡ−ｅを蒸着（又は
スパッタ）しホトレジスト処理により、ｐ−型領域８と
ｎ＋型領領域５短絡し、その一部はゲートの上を延在さ
せるソース電極１２を形成する。(7) Finally, as shown in FIG. 13, by vapor depositing (or sputtering) A-e and photoresist processing, the p- type region 8 and the n+ type region 5 are short-circuited, and a part of the region extends above the gate. A source electrode 12 is formed.
なお裏面のｎ＋＋Ｓｉ基板上にもドレイン電極１３な形
成する。Note that a drain electrode 13 is also formed on the n++ Si substrate on the back side.
以上実施例で述べた本発明によればチャネル部となるｐ
型領域とそれに囲まれたｐ−型ウェルを別工程で形成で
き、またチャネル部となるｐ型領域とンースｎ＋型領域
はゲートをマスクとすることで自己整合的に形成でき、
ドレイン・ソース間の出力容量をｌ０ＦＦから３ＰＦに
減少させることでｆＴを７０ＭＨｚから２００ ＧＨｚ
に向上することができた。このことはＭＯＳＦＥＴとし
ての速度を犬ならしめるとともに、ディスプレイの高精
密微細化を可能ならしめるものである。According to the present invention described in the embodiments above, p
The type region and the p-type well surrounded by it can be formed in separate steps, and the p-type region and n+-type region that will become the channel part can be formed in a self-aligned manner by using the gate as a mask.
By reducing the drain-source output capacitance from 10FF to 3PF, fT can be increased from 70MHz to 200GHz.
was able to improve. This not only makes the speed of the MOSFET comparable, but also enables highly precise miniaturization of displays.
本発明は縦形のパワーＭＯ８ＦＥＴ全般に適用できるも
のである。The present invention is applicable to all vertical power MO8FETs.
第１図及び第２図は縦形ｎチャネルＭＯ８ＦＥＴのこれ
までの例を示す断面図である。
第３図は本発明による縦形ｎチャネルＭＯ８ＦＥＴを原
理的に示す一実施例の断面図、
第４図は第３図のＭＯ８’ＦＥＴの拡散パターンを示す
平面図である。
第５図は本発明による縦形ｎチャネルＭＯ８ＦＥＴの他
の実施例を示す断面図である。
第６図はｐｎ接合よりの空乏層の延びと電界強度の関係
を示す曲線図である。
第７図乃至第１３図は本発明によるＭＯＳ Ｆ ＥＴの
製造法の実施例プロセスで示す工程断面図である。
１・・・ｎ Ｗ Ｓ ｉ基体、２・・・ｎ＋型Ｓｉ層、
３・・・ｐ型領域、４・・・ｐ型ウェル領域、５・・・
ｎ＋型ンソー領域、６・・・絶縁膜、７・・・ゲート、
８・・・ｐ−型領域、９・・・酸化膜、１０・・・フィ
ールド酸化膜、１１・・・ＰＳＧ膜、１２・・・電極。
第 １ 図
、？
第 ３ 図
第 ５ 図
第 ６ 図
０）
（２） □
（１） −
第 ７ 図
第 ９ 図
第１０図FIGS. 1 and 2 are cross-sectional views showing conventional examples of vertical n-channel MO8FETs. FIG. 3 is a cross-sectional view of an embodiment showing the principle of a vertical n-channel MO8FET according to the present invention, and FIG. 4 is a plan view showing a diffusion pattern of the MO8'FET of FIG. 3. FIG. 5 is a sectional view showing another embodiment of a vertical n-channel MO8FET according to the present invention. FIG. 6 is a curve diagram showing the relationship between the extension of the depletion layer from the pn junction and the electric field strength. FIGS. 7 to 13 are process cross-sectional views showing an embodiment of the method for manufacturing a MOSFET according to the present invention. 1...n W Si substrate, 2... n+ type Si layer,
3...p-type region, 4...p-type well region, 5...
n+ type source region, 6... insulating film, 7... gate,
8...p-type region, 9...oxide film, 10...field oxide film, 11...PSG film, 12...electrode. Figure 1, ? Figure 3 Figure 5 Figure 6 Figure 0) (2) □ (1) - Figure 7 Figure 9 Figure 10
Claims (1)
の一生面表面に第２導電型領域な形成し、この第２導電
型領域表面の一部に第１導電型高濃度領域を形成してソ
ースとなし、第１導電型高濃度領域の形成されない第２
導電型領域表面上に絶縁膜を介してゲート（電極）を設
け、このゲートへの電圧印加によってその直下の第２導
電型領域表面をチャネル部としてのソース・ドレイン電
流を制御する絶縁ゲート電界効果半導体装置において、
チャネル部となる第２導電型領域をゲート近傍下に限定
し、この領域に囲まれた第２導電型領域の不純物濃度を
上記チャネル部となる第２導電型領域のそれよりも低い
ものとしたことを特徴とする絶縁ゲート半導体装置。 ２、ｎ−ｎ□＋型シリコン基板を用意し、そのｎ型シリ
コン層表面の一部に低濃度ｐ−型領領域形成する工程、
ｐ−型領域の周辺部表面にうすいシリコン酸化膜を介し
て多結晶シリコン層かりなるゲートを形成する工程、ｐ
二型領域上に形成した厚い酸化膜と上記多結晶シリコン
層をマスクとしてその間にはさまれたｎ型シリコン層表
面に自己整合的に不純物を導入し、前記ｐ−型領領域り
も高い濃度のｐ型領域なチャネル部として形成するとと
もに浅い高濃度ｎ＋型領領域ソースとして形成する工程
及び上記ｐ−型領領域ｎ＋型領領域一部に対して抵抗接
触する電極を形成する工程とを含む絶縁ゲート半導体装
置の製造法。[Claims] 1. A semiconductor substrate of a first conductivity type is used as a drain, a second conductivity type region is formed on the entire surface of this substrate, and a first conductivity type high-temperature region is formed on a part of the surface of the second conductivity type region. A high concentration region of the first conductivity type is formed to serve as a source, and a second high concentration region of the first conductivity type is not formed.
Insulated gate field effect: A gate (electrode) is provided on the surface of a conductivity type region via an insulating film, and by applying a voltage to this gate, the source/drain current is controlled using the surface of the second conductivity type region immediately below as a channel part. In semiconductor devices,
The second conductivity type region that will become the channel portion is limited to the area below the vicinity of the gate, and the impurity concentration of the second conductivity type region surrounded by this region is lower than that of the second conductivity type region that will become the channel portion. An insulated gate semiconductor device characterized by: 2. Step of preparing an n-n□+ type silicon substrate and forming a low concentration p- type region on a part of the surface of the n-type silicon layer;
a step of forming a gate made of a polycrystalline silicon layer on the peripheral surface of the p-type region through a thin silicon oxide film, p
Using the thick oxide film formed on the type 2 region and the polycrystalline silicon layer as a mask, impurities are introduced into the surface of the n-type silicon layer sandwiched between them in a self-aligned manner, and the p-type region also has a high concentration. A step of forming a p-type region as a channel part and a shallow high concentration n+ type region as a source, and a step of forming an electrode in resistive contact with a part of the p-type region and n+ type region. A method for manufacturing an insulated gate semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57197530A JPS5987872A (en) | 1982-11-12 | 1982-11-12 | Insulated gate semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57197530A JPS5987872A (en) | 1982-11-12 | 1982-11-12 | Insulated gate semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5987872A true JPS5987872A (en) | 1984-05-21 |
Family
ID=16375996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57197530A Pending JPS5987872A (en) | 1982-11-12 | 1982-11-12 | Insulated gate semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5987872A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03238871A (en) * | 1990-02-15 | 1991-10-24 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1982
- 1982-11-12 JP JP57197530A patent/JPS5987872A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03238871A (en) * | 1990-02-15 | 1991-10-24 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
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