JPH0382163A - Power mosfet and manufacture thereof - Google Patents
Power mosfet and manufacture thereofInfo
- Publication number
- JPH0382163A JPH0382163A JP1217346A JP21734689A JPH0382163A JP H0382163 A JPH0382163 A JP H0382163A JP 1217346 A JP1217346 A JP 1217346A JP 21734689 A JP21734689 A JP 21734689A JP H0382163 A JPH0382163 A JP H0382163A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- conductivity type
- gate electrode
- drain
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/086—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、パワーＭＯＳＦＥＴ、さらには半導体基板を
ドレイン領域とする高速型パワーＭＯＳＦＥＴに適用し
て有効な技術に関するもので、例えば通常の論理ＩＣ（
半導体集積回路装置）によって直接開動できるような高
ＧｍのパワーＭＯＳＦＥＴに利用して有効な技術に関す
るものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technology that is effective when applied to power MOSFETs, and furthermore, high-speed power MOSFETs whose drain region is a semiconductor substrate. (
The present invention relates to a technology that is effective for use in high Gm power MOSFETs that can be directly operated by semiconductor integrated circuit devices.
［従来の技術］
従来、高速型パワーＭＯ５ＦＥＴとしては、例えば、米
国特許４，３７６．２８６％明細書に記載されているよ
うに、ＤＳＡ（ＤｊｆｆｕｓｉｏｎＳｅｌｆ−Ａｌｉｇ
ｎ）と呼ばれる方法によって自己整合的に形成される二
重拡散型パワーＭＯ５ＦＥＴがある。[Prior Art] Conventionally, as a high-speed power MO5FET, for example, as described in the specification of US Pat.
There is a double diffused power MO5FET that is formed in a self-aligned manner by a method called n).
第３図は上述した二重拡散型パワーＭＯＳＦＥＴの概略
構成を示したものであって、１はドレイン領域をなす低
不純物濃度のｎ型単結晶シリコン半導体基板、２はゲー
ト酸化膜、３は多結晶シリコンからなるゲート電極、４
はチャンネル領域をなすｐ型拡散層、５はソース電極、
６はｎ型のソース拡散層、Ｇはゲート、Ｓはソース、Ｄ
はドレインである。FIG. 3 shows a schematic configuration of the above-mentioned double diffused power MOSFET, in which 1 is a low impurity concentration n-type single crystal silicon semiconductor substrate forming the drain region, 2 is a gate oxide film, and 3 is a polycrystalline silicon semiconductor substrate with a low impurity concentration. Gate electrode made of crystalline silicon, 4
5 is a p-type diffusion layer forming a channel region, 5 is a source electrode,
6 is an n-type source diffusion layer, G is a gate, S is a source, D
is the drain.
ここで、チャンネル領域をなすｐ型拡散層４およびｎ型
ソース拡散層６はそれぞれ、ゲート電極３でマスクされ
た窓からｐとｎの２種類の導電性付与不純物を拡散させ
ることによって一緒に形成される。Here, the p-type diffusion layer 4 and the n-type source diffusion layer 6, which form the channel region, are formed together by diffusing two types of conductivity-imparting impurities, p and n, through a window masked by the gate electrode 3. be done.
［発明が解決しようとする課題］
しかしながら、上述した技術には０次のような問題のあ
ることが本発明者らによってあきらかとされた。[Problems to be Solved by the Invention] However, the present inventors have found that the above-mentioned technique has the following zero-order problem.
すなわち、チャンネル領域をなすｐ型拡散層４が、ゲー
ト電極３でマスクされた窓からの拡散によって形成され
ていたため、ゲート電極３の中央部分の下はｎ型半導体
基板１となっていた。このため、ゲート電極３とｎ型半
導体基板ｔとの間のＭＯ８ｇｊｌによって、ゲートＧと
ドレインＤの間に大きな寄生容量Ｃｇｄが並列に生じ、
この寄生容＃ｃｇｄが入力容量および帰還容量を増大さ
せて、動作の高速化および安定化を妨げる原因となって
いた。That is, since the p-type diffusion layer 4 forming the channel region was formed by diffusion through the window masked by the gate electrode 3, the n-type semiconductor substrate 1 was located below the central portion of the gate electrode 3. Therefore, a large parasitic capacitance Cgd is generated in parallel between the gate G and the drain D due to MO8gjl between the gate electrode 3 and the n-type semiconductor substrate t.
This parasitic capacitance #cgd increases the input capacitance and the feedback capacitance, and becomes a cause of hindering high-speed and stable operation.
また、上述した二重拡散型パワーＭＯ５ＦＥＴでは、ｎ
型ソース拡散Ｎ６とｐ型拡散層４とが二重拡散によって
一緒に形成されるために、Ｖｔｈ（しきい値）やＧｍな
どの特性を決めるチャンネル長やチャンネル濃度などの
諸元をそれぞれ正確かつ独立に制御することができず、
このことが特性の再現性および特性設計の自由度を悪く
していた。Furthermore, in the double diffused power MO5FET mentioned above, n
Since the type source diffusion N6 and the p-type diffusion layer 4 are formed together by double diffusion, the specifications such as channel length and channel concentration, which determine characteristics such as Vth (threshold value) and Gm, must be accurately and accurately determined. cannot be independently controlled;
This impairs the reproducibility of characteristics and the degree of freedom in designing characteristics.
本発明の目的は、半導体基板をドレイン領域とするパワ
ーＭＯ５ＦＥＴの六方容量および帰還容量を小さくして
、その動作の高速化および安定化を可能にするという技
術を提供することにある。An object of the present invention is to provide a technique for reducing the hexagonal capacitance and feedback capacitance of a power MO5FET whose drain region is a semiconductor substrate, thereby making it possible to speed up and stabilize its operation.
この発明の前記ならびにそのほがの目的と新規な特徴に
ついては、本明細書の記述および添附図面から明らかに
なるであろう。The above-mentioned and further objects and novel features of this invention will become clear from the description of this specification and the accompanying drawings.
［課題を解決するための手段］
本願において開示される発明のうち代表的なものの概要
を説明すれば、下記のとおりである。[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.
すなわち、ドレイン領域をなす第１導電型半導体基板に
チャンネル領域をなす第２導電一拡散層を形成し、この
第２導電一拡散層の上にゲート絶縁膜を挾んでゲート電
極を形成し、このゲート電極をマスクに用いてソース電
極コンタクト用拡散層に接続するソース拡散層および基
板に接続するドレイン拡散層を自己整合的に形成すると
いうものである。That is, a second conductive diffusion layer which constitutes a channel region is formed on a first conductivity type semiconductor substrate which constitutes a drain region, a gate electrode is formed by sandwiching a gate insulating film on this second conductive diffusion layer, and a gate electrode is formed on this second conductive diffusion layer. Using the gate electrode as a mask, a source diffusion layer connected to a source electrode contact diffusion layer and a drain diffusion layer connected to a substrate are formed in a self-aligned manner.
［作用］
上記した手段によれば、ゲート電極と半導体基板とが直
接対向しないことにより、ゲートとドレイン間のＭＯ８
容量を大幅に小さくすることができる。[Operation] According to the above-described means, since the gate electrode and the semiconductor substrate do not directly face each other, the MO8 between the gate and the drain
Capacity can be significantly reduced.
これにより、半導体基板をドレイン領域とするパワーＭ
ＯＳＦＥＴの動作を高速化および安定化させるという目
的が達成される。As a result, the power M with the semiconductor substrate as the drain region
The objective of speeding up and stabilizing the operation of the OSFET is achieved.
［実施例］
以下、本発明の好適な実施例を図面に基づいて説明する
。[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.
なお、各図中、同一符号は同一あるいは相当部分を示す
。In each figure, the same reference numerals indicate the same or corresponding parts.
第１図は本発明の一実施例によるパワーＭＯ５Ｆ Ｅ
Ｔの概略構成を示す。FIG. 1 shows a power MO5F E according to an embodiment of the present invention.
The schematic configuration of T is shown.
同図に示すパワーＭＯ５ＦＥＴは、ドレイン領域をなす
ｎ型（第１導電型）シリコン半導体基板ｌ、チャンネル
領域をなすｐ型（第２導電型）拡散層４０．このｐ型拡
散Ｍ４０の上にゲート酸化膜２を挾んで形成されたゲー
ト電極３０、ソース電極５、ソース電極コンタクト用の
ｎ型拡散層５１、ゲート電極３０下のチャンネル領域を
上記ソース電極コンタクト拡散層５１に接続するｎ型ソ
ース拡散層６０、上記チャンネル領域をｐ型拡散層４０
外のドレイン領域すなわち基板１に接続するｎ型ドレイ
ン拡散層７０などによって構成されている。The power MO5FET shown in the figure includes an n-type (first conductivity type) silicon semiconductor substrate l forming a drain region, a p-type (second conductivity type) diffusion layer 40 forming a channel region. A gate electrode 30, a source electrode 5, an n-type diffusion layer 51 for source electrode contact, and a channel region under the gate electrode 30 are formed on the p-type diffusion M40 with the gate oxide film 2 interposed therebetween. An n-type source diffusion layer 60 is connected to the layer 51, and a p-type diffusion layer 40 is connected to the channel region.
It is composed of an n-type drain diffusion layer 70 connected to the outer drain region, that is, the substrate 1, and the like.
ここで、ゲート電極３０はモリブデンなどの高融点金属
を用いて構成されている。このゲート電極３０はチャン
ネル領域をなすｐ型拡散層４０とともに２つの分割形成
されている。これとともに、ｎドレイン拡散層７０が、
分割形成されたゲート電極３０．３０の間をまたがって
形成されている。Here, the gate electrode 30 is made of a high melting point metal such as molybdenum. This gate electrode 30 is formed into two parts together with a p-type diffusion layer 40 forming a channel region. Along with this, the n drain diffusion layer 70 is
It is formed across the gate electrodes 30 and 30 that are formed in sections.
上述したパワーＭＯＳＦＥＴでは、ゲート電極３０と半
導体基板１とが直接対向しないため、ゲート電極３０と
半導体基板１との間すなわちゲートＧとドレインＤとの
間の並列寄生容量Ｃｇｄ’が大幅に小さくなる。これに
より、基板１をドレイン領域とするパワーＭＯ５ＦＥＴ
の入力容量および帰還容量を小さくして、高Ｇｍ化した
場合でも、動作を高速化および安定化させることができ
るようになる。In the power MOSFET described above, since the gate electrode 30 and the semiconductor substrate 1 do not directly oppose each other, the parallel parasitic capacitance Cgd' between the gate electrode 30 and the semiconductor substrate 1, that is, between the gate G and the drain D, is significantly reduced. . This creates a power MO5FET with the substrate 1 as the drain region.
Even when the input capacitance and the feedback capacitance of the device are made small and the Gm is increased, the operation can be made faster and more stable.
第２図は第１図に示したパワーＭＯＳＦＥＴの製造方法
の要部を示す。FIG. 2 shows the main part of the method for manufacturing the power MOSFET shown in FIG. 1.
まず、同図（Ａ）に示すように、ドレイン領域をなす低
不純物濃度のｐ型シリコン半導体１内に。First, as shown in the same figure (A), in a p-type silicon semiconductor 1 with a low impurity concentration that forms a drain region.
チャンネル領域をなすｐ型拡散層（ｐ−Ｗｅｌｌ）４０
を選択的に形成する。p-type diffusion layer (p-well) 40 forming a channel region
selectively formed.
続いて、同図（Ｂ）に示すように、ソース電極とコンタ
クトをとるために高不純物濃度のｎ型拡散層５１を選択
的に形成する。Subsequently, as shown in FIG. 2B, an n-type diffusion layer 51 with a high impurity concentration is selectively formed to make contact with the source electrode.
次に、同図に（Ｃ）に示すように、基板表面の能動部の
酸化膜を一旦除去してからゲート酸化膜２を形成した後
、ｐ型拡散層４０の上に高融点金属のシリサイドからな
るゲート電極３０をバターニング形成する。そして、こ
のゲート電極３０をマスクにしてｎ導電性付与不純物を
低濃度にイオン打込みし、さらにアニール処理を行なう
ことにより、ｎ型のソース拡散層６０およびドレイン拡
散層７０を自己整合的に形成する。Next, as shown in (C) in the same figure, after removing the oxide film of the active part on the substrate surface and forming the gate oxide film 2, a high-melting point metal silicide is formed on the p-type diffusion layer 40. A gate electrode 30 is formed by patterning. Then, using this gate electrode 30 as a mask, n-conductivity imparting impurities are ion-implanted at a low concentration and further annealing is performed to form an n-type source diffusion layer 60 and drain diffusion layer 70 in a self-aligned manner. .
この後、同図（Ｄ）および（Ｅ）に示すように、ＰＳＧ
（リン・シリケート・ガラス）などによる第１パシベ
ーシヨン８１の形成、アルミニウムによるソース電極５
の取り出し、第２パシベーシヨン８２の形成などの工程
を経て、第１図に示したようなパワーＭＯＳＦＥＴを得
る。After this, as shown in (D) and (E) of the same figure, PSG
Formation of the first passivation 81 using (phosphorus silicate glass) etc., and source electrode 5 using aluminum.
Through steps such as extraction of the MOSFET and formation of the second passivation 82, a power MOSFET as shown in FIG. 1 is obtained.
上述した製造方法によれば、パワーＭＯＳＦＥＴのチャ
ンネル長はゲート電極５の長さとソース／ドレイン拡散
層６０および７０の拡がり状態によって決めることがで
きる。また、チャンネル濃度はｐ型拡散層４０の拡散濃
度によって、上記ソース／ドレイン拡散層６０の拡散濃
度とは別に決めることができる。このように、チャンネ
ル長やチャンネル濃度などの諸元をそれぞれ独立して決
めることができるので、 Ｖｔｈ （Ｌ、きい値）やＧ
ｍなどの特性の設計自由度が非常に高いという利点が得
られる６
さらに、ソース／ドレイン拡散層６０および７０は、イ
オン打込みによって比較的短時間に形成できるとともに
、その拡がり状態および濃度を拡散の場合よりも正確に
制御することができる。これにより、所定の特性が再現
性よく得られるとともに、ゲート電極３の長さおよびチ
ャンネル長を非常に短くすることができるようになって
、オン抵抗およびゲート容量の一層の低減が可能になる
。According to the manufacturing method described above, the channel length of the power MOSFET can be determined by the length of the gate electrode 5 and the spread state of the source/drain diffusion layers 60 and 70. Further, the channel concentration can be determined separately from the diffusion concentration of the source/drain diffusion layer 60 by the diffusion concentration of the p-type diffusion layer 40. In this way, specifications such as channel length and channel density can be determined independently, so Vth (L, threshold) and G
The advantage is that there is a very high degree of freedom in designing characteristics such as can be controlled more precisely than before. As a result, predetermined characteristics can be obtained with good reproducibility, and the length of the gate electrode 3 and channel length can be made extremely short, making it possible to further reduce on-resistance and gate capacitance.
さらにまた、ゲート電極３０を分割することによりゲー
ト面積が縮小され′、これによってゲート容量をさらに
一層小さくすることができる。Furthermore, by dividing the gate electrode 30, the gate area is reduced, thereby making it possible to further reduce the gate capacitance.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが９本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically described above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Nor.
例えば、チャンネルタイプはｎまたはＰのいずれであっ
てもよい。For example, the channel type may be either n or p.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるパワーＭＯＳＦＥＴ
に適用した場合について説明したが、それに限定される
ものではなく、例えば高周波用のパワーＭＯＳＦＥＴに
も適用できる。In the above explanation, the invention made by the present inventor will be mainly explained in relation to the power MOSFET, which is the application field that is the background of the invention.
Although the case where the present invention is applied has been described, the present invention is not limited thereto, and can also be applied to, for example, a high frequency power MOSFET.
［発明の効果コ
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.
すなわち、半導体基板をドレイン領域とするパワーＭＯ
ＳＦＥＴのゲートとドレインの間に寄生する容量を小さ
くして、動作の一層の高速化および安定化を可能にする
という効果が得られる。In other words, a power MO using a semiconductor substrate as a drain region
It is possible to reduce the parasitic capacitance between the gate and drain of the SFET, thereby achieving the effect of further speeding up and stabilizing the operation.
第１図は本発明の一実施例によるパワーＭＯＳ製造方法
の要部を示す図。
第３図は従来のパワーＭＯＳＦＥＴの概略構成図である
。
１・・・・ｎ型（第１導電型）半導体基板、２・・・・
ゲート酸化膜、３０・・・・ゲート電極、４０・・・・
ｐ型（第２導電型）拡散層、５・・・・ソース電極、５
１・・・・ソース電極コンタクト用のｎ型拡散層、６０
・・・・ソース拡散層、７０・・・・ドレイン拡散層、
８１．８２・・・・パシベーション。
第
図
第
図
（Ａ）
（Ｂ）FIG. 1 is a diagram showing a main part of a power MOS manufacturing method according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a conventional power MOSFET. 1... n-type (first conductivity type) semiconductor substrate, 2...
Gate oxide film, 30... Gate electrode, 40...
p-type (second conductivity type) diffusion layer, 5... source electrode, 5
1... N-type diffusion layer for source electrode contact, 60
... Source diffusion layer, 70... Drain diffusion layer,
81.82...Passivation. Figure Figure (A) (B)
Claims (1)
第１導電型半導体基板にてチャンネル領域を形成する第
２導電型拡散層内に形成された第１導電型のソース電極
コンタクト用拡散層と、上記第２導電一拡散層の上にゲ
ート酸化膜を挾んで形成されたゲート電極と、このゲー
ト電極下のチャンネル領域を上記ソース電極コンタクト
拡散層に接続する第１導電型のソース拡散層と、上記チ
ャンネル領域を上記第２導電型拡散層外のドレイン領域
に接続する第１導電型のドレイン拡散層とを有するパワ
ーＭＯＳＦＥＴ。 ２、ゲート電極が高融点金属によって構成されているこ
とを特徴とする特許請求の範囲第１項記載のパワーＭＯ
ＳＦＥＴ。 ３、ゲート電極がチャンネル領域をなす第２導電型拡散
層とともに分割形成されているとともに、この分割形成
されたゲート電極の間に第１導電型のドレイン拡散層が
形成されていることを特徴とする特許請求の範囲第１項
または第２項記載のパワーＭＯＳＦＥＴ。 ４、ドレイン領域をなす第１導電型半導体基板にチャン
ネル領域をなす第２導電型拡散層を形成し、この第２導
電型拡散層の上にゲート絶縁膜を挾んでゲート電極を形
成し、このゲート電極をマスクに用いて上記第２導電型
拡散層に第１導電型のソース拡散層およびドレイン拡散
層を自己整合的に形成することを特徴とするパワーＭＯ
ＳＦＥＴの製造方法。 ５、ドレイン拡散層およびソース拡散層をイオン打込み
によって形成することを特徴とする特許請求の範囲第４
項記載のパワーＭＯＳＦＥＴの製造方法。[Claims] 1. A first conductivity type semiconductor substrate forming a drain region, and a first conductivity type semiconductor substrate formed in a second conductivity type diffusion layer forming a channel region in this first conductivity type semiconductor substrate. a source electrode contact diffusion layer; a gate electrode formed on the second conductive diffusion layer with a gate oxide film sandwiched therebetween; and a first conductive diffusion layer that connects a channel region under the gate electrode to the source electrode contact diffusion layer. A power MOSFET comprising a source diffusion layer of a conductivity type and a drain diffusion layer of a first conductivity type that connects the channel region to a drain region outside the second conductivity type diffusion layer. 2. The power MO according to claim 1, wherein the gate electrode is made of a high melting point metal.
SFET. 3. The gate electrode is formed separately together with the second conductivity type diffusion layer forming the channel region, and the first conductivity type drain diffusion layer is formed between the divided gate electrodes. A power MOSFET according to claim 1 or 2. 4. A second conductivity type diffusion layer forming a channel region is formed on a first conductivity type semiconductor substrate forming a drain region, and a gate electrode is formed by sandwiching a gate insulating film on this second conductivity type diffusion layer. A power MO characterized in that a source diffusion layer and a drain diffusion layer of a first conductivity type are formed in the second conductivity type diffusion layer in a self-aligned manner using a gate electrode as a mask.
SFET manufacturing method. 5. Claim 4, characterized in that the drain diffusion layer and the source diffusion layer are formed by ion implantation.
A method for manufacturing a power MOSFET as described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1217346A JPH0382163A (en) | 1989-08-25 | 1989-08-25 | Power mosfet and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1217346A JPH0382163A (en) | 1989-08-25 | 1989-08-25 | Power mosfet and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0382163A true JPH0382163A (en) | 1991-04-08 |
Family
ID=16702737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1217346A Pending JPH0382163A (en) | 1989-08-25 | 1989-08-25 | Power mosfet and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0382163A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005578A (en) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2006303324A (en) * | 2005-04-22 | 2006-11-02 | Rohm Co Ltd | Semiconductor device and its fabrication process |
| EP2075847A1 (en) * | 2006-10-16 | 2009-07-01 | National Institute Of Advanced Industrial Science | Silicon carbide semiconductor device and method for fabricating the same |
| WO2010044226A1 (en) * | 2008-10-17 | 2010-04-22 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| JP2012156544A (en) * | 2012-04-11 | 2012-08-16 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
| JP2014140082A (en) * | 2014-05-07 | 2014-07-31 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
-
1989
- 1989-08-25 JP JP1217346A patent/JPH0382163A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005578A (en) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2006303324A (en) * | 2005-04-22 | 2006-11-02 | Rohm Co Ltd | Semiconductor device and its fabrication process |
| EP1873838A1 (en) * | 2005-04-22 | 2008-01-02 | Rohm, Co., Ltd. | Semiconductor device and method for manufacturing same |
| EP1873838A4 (en) * | 2005-04-22 | 2009-06-03 | Rohm Co Ltd | Semiconductor device and method for manufacturing same |
| US7888712B2 (en) | 2005-04-22 | 2011-02-15 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing same |
| EP2075847A1 (en) * | 2006-10-16 | 2009-07-01 | National Institute Of Advanced Industrial Science | Silicon carbide semiconductor device and method for fabricating the same |
| EP2075847A4 (en) * | 2006-10-16 | 2010-10-20 | Nat Inst Of Advanced Ind Scien | Silicon carbide semiconductor device and method for fabricating the same |
| WO2010044226A1 (en) * | 2008-10-17 | 2010-04-22 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| CN102187463A (en) * | 2008-10-17 | 2011-09-14 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing same |
| JP2012156544A (en) * | 2012-04-11 | 2012-08-16 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
| JP2014140082A (en) * | 2014-05-07 | 2014-07-31 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
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