JP2005005578A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SiC semiconductor device having high voltage resistance and low loss. <P>SOLUTION: The semiconductor device comprises a substrate 1, a 1st SiC layer 2 formed on the substrate 1 and a 2nd SiC layer 12 formed on the 1st SiC layer 2. An n-type drift area 14 and a p-type well area 3 are formed in the 1st SiC layer 2, an n-type accumulation channel layer 6 is formed on the center part of the 2nd SiC layer 12 and n-type contact layers 4 are formed on both the end parts of the 2nd SiC layer 12. A gate electrode 8 is formed on the accumulation type channel layer 6 through a gate insulating film 5. The contact layer 4 comes into contact with a source electrode 9 and the substrate 1 comes into contact with a drain electrode 10. Current induction layers 7 having an n-type impurity concentration higher than that of the other area of the n-type drift layer 14 are formed in a part of the drift area 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using silicon carbide and a manufacturing method thereof, and more particularly to a MISFET using silicon carbide and a manufacturing method thereof.
[0002]
[Prior art]
Silicon carbide (silicon carbide, SiC) is harder than silicon (Si), hard to be attacked by chemicals, and has a large band gap, so it can be applied to next-generation power devices and high-temperature devices. It is expected as a possible semiconductor material.
[0003]
SiC is classified into many polytypes such as cubic 3C-SiC, hexagonal 6H-SiC, and 4H-SiC. Of these polytypes, 6H—SiC and 4H—SiC are commonly used to produce practical SiC semiconductor devices. As 6H-SiC and 4H-SiC substrates, substrates having a main surface substantially coincident with the (0 0 0 1) plane perpendicular to the c-axis crystal axis are widely used.
[0004]
In a semiconductor device using SiC, an epitaxial growth layer that functions as an active region is provided on a SiC substrate. In this epitaxial growth layer, necessary regions are provided according to the type of element. For example, in the case of an FET, a source / drain region and a channel region are provided in the epitaxial growth layer.
[0005]
As a power FET using SiC, a storage type (accumulation type) MISFET (ACCUFET) is widely used. In the storage-type MISFET, a storage-type channel layer is formed between a p-type well region and a gate insulating film, each provided in a part of SiC.
[0006]
Hereinafter, such a structure will be described with reference to FIG. FIG. 8 is a cross-sectional view showing the structure of a conventional storage MISFET using SiC.
[0007]
As shown in FIG. 8, in a general SiC storage MISFET, a first SiC layer 102 is formed on a SiC substrate 101.
[0008]
A well region 103 containing a p-type impurity is provided in a part of the upper portion of the first SiC layer 102, and a region surrounding the well region 103 in the first SiC layer 102 contains an n-type impurity. A drift region 114 is provided.
[0009]
In the first SiC layer 102, a second SiC layer 112 having an opening (groove) 111 is provided on the two well regions 103 separated from each other from above the drift region 114. A storage channel layer 106 containing a p-type impurity is provided in a portion of the second SiC layer 112 excluding both ends. A contact region 104 containing a p-type impurity is provided from both ends of the second SiC layer 112 to a portion of the first SiC layer 102 located below the both ends.
[0010]
A first ohmic electrode (source electrode) 109 is provided over the contact region 104 and over the well region 103 exposed on the lower surface of the opening 111.
[0011]
A gate insulating film 105 is provided from above the storage channel layer 106 of the second SiC layer 112 to a portion of the contact region 104 positioned at the boundary with the storage channel layer 106. A gate electrode 108 is provided on the gate insulating film 105.
[0012]
A second ohmic electrode (drain electrode) 110 is provided on the surface (lower surface) facing the main surface of SiC substrate 101 (see, for example, Patent Document 1).
[0013]
[Patent Document 1]
JP 2001-144292 A
[0014]
[Problems to be solved by the invention]
However, the conventional MISFET has the following problems. In the MISFET as shown in FIG. 8, there is a trade-off relationship between on-resistance and breakdown voltage. That is, if the on-resistance is decreased by increasing the dopant concentration of the impurity in the drift region 114 in order to obtain a low-loss MISFET, the breakdown voltage decreases.
[0015]
In view of the above-described conventional problems, an object of the present invention is to provide a SiC semiconductor device with high breakdown voltage and low loss.
[0016]
[Means for Solving the Problems]
The semiconductor device of the present invention is provided in a part of the silicon carbide layer, provided in a first impurity doped layer (drift region) containing an impurity of a first conductivity type, and in a part of the silicon carbide layer, A second impurity doped layer (well region) containing impurities of two conductivity types, provided above the first impurity doped layer and the second impurity doped layer, and higher than the first impurity doped layer A third impurity doped layer (channel layer) containing a first conductivity type impurity at a concentration and a side surface of the third impurity doped layer provided in contact with the third impurity doped layer and having a higher concentration than the third impurity doped layer; A fourth impurity doped layer (contact layer) containing impurities of one conductivity type, a gate insulating film provided on the third impurity doped layer, and a gate electrode provided on the gate insulating film; The fourth impurity doped layer; A first ohmic electrode (source electrode) provided and a second ohmic electrode (drain electrode) provided below the silicon carbide layer, and a part of the first impurity doped layer. Is provided with a fifth impurity doped layer (current induction layer) containing a first conductivity type impurity having a concentration higher than that of the first impurity doped layer.
[0017]
As a result, the current flowing from the first ohmic electrode toward the second ohmic electrode selectively passes through the fifth impurity doped layer having a lower resistance than the first impurity doped layer. Therefore, the on-resistance is reduced, and a current having a high current density can be obtained. On the other hand, since the fifth impurity doped layer is provided only in a part of the first impurity doped layer, it is possible to suppress a decrease in breakdown voltage.
[0018]
Since the fifth impurity-doped layer is provided in contact with the third impurity-doped layer, the path through which the current passes through the first impurity-doped layer is the shortest. Resistance can be reduced. In addition, the current induction layer may be provided in the third impurity doped layer, and in this case, the on-resistance can be reduced also in the third impurity doped layer.
[0019]
Since the fifth impurity-doped layer is provided in contact with the second impurity-doped layer, the path through which the current passes through the first impurity-doped layer is the shortest. Resistance can be reduced. Further, when viewed from above, the outer side of the first impurity doped layer is surrounded by the fifth impurity doped layer, and the outer side of the fifth impurity doped layer is surrounded by the second impurity doped layer. In this case, as much current as possible flowing from the first ohmic electrode toward the first impurity doped layer can flow as much as possible to the fifth impurity doped layer.
[0020]
In a portion of the first impurity doped layer located on the side of the fifth impurity doped layer, a sixth impurity doped having a lower concentration of the first conductivity type impurity than the first impurity doped layer. By providing the layer, the depletion layer is more easily formed under the gate insulating film, so that a decrease in breakdown voltage is further suppressed.
[0021]
The width of the fifth impurity doped layer is preferably smaller than the depth. That is, since the depth of the fifth impurity doped layer is deep, the distance during which the current during the ON operation flows through the fifth impurity doped layer instead of the first impurity doped layer becomes longer. In addition, since the depletion layer is easily formed under the gate insulating film due to the narrow width, a decrease in breakdown voltage can be suppressed.
[0022]
The concentration of the first conductivity type impurity in the fifth impurity doped layer is 10 times or more the impurity concentration of the first impurity doped layer. ⁵ By being less than twice, the on-resistance can be more effectively reduced.
[0023]
The method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a silicon carbide layer having a first impurity doped layer (drift region) containing a first conductivity type impurity on a semiconductor substrate, After a), a step (b) of forming a second impurity doped layer (well region) by ion-implanting a second conductivity type impurity into a part of the silicon carbide layer, and the step (b) After, a third impurity doped layer (channel) containing impurities of a first conductivity type having a higher concentration than the first impurity doped layer on the first impurity doped layer and the second impurity doped layer. Region (1), and ion implantation of a first conductivity type impurity into the side of the third impurity doped layer, thereby providing a first concentration higher than that of the third impurity doped layer. 4th impurity dope which has a conductivity type impurity A step (d) of forming a layer (contact region), and ion implantation of a first conductivity type impurity into a part of the first impurity doped layer, whereby one of the first impurity doped layers is formed. A step (e) of forming a fifth impurity doped layer (current induction layer) containing a first conductivity type impurity at a higher concentration than the first impurity doped layer in the portion; and A step (f) of forming a first ohmic electrode in contact therewith, a step (g) of forming a gate insulating film on the third impurity doped layer, and the gate insulating film after the step (g). A step (h) of forming a gate electrode on the substrate, and a step (i) of forming a second ohmic electrode below the semiconductor substrate.
[0024]
In the semiconductor device manufactured by this method, the current flowing from the first ohmic electrode toward the second ohmic electrode selectively passes through the fifth impurity doped layer having a lower resistance than the first impurity doped layer. To do. On the other hand, since the fifth impurity doped layer is provided only in a part of the first impurity doped layer, it is possible to suppress a decrease in breakdown voltage. Therefore, according to this manufacturing method, a semiconductor device having a high breakdown voltage, a low on-resistance, and a high current density can be obtained.
[0025]
A mask having an opening located above the first impurity doped layer is formed and ion implantation is performed, and the fourth impurity doped layer in the step (d) and the fifth impurity in the step (e) are performed. By forming the impurity doped layer, the fifth impurity doped layer can be formed without increasing the number of steps. Note that the ion implantation is performed in a state where a recess or an opening for forming the fourth impurity doped layer is formed in a portion of the mask located above the third impurity doped layer.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
In the present embodiment, a method for reducing the on-resistance by providing a current inducing layer including an impurity at a concentration higher than that of the drift region in a region in contact with the drift region will be described.
[0027]
FIG. 1 is a cross-sectional view showing a structure of a MISFET using SiC in the first embodiment. As shown in FIG. 1, in the MISFET in this embodiment, the concentration is 1 × 10. ¹⁸ cm ^-3 A first SiC layer 2 having a thickness of 10 μm is formed on a SiC substrate 1 having a thickness of 400 μm containing the n-type impurity. On the first SiC layer 2, a second SiC layer 12 having an opening (groove) and having a thickness of 0.3 μm is provided.
[0028]
A portion of the second SiC layer 12 excluding both ends has a concentration of 5 × 10 ¹⁷ cm ^-3 The storage channel layer 6 containing the n-type impurity is provided. A concentration of 1 × 10 10 extends from both ends of the second SiC layer 12 to a portion of the first SiC layer 2 positioned below the both ends. ¹⁸ cm ^-3 A contact region 4 having a depth of 0.5 μm containing the n-type impurity is provided.
[0029]
In the region surrounding the side and lower side of the contact region 4 in the first SiC layer 2, the concentration is 5 × 10 5. ¹⁷ cm ^-3 A well region 3 having a depth of 2 μm containing the p-type impurity is provided. Then, in the region located inside the well region 3 in the second SiC layer 12 and the first SiC layer 2, the concentration is 1 × 10. ¹⁸ cm ^-3 A current induction layer 7 having a width of 0.5 μm and a depth of 2 μm containing the n-type impurity is provided. The region of the first SiC layer 2 excluding the current induction layer 7 and the well region 3 has a concentration of 5 × 10. ¹⁵ cm ^-3 This is a drift region 14 containing n-type impurities. The width of the drift region 14 facing the upper surface of the first SiC layer 2 is 10 μm, and the side of the drift region 14 is surrounded by the current induction layer 7 in the vicinity of the upper surface of the first SiC layer 2. The side of the induction layer 7 is surrounded by the well region 3.
[0030]
A source electrode (first ohmic electrode) 9 made of a Ni film having a thickness of 200 nm is provided over the contact region 4 and the well region 3 exposed on the lower surface of the opening 11. In general, in the power FET, the source electrode 9 is brought into contact with the contact region 4 and the well region 3 in order to determine the potential of the well region 3.
[0031]
A gate insulating film 5 made of an oxide film having a thickness of 30 nm is provided from above the storage channel layer 6 to a portion of the contact region 4 located at the boundary with the storage channel layer 6. A gate electrode 8 made of an Al film having a thickness of 200 nm is provided on the gate insulating film 5.
[0032]
A drain electrode (second ohmic electrode) 10 made of a Ni film having a thickness of 200 nm is provided on the surface (lower surface) facing the main surface of SiC substrate 1.
[0033]
Next, a manufacturing method of the MISFET of this embodiment will be described with reference to FIGS. 2 (a) to 3 (c). FIG. 2A to FIG. 3C are cross-sectional views showing the manufacturing process of the storage MISFET in the first embodiment.
[0034]
First, the SiC substrate 1 is prepared in the process shown in FIG. As the SiC substrate 1, for example, the main surface is 4H− with a diameter of 50 mm, which is off-cut by tilting by 8 degrees from the (0 0 0 1) plane toward the [1 1 −2 0] (1 1 2 bar 0) direction A SiC substrate is used. The SiC substrate 1 has a carrier concentration of 1 × 10 ¹⁸ cm ^-3 N-type impurities.
[0035]
Next, the first SiC layer 2 having a thickness of 10 μm is epitaxially grown on the SiC substrate 1 by the CVD method. Since this epitaxial growth is performed while supplying an n-type impurity, the first SiC layer 2 has 5 × 10 5. ¹⁵ cm ^-3 N-type carrier concentration.
[0036]
Subsequently, an implantation mask 15 made of nickel (Ni) is formed on the first SiC layer 2. The implantation mask 15 has an opening 16 on the portion of the first SiC layer 2 that becomes the well region 3. Then, multistage Al ions are implanted into the first SiC layer 2 from above the implantation mask 15. Thereafter, activation annealing is performed, so that a p-type carrier concentration of 5 × 10 × 2 μm deep is partially formed above the first SiC layer 2. ¹⁷ cm ^-3 The well region 3 is formed. Thereafter, the implantation mask 15 is removed.
[0037]
Next, in the step shown in FIG. 2B, the second SiC layer 12 having a thickness of 0.3 μm is epitaxially grown on the first SiC layer 2 by the CVD method. Since this epitaxial growth is performed while supplying n-type impurities, the second SiC layer 12 has a thickness of about 5 × 10 10. ¹⁷ cm ^-3 N-type carrier concentration.
[0038]
Next, in the step shown in FIG. 2C, an implantation mask 19 having a recess 17 and an opening 18 is formed on the second SiC layer 12. At this time, the concave portion 17 is provided in a shape in which a portion of the implantation mask 19 located above the central portion of the well region 3 is recessed, and the opening 18 is formed between the first SiC layer 2 and the well region 3. The upper surface of the second SiC layer 12 located on the portion located at the boundary is provided so as to open.
[0039]
Next, in the step shown in FIG. 3A, after ion implantation of nitrogen (N) into the second SiC layer 12 from above the implantation mask 19, the implantation mask 19 is removed and activation annealing is performed. Accordingly, the n-type carrier concentration is 1 × 10 5 at a depth of 0.5 μm in a part of the second SiC layer 12 and a part of the well region 3 positioned below the part. ¹⁸ cm ^-3 The contact region 4 is formed. At this time, the portion of the second SiC layer 12 sandwiched between the two contact regions 4 becomes the storage channel layer 6 while maintaining the n-type impurity concentration. Then, a part of the storage channel layer 6 and the first SiC layer 2 positioned therebelow have a width of 0.5 μm, a depth of 2 μm, and an n-type carrier concentration of 1 × 10 ¹⁸ cm ^-3 The current induction layer 7 is formed. The current induction layer 7 is formed in the storage channel layer 6 and the first SiC layer 2, and a portion located in the first SiC layer 2 is provided in contact with the well region 3. Note that the region of the first SiC layer 2 excluding the well region 3 and the current induction layer 7 has a concentration of 5 × 10. ¹⁵ cm ^-3 This becomes the drift region 14 containing the n-type impurity. The depth and impurity concentration of the contact region 4 and the current induction layer 7 can be adjusted by adjusting the size and shape of the implantation mask and the ion implantation acceleration voltage in these processing steps. If the contact region 4 and the current induction layer 7 have the same depth, the implantation mask 19 is provided with an opening instead of the recess 17.
[0040]
Next, in the step shown in FIG. 3B, a resist pattern (not shown) is applied on the second SiC layer 12, and exposure and development are performed, whereby a mask pattern having an opening (not shown) (not shown). (Not shown). Then, the opening 11 is formed by performing etching using a mask pattern (not shown) as an etching mask. Opening 11 penetrates through second SiC layer 12 and exposes part of well region 3 in first SiC layer 2.
[0041]
Subsequently, the upper portion of the second SiC layer 12 is thermally oxidized at a temperature of 1100 ° C., thereby forming a gate insulating film 5 having a thickness of 30 nm.
[0042]
Next, in the step shown in FIG. 3 (c), using an electron beam (EB) vapor deposition apparatus, the well region 3 exposed from the opening 11 is spread over the contact region 4 located around the well region 3. A 200 nm thick Ni film (not shown) is deposited. Subsequently, a Ni (not shown) film having a thickness of 200 nm is deposited on the back surface of the SiC substrate 1. Thereafter, the substrate is heated to a temperature of 1000 ° C. in a heating furnace, so that the source electrode serving as an ohmic electrode extends from above the well region 3 exposed to the opening 11 to the contact region 4 positioned around the well region 3. 9 is formed, and a drain electrode 10 to be an ohmic electrode is formed on the back surface of the SiC substrate 1.
[0043]
Subsequently, Al having a thickness of 200 nm is deposited on the gate insulating film 5 to form the gate electrode 8. Through the above steps, a storage MISFET as shown in FIG. 1 is formed.
[0044]
Next, measurement results of current-voltage characteristics of the storage MISFET according to the present embodiment will be described. In this measurement, the performance of the storage type MISFET of this embodiment was evaluated in comparison with the performance of the conventional storage type MISFET. Specifically, the drain current (on-current) was measured in the on state in which the same value of 10V gate electrode and 30V drain voltage were applied to these two types of storage MISFETs.
[0045]
A conventional storage type MISFET as shown in FIG. 8 was prepared. For comparison, the same structure as the MISFET of this embodiment except for the current induction layer 7 was used.
[0046]
From the measurement results, it was found that in the storage type MISFET of this embodiment, the drain current was increased by nearly 30% compared to the conventional MISFET, but the decrease in breakdown voltage could be suppressed. The reason will be described below.
[0047]
First, in the conventional MISFET as shown in FIG. 8, since a current flows through the high-resistance drift region 114 during the on operation, the drain current decreases.
[0048]
On the other hand, in the MISFET of this embodiment, a current flows through the current induction layer 7 containing an n-type impurity having a concentration higher than that of the drift region 14 during the on operation. Since the resistance of the current induction layer 7 is lower than that of the drift region 14, the on-resistance is reduced, and a drain current having a high current density can be obtained. Since the width of the current induction layer 7 is almost an order of magnitude smaller than the drift region 14 immediately below the gate insulating film 5, the current induction layer 7 may prevent the depletion layer from spreading immediately below the gate insulating film 5. It seems that we were able to keep it to a minimum.
[0049]
As described above, in the present embodiment, by providing the current induction layer 7, it is possible to reduce resistance while suppressing a decrease in breakdown voltage, and to obtain a drain current having a high current density.
[0050]
In the present embodiment, the current inducing layer 7 is provided so as to surround the side of the drift region 14 in plan view, so that the current flowing from the source electrode 9 toward the drift region 4 can be generated. As much as possible can flow through the current induction layer 7. However, in the present invention, the current induction layer 7 may be provided so as to contact only a part of the side of the drift region 14.
[0051]
In the present embodiment, the current induction layer 7 is provided in contact with the channel layer 6 and the well region 3 in the drift region 14. As a result, the path through which the current flowing during the ON operation passes through the drift region 14 can be the shortest, so that the ON resistance can be further reduced. Further, by providing the current induction layer 7 also in the storage channel layer 6, the n-type impurity concentration is higher in the region where the current induction layer 7 is formed in the storage channel layer 6 than in other regions. It has become. Accordingly, the on-resistance can also be reduced in the storage channel layer 6.
[0052]
However, in the present invention, as shown in FIG. 4, even if the current induction layer 7 is provided away from the well region 3, the effect of reducing the on-resistance can be obtained. FIG. 4 is a cross-sectional view showing a modification of the semiconductor device of the first embodiment. Further, the current induction layer 7 does not necessarily have to be formed in the storage channel layer 6 and the drift region 14, and even if it is provided only in the drift region 14, the effect of reducing the on-resistance can be obtained. it can. In these cases, by bringing the current induction layer 7 closer to the well region 3 and the storage channel layer 6, the path through which the current flows to the drift region 14 can be shortened, so that the on-resistance can be reduced. .
[0053]
In this embodiment, the p-type well region 3 is formed in the n-type first SiC layer 2. However, in the present invention, the n-type well region 3 may be formed in the p-type first SiC layer 2. . In this case, the p-type current induction layer 7 is formed.
[0054]
(Second Embodiment)
In the second embodiment, a method for improving the breakdown voltage by providing a depletion layer formation region in addition to the current induction layer described in the first embodiment will be described.
[0055]
FIG. 5 is a cross-sectional view showing the structure of a MISFET using SiC in the second embodiment. As shown in FIG. 5, in the MISFET in the present embodiment, a first SiC layer 42 having a thickness of 10 μm is formed on a SiC substrate 41 having a thickness of 400 μm.
[0056]
On the first SiC layer 42, a second SiC layer 52 having an opening (groove) 51 and having a thickness of 0.3 μm is provided. A portion of the second SiC layer 52 excluding both ends has a concentration of 5 × 10. ¹⁷ cm ^-3 A storage channel layer 46 containing n-type impurities is provided. A concentration of 1 × 10 6 extends from both end portions of the second SiC layer 52 to a portion of the first SiC layer 42 located below the both end portions. ¹⁸ cm ^-3 A contact region 44 having a depth of 0.5 μm containing the n-type impurity is provided.
[0057]
In the region surrounding the side and lower side of the contact region 44 in the first SiC layer 42, the concentration is 5 × 10 5. ¹⁷ cm ^-3 A well region 43 having a depth of 2 μm containing a p-type impurity is provided. A region located inside the well region 43 in the first SiC layer 42 and the second SiC layer 52 has a concentration of 1 × 10 ¹⁸ cm ^-3 A current induction layer 47 having a depth of 2 μm is provided. In the region located on the inner side of the current induction layer 47 in the first SiC layer 42, the concentration is 1 × 10 10. ¹⁵ cm ^-3 A depletion layer forming region 55 having a depth of 2 μm containing the n-type impurity is provided. Of the first SiC layer 42, the region excluding the depletion layer forming region 55, the current induction layer 47, and the well region 43 has a concentration of 5 × 10. ¹⁵ cm ^-3 The drift region 54 contains n-type impurities.
[0058]
A source electrode (first ohmic electrode) 49 made of a Ni film having a thickness of 200 nm is provided over the contact region 44 and the well region 43 exposed on the lower surface of the opening 51. In general, in the power FET, the source electrode 49 is brought into contact with the contact region 44 and the well region 43 in order to determine the potential of the well region 43.
[0059]
A gate insulating film 45 made of an oxide film having a thickness of 30 nm is provided from above the storage channel layer 46 to a portion of the contact region 44 located at the boundary with the storage channel layer 46. A gate electrode 48 made of an Al film having a thickness of 200 nm is provided on the gate insulating film 45.
[0060]
A drain electrode (second ohmic electrode) 50 made of a Ni film having a thickness of 200 nm is provided on the surface (lower surface) facing the main surface of SiC substrate 41.
[0061]
Next, a method for manufacturing the MISFET of this embodiment will be described with reference to FIGS. 6 (a) to 7 (c). FIG. 6A to FIG. 7C are cross-sectional views showing the manufacturing process of the storage MISFET in the second embodiment.
[0062]
First, the SiC substrate 41 is prepared in the step shown in FIG. As the SiC substrate 41, for example, the main surface is 4H− with a diameter of 50 mm, which is off-cut by tilting by 8 degrees from the (0 0 0 1) plane to the [1 1 −2 0] (1 1 2 bar 0) direction. A SiC substrate is used. The SiC substrate 41 has a carrier concentration of 1 × 10 ¹⁸ cm ^-3 N-type impurities.
[0063]
Next, the first SiC layer 42 is epitaxially grown on the SiC substrate 41 while supplying an n-type impurity by the CVD method. At this time, when the thickness of the growth layer reaches 8 μm, the amount of n-type impurity supplied is reduced to form a layer having a thickness of 2 μm. This gives a concentration of 5 × 10 ¹⁵ cm ^-3 Lower layer 56 containing n-type impurities and a concentration of 1 × 10 ¹⁵ cm ^-3 First SiC layer 42 composed of two layers of upper layer 57 containing n-type impurities is formed.
[0064]
6B, after forming an implantation mask (not shown) made of, for example, nickel (Ni) on the first SiC layer 42 and performing multi-stage Al ion implantation, Perform activation annealing. As a result, a concentration of 5 × 10 5 is applied to a part of the upper layer 57 and a part of the lower layer 56 located below the part. ¹⁷ cm ^-3 A well region 43 having a depth of 2 μm containing the p-type impurity is formed.
[0065]
Subsequently, a concentration of 5 × 10 6 is formed on the first SiC layer 42 by CVD. ¹⁷ cm ^-3 A second SiC layer 52 having a thickness of 0.3 μm is formed.
[0066]
Next, in the step shown in FIG. 6C, an implantation mask 58 having a recess 59 and an opening 60 is formed on the second SiC layer 52. At this time, the recess 59 is provided in a shape in which a portion of the implantation mask 58 located above the central portion of the well region 43 is depressed, and the opening 60 is formed with the well region 43 in the first SiC layer 42. The upper surface of second SiC layer 52 located on the portion located at the boundary is provided so as to open.
[0067]
Next, in the step shown in FIG. 7A, after implanting nitrogen (N) into the second SiC layer 52 from above the implantation mask 58, the implantation mask 58 is removed and activation annealing is performed. As a result, an n-type carrier concentration of 1 × 10 5 at a depth of 0.5 μm is formed in a part of the second SiC layer 52 and a part of the well region 43 located below the part. ¹⁸ cm ^-3 The contact region 44 is formed. At this time, the portion sandwiched between the two contact regions 44 in the second SiC layer 52 becomes the storage channel layer 46 while maintaining the n-type impurity concentration. Then, a part of the storage channel layer 46 and the first SiC layer 42 located therebelow have a width of 0.5 μm, a depth of 2 μm, and an n-type carrier concentration of 1 × 10 6. ¹⁸ cm ^-3 The current induction layer 47 is formed. The current induction layer 47 is formed in the storage channel layer 46 and the first SiC layer 42, and a portion located in the first SiC layer 42 is provided in contact with the well region 43. Of the upper layer 57 of the first SiC layer 42, the region excluding the well region 43 and the current induction layer 47 has a concentration of 1 × 10. ¹⁵ cm ^-3 This is a depletion layer forming region 55 containing the n-type impurity. The region excluding the well region 43 in the lower layer 55 of the first SiC layer 42 becomes the drift region 54.
[0068]
By adjusting the dimensions and shape of the implantation mask and the ion implantation acceleration voltage in these processing steps, the current induction layer 47 having a width of 0.5 μm and a thickness of 2 μm can be formed simultaneously with the contact region 44. .
[0069]
Next, in the step shown in FIG. 7B, a resist pattern is applied on the second SiC layer 52, and exposure and development are performed to form a mask pattern (not shown) having an opening (not shown). Form. Then, an opening 51 is formed by performing etching using a mask pattern (not shown) as an etching mask. Opening 51 penetrates through second SiC layer 52 and exposes part of well region 43 in first SiC layer 42.
[0070]
Subsequently, the upper portion of the second SiC layer 52 is thermally oxidized at a temperature of 1100 ° C., thereby forming a gate insulating film 45 having a thickness of 30 nm.
[0071]
Next, in the step shown in FIG. 6C, using an electron beam (EB) vapor deposition apparatus, the well region 43 exposed from the opening 11 is spread over the contact region 44 located around the well region 43. A 200 nm thick Ni film (not shown) is deposited. Subsequently, a Ni (not shown) film having a thickness of 200 nm is deposited on the back surface of the SiC substrate 41. Thereafter, the substrate is heated to a temperature of 1000 ° C. in a heating furnace, so that the source electrode serving as an ohmic electrode extends from above the well region 43 exposed at the opening 51 to the contact region 44 positioned around the well region 43. 49, and a drain electrode 50 to be an ohmic electrode is formed on the back surface of the SiC substrate 41.
[0072]
Subsequently, Al having a thickness of 200 nm is deposited on the gate insulating film 45 to form a gate electrode 48. Through the above steps, a storage type MISFET as shown in FIG. 5 is formed.
[0073]
Next, measurement results of current-voltage characteristics of the storage MISFET according to the present embodiment will be described. In this measurement, the performance of the storage type MISFET of this embodiment was evaluated in comparison with the performance of the conventional storage type MISFET. Specifically, the drain current (on-current) was measured in an on state in which a 10 V gate electrode and a 30 V drain voltage were applied to these two types of storage MISFETs.
[0074]
A conventional storage type MISFET as shown in FIG. 8 was prepared. For comparison, the same structure as that of the MISFET of this embodiment except for the current induction layer 47 and the depletion layer formation region 55 was used.
[0075]
From the measurement results, it was found that the drain current increased by nearly 30% in the storage type MISFET of this embodiment compared to the conventional MISFET. Further, no decrease in breakdown voltage was observed.
[0076]
The reason why the drain current has increased may be the same reason as in the first embodiment. Furthermore, since the depletion layer is more easily formed by providing the depletion layer formation region 55 whose impurity concentration is lower than that of the drift region 54, it is considered that the decrease in breakdown voltage is suppressed.
[0077]
As described above, in the present embodiment, by providing the current induction layer 47, the resistance can be reduced and a drain current having a high current density can be obtained. Furthermore, by providing the depletion layer formation region 55, it is possible to further suppress a decrease in breakdown voltage.
[0078]
In the present embodiment, the current inducing layer 47 is provided so as to surround the side of the drift region 54 in plan view, so that the current flowing from the source electrode 49 toward the drift region 54 can be generated. As much as possible can flow through the current induction layer 47. However, in the present invention, the current induction layer 47 may be provided so as to contact only a part of the side of the drift region 54.
[0079]
In the present embodiment, the current induction layer 47 is provided so as to be in contact with the well region 43 in the drift region 54. As a result, the path through which the current flowing during the ON operation passes through the drift region 54 can be the shortest, and the ON resistance can be further reduced. Further, by providing the current induction layer 47 also in the storage channel layer 46, the n-type impurity concentration is higher in the region where the current induction layer 47 is formed in the storage channel layer 46 than in other regions. It has become. Therefore, the on-resistance can also be reduced in the storage channel layer 46.
[0080]
However, in the present invention, even if the current induction layer 47 is provided away from the well region 43, the effect of reducing the on-resistance can be obtained. Further, the current induction layer 47 does not necessarily have to be formed in the storage channel layer 46 and the drift region 54. Even if the current induction layer 47 is provided only in the drift region 54, the effect of reducing the on-resistance can be obtained. it can. In these cases, by bringing the current induction layer 47 closer to the well region 43 and the storage channel layer 46, the path through which current flows to the drift region 54 can be shortened, so that the on-resistance can be reduced. .
[0081]
In this embodiment, the p-type well region 43 is formed in the n-type first SiC layer 42. However, in the present invention, the n-type well region 43 may be formed in the p-type first SiC layer 42. . In this case, the p-type current induction layer 47 is formed.
[0082]
(Other embodiments)
In the above-described embodiment, the current induction layer is formed in the drift region of the MISFET. However, in the present invention, the effect can be obtained even if the current induction layer is formed in the n-type current induction layer of the IGBT using SiC.
[0083]
In the above-described embodiment, the impurity diffusion layer having a uniform concentration distribution is formed as the storage channel layer. However, in the present invention, the effect can be obtained even by using a layer having a delta doped structure.
[0084]
Moreover, in the above-mentioned embodiment, although it used as a SiC substrate of 4H-SiC, you may use the board | substrate which consists of polytypes other than 4H-SiC.
[0085]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain an SiC semiconductor device capable of flowing a drain current having a high current density while suppressing a decrease in breakdown voltage.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of a MISFET using SiC in the first embodiment.
FIGS. 2A to 2C are cross-sectional views illustrating manufacturing steps of the storage MISFET according to the first embodiment. FIGS.
FIGS. 3A to 3C are cross-sectional views illustrating manufacturing steps of the storage MISFET according to the first embodiment. FIGS.
FIG. 4 is a sectional view showing a modification of the semiconductor device of the first embodiment.
FIG. 5 is a cross-sectional view showing the structure of a MISFET using SiC in the second embodiment.
FIGS. 6A to 6C are cross-sectional views illustrating manufacturing steps of the storage MISFET according to the second embodiment. FIGS.
FIGS. 7A to 7C are cross-sectional views illustrating manufacturing steps of the storage MISFET according to the second embodiment. FIGS.
FIG. 8 is a cross-sectional view showing the structure of a conventional storage MISFET using SiC.
[Explanation of symbols]
1 SiC substrate
2 First SiC layer
3 well region
4 Contact area
5 Gate insulation film
6 Storage channel layer
7 Current induction layer
8 Gate electrode
9 Source electrode
10 Drain electrode
11 opening
12 Second SiC layer
14 Drift region
15 Implant mask
16 opening
17 recess
18 opening
19 Implant mask
41 SiC substrate
42 First SiC layer
43 well region
44 Contact area
45 Gate insulation film
46 Storage channel layer
47 Current induction layer
48 Gate electrode
49 Source electrode
50 substrates
51 opening
52 Second SiC layer
54 Drift region
55 Depletion layer formation region
56 Lower layer
57 Upper layer
58 implantation mask
59 Recess
60 opening

Claims (8)

A silicon carbide layer;
A first impurity doped layer that is provided in a part of the silicon carbide layer and includes an impurity of a first conductivity type;
A second impurity-doped layer provided in a part of the silicon carbide layer and containing an impurity of a second conductivity type;
A third impurity doped layer which is provided above the first impurity doped layer and the second impurity doped layer and contains a first conductivity type impurity having a concentration higher than that of the first impurity doped layer;
A fourth impurity doped layer provided in contact with the side surface of the third impurity doped layer and containing a first conductivity type impurity at a higher concentration than the third impurity doped layer;
A gate insulating film provided on the third impurity-doped layer;
A gate electrode provided on the gate insulating film;
A first ohmic electrode provided in contact with the fourth impurity doped layer;
A second ohmic electrode provided below the silicon carbide layer,
A semiconductor device, wherein a part of the first impurity doped layer is provided with a fifth impurity doped layer containing a first conductivity type impurity having a higher concentration than the first impurity doped layer. The semiconductor device according to claim 1,
A semiconductor device in which the fifth impurity doped layer is provided in contact with the third impurity doped layer. The semiconductor device according to claim 1, wherein
A semiconductor device in which the fifth impurity doped layer is provided in contact with the second impurity doped layer. It is a semiconductor device given in any 1 paragraph among Claims 1-3,
In a portion of the first impurity doped layer located on the side of the fifth impurity doped layer, a sixth impurity doped having a lower concentration of the first conductivity type impurity than the first impurity doped layer. A semiconductor device provided with a layer. The semiconductor device according to any one of claims 1 to 4,
The width of the fifth impurity doped layer is a semiconductor device smaller than the depth. A semiconductor device according to any one of claims 1 to 5,
The semiconductor device wherein the concentration of the first conductivity type impurity in the fifth impurity doped layer is not less than 10 times and not more than 10 ⁵ times the impurity concentration of the first impurity doped layer. Forming a silicon carbide layer having a first impurity doped layer containing an impurity of a first conductivity type on a semiconductor substrate;
After the step (a), a step (b) of forming a second impurity doped layer by ion-implanting a second conductivity type impurity into a part of the silicon carbide layer;
After the step (b), a third impurity containing a first conductivity type impurity having a higher concentration than the first impurity doped layer is formed on the first impurity doped layer and the second impurity doped layer. A step (c) of forming an impurity doped layer;
A fourth impurity doped layer having a first conductivity type impurity having a concentration higher than that of the third impurity doped layer by performing ion implantation of the first conductivity type impurity to the side of the third impurity doped layer. Forming step (d);
By performing ion implantation of a first conductivity type impurity into a part of the first impurity doped layer, a part of the first impurity doped layer has a higher concentration than the first impurity doped layer. A step (e) of forming a fifth impurity doped layer containing the first conductivity type impurity of
Forming a first ohmic electrode in contact with the fourth impurity-doped layer;
Forming a gate insulating film on the third impurity doped layer (g);
A step (h) of forming a gate electrode on the gate insulating film after the step (g);
Forming a second ohmic electrode below the semiconductor substrate (i). A method of manufacturing a semiconductor device according to claim 7,
By forming a mask having an opening located above the first impurity doped layer and performing ion implantation, the fourth impurity doped layer in the step (d) and the second impurity doped layer in the step (e) are performed. 5. A method for manufacturing a semiconductor device, wherein the impurity doped layer is formed.

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