JPH10242458A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously achieve improved feedback capacitance characteristics and a low ON voltage by forming a heavily doped N<+> -type region in contact with a base at an N-type drift region and preventing an N<+> - type region from being formed directly below the gate. SOLUTION: By forming a heavily doped N<+> -type impurity region 4 in advance, a diffusion in side direction is suppressed when a P-type base region 3 is formed, thus suppressing a channel resistance due to the short-channel effect in the P-type base region 3 and reducing an ON voltage. At the same time, the spread of a depletion layer toward the outside of the P-type base region 3 is suppressed and a junction FET resistance is reduced, thus further reducing the ON voltage. Also, by bringing the large-part region directly below a gate electrode 5 into contact with a drift region 2, a part in contact with the heavily doped N<+> -type impurity region 4 is reduced, thus enabling the depletion layer to be spread easily and reducing a feedback capacitance and discharging an electric charge with a low drain voltage in switching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOS type semiconductor device characterized by a structure for achieving good feedback capacitance characteristics and low on-voltage.

[0002]

2. Description of the Related Art MOs such as power MOSFETs and IGBTs
Semiconductor devices having the S structure are used in various applications as power devices, such as power semiconductor elements and inverters for motor drives.

FIG. 7 is a sectional view showing the structure of a conventional MOS type semiconductor device. FIG. 8 is a sectional view showing the structure of another conventional MOS type semiconductor device. Here, the structure illustrated in FIG. 7 is referred to as a semiconductor device having an A structure, and the structure illustrated in FIG. 8 is referred to as a semiconductor device having a B structure.

In the semiconductor device having the structure A shown in FIG. 7, an N− type drift region 22 is stacked on a semiconductor substrate 21, and a P type base region 23 and an N + type source region 26 are provided in the drift region 22. A gate electrode 25 made of polysilicon is provided between the drift region 22, the base region 23, and the source region 26.

On the other hand, the semiconductor device having the structure B shown in FIG. 8 has the same structure as that of the semiconductor device having the structure A, and has a portion facing the polysilicon gate electrode 25 and on the drift region excluding the base region 23. , A high-concentration N + -type impurity region 24 of the same conductivity type as the drift region 22 is provided.

The P-type base region 23 and the N + -type source region 26 are formed using a polysilicon gate electrode as a mask material. Here, if a high-concentration N + type region is formed in the N− type drift region before the P type base region is formed as in the case of the B structure, when the P type base region is formed, the lateral diffusion is reduced. Since the channel is suppressed and the channel length is reduced, and the junction FET resistance can be reduced (JFET effect), the ON voltage is improved with respect to the semiconductor device having the A structure.

On the other hand, the capacitance characteristics of a MOS type semiconductor device depend on the drain voltage, and in particular, the gate-drain capacitance (feedback capacitance) has a large voltage dependence. Since the feedback capacitance is the series capacitance of the insulating capacitance of the gate oxide film and the depletion layer formed on the semiconductor surface, if a high-concentration N + type impurity region 24 is formed between the P type base regions 23 as in the B structure. In addition, the extension of the depletion layer below the gate electrode 25 is suppressed. Therefore, in the B structure, the charge stored in the gate electrode 25 does not decrease until a high drain voltage is reached (hereinafter, discharge of this charge is also referred to as a decrease in feedback capacity).

As described above, in the semiconductor device having the B structure, since the feedback capacitance does not decrease until the drain voltage becomes high, the applied drain voltage is divided into the input capacitance and the feedback capacitance. Also, the gate potential increases. As a result, malfunctions are likely to occur, and switching loss will increase.

[0009]

SUMMARY OF THE INVENTION The above-mentioned conventional A, B
In the semiconductor device of each structure, there is a problem that the improvement of the capacitance characteristic and the improvement of the on-voltage are in conflict with each other, and one of the characteristics has to be sacrificed.

The present invention has been made in view of such circumstances, and provides a semiconductor device having a structure capable of simultaneously realizing a good feedback capacitance characteristic and a low on-state voltage and ensuring a stable operation. The purpose is to provide.

[0011]

The gist of the present invention is a MOS transistor.
With respect to the structure of the p-type semiconductor device, N
Forming an N + type region having a higher concentration than the − type drift region,
By preventing the formation of the high-concentration N + type region in the central portion immediately below the gate between adjacent P-type base regions (MOS portion), good feedback capacitance characteristics and low on-voltage are simultaneously realized. .

[0012] The above-mentioned object can be more specifically achieved by the following means. First, an invention corresponding to claim 1 includes a first conductivity type drift region formed on a semiconductor substrate, a second conductivity type base region selectively formed on one main surface of the drift region, Formed via a first conductivity type source region selectively formed in the base region, and a first conductivity type drift region, a second conductivity type base region, and an insulating film formed on the first conductivity type source region. A MOS type semiconductor device having a doped gate electrode, a first conductivity type impurity region doped at a higher concentration than the drift region on the side surface of the base region, and a drift region below the gate electrode. A semiconductor device in which a first conductivity type region having an impurity concentration lower than an impurity region is formed.

According to the present invention, such a configuration is provided.
For example, in a MOSFET or an IGBT, the presence of a high-concentration impurity region on the side surface of the base region causes a short-channel effect and a JFET effect to reduce the on-voltage.
Further, since the first conductivity type region having a low impurity concentration is formed in the region below the gate electrode, the feedback capacitance at this portion can be reduced, and the capacitance can be reduced at a low drain voltage.

Therefore, good feedback capacitance characteristics and low on-state voltage can be simultaneously realized. Next, claim 2
The invention corresponding to claim 1 is the invention according to claim 1,
The impurity region is formed such that an end on the side of the first conductivity type region having a low impurity concentration below the gate electrode is 5 μm from the end of the gate electrode.
m is a semiconductor device at a position of m or less.

The present invention is provided with such a configuration.
In addition to having the same function and effect as the semiconductor device of the invention corresponding to claim 1, the area occupied by the high-concentration impurity region immediately below the gate electrode can be reliably reduced, so that the above-described effect can be more reliably achieved. .

The invention according to claim 3 is the semiconductor device according to claim 1 or 2, wherein the first conductivity type region having a low impurity concentration is a drift region. The present invention has such a configuration.
Alternatively, the same operation and effect as those of the semiconductor device according to the second aspect of the invention can be obtained.

Further, the invention according to claim 4 is the first invention.
A conductivity type drift region, a second conductivity type base region,
A MOS type semiconductor device including a first conductivity type source region and a gate electrode formed with an insulating film interposed therebetween, wherein an impurity is doped at a higher concentration than the drift region on a drift region side of a base region; A semiconductor device having a first conductivity type impurity region, wherein an area of the impurity region below the gate electrode and facing the gate electrode is smaller than an area of the drift region facing the gate electrode.

Since the present invention has such a configuration,
For example, the lateral MOS type semiconductor device having all the electrodes on the chip surface has the same operation and effect as the semiconductor device according to the first aspect of the present invention.

[0019]

Embodiments of the present invention will be described below. (First Embodiment of the Invention) FIG. 1 is a sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention.

This semiconductor device is a power MOSFET. As shown in FIG. 1, an N-type drift region 2 formed on a main surface of an N-type semiconductor substrate 1 with an impurity concentration and a thickness corresponding to a breakdown voltage system. Is formed. On the drift region 2, a gate oxide film 5a and a polysilicon gate electrode 5b are formed.
Are formed at predetermined intervals.

On the main surface of the drift region 2 on the side of the gate electrode 5, an N + type impurity region 4 diffused and formed by impurity implantation is selectively formed.
A P-type base region 3 and an N + -type source region 6 are formed on the main surface on the side of the gate electrode 5. Although not particularly shown, power MOSFETs such as a source electrode and a drain electrode
Other components are also provided.

Here, the structure of the N + type impurity region 4 will be described in more detail. In the manufacturing process of this semiconductor device, first, impurity region 4 is formed at a position between gate electrodes 5 to a depth of 2 to 3 μm, and base region 3 is formed inside main region so as to penetrate impurity region 4 from the main surface. Therefore, as shown in FIG. 1, the impurity region 4
It is configured as a thin layer sandwiched between the base region 3 and the drift region 2 below. Here, distance x from the end of polysilicon gate electrode 5b to the end of impurity region 4 on the drift region 2 side is 5 μm or less. Therefore, most of the gate oxide film 5a on the semiconductor substrate 1 side is in direct contact with the drift region 2.

The impurity region 4 has a doping amount of 10 ¹² c
About m ⁻³ of phosphorus P or arsenic As is added, and is a low-resistance impurity region of the same conductivity type as the drift region 2. Therefore, in this semiconductor device, a selectively high-concentration N + type region is formed in the N− type drift region, and no N + type region is formed immediately below the center of the gate electrode 5.

FIG. 2 is a view of the semiconductor device according to the present embodiment as viewed from above. As shown in FIG. 1A, this semiconductor device uses a mesh gate as the gate 5 (part of the drawing is omitted). As shown in FIG. 2B, the semiconductor device of the present embodiment may be applied to a case where a stripe gate is used as the gate 5 (part of the drawing is omitted).

Next, the operation of the semiconductor device thus configured according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 shows N + in the semiconductor device of the present embodiment.
FIG. 4 is a diagram for explaining the function of a type impurity region and a drift region.

The formation of the P-type base region 3 is performed by using the gate electrode 5
This is performed by adding impurities using the mask as a mask. At the time of this impurity addition, since the high-concentration N + type impurity region 4 is formed in advance, the lateral diffusion of the P type base region 4 is suppressed. Therefore, as shown in FIG. 3A, the short channel effect in the base region 4 works, the channel resistance is reduced, and the on-voltage is reduced.

Next, the on-resistance is the sum of the resistances of the carrier paths from the source to the drain. Among them, there is a so-called JFET resistance. The JFET resistance is
This resistance is present in a portion surrounded by the base region from immediately below the gate electrode to the eighth circle when both ends of the base region are approximated to be a quadrant. It can also be understood as the effect (JFET effect) of expanding the depletion layer shown in FIG.

If the high-concentration impurity region 4 is provided outside the base region 3 here, the depletion layer shown in FIG. In other words, the JFET resistance is reduced due to the presence of the low-resistance impurity region 4, and the ON voltage is reduced.

As described above, the presence of the N + type impurity region 4 contributes to the reduction of the on-state voltage due to the short channel effect and the JFET effect. Therefore, when a current flows between the source and the drain, an advantage due to a reduction in on-resistance can be obtained.

Next, when switching is performed, it is advantageous that the feedback capacitance is small. That is, the switching speed is determined by the speed at which the parasitic capacitance can be charged and discharged.
Also, the charge can be discharged with a low drain voltage during switching.

In the structure of the present embodiment, the drift region 2 is in contact with most of the portion immediately below the gate electrode 5, and the portion where the high-concentration N + type impurity region 4 is in contact is small.
Therefore, as shown in FIG. 3C, it can be considered that the depletion layer easily spreads in this portion and the feedback capacitance is small. Therefore, a decrease in the feedback capacitance (discharge of electric charge) occurs from a low drain voltage. For this reason, the rise of the gate potential during switching is unlikely to occur.

As described above, according to the semiconductor device according to the embodiment of the present invention, with respect to the structure of the MOS type semiconductor device, an N + type impurity having a higher concentration than the N− type drift region is provided on the side surface of the P type base region 3. Since the region 4 is formed and the high-concentration N + type region is not formed in the central portion immediately below the gate between the adjacent P-type base regions 3 (MOS portion), low ON-state due to short channel and JFET effect is achieved. The voltage can be increased, and the feedback capacitance can be reduced from a low drain voltage.

As described above, since the ON voltage is reduced and the gate potential is hardly increased due to the improvement of the feedback capacitance characteristic, the switching oscillation and malfunction can be suppressed, and the switching loss can be reduced.

In addition, since the JFET resistance can be reduced and the expansion of the depletion layer outside the base region 3 can be suppressed, the element spacing can be reduced, and the device of the present embodiment can be manufactured by the same process as the conventional one. Therefore, the chip can be reduced by improving the on-state voltage, and the manufacturing cost can be reduced.

Although the base region 3 is formed to penetrate the impurity region 4 in the semiconductor device of the present embodiment, the present invention is not limited to this.
If the structure immediately below is the same, the base region 3 becomes the impurity region 4
May be formed so as not to pass through. Further, the material of the gate electrode is not limited to polysilicon, and another material may be used.

Further, in the semiconductor device of the present embodiment, the case where an N-channel MOSFET is formed has been described, but the present invention is not limited to this. For example, the present invention can be applied to an IGBT by selecting a semiconductor wafer. Further, the present invention can be applied to a P-channel type by reversing the conductivity type.

FIGS. 4 and 5 show static characteristics and capacitance characteristics when the present embodiment is applied to an IGBT. FIG. 4 is a diagram showing a comparative example of the static characteristics (Ic-Vce) of the IGBT having the structure of the present invention and the conventional structure.

FIG. 5 shows an IG of the structure of the present invention and an IG of the conventional structure.
It is a figure showing the comparative example of the capacity characteristic (Cres-Vce) in BT. 4 and 5, the structures A and B are obtained by applying the structures described with reference to FIGS. 7 and 8 in the related art to the IGBT.

As shown in FIG. 4, in the IGBT of the present invention, the on-resistance is reduced, so that the static characteristics are better than those of the conventional A structure. Specifically, the parameter g _m = ΔI _c / Δ
V _ge (where [Delta] I _c is the collector current, [Delta] V _ge gate voltage) becomes higher, in which the gradient of the static characteristics increases.

On the other hand, FIG. 5 shows that in the IGBT of the present invention,
It is shown that the feedback capacitance is reduced from a low drain voltage as compared with that of the B structure. That is, the IGBT of the present invention
Thus, the advantages of both the A structure and the B structure can be obtained. (Second Embodiment of the Invention) In this embodiment, a method of manufacturing the semiconductor device described in the first embodiment shown in FIG. 1 will be described.

FIG. 6 is a view showing an example of main manufacturing steps in a semiconductor device manufacturing method according to the second embodiment of the present invention. The same parts as those in FIG. .

First, the process up to the manufacture of the drift region 2 is the same as that of a general semiconductor device, and a description thereof will be omitted. Next, as shown in FIG. ^6A , phosphorus P or arsenic As having a doping amount of about 10 ¹² cm ⁻³ is added to the main surface of the N-type drift region 2 to selectively add an N + type impurity region to a selective region. 4 is formed. The formation of the impurity region 4 is performed by ion-implanting an impurity serving as a dopant to a depth of 2 to 3 (μm). Further, other general methods may be used. In addition,
This impurity region 4 is formed except for a portion where the polysilicon gate electrode is formed (more precisely, the inside of 1-2 (μm) thereof).

Next, a gate oxide film is formed, and polysilicon is formed as the gate electrode 5. (FIG. 6 (b)). Next, P is formed by ion implantation using polysilicon as a mask material.
The mold base region 3 is formed (FIG. 6C).

Hereinafter, an N + type source region is formed, and further, a source electrode and other components are provided to complete the semiconductor device. As described above, according to the method of manufacturing a semiconductor device of the embodiment of the present invention, only the step of forming the N + type impurity region 4 is provided. The semiconductor device of the embodiment can be manufactured.

In this embodiment, the N-channel MOS
Although the case of manufacturing a semiconductor device of an FET has been described, the present invention is not limited to this, and can be applied to an IGBT. Further, the present invention can be applied to a P-channel type by reversing the conductivity type. In addition, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.

[0046]

As described in detail above, according to the present invention, N
Since a high-concentration N + type region in contact with the base is formed in the − type drift region and the N + type region is hardly formed immediately below the gate, good feedback capacitance characteristics and low on-voltage are simultaneously realized. Thus, a semiconductor device having a structure capable of ensuring stable operation can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view of the semiconductor device of the embodiment as viewed from above;

FIG. 3 is an exemplary view for explaining the function of an N + type impurity region and a drift region in the semiconductor device according to the embodiment;

FIG. 4 is a diagram showing a comparative example of static characteristics (Ic-Vce) of IGBTs of the structure of the present invention and a conventional structure.

FIG. 5 is a diagram showing a comparative example of capacitance characteristics (Cres-Vce) of the IGBT having the structure of the present invention and the conventional structure.

FIG. 6 is a diagram showing an example of main manufacturing steps in a semiconductor device manufacturing method according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing the structure of a conventional MOS type semiconductor device.

FIG. 8 is a sectional view showing the structure of another conventional MOS type semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 drift region 3 base region 4 impurity region 5 gate electrode 6 source region

Claims (4)

[Claims] A first conductivity type drift region formed on a semiconductor substrate; a second conductivity type base region selectively formed on one main surface of the drift region; A source region of the first conductivity type selectively formed, and an insulating film formed on the first conductivity type drift region, the second conductivity type base region, and the first conductivity type source region. A MOS type semiconductor device having a gate electrode, a first conductivity type impurity region doped at a higher concentration than the drift region on a side surface of the base region, and the drift region below the gate electrode. A first conductivity type region having an impurity concentration lower than that of the impurity region. 2. The semiconductor device according to claim 1, wherein the impurity region has an end on the side of the first conductivity type region having a low impurity concentration below the gate electrode at a position of 5 μm or less from the end of the gate electrode. Item 2. The semiconductor device according to item 1. 3. The drift region according to claim 1, wherein the first conductivity type region having a low impurity concentration is the drift region.
Or the semiconductor device according to 2. 4. A semiconductor device comprising a first conductivity type drift region, a second conductivity type base region, a first conductivity type source region, and a gate electrode formed via an insulating film.
An OS type semiconductor device, a first conductivity type impurity region doped at a higher concentration than the drift region on a side of the base region on the drift region side, and the gate electrode of the impurity region; A semiconductor device, wherein an area occupying a lower side of the drift region facing the gate electrode is smaller than an area of the drift region facing the gate electrode.