JPH04276663A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04276663A JPH04276663A JP3038230A JP3823091A JPH04276663A JP H04276663 A JPH04276663 A JP H04276663A JP 3038230 A JP3038230 A JP 3038230A JP 3823091 A JP3823091 A JP 3823091A JP H04276663 A JPH04276663 A JP H04276663A
- Authority
- JP
- Japan
- Prior art keywords
- concentration
- drain region
- region
- low
- type drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 14
- -1 boron ions Chemical class 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体装置に関し、特
に縦型二重拡散ＭＯＳＦＥＴを有する半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a vertical double-diffused MOSFET.
【０００２】0002
【従来の技術】従来の半導体装置は、図２に示すように
、高濃度ｎ型ドレイン領域４の上に設けた不純物濃度が
１０１６ｃｍ−３の低濃度ｎ型ドレイン領域５の上面に
チャネル領域となる不純物濃度が１０１８ｃｍ−３のｐ
型ベース領域６が形成され、ｐ型ベース領域６内にはｎ
型ソース領域７と破壊耐量を向上させるためのバックゲ
ート層として高濃度ｐ型領域９が形成されている。低濃
度ｎ型ドレイン領域５，ｐ型ベース領域６，ｎ型ソース
領域７を含む表面にゲート酸化膜１０及び多結晶シリコ
ン層からなるゲート電極３が形成されている。このゲー
ト酸化膜１０及びゲート電極３は、ｎ型ソース領域７の
一部と高濃度ｐ型領域９の部分で開孔されている。ゲー
ト電極３を含む表面には層間絶縁膜１１が形成され、層
間絶縁膜１１は前記開孔部のさらに内側で開孔され、こ
の部分でｎ型ソース領域７の一部と高濃度ｐ型領域９に
接続するようにソース電極２が形成されている。ソース
電極２上には表面保護膜１２が形成され、また、下面に
はドレイン電極１が形成されている。2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. p with an impurity concentration of 1018 cm-3
A type base region 6 is formed, and an n-type base region 6 is formed in the p-type base region 6.
A heavily doped p-type region 9 is formed as a type source region 7 and a back gate layer for improving breakdown resistance. A gate oxide film 10 and a gate electrode 3 made of a polycrystalline silicon layer are formed on a surface including a lightly doped n-type drain region 5, a p-type base region 6, and an n-type source region 7. This gate oxide film 10 and gate electrode 3 have holes formed in a part of the n-type source region 7 and a part of the heavily doped p-type region 9. An interlayer insulating film 11 is formed on the surface including the gate electrode 3, and the interlayer insulating film 11 is opened further inside the opening, and in this part, a part of the n-type source region 7 and the highly doped p-type region are formed. A source electrode 2 is formed so as to be connected to 9. A surface protection film 12 is formed on the source electrode 2, and a drain electrode 1 is formed on the lower surface.
【０００３】0003
【発明が解決しようとする課題】上述した従来の半導体
装置は、ゲート・チャネル領域となるＰ型ベース領域の
基板表面付近での不純物濃度が高いためチャネル濃度が
高くなり、ＭＯＳＦＥＴを導通状態にするためのゲート
・ソース間のしきい電圧ＶＧＳ（ｏｆｆ） が高くなり
、このＭＯＳＦＥＴを低しきい電圧駆動の集積回路と接
続した場合の集積回路からの直接駆動や、１．５〜２Ｖ
の乾電池によるこのＭＯＳＦＥＴの駆動が困難であると
いう問題点があった。[Problems to be Solved by the Invention] In the conventional semiconductor device described above, since the impurity concentration near the substrate surface of the P-type base region which becomes the gate/channel region is high, the channel concentration becomes high and the MOSFET becomes conductive. The threshold voltage VGS(off) between the gate and source becomes high, and when this MOSFET is connected to an integrated circuit with a low threshold voltage drive, direct drive from the integrated circuit or 1.5 to 2V
There was a problem in that it was difficult to drive this MOSFET with a dry battery.
【０００４】0004
【課題を解決するための手段】本発明の半導体装置は、
高濃度の一導電型ドレイン領域上に順次積層して形成し
た第１の低濃度一導電型ドレイン領域及び前記第１の低
濃度一導電型ドレイン領域よりも低不純物濃度の第２の
低濃度一導電型ドレイン領域と、前記第２の低濃度一導
電型ドレイン領域上にゲート酸化膜を介して設けたゲー
ト電極と、前記ゲート電極に整合して前記第１及び第２
の低濃度一導電型ドレイン領域内に設けた低キャリア濃
度の逆導電型ベース領域と、前記ゲート電極に整合して
前記ベース領域内に設けた一導電型のソース領域とを有
する。[Means for Solving the Problems] A semiconductor device of the present invention includes:
A first low concentration one conductivity type drain region formed by sequentially stacking on the high concentration one conductivity type drain region and a second low concentration one conductivity type drain region having an impurity concentration lower than that of the first low concentration one conductivity type drain region. a conductivity type drain region, a gate electrode provided on the second low concentration one conductivity type drain region via a gate oxide film, and a gate electrode provided on the first and second conductivity type drain regions in alignment with the gate electrode.
a base region of a low carrier concentration and an opposite conductivity type provided in a low concentration drain region of one conductivity type; and a source region of one conductivity type provided in the base region in alignment with the gate electrode.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００６】図１は本発明の一実施例を示す半導体チッ
プの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.
【０００７】図１に示すように、高濃度ｎ型ドレイン領
域４の上にエピタキシャル成長法により不純物濃度が１
０１６ｃｍ−３の第１の低濃度ｎ型ドレイン領域５と、
低濃度ｎ型ドレイン領域５よりも更に低不純物濃度であ
る不純物濃度が１０１５ｃｍ−３の第２の低濃度ｎ型ド
レイン領域８を順次積層して形成する。次に、低濃度ｎ
型ドレイン領域８の上にゲート酸化膜１０を設け、ゲー
ト酸化膜１０の上に多結晶シリコン層を堆積してパター
ニングしゲート電極３を形成する。次に、ゲート電極３
をマスクとして低濃度ｎ型ドレイン領域８，５にホウ素
イオンを深くイオン注入して不純物濃度が１０１７ｃｍ
−３のｐ型のベース領域６を形成する。次に、同様にゲ
ート電極３をマスクとしてベース領域６内にリンイオン
を浅くイオン注入してｎ型のソース領域７を形成し、ソ
ース領域７内に破壊耐圧を向上させるためのバックゲー
ト領域として高濃度ｐ型領域９を選択的に形成する。次
に、ゲート電極３をマスクとしてゲート酸化膜１０をエ
ッチング除去して第１の開孔部を設け、第１の開孔部を
含む表面に層間絶縁膜１１を堆積する。次に、第１の開
孔部の内側の層間絶縁膜１１を選択的にエッチングして
第２の開孔部を設け、第２の開孔部を含む表面にｎ型ソ
ース領域７及び高濃度ｐ型領域９と接続するソース電極
２を設け、ソース電極２を含む表面に表面保護膜１２を
形成し、高濃度ｎ型ドレイン領域４の裏面にドレイン電
極１を形成し縦型ＭＯＳＦＥＴを形成する。As shown in FIG. 1, an impurity concentration of 1 is formed on the heavily doped n-type drain region 4 by epitaxial growth.
016 cm −3 of a first low concentration n-type drain region 5;
A second low-concentration n-type drain region 8 having an impurity concentration of 10<15 >cm<-3>, which is an even lower impurity concentration than the low-concentration n-type drain region 5, is formed by sequentially stacking layers. Next, low concentration n
A gate oxide film 10 is provided on the type drain region 8, and a polycrystalline silicon layer is deposited on the gate oxide film 10 and patterned to form the gate electrode 3. Next, gate electrode 3
Using as a mask, boron ions are deeply implanted into the low concentration n-type drain regions 8 and 5 until the impurity concentration is 1017 cm.
-3 p-type base region 6 is formed. Next, similarly, using the gate electrode 3 as a mask, phosphorus ions are shallowly implanted into the base region 6 to form an n-type source region 7. A doped p-type region 9 is selectively formed. Next, using the gate electrode 3 as a mask, the gate oxide film 10 is removed by etching to form a first opening, and an interlayer insulating film 11 is deposited on the surface including the first opening. Next, the interlayer insulating film 11 inside the first opening is selectively etched to form a second opening, and the n-type source region 7 and the high concentration are formed on the surface including the second opening. A source electrode 2 connected to the p-type region 9 is provided, a surface protective film 12 is formed on the surface including the source electrode 2, and a drain electrode 1 is formed on the back surface of the high concentration n-type drain region 4 to form a vertical MOSFET. .
【０００８】本発明によれば、チャネル領域となるベー
ス領域６の基板表面近傍の不純物濃度が低いため下式に
示すチャネル濃度Ｑｂ が低くなり、ＭＯＳＦＥＴを導
通状態にするためのゲート・ソース間のしきい電圧ＶＧ
Ｓ（ｏｆｆ） が小さくできる。According to the present invention, since the impurity concentration near the substrate surface of the base region 6 serving as the channel region is low, the channel concentration Qb expressed by the following equation is low, and the concentration between the gate and source to make the MOSFET conductive is low. Threshold voltage VG
S(off) can be made small.
【０００９】[0009]
【００１０】したがって、このＭＯＳＦＥＴを低しきい
電圧駆動の集積回路と接続した場合の集積回路からの直
接駆動や、乾電池（１．５Ｖ〜２Ｖ）によるこのＭＯＳ
ＦＥＴの駆動が実現できる。Therefore, when this MOSFET is connected to an integrated circuit driven by a low threshold voltage, this MOS can be driven directly from the integrated circuit, or by using a dry battery (1.5V to 2V)
FET driving can be realized.
【００１１】なお、低濃度ｎ型ドレイン領域８はエピタ
キシャル成長法で形成する代りに低濃度ｎ型ドレイン領
域５の表面にｐ型不純物を低濃度にイオン注入してキャ
リア濃度を低減させることにより形成しても良い。Note that instead of forming the lightly doped n-type drain region 8 by epitaxial growth, it is formed by ion-implanting p-type impurities into the surface of the lightly doped n-type drain region 5 at a low concentration to reduce the carrier concentration. It's okay.
【００１２】0012
【発明の効果】以上説明したように、本発明は第１の低
濃度ｎ型ドレイン領域の上に更に低濃度の第２の低濃度
ｎ型ドレイン領域を形成することにより、チャネル領域
となるベース領域のキャリア濃度を低減してしきい電圧
ＶＧＳ（ｏｆｆ） を小さくすることができ、集積回路
からの直接駆動や、１．５〜２Ｖの乾電池による駆動が
可能な縦型ＭＯＳＦＥＴを備えた半導体装置を実現でき
るという効果を有する。Effects of the Invention As explained above, the present invention forms a second lightly doped n-type drain region on top of the first lightly doped n-type drain region. A semiconductor device equipped with a vertical MOSFET that can reduce the threshold voltage VGS(off) by reducing the carrier concentration in the region, and can be driven directly from an integrated circuit or by a 1.5-2V dry cell battery. This has the effect of realizing the following.
【図１】本発明の一実施例を示す半導体チップの断面図
である。FIG. 1 is a cross-sectional view of a semiconductor chip showing one embodiment of the present invention.
【図２】従来の半導体装置の一例を示す半導体チップの
断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
１ ドレイン電極
２ ソース電極
３ ゲート電極
４ 高濃度ｎ型ドレイン領域
５，８ 低濃度ｎ型ドレイン領域６ ｐ型
ベース領域
７ ｎ型ベース領域
９ 高濃度ｐ型領域
１０ ゲート酸化膜
１１ 層間絶縁膜
１２ 表面保護膜1 Drain electrode 2 Source electrode 3 Gate electrode 4 High concentration n-type drain regions 5, 8 Low concentration n-type drain region 6 P-type base region 7 N-type base region 9 High concentration p-type region 10 Gate oxide film 11 Interlayer insulating film 12 surface protective film
Claims (1)
次積層して形成した第１の低濃度一導電型ドレイン領域
及び前記第１の低濃度一導電型ドレイン領域よりも低不
純物濃度の第２の低濃度一導電型ドレイン領域と、前記
第２の低濃度一導電型ドレイン領域上にゲート酸化膜を
介して設けたゲート電極と、前記ゲート電極に整合して
前記第１及び第２の低濃度一導電型ドレイン領域内に設
けた低キャリア濃度の逆導電型ベース領域と、前記ゲー
ト電極に整合して前記ベース領域内に設けた一導電型の
ソース領域とを有することを特徴とする半導体装置。1. A first low concentration one conductivity type drain region formed by sequentially stacking on a high concentration one conductivity type drain region, and a first low concentration one conductivity type drain region having an impurity concentration lower than the first low concentration one conductivity type drain region. a gate electrode provided on the second low concentration one conductivity type drain region via a gate oxide film; It is characterized by having a base region of a low carrier concentration and an opposite conductivity type provided in a drain region of one conductivity type with low concentration, and a source region of one conductivity type provided in the base region in alignment with the gate electrode. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3038230A JPH04276663A (en) | 1991-03-05 | 1991-03-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3038230A JPH04276663A (en) | 1991-03-05 | 1991-03-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04276663A true JPH04276663A (en) | 1992-10-01 |
Family
ID=12519507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3038230A Pending JPH04276663A (en) | 1991-03-05 | 1991-03-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04276663A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005578A (en) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2005175416A (en) * | 2003-11-19 | 2005-06-30 | Fuji Electric Device Technology Co Ltd | Semiconductor device for use in space |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58165380A (en) * | 1982-03-26 | 1983-09-30 | Hitachi Ltd | High withstand voltage semiconductor device |
| JPS59132671A (en) * | 1983-01-19 | 1984-07-30 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor transistor |
-
1991
- 1991-03-05 JP JP3038230A patent/JPH04276663A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58165380A (en) * | 1982-03-26 | 1983-09-30 | Hitachi Ltd | High withstand voltage semiconductor device |
| JPS59132671A (en) * | 1983-01-19 | 1984-07-30 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005578A (en) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2005175416A (en) * | 2003-11-19 | 2005-06-30 | Fuji Electric Device Technology Co Ltd | Semiconductor device for use in space |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970924 |