JPS6143865B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a MOS type semiconductor device (MOSIC), and relates to a MOS transistor (hereinafter referred to as
The present invention provides an element structure that prevents the punch-through phenomenon between the source and drain that occurs in a MOS-Tr (hereinafter referred to as a MOS-Tr) having a short channel length, and has a large mutual conductance gm.

As an element structure for preventing the punch-through phenomenon of MOS-Tr, the structure shown in FIG. 1 has been proposed in Japanese Patent Laid-Open No. 8483/1983. The MOS-Tr in FIG. 1 includes a semiconductor substrate (hereinafter referred to as Si substrate) 1, a gate oxide film (hereinafter referred to as gate SiO ₂ film) 2, a source region 3,
drain region 4, field SiO ₂ film 5, polysilicon gate film 6, gate electrode 7, source electrode 8,
It consists of the structure of the drain electrode 9. A drain depletion layer 10 is formed in the Si substrate 1 due to the voltage applied to the drain region 4, and 11 indicates a channel in this structure.

The above structure allows the drain depletion layer 10 to expand by burying the surface in contact with the gate SiO ₂ film 2 deeper into the Si substrate 1 than the drain region 4, and by bending the semiconductor surface 11 in the channel portion in the source/drain direction. The direction of the film was oriented toward the substrate to increase the punch-through voltage.

However, the above structure has the following problems.

First, when the impurity concentration in the source/drain regions is high, the contacting surface of the gate SiO ₂ film 2 is buried sufficiently deep into the Si substrate 1 to separate the bottom surface of the source/drain regions 3 and 4 and the gate SiO ₂ film 2. It is difficult to increase the punch-through pressure without increasing the difference in the depth of the lower surface. This is because the impurity concentration of the source and drain is high, so the drain depletion layer 10 does not extend into the drain region, but only in the direction of the substrate, and the lower surface of the gate SiO ₂ film 2 becomes the source and drain region.
If the depth is not too deep below the bottom surface of the drain region, punch-through will occur immediately.

Second, since the bottom surface of the gate SiO ₂ film must be buried deeper into the Si substrate than the bottom surfaces of the source/drain regions 3 and 4, the Si
If it is necessary to bury the Si substrate in the substrate 1, it is extremely difficult to remove a portion of the Si substrate with a gate width of 1 μ or more.

Third, because the channels are bent, it is extremely difficult to obtain good reproducible characteristics.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an element structure which solves the above-mentioned problems and has a high punch-through voltage and good characteristics. That is, the present invention completely eliminates the drawbacks of the MOS-Tr shown in FIG.
The characteristics of the MOS-Tr structure are shown in Figures 2, 3, and 4.
This will be explained in detail with reference to the drawings.

As shown in FIG. 2, a Si substrate 20, a gate SiO ₂
Film 21, source region 22, drain region 23, out-diffused low concentration source region 24, out-diffused low concentration drain region 25, gate electrode 26, metal electrodes 27, 28, 29, field SiO ₂ film 3
0, CVD-SiO ₂ film 31. According to this structure, the source located below the gate part
The impurity concentration of the drain regions 24 and 25 is much lower than that of the surfaces of the source/drain regions 22 and 23.

This is because, as shown in FIG. 3, if we take the impurity concentration distribution of the source/drain regions 24 and 25, the impurity concentration at the surface is high, and as we go from the surface to the inside, the impurity penetration becomes smaller.
Therefore, the impurity concentration is gradually decreasing. In a source/drain region that also has such an impurity concentration distribution, for example, a buried gate
The position of the drain region 25 on the bottom surface of the SiO ₂ film 21 is
In this case, the impurity concentration c of the drain region 25 at that position is considerably lower than the surface concentration b of the drain region 25. This relationship is the same on the source side. Moreover, the source/drain regions 24 and 25 in contact with the SiO ₂ film 21 are outwardly diffused and have a low concentration as described later, and when looking at the concentration in the direction of arrow x from A, as shown in FIG. The impurity concentration c at the position A is lower than the impurity concentration d of the source/drain regions 22 and 24 which are not outdiffused at the same depth. This is the gate SiO ₂ film 21
Outdiffused source/drain region 2 in contact with
The same thing happens at other positions 4 and 25.
Note that e in FIG. 4 indicates the outwardly diffused portion.

In this way, by making the impurity concentration of the drain region 25 located from the bottom surface of the gate part to the side surface of the gate part lower than that of the other drain regions 23, a channel can be formed as shown in FIG. Since the expansion direction of the drain depletion layer 32 near the region can be directed not only toward the substrate but also into the drain region 25, the punch-through breakdown voltage is high, and
We were able to realize a MOS-Tr with a short channel length.

Next, one manufacturing method for obtaining the structure of the present invention will be explained with reference to FIG.

An embodiment in which the present invention is applied to an A-gate MOS-Tr and a manufacturing method thereof will be described in detail with reference to FIG.

A Si ₃ N ₄ film 41 with a thickness of about 1000 Å to 3000 Å is formed on an N-type or P-type Si substrate 20 by the CVD method, and a photosensitive resin film 42 is further applied on the Si ₃ N ₄ film 41, and a gate is formed by photoetching. The photosensitive resin film 42 in other regions is removed, leaving the photosensitive resin film 42 on the source/drain regions including the upper part (FIG. 5a).

After that, using the photosensitive resin film 42 as a mask, CF ₄
In a plasma atmosphere, the Si ₃ N ₄ film 41 other than on the source/drain region including the gate portion is removed, and then
When the Si substrate 20 is removed to a desired depth, for example, about 3000 Å to 4000 Å, and the photosensitive resin film 42 is removed in an O ₂ plasma atmosphere, the structure shown in FIG. 5B is obtained. Alternatively, using the photosensitive resin film 42 as a mask, it is possible to
After removing the Si ₃ N ₄ film 41 and removing the photosensitive resin film 42, the Si substrate 20 is removed using the Si ₃ N ₄ film 41 as a mask.
A portion of the film may be etched with a hydrofluoric acid (hereinafter referred to as HF) based etchant.

Next, the Si substrate 20 is heated in an oxidizing atmosphere.
By performing selective oxidation to a depth of about 6000 Å to 8000 Å, it is possible to form a SiO ₂ film 30 that is flush with the surface of the Si substrate 20 under the Si ₃ N ₄ film 41, as shown in FIG. 5c.

Next, a photosensitive resin film 44 is applied, and only the photosensitive resin film 44 on the gate portion is left by a photoengraving method, and the other photosensitive resin films are removed.
Then, using the SiO ₂ film 30 as a mask, the Si ₃ N ₄ film 41 on the source/drain regions is removed in a CF ₄ plasma atmosphere (FIG. 5d). Then, the photosensitive resin film 44
is removed in an O ₂ plasma atmosphere or with hot sulfuric acid, and using the Si ₃ N ₄ film 41 and the SiO ₂ film 30 as masks, a P film having a conductivity type different from this is applied to the Si substrate 20.
source region 22 by diffusing type or N type impurities.
and drain region 23 was formed (diffusion depth was
(approximately 5000Å), then heated in an oxygen atmosphere.
Selective oxidation of about 1000 Å to 2000 Å forms a SiO ₂ film 47
can be formed on the source region 22 and drain region 23 (FIG. 5e).

Next, the Si ₃ N ₄ film 41 is removed by a weight etching method using phosphoric acid or a CF ₄ plasma method, and the Si substrate 20 is etched, for example, deeply into the Si substrate 20 by a CF ₄ plasma method using the SiO ₂ film 47 as a mask to form a gate portion. A recess 48 with a diameter of about 6000 Å is formed (fifth
Figure f), the impurities on the Si substrate surface on the inner surface of the recess in the source/drain region are outwardly diffused by heating at high temperature in vacuum or inert gas, and the diffusion depth is increased to 500 Å to 2000 Å by thermal oxidation. A gate SiO ₂ film 11 of about 100 mL is formed in the recess 48 (FIG. 5g). That is, through this step, the impurities on the inner surface of the recess 48 are reduced by outward diffusion, and the low concentration source/drain regions 24 and 25 can be formed.

Next, a SiO ₂ film 47 is formed in the gate SiO ₂ film 21.
A having a thickness equivalent to the depth excluding the thickness of
If the film 50 is deposited by a sputtering method, a resistance heating method, or an electron beam method, the recesses 48
The A gate layer 26 is also buried therein as shown in FIG. 2h. Furthermore, if the photosensitive resin film 52 is applied to a thickness of about 2 μm, a photosensitive resin film of about 2.6 μm will be formed on the A gate layer 26, and the photosensitive resin film 52 can have a substantially flat surface (5th Figure h),
The thickness of the photosensitive resin film 52 on the A film 50 is approximately 2 μm.
The A gate layer 2 can be completely removed by O ₂ plasma method, or exposed and developed by photoetching to a thickness of about 2 μm, as shown in FIG. 5i.
It is possible to leave the photosensitive resin film 52 of about 0.6 μm only on the photosensitive resin film 6.

After that, the A film 50 is removed with a phosphoric acid solution,
Furthermore, after removing the SiO ₂ film 47 with an HF solution,
If the photosensitive resin film 52 on the A-gate layer 26 is removed by O ₂ plasma method, the structure shown in FIG. 5j is obtained. Next, a SiO ₂ film 31 with a thickness of about 8000 Å is formed by the CVD method (Fig. 5k), and the SiO ₂ film 31 in the portions corresponding to the electrode windows and electrode wiring of the source region 22, drain region 23, and A gate layer 26 is Through holes 54, 55, and 56 are bored by photoetching (FIG. 5l).

Thereafter, an A film 57 having a thickness similar to that of the SiO ₂ film 31 is deposited by a sputtering method, a resistance heating method, or an electron beam method, and a photosensitive resin film 58 is further applied to a thickness of about 2 μm.
A photosensitive resin film 58 is left only on each electrode wiring by photolithography or O ₂ plasma method, similar to the method used to form the gate layer 26 (FIG. 5m).
Then, the exposed A film 57 is removed, the photosensitive resin film 58 is removed, the source electrode 27, the drain electrode 28, and the gate electrode 29 are formed, and the final structure of the A gate MOS-Tr shown in FIG. 5n is obtained. It will be done.

According to the method shown in FIG. 5, the field portion and the gate portion are buried in the Si substrate, and the surface of the previous Si substrate where the source and drain regions are formed and the surface of the field portion and the gate portion are buried. It is possible to obtain a MOS-Tr having the same plane. Therefore, disconnection of the photosensitive resin film and blurring of the mask image during electrode formation are eliminated, high resolution can be obtained, and since disconnection of the electrode wiring is eliminated, a MOS-Tr with a high-density structure can be obtained. I can do it. And in Figure 5, A gate
In a MOS-Tr, since the gate portion can be formed by a self-alignment method, mask alignment is unnecessary and high density is possible.

Although the above method is an example of creating an A-gate MOS-Tr, it is also possible to create a silicon gate MOS-Tr by forming a silicon gate instead of the A-gate. In this case, after Figure 5g,
A polycrystalline silicon film is formed by CVD method, and A
A silicon gate can be embedded instead of gate 26. After this, using the SiO ₂ film 47 as a mask, the source and
desired N regardless of the conductivity type of the drain impurity.
Conductivity can be imparted by diffusing type and P type impurities.

Silicon gate MOS created using the above method
-Tr allows selective diffusion of impurities into the silicon gate. For example, P channel silicon gate
In a MOS-Tr, penetration of the impurity into the Si substrate can be reduced more by diffusing N-type impurities than by diffusing P-type impurities into the silicon gate. In addition, since the work function difference Φ _MS of a silicon gate with P-type impurities diffused is larger than that of a silicon gate with N-type impurities diffused, for example, a depletion type N-channel silicon gate MOS-
By diffusing P-type impurities into the silicon gate in the transistor, V _r can be increased, thereby making it possible to form an enhancement type n-channel silicon gate MOS-Tr.

As described above, in the MOS transistor according to the present invention, by making the impurity concentration of the source/drain region located below the gate part lower than the impurity concentration of other source/drain regions, depletion of the part near the channel part is reduced. Since the layer extends not only toward the substrate but also into the source/drain regions, the punch-through breakdown voltage can be increased and the channel length can be shortened. Therefore, it was possible to increase the mutual conductance gm and obtain a MOS-Tr with good switching characteristics and frequency characteristics.

[Brief explanation of the drawing]

Figure 1 is a structural cross-sectional view of a conventional buried gate MOS-Tr, and Figure 2 is an embodiment of the present invention.
Structure cross-sectional diagram of MOS-Tr, Figures 3 and 4 are as shown in Figure 2.
FIG. 5 is a diagram showing the impurity concentration distribution of the source/drain region in the Si substrate of the MOS-Tr shown in FIG. 20...Si substrate, 21...gate SiO ₂ film, 2
2, 23...source/drain region, 24, 25
...Low concentration source/drain region, 26... Gate electrode, 27, 28, 29... Gate electrode, 30
...Field SiO ₂ film, 48 ... recess.

Claims (1)

[Scope of Claims] 1. A gate region buried in the main surface of one conductivity type semiconductor substrate via a gate insulating layer, and the other gate region formed deeper than the lower surface of the gate insulating film in the substrate on both sides of the gate region. conductive type source/drain regions, and in the source/drain regions, a region located directly under the gate insulating layer has a lower impurity concentration than other regions.
MOS type semiconductor device. 2. The MOS type semiconductor device according to claim 1, wherein the surface of the gate electrode region and the surface of the source/drain region form the same plane. 3. The MOS semiconductor device according to claim 1, wherein the gate electrode is an A electrode.