JPS62177974A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62177974A JPS62177974A JP1809686A JP1809686A JPS62177974A JP S62177974 A JPS62177974 A JP S62177974A JP 1809686 A JP1809686 A JP 1809686A JP 1809686 A JP1809686 A JP 1809686A JP S62177974 A JPS62177974 A JP S62177974A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- metal
- gate electrode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 20
- 239000003870 refractory metal Substances 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電極や配線の低抵抗化を図った半導体装置の製
造方法に関し、特に半導体素子の製造自由度を大幅に拡
大した製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device in which the resistance of electrodes and wiring is reduced, and particularly to a method of manufacturing a semiconductor device that greatly expands the degree of freedom in manufacturing semiconductor elements.
近年、Ｇ ａ Ａ ｓを中心とする化合物半導体を用い
る集積回路の開発が活発化しているが、その基本となる
シジソトキ接合型電解効果トランジスタ（ＭＥＳＦＥＴ
）のゲート電極にＷ、 Ｔ ａ 、 Ｍ 。In recent years, the development of integrated circuits using compound semiconductors centered on GaAs has become active, but the basic technology is the syjisotoki junction field-effect transistor (MESFET).
) on the gate electrode of W, Ta, M.
等の所謂リフラクトリメタル又はそのシリサイドが用い
られている。これは、後工程におけるゲート電極をマス
クとして高濃度のイオン注入（例えばＧａＡｓではＳｔ
、Ｓ、Ｓｎ等）や８００℃以上での高温条件でのアニー
ル（熱処理）に対してもゲート電極の信転性を確保する
ためである。また、この種の金属は素子の製造工程をｍ
単なものにできるとともに特性の均一化を保持すること
が容昌であるという理由もある。So-called refractorimetals such as these or their silicides are used. This is done by high-concentration ion implantation using the gate electrode as a mask (for example, St
, S, Sn, etc.) and annealing (heat treatment) at a high temperature of 800° C. or higher to ensure reliability of the gate electrode. In addition, this type of metal reduces the manufacturing process of elements by m
Another reason is that it is advantageous to make it simple and maintain uniformity of characteristics.
」１述した従来の半導体装置では、Ｇ ａ Ａ ｓ等の
化合物半導体材料自身が有する高速性を一１分に引出す
ためには、ゲート電極の材料として前記したようなリフ
ラクトリメタルのみでは抵抗が大き過ぎ、ゲート抵抗や
配線抵抗が大きくなっ゛ζ高速性が失われるごとになる
。このため、低抵抗金属としてアルミニウムや金等の低
抵抗金属が考えられているが、これらを単にリフラクト
リメタルの−１−に重ねて形成するのみでは、後二「稈
における高温熱処理に刑応できず、これら低抵抗金属が
拡散したり合金化反応を起こして良好なショットキ接合
を維持することが困難になる。In the conventional semiconductor device mentioned above, in order to bring out the high speed of the compound semiconductor material itself such as GaAs in 11 minutes, it is difficult to use only the refractory metal as the material for the gate electrode. If it is too large, the gate resistance and wiring resistance will increase and high speed performance will be lost. For this reason, low-resistance metals such as aluminum and gold are considered as low-resistance metals, but simply forming them on top of the refractory metal will result in a high temperature heat treatment in the culm. Otherwise, these low-resistance metals will diffuse or cause an alloying reaction, making it difficult to maintain a good Schottky junction.
これに対処するためには、熱処理が完了した後にリフラ
クトリメタルートに低抵抗金属を選択的に形成すればよ
く、例えばフォトレジスト等を用いたパターン形成方法
が考えられる。しかしながら、近年における電極や配線
の微細化によってリフラクトリメタル以外の領域にのみ
フォトレジストを高精度にマスク形成することは極めて
困デ１ｆであり、（☆置ずれを１Ｆシて低抵抗化の実現
が不ｉｆｆ ｆｉヒとされたり、或いは電極相１１−を
短絡する等率ｒのイ、１軸↑１１を低下さ一ロるおそれ
がある。In order to deal with this, a low resistance metal may be selectively formed on the refractory metal route after the heat treatment is completed; for example, a pattern forming method using photoresist or the like may be considered. However, due to the miniaturization of electrodes and wiring in recent years, it is extremely difficult to form a photoresist mask with high precision only in areas other than refractory metal. There is a risk that the electrode phase 11- may be short-circuited, or the constant ratio r may be lowered by one axis ↑11.
本発明の半導体装置の製造方法は、熱処理等の所定の］
１″程の後においてリフラクトリメタル等の電極や配線
十に高精度に低抵抗金属を形成して電極や配線の低抵抗
化を図り、半導体装７ｙの晶速化や高信頼性を図るとと
もに素子−の製造の自由度を向上するものである。The method for manufacturing a semiconductor device of the present invention includes predetermined steps such as heat treatment.
After about 1 inch, a low resistance metal such as refractory metal is formed on the electrodes and wiring with high precision to lower the resistance of the electrodes and wiring, and to increase the crystal speed and reliability of the semiconductor device 7y. This improves the degree of freedom in manufacturing the device.
本発明の半導体装置の製造方法は〜電極や配線を形成し
た後に、これを覆うように軟化可能な被膜を形成しかつ
これを低温熱処理して平坦化した後、これをエツチング
ｔ７て電極や配線の−１−面を露呈させ、この十に低抵
抗金属を被着しかつごれをパターニングする工程を含む
ものである。The method for manufacturing a semiconductor device of the present invention is to form a softenable film to cover the electrodes and wiring, flatten it by low-temperature heat treatment, and then etch it to form the electrode and wiring. The method includes the steps of exposing the -1- side of the substrate, depositing a low-resistance metal on the surface, and patterning the dirt.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図乃至第８図は本発明をＧ ａ Ａ ｓ Ｍ Ｅ
Ｓ ＦＥＴに適用した実施例を製造工程順に示す断面図
である。FIGS. 1 to 8 illustrate the present invention.
FIG. 3 is a cross-sectional view showing an example applied to an S FET in the order of manufacturing steps.
先ず、第１図のように、ＧａＡｓ半絶縁性基板１に選択
イオン注入法により所定領域にＳｉ”等のＮ型不純物を
導入してＮ型能動層２を形成する。First, as shown in FIG. 1, an N-type active layer 2 is formed by introducing N-type impurities such as Si'' into a predetermined region of a GaAs semi-insulating substrate 1 by selective ion implantation.
その−Ｆで、基板１上にＷ Ｓ ｉ ｘ （Ｘ ＝
Ｏ〜２）の所謂高融点リフラクトリメタルをスパッタ法
又番Ｊ゛化学蒸着法により被着し、図外のフォトレジス
トをマスクとしたフレオン系ガス（ＣＦ４ 、ＳＦ、。At -F, W Si x (X =
A so-called high melting point refractory metal (O~2) was deposited by sputtering or chemical vapor deposition, and a Freon gas (CF4, SF, etc.) was applied using a photoresist (not shown) as a mask.
Ｎ Ｆ ３等）による反応性イオンエツチング（ＲＩＥ
）法でパターニングしてショットキ接合のゲート電極３
を形成する。Reactive ion etching (RIE) using NF3, etc.)
) method to form a Schottky junction gate electrode 3
form.
次いで、第２図のようにこのゲート電極３と、新たにパ
ターン形成したフォトレジスト４をマスクとしてＳｉ゛
をイオン注入法により基板１に選択的かつ自己整合的に
導入し、ソース・ドレイン相当領域に所定濃度、所定深
さの高濃度Ｎ型領域５．５を形成する。その後、イオン
注入層をアルシン（Ａｓ Ｈｓ ）中キャンプレスアニ
ール法により８００〜９００℃の範囲で所定時間熱処理
し、活性化させる。Next, as shown in FIG. 2, using the gate electrode 3 and the newly patterned photoresist 4 as masks, Si is selectively and self-alignedly introduced into the substrate 1 by ion implantation to form regions corresponding to the source and drain. A heavily doped N-type region 5.5 having a predetermined concentration and a predetermined depth is formed in the area. Thereafter, the ion-implanted layer is activated by heat treatment in the range of 800 to 900° C. for a predetermined time by campless annealing in arsine (As Hs).
続いて、第３図のようにシリコン酸化膜、シリコン窒化
膜又はポリイミド等の絶縁１摸６を全面に被着した後、
第４図のようにフォトレジスト７を厚く塗布形成する。Subsequently, as shown in FIG. 3, an insulating layer 16 such as a silicon oxide film, silicon nitride film, or polyimide is deposited on the entire surface.
As shown in FIG. 4, photoresist 7 is coated thickly.
そして、これを１５０〜２５０℃の低温で加熱してフォ
トレジス１〜７を軟化処理し、このリフロー又はリフロ
ーと等価な作用によってフォトレジスｌ−７の表面を平
坦化する。Then, this is heated at a low temperature of 150 to 250° C. to soften the photoresists 1 to 7, and the surface of the photoresist 1-7 is flattened by this reflow or an action equivalent to reflow.
次に、ＣＦ ４ガス等のフレオン系ガスに０２を所定流
量添加したＲ Ｉ Ｅ法によって前記フォトレジスト７
をドライエツチングし、第５図のように前記絶縁膜６に
到るまでエツチングを行ってケート電極３の上面を露呈
させる。このとき、他の部分はフォトレジスト７で覆わ
れたままである。この状態を実現するためには、Ｒ■Ｅ
条件を、ゲート電極３はエツチングしないでフォＩ・レ
ジスト７と絶縁膜６とのエツチング速度比が等しく或い
は極めて近い値となるように設定することが肝要である
。例えば前記ＷＳｉ、リフラクトリメタルの場合にはＣ
Ｆ、に０２を０〜５０％、好ましくは１０〜５０％添加
すればよい。他のＳＦ６やＮＦ、ではゲート電極自身の
エツチング速凌が速くゲート電極の１−面がｎ早８され
ると同時に電極のエツチングが進行されてしまう。Next, the photoresist 7 is removed by the RIE method in which a predetermined flow rate of 02 is added to a Freon gas such as CF4 gas.
Dry etching is performed until the insulating film 6 is reached, as shown in FIG. 5, to expose the upper surface of the gate electrode 3. At this time, other parts remain covered with the photoresist 7. In order to achieve this state, R
It is important to set the conditions so that the gate electrode 3 is not etched and the etching rate ratios of the photoresist 7 and the insulating film 6 are equal or very close to each other. For example, in the case of WSi and refractory metal, C
02 may be added to F in an amount of 0 to 50%, preferably 10 to 50%. In other SF6 and NF, the etching speed of the gate electrode itself is fast, and the etching of the electrode progresses at the same time as the first surface of the gate electrode is etched.
しかる上で、エツチングを停正し、不要なフォトレジス
トを洗浄除去した後に、第６図のように低抵抗金属であ
る金（Ａｕ）をＴ ｉ Ｐ ｔ Ａ ＩＩ等の多層金属
膜構成でスパッタ法又は真空蒸着法により全面に被着し
７て低抵抗金属膜８を形成する。そして、フォトレジス
ト９をマスクしてゲート電極３Ｆを覆い、Ａｒイオンに
よるイオンミリング法又は塩素系ＲＩＢ法により選択エ
ツチングし、第７図のようにゲート電極３−１−位置に
のみ低抵抗金属膜８を残存させる。この選択エツチング
では、前記絶縁膜６が下地能動層へのダメージ、汚染防
ｌＬ用ストッパとして機能する。また、このとき多層金
属膜、即ち低抵抗金属膜８はゲート電極３に接触する状
態にエツチングされればよいため、高精度のマスク合わ
せ精度は不要であり、フォトレジスト９の工程の容易化
を図ることができる。After stopping the etching and cleaning and removing unnecessary photoresist, gold (Au), which is a low resistance metal, is sputtered in a multilayer metal film structure such as TiPtA II as shown in Figure 6. A low-resistance metal film 8 is formed by depositing the metal film 7 on the entire surface by a method or a vacuum evaporation method. Then, the photoresist 9 is masked to cover the gate electrode 3F, and selective etching is performed by ion milling using Ar ions or chlorine-based RIB to form a low-resistance metal film only at the gate electrode 3-1 position as shown in FIG. 8 remains. In this selective etching, the insulating film 6 functions as a stopper to prevent damage and contamination to the underlying active layer. In addition, at this time, the multilayer metal film, that is, the low resistance metal film 8 only needs to be etched in a state in which it contacts the gate electrode 3, so there is no need for high mask alignment accuracy, which simplifies the process of forming the photoresist 9. can be achieved.
その後、第８図のよう乙こソース・トレイン領域のオー
ミック電極１０．１０をリフトオフ法を利用して選択形
成しかつ熱処理し２てオー・ミンク化ＵまたＮＩ／Ａｕ
Ｇｅ膜で形成する。また１、二の上に低抵抗金属でソー
ス・ドｌ／−イン電極１１．１１及びこれに繋がる配線
を形成する。また、前記ゲート電極３及び低１１（抗金
属膜８はシリコン酸化膜等の絶縁膜１２で被覆する。Thereafter, as shown in FIG. 8, ohmic electrodes 10 and 10 in the source train region are selectively formed using the lift-off method and heat treated to form ohmic electrodes 10 and 10 in the source train region.
It is formed from a Ge film. Further, on top of 1 and 2, source/domain/-in electrodes 11 and 11 and wiring connected thereto are formed using a low resistance metal. Further, the gate electrode 3 and the lower layer 11 (anti-metal film 8) are covered with an insulating film 12 such as a silicon oxide film.
以上のに程によりＧ ａ Ａ ｓ Ｍ ＥＳ Ｆ Ｅ
Ｔを完成する。Due to the above, G a A s M ES F E
Complete T.
この製造方法によると、ゲート電極３をリフラフｉ・リ
メタルで構成し、これを用いた自己整合法により高濃度
Ｎ型領域５，５を形成した後に、フォＩ・レジスト７を
塗布しかつこれを平Ｉｌ）化し２てエツチングすること
によりデー１−電極のト、面のみを露呈さセることがで
き、この上に低抵抗金属８を一体的に選択形成すること
ができる。このため、高濃度Ｎ型領域５．５の形成工程
まではリフラクトリメタルの有する利点を１゛分に発揮
さ−Ｕて素子を構成できる。また、その後にお心」る低
抵抗金属膜８の選択エツチング時には多少の位置ずれが
生していてもゲート電極３と低抵抗金属膜８との一体化
を実現できるので、フォトレジスト９のマスク合わせに
高精度を必要とすることはなく、ゲート電極の低抵抗化
を容易に実現できる。したかって、素子製造の自由度を
大幅に向］−するとともにＭＥＳＦＦ、Ｔの特性の向−
１−を達成することができる。According to this manufacturing method, the gate electrode 3 is made of riffraff i-remetal, and after high concentration N-type regions 5, 5 are formed by a self-alignment method using this, a photo resist 7 is applied and this is By planarizing and etching, only the top and bottom surfaces of the electrode can be exposed, and the low resistance metal 8 can be integrally and selectively formed thereon. Therefore, up to the step of forming the highly doped N-type region 5.5, it is possible to construct an element that takes advantage of the advantages of refractory metal in one minute. Furthermore, during the subsequent selective etching of the low resistance metal film 8, it is possible to integrate the gate electrode 3 and the low resistance metal film 8 even if there is some misalignment, so that the photoresist 9 can be masked. Additionally, high precision is not required, and low resistance of the gate electrode can be easily achieved. Therefore, the degree of freedom in device manufacturing is greatly improved] and the characteristics of MESFF and T are improved.
1- can be achieved.
なお、前記実施例では軟化可能な膜としてフォトレジス
トを利用しているが、ポリイミドやスピンオングラス等
を利用することも可能である。Although photoresist is used as the softenable film in the above embodiments, it is also possible to use polyimide, spin-on glass, or the like.
ここで、前記実施例は本発明の一例に過ぎず、各工程は
適宜の変更が可能であることは言うまでもない。例えば
、ＭＥＳＦＥＴのゲート電極以外の電極や配線を高融点
金属で構成した場合にも同様に適用できる。Here, it goes without saying that the above-mentioned embodiment is merely an example of the present invention, and each step can be modified as appropriate. For example, the present invention can be similarly applied to a case where electrodes and wiring other than the gate electrode of a MESFET are made of a high melting point metal.
以−Ｌ説明したように本発明は、電極や配線を形成した
後に、これを覆うように軟化可能な被膜を形成しかつこ
れを平坦化するとともにエツチングして電極や配線の上
面を露呈さＩＬｌ、二の−１−に低抵抗金属を被着しか
つこれをパターニングしているので、電極や配線を高融
点金属＋Ａ料で形成しが−っ所定の不純物領域を形成し
た後に、電極や配線上に自己整合的に低抵抗金属を選択
形成することができ、これに上り素子の低抵抗化を図っ
て特性を向」ニするとともに、素子製造の自由度を大幅
に向上することができる。As explained below, in the present invention, after forming electrodes and wiring, a softenable film is formed to cover the electrodes and wiring, and this is flattened and etched to expose the upper surfaces of the electrodes and wiring. Since the low-resistance metal is deposited on the second-1- and patterned, the electrodes and wiring can be formed using the high melting point metal + A material. A low-resistance metal can be selectively formed on the top in a self-aligned manner, thereby making it possible to lower the resistance of the element and improve its characteristics, as well as greatly improving the degree of freedom in manufacturing the element.
第１図乃至第８図は本発明の一実施例を二Ｆ程１１ｎに
示す断面図である。
１・・・ＧａＡｓ半絶縁性基板、２・・・Ｎ型能動層、
３・・・ゲート電極、４・・・フォトレジスト、５・・
・高温度Ｎ型領域、６・・・絶縁膜、７・・・フォトレ
ジスト、８・・・多層金属膜（低抵抗金属膜）、９・・
・フォトレジスト、１０・・・オーミック電極、１１・
・・ソース・Ｆレイン電極、１２・・・絶縁膜。
代理人 弁理士 鈴 木 章 夫′
第１図FIGS. 1 to 8 are cross-sectional views showing one embodiment of the present invention at the 2F level 11n. 1... GaAs semi-insulating substrate, 2... N-type active layer,
3... Gate electrode, 4... Photoresist, 5...
・High temperature N-type region, 6... Insulating film, 7... Photoresist, 8... Multilayer metal film (low resistance metal film), 9...
・Photoresist, 10... Ohmic electrode, 11.
... Source/F rain electrode, 12... Insulating film. Agent Patent Attorney Akio Suzuki Figure 1
Claims (3)
した後に、これを覆うように軟化可能な被膜を形成する
工程と、この被膜を低温熱処理して軟化・平坦化した後
、エッチング処理して前記電極や配線の上面を露呈させ
る工程と、この上に低抵抗金属を被着しかつこれをパタ
ーニングして前記電極や配線上に前記低抵抗金属を残す
工程を含むことを特徴とする半導体装置の製造方法。(1) After forming electrodes and wiring using high-melting point metal etc. on a semiconductor substrate, a process of forming a softenable film to cover them, and after softening and flattening this film by low-temperature heat treatment, etching. The method is characterized by comprising a step of processing to expose the upper surface of the electrode or wiring, and a step of depositing a low-resistance metal thereon and patterning it to leave the low-resistance metal on the electrode or wiring. A method for manufacturing a semiconductor device.
で形成し、これを利用した自己整合法によりソース・ド
レイン領域を形成し、しかる後に前記軟化可能な被膜の
形成、その平坦化、エッチング等を行ってなる特許請求
の範囲第１項記載の半導体装置の製造方法。(2) Form the gate electrode of the field effect transistor with a high-melting point metal, form the source/drain region by a self-alignment method using this, and then form the softenable film, planarize it, and perform etching. A method for manufacturing a semiconductor device according to claim 1, wherein the method is performed by:
０％の比率でＯ＿２を添加したガスを用いた反応性イオ
ンエッチング法で行ってなる特許請求の範囲第１項記載
の半導体装置の製造方法。(3) Etching the softenable film to CF_4 from 0 to 5
2. The method of manufacturing a semiconductor device according to claim 1, which is carried out by a reactive ion etching method using a gas to which O_2 is added at a ratio of 0%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61018096A JPH0821594B2 (en) | 1986-01-31 | 1986-01-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61018096A JPH0821594B2 (en) | 1986-01-31 | 1986-01-31 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62177974A true JPS62177974A (en) | 1987-08-04 |
| JPH0821594B2 JPH0821594B2 (en) | 1996-03-04 |
Family
ID=11962096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61018096A Expired - Lifetime JPH0821594B2 (en) | 1986-01-31 | 1986-01-31 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821594B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02138750A (en) * | 1988-08-24 | 1990-05-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4953780A (en) * | 1972-09-28 | 1974-05-24 | ||
| JPS5012983A (en) * | 1973-05-28 | 1975-02-10 | ||
| JPS60165764A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Manufacture of compound semiconductor device |
| JPS60225477A (en) * | 1984-04-23 | 1985-11-09 | Nec Corp | Formation of electrode |
-
1986
- 1986-01-31 JP JP61018096A patent/JPH0821594B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4953780A (en) * | 1972-09-28 | 1974-05-24 | ||
| JPS5012983A (en) * | 1973-05-28 | 1975-02-10 | ||
| JPS60165764A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Manufacture of compound semiconductor device |
| JPS60225477A (en) * | 1984-04-23 | 1985-11-09 | Nec Corp | Formation of electrode |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02138750A (en) * | 1988-08-24 | 1990-05-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0821594B2 (en) | 1996-03-04 |
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