JP2003124234A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can prevent the surface of a GaAs wafer from being damaged due to organic chemicals and plasma and has a small number of steps. SOLUTION: A step of forming a gate electrode and a step of forming a drain electrode and a source electrode comprise a step of forming a first resist pattern having a first opening at a location where the gate electrode or the drain electrode and the source electrode are formed on an inorganic-based insulating layer; a step of etching the inorganic-based insulating layer exposed from the first opening down to a predetermined film thickness by dry-etching; a step of removing a first resist pattern; a step of forming a second resist pattern having a second opening wider than the first opening at the same location as the location of the first opening of the first resist pattern by image reverse patterning; and a step of etching the inorganic-based insulating layer of a predetermined film thickness exposed from the first opening by wet-etching until the layer is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a Ga of an IC built-in Hall sensor chip.
The present invention relates to a method for manufacturing a semiconductor device for forming an As field effect transistor.

[0002]

2. Description of the Related Art In the GaAs semiconductor process, Ga
A channel pattern is completed by an annealing process after forming a resist pattern on the As wafer, forming an alignment mark, and performing an ion implantation process. Next, a source electrode and a drain electrode which are joined by ohmic contact and a gate electrode which is joined by Schottky junction are formed on the channel layer.

In forming a conventional electrode, titanium tungsten (Ti / W) is deposited as a gate electrode by a sputtering apparatus. After patterning the resist, an electrode is formed by a reactive ion etching (RIE) process and the resist is peeled off to complete the gate electrode. After the image reverse patterning of the ohmic electrode, the metal forming the ohmic electrode is deposited by vapor deposition, and the excess metal is removed by lift-off to complete the ohmic electrode.

7 and 8 are flow charts showing the manufacturing process of a conventional GaAs field effect transistor (GaAs MESFET). The GaAs MESFET manufacturing process includes a drain region, a source region and a channel layer forming process (ST100) and a gate electrode forming process (ST11).
0) and the drain electrode and source electrode forming step (ST1
20).

The gate electrode forming step (ST110) includes a gate electrode metal depositing step (ST111), a resist patterning step (ST112), a reactive ion etching step (ST113), and a resist stripping step (ST11).
It consists of 4).

The drain electrode and source electrode forming step (ST120) is performed by an inorganic insulating layer depositing step (ST12).
1) and drain electrode and source electrode window opening step (ST
122), a resist patterning process by image reverse patterning (ST126), a drain metal / source metal deposition process (ST127), and a lift-off process (ST128).

The drain electrode and source electrode window opening process (ST122) is a resist patterning process (ST1).
23) and a step of etching the inorganic insulating layer in the portion where the gate electrode is formed by dry etching (ST12
4) and the resist stripping step (ST125).

The step of forming the drain region, the source region and the channel layer (ST100) is first suitable for forming a high impurity concentration active layer forming the drain region and the source region on the GaAs semiconductor substrate on which the alignment mark is formed. Through a transparent mask, 160 keV, 2.0 × 1
High-dose Si ⁺ ion implantation of 0 ¹³ / cm ² is performed. Next, in order to form a channel layer on the GaAs semiconductor substrate, Si ⁺ is added to 120 keV through an appropriate mask.
Ion implantation is performed at 2.0 × 10 ¹² / cm ² . Then G
The aAs semiconductor substrate is placed in an annealing furnace and heated at 850 ° C. for about 15 minutes in an arsine (AsH ₃ ) atmosphere. Thereby, Si ions are activated and a channel layer, a drain region, and a source region are formed.

The gate electrode forming step (ST110) is performed as follows. FIG. 9 shows a gate electrode forming step (ST
110) is a sectional view of a GaAs semiconductor substrate in each step of (110).

Metal deposition process for gate electrode (ST11
In 1), the gate metal corresponds to the channel layer 100, the drain region 101, the source region 102 in FIG. 9A.
Titanium tungsten (Ti / W) 104 having a film thickness of 3000 angstrom is formed by sputtering on the GaAs semiconductor substrate 103 having the film formed therein. Then, in FIG. 9B, resist patterning is performed with the resist 105 (ST112), and in FIG. 9C, the titanium tungsten (Ti / W) 104 is etched by reactive ion etching (RIE) (ST).
113). After that, by removing the resist (S
T114), and the gate electrode 106 is formed. (Fig. 9
(D)).

The step of forming the drain electrode and the source electrode (ST120) is performed as follows. 10 and 1
1 is a drain electrode and source electrode forming step (ST1
FIG. 20 is a sectional view of the GaAs semiconductor substrate in each step of 20).

The inorganic insulating layer deposition step (ST121)
In FIG. 10A, the channel layer 100, the drain region 101, and the source region 102 shown in FIG. 9D are formed, and 3600 angstroms are formed by plasma CVD on the GaAs semiconductor substrate 103 on which the gate electrode 106 is formed. The SiO ₂ film 107 having the film thickness of is formed as an inorganic insulating layer.

In the drain electrode and source electrode window opening step (ST122), first, in FIG.
A resist 108 is uniformly applied by a spin coater or the like on the SiO ₂ film 107 which is an inorganic insulating layer deposited on the As semiconductor substrate 103. Next, a mask having a portion where the drain electrode and the source electrode are formed to transmit light is brought into close contact with the resist 108 on the SiO ₂ film 107 which is the inorganic insulating layer on the GaAs semiconductor substrate 103, and the resist 108 is removed. Exposure with light of a reactive wavelength,
Then, the exposed portion of the resist is melted by immersing it in a developing solution to form openings 109 and 110 (ST1).
23). Then, the developing solution is washed with the rinse solution.

After that, the developing solution or rinsing solution existing in the resist 108 is removed, and post-baking is performed in order to increase the adhesiveness between the resist 108 and the SiO ₂ film 107 which is the inorganic insulating layer.

Next, in FIG. 10C, SiO ₂ in the openings 109 and 110 of the resist 108 is removed by reactive ion etching (RIE) (ST12).
4). Then, in FIG. 10D, the resist is removed (ST125).

Then, in FIG. 11A, a resist 111 is applied and image reverse patterning is performed to form a resist pattern (ST126). For the drain metal and the source metal, as shown in FIG. 11B, for example, 3600 AuGe / Ni / Au film 112 is used.
A film is formed by vapor deposition to a film thickness of angstrom (ST12
7). After that, by lifting off (ST12
8), the drain electrode 113 and the source electrode 114 are formed. (FIG.11 (c)).

[0017]

However, in the above-mentioned conventional method for manufacturing a semiconductor device, the GaAs is removed by the step of stripping the resist with an organic solvent at the end of each step.
The wafer surface was damaged. Further, when the lift-off is involved, there is a risk that resist residue may occur due to damage to the resist during vapor deposition. Therefore, the peeling condition is G
It is necessary to carry out in the direction of promoting damage to the aAs wafer. The condition is that the GaAs surface is etched by several hundred angstroms, and the channel layer itself is lost. In addition, since the resist residue that cannot be completely peeled off must be removed by dry etching, plasma damage to the channel layer occurs. Of course, plasma damage occurs on the GaAs surface even in the reactive ion etching (RIE) process. Due to the damage, there has been a problem that the transistor characteristics of the completed semiconductor device are not stable, that is, they are dispersed on the wafer.

A method of manufacturing a semiconductor device which solves the above problems is disclosed in Japanese Patent Laid-Open No. 5-175243. According to this method, a source electrode and a drain electrode are formed on an active layer selectively formed by an ion implantation method on one main surface of a semi-insulating semiconductor substrate, and then a first insulating film such as SiO 2 is formed by a CVD method. _Two films are deposited, and a second insulating film, for example, a SiNx film is laminated on the two films by a plasma CVD method. Next, a photoresist layer is deposited and an opening is formed in the area where the gate electrode is to be formed. An opening is formed by etching the second insulating film by a reactive ion etching (RIE) method using the photoresist layer having the opening as a mask. Next, using the second insulating film as a mask, the first insulating film on the active layer is etched using ammonium fluoride solution through the opening. At this time, the second insulating film is hardly etched. According to this, since the reactive ion etching (RIE) process is performed only on the second insulating film (SiNx) on the first insulating film (SiO ₂ ), ions do not directly hit the active layer. Therefore, the active layer is not damaged.

However, in the above manufacturing method,
As the insulating film (inorganic insulating layer), it is necessary to stack two kinds of insulating films, that is, Si as the first insulating film.
The O ₂ film needs to be deposited by the CVD method, and the SiNx film as the second insulating film needs to be deposited by the plasma CVD method. Two types of devices are required for the step of forming the insulating film, and the number of steps is reduced. There is a problem that it will increase.

In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent the surface of a GaAs wafer from being damaged by organic chemicals and plasma in the GaAs semiconductor process and has a small number of steps. Especially.

[0021]

The method for manufacturing a semiconductor device according to the present invention is configured as follows in order to achieve the above object.

According to a first method of manufacturing a semiconductor device (corresponding to claim 1), a drain region joined to a drain electrode is formed in a GaAs semiconductor substrate by a plurality of ion implantation steps and at least one annealing step. The high impurity concentration active layer forming the source region, the high impurity concentration active layer forming the source region joined to the source electrode, the high impurity concentration active layer forming the drain region, and the high impurity concentration active layer forming the source region are interposed. In a method of manufacturing a semiconductor device having a channel layer bonded to a gate electrode, an inorganic insulating layer is formed on the high impurity concentration active layer forming the drain region, the high impurity concentration active layer forming the source region, and the channel layer. It includes a step of forming a gate electrode of a semiconductor device provided as an interlayer film and a step of forming a drain electrode and a source electrode. The step of forming the gate electrode and the step of forming the drain electrode and the source electrode form a first resist pattern having a first opening on the inorganic insulating layer where the gate electrode or the drain electrode and the source electrode are formed. Forming step, a step of etching the inorganic insulating layer exposed by the first opening by dry etching to a predetermined thickness, a step of removing the first resist pattern, and a step of removing the first resist by image reverse patterning. The first position is the same as the position of the first opening of the pattern.
Forming a second resist pattern having a second opening having an opening width wider than that of the opening, and etching by wet etching until the inorganic insulating layer having a predetermined film thickness exposed by the first opening is removed. Characterized by having a step, a step of forming a metal forming a gate electrode, a drain electrode, and a source electrode, and a step of removing a metal other than the metal forming the gate electrode, the drain electrode, and the source electrode by lift-off. To be

According to the first method of manufacturing a semiconductor device, an inorganic insulating layer is used as an interlayer film on the high impurity concentration active layer forming the drain region, the high impurity concentration active layer forming the source region, and the channel layer. A step of forming an electrode of the semiconductor device provided, a step of forming a first resist pattern having a first opening at a position where a drain electrode and a source electrode or a gate electrode are formed on the inorganic insulating layer; And a step of etching the inorganic insulating layer exposed by the opening by dry etching to a predetermined thickness,
A step of removing the first resist pattern and a second resist pattern having a second opening wider than the first opening at the same position as the position of the first opening of the first resist pattern by image reverse patterning are formed. Forming process,
The steps of etching by wet etching until the inorganic insulating layer having a predetermined film thickness exposed by the first opening is removed, the step of forming a metal film forming the gate electrode, the drain electrode and the source electrode, and the lift-off method. Since it has a step of removing a metal other than the metal forming the gate electrode, the drain electrode, and the source electrode, the channel layer, the drain region, and the source region are not damaged by the organic chemicals and plasma. Further, since the electrodes are formed in a T shape, it is possible to prevent the chemical solution from soaking into the electrodes. As a result, the transistor characteristics of the semiconductor device do not vary due to damage and are stable. Moreover, since there is only one type of inorganic insulating layer, the number of steps for depositing the inorganic insulating layer can be reduced.

The second semiconductor device manufacturing method (corresponding to claim 2) is characterized in that in the above method, the predetermined film thickness is preferably 300 angstroms or more and 700 angstroms or less.

A third semiconductor device manufacturing method (corresponding to claim 3) is characterized in that, in the above method, preferably, the dry etching is reactive ion etching (RIE).

According to the third method for manufacturing a semiconductor device, since dry etching is reactive ion etching (RIE), it is possible to process a fine pattern having excellent anisotropy.

In the fourth method for manufacturing a semiconductor device (corresponding to claim 4), preferably, the etchant for wet etching is buffered hydrofluoric acid (BH).
It is characterized by being F).

According to the fourth method for manufacturing a semiconductor device, buffered hydrofluoric acid (BHF) is used as an etchant for wet etching. Therefore, when a resist is used as a mask, it is possible to suppress the penetration of the interface between the resist and SiO _2. Therefore, good etching can be performed.

A fifth semiconductor device manufacturing method (corresponding to claim 5) is characterized in that, in the above method, preferably, the inorganic insulating layer is a silicon oxide film or a silicon nitride film.

According to the fifth method of manufacturing a semiconductor device, since the inorganic insulating layer is a silicon oxide film or a silicon nitride film, it can be easily formed by thermal CVD, plasma CVD, or sputtering. In addition, there is no thermal stability with respect to the substrate, denseness, adhesiveness, crack resistance, and no diffusion of substrate constituent substances into the inorganic insulating layer.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

The configurations, shapes, sizes, and arrangement relationships described in the embodiments are merely shown to the extent that the present invention can be understood and put into practice, and numerical values and compositions (materials) of each configuration Is merely an example. Therefore, the present invention is not limited to the embodiments described below, and can be modified into various forms without departing from the scope of the technical idea shown in the claims.

1 and 2 are flowcharts showing steps of manufacturing a GaAs field effect transistor (GaAs MESFET) by the method of manufacturing a semiconductor device according to the embodiment of the present invention. The manufacturing process of the GaAs MESFET includes a drain region, source region and channel layer forming process (ST10), a gate electrode forming process (ST20) and a drain electrode and source electrode forming process (ST30).

The gate electrode forming step (ST20) includes the inorganic insulating layer depositing step (ST21), the first resist patterning step (ST22) and the inorganic material exposed by the first opening in the portion where the gate electrode is formed by dry etching. Step of etching the system insulating layer to a predetermined thickness (ST2
3) and the first resist stripping step (ST24) and the image reverse patterning, the second opening having a wider opening than the first opening is formed at the same position as the position of the first opening of the first resist pattern. Second resist patterning step (ST25), ashing step (ST26), and etching step (ST27) for removing the inorganic insulating layer of a predetermined thickness exposed by the first opening by wet etching and gate electrode Metal deposition process (S
T28) and the lift-off process (ST29).

In the drain electrode and source electrode forming step (ST30), the first resist patterning step (S
T31) and a step of etching the inorganic insulating layer exposed by the first opening in the portion where the drain electrode and the source electrode are formed to a predetermined thickness by dry etching (S)
T32), the first resist stripping step (ST33), and image reverse patterning to form a second opening having a wider opening than the first opening at the same location as the first opening of the first resist pattern. 2 resist patterning step (ST34), ashing step (ST35), and step (ST36) of etching the remaining inorganic insulating layer of a predetermined film thickness exposed by the first opening by wet etching, drain metal and source It comprises a metal deposition step (ST37) and a lift-off step (ST38).

Drain region, source region and channel
The layer forming step (ST10) is the same as the conventional technique.
First, a GaAs semiconductor substrate with alignment marks formed
High impurity concentration in the drain and source regions of the plate
Hundreds of Angstroms on the surface to form the active layer
Oxide film is formed, and through a suitable mask, 160 ke
V, 2.0 x 10¹³/ Cm²High dose Si⁺Ion injection
Turn on. Next, a channel layer is formed on the GaAs semiconductor substrate.
Through a suitable mask to form Si ⁺1
20 keV, 2.0 x 10¹²/ Cm²Ion implantation with
It After that, SiO₂Deposition of film on GaAs semiconductor substrate
Then, put the GaAs semiconductor substrate in an annealing furnace,
Hydrogen (H₂) Heat at 850 ℃ for about 15 minutes in the atmosphere
Then, cap annealing is performed. Thereby, Si ion
Are activated, channel layer, drain region, source region
Is formed.

The gate electrode forming step (ST20) is performed as follows. 3 and 4 are cross-sectional views of the GaAs semiconductor substrate in each step of the gate electrode forming step (ST20).

In the step of depositing the inorganic insulating layer (ST21), the channel layer 10 and the drain region 1 are shown in FIG. 3 (a).
1. GaAs semiconductor substrate 1 on which source region 12 is formed
3, a SiO ₂ film 14 having a thickness of 3000 Å is formed as an inorganic insulating layer by plasma CVD.

First resist patterning step (ST2
2) is a SiO ₂ film 14 which is an inorganic insulating layer deposited on the GaAs semiconductor substrate 13 in FIG. 3B.
The first resist 15 on top of it by a spin coater or the like,
Apply evenly. Next, the GaAs semiconductor substrate 1 is provided with a mask that allows light to pass through where the gate electrode is formed.
3 is brought into close contact with the resist 15 on the SiO ₂ film 14 which is an inorganic insulating layer, exposed by light having a wavelength with which the resist 15 reacts, and then immersed in a developing solution to dissolve the exposed portion of the resist, The first opening 16 is formed (ST22). Then, the developing solution is washed with the rinse solution.

After that, the developing solution or the rinsing solution existing in the first resist 15 is removed, and post-baking is performed in order to increase the adhesiveness between the first resist 15 and the SiO ₂ film 14 which is the inorganic insulating layer. .

Next, in FIG. 3 (c), the by reactive ion etching (RIE), the first SiO ₂ a predetermined thickness of the opening 16 of the resist 15, for example, 500 Å in the thickness of the SiO ₂ film Etching is performed so as to leave 17 (ST23).

Thereafter, in FIG. 3D, the first resist 15 is peeled off (ST24), and by image reverse patterning in FIG. 4A, the same position as the position of the first opening 16 of the first resist pattern is obtained. A second resist pattern 19 having a second opening 18 having an opening width wider than that of the first opening 16 is formed at this location (ST25).

In the step of forming the second resist pattern 19, first, a positive type resist is applied to the entire surface of the wafer. Next, a first exposure is performed on the first opening 16 forming the gate electrode by ultraviolet rays using a mask in which a region wider than the first opening 16 is shielded. Next, as image reverse processing, baking is performed at 110 ° C., and then the entire surface of the wafer is subjected to second exposure with ultraviolet rays and development is performed to remove the unexposed portion of the resist film during the first exposure. As a result, the second opening having a wide opening width and an undercut shape on the first opening 16 to enable lift-off.
The opening 18 is formed.

Next, in order to remove the development residue, oxygen (O ₂ ) plasma is generated by a plasma ashing device to perform ashing. After that, in FIG. 4B, the remaining SiO ₂ film 17 having a thickness of 500 Å is formed.
Are removed by wet etching with buffered hydrofluoric acid (BHF) (ST27). At that time, the upper portion of the SiO ₂ film exposed by the second opening 18 is also etched.

As described above, the step of etching the inorganic insulating layer exposed by the first opening 16 by dry etching to a predetermined thickness (ST23), and the first opening width on the first opening 16 Since the second opening 18 wider than the first opening 16 is formed, the etching is performed by the wet etching step (ST27) until the inorganic insulating layer having a predetermined film thickness exposed by the first opening 16 is completely removed. The plasma does not damage the channel layer 10. As a result, the transistor characteristics of the semiconductor device will not vary due to damage and will be stable. Moreover, since the inorganic insulating layer is one type of the SiO ₂ film 14, the number of steps for depositing the inorganic insulating layer can be reduced.

Metal deposition process for gate electrodes (ST28)
Then, the gate metal is, for example, as shown in FIG.
Titanium gold titanium (Ti / Au / Ti) 20 is formed into a film having a thickness of 3000 angstrom by a vapor deposition method. After that, the gate electrode 21 is formed by lift-off in FIG. As a result, the gate electrode 21 becomes T-shaped, so that it is possible to prevent the chemical solution from penetrating from the end of the electrode. Also, the flatness is improved.

The step of forming the drain electrode and the source electrode (ST30) is performed as follows. 5 and 6 show
It is sectional drawing of a GaAs semiconductor substrate in each process of a drain electrode and a source electrode formation process (ST30).

First, in FIG. 5A, the first resist 22 is uniformly applied on the SiO ₂ film 14 which is the inorganic insulating layer deposited on the GaAs semiconductor substrate 13 by a spin coater or the like. Next, in FIG. 5B, a mask having a portion for forming a drain electrode and a source electrode that allows light to pass through is provided with a resist 22 on the SiO ₂ film 14 which is an inorganic insulating layer on the GaAs semiconductor substrate 13. The resist 22 is exposed to light having a wavelength with which the resist 22 reacts, and then the exposed portion of the resist is melted by immersing it in a developing solution to form first openings 23 and 24 (ST31). Then, the developing solution is washed with the rinse solution.

After that, the developing solution or the rinsing solution existing in the resist 22 is removed, and post-baking is performed in order to increase the adhesiveness between the resist 22 and the SiO ₂ film 14 which is the inorganic insulating layer.

Next, as shown in FIG. 5C, the SiO ₂ in the first openings 23 and 24 of the resist 22 is etched to a predetermined film thickness, for example, 500 by reactive ion etching (RIE).
Etching is performed so as to leave the SiO ₂ films 25 and 26 having a film thickness of angstrom (ST32).

After that, in FIG. 5D, the first resist is stripped (ST33), and in 6 (a), the same positions as the first openings 23 and 24 of the first resist pattern are formed by image reverse patterning. Second opening 27, 28 having a wider opening than the first opening at the second position
A resist pattern 29 is formed (ST34).

In the step of forming the second resist pattern 29, first, a positive type resist is applied to the entire surface of the wafer. Next, a first exposure is performed on the first openings 23 and 24 forming the ohmic electrodes by ultraviolet rays using a mask in which a region wider than the first openings is shielded. Next, as image reverse processing, baking is performed at 110 ° C., and then the entire surface of the wafer is subjected to second exposure with ultraviolet rays and development is performed to remove the unexposed portion of the resist film during the first exposure. As a result, the second openings 27, 28 having a wide opening width and having an undercut shape so that lift-off is possible are formed on the first opening.

Next, in order to remove the development residue, oxygen (O ₂ ) plasma is generated by a plasma ashing device to perform ashing. Then, in FIG. 6B, the remaining 500 Å thick SiO ₂ films 25 and 26 are removed by wet etching using buffered hydrofluoric acid (BHF) (ST36). At that time, the SiO 2 in the portion exposed by the second openings 27 and 28
_The upper parts of the _two films are also etched.

In this way, the first openings 23, 24
SiO that is an exposed inorganic insulating layer ₂To the specified film thickness
Process by dry etching until
T32) and a first opening wider than the first opening width on the first opening.
After forming the two openings 27, 28, the first opening
Until the exposed inorganic insulating layer with the specified thickness is removed
Step of etching by wet etching (ST3
6) Etching due to plasma drain
It does not damage the source and source regions. It
Causes the transistor characteristics of the semiconductor device due to damage
It will be stable with no variation. In addition, the inorganic insulating layer
Is SiO₂Since it is a type of film,
Therefore, the number of steps can be reduced.

Next, in FIG. 6C, as the drain metal and the source metal, for example, AuGe / Ni is used.
The / Au film 30 is formed to a thickness of 3000 angstrom by vapor deposition (ST37). Then, the metal other than the drain region and the source region is peeled off by the lift-off technique (ST38) to form the drain metal electrode 31 and the source metal electrode 32 (FIG. 6).
(D)). As a result, the gate electrode becomes T-shaped,
It is possible to prevent the chemical solution from penetrating from the end of the electrode. Also, the flatness is improved.

In the present embodiment, the SiO ₂ film is used as the inorganic insulating layer, but SiNx may be used as the inorganic insulating layer. Further, in the present embodiment, the SiO in the first opening of the resist is
_{Although the second} reactive ion etching (RIE) etching was performed so as to leave 500 angstroms with a predetermined film thickness, a predetermined thickness was taken into consideration in consideration of the side etching effect that the pattern spreads and the accuracy of the dry etching. Thickness of 300 angstroms or more 70
A film thickness other than 500 angstroms is possible as long as it is within the range of 0 angstroms or less.

[0057]

As is apparent from the above description, the present invention has the following effects.

In the GaAs semiconductor process, the entire channel layer is prevented from being damaged by plasma and organic chemicals, and by making the electrode T-shaped, the chemical solution can be prevented from penetrating from the end of the electrode. Further, since the damage to the channel layer is small and the bonding state with the electrode is favorable, the transistor characteristics of the completed semiconductor device can be stabilized. Moreover, since one type of inorganic insulating layer is used, the number of steps can be reduced.

[Brief description of drawings]

FIG. 1 shows a GaAs field effect transistor (GaAs MES) manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention.
It is a flowchart which shows the process of manufacturing (FET).

FIG. 2 shows a GaAs field effect transistor (GaAs MES) manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention.
It is a flowchart which shows the process of manufacturing (FET).

FIG. 3 is a sectional view of a GaAs semiconductor substrate in each step of a gate electrode forming step.

FIG. 4 is a sectional view of a GaAs semiconductor substrate in each step of a gate electrode forming step.

FIG. 5 is a sectional view of a GaAs semiconductor substrate in each step of forming a drain electrode and a source electrode.

FIG. 6 is a cross-sectional view of a GaAs semiconductor substrate in each step of forming a drain electrode and a source electrode.

FIG. 7 shows a conventional GaAs field effect transistor (GaA).
It is a flowchart which shows the manufacturing process of sMESFET).

FIG. 8 shows a conventional GaAs field effect transistor (GaA).
It is a flowchart which shows the manufacturing process of sMESFET).

FIG. 9 is GaA in each step of the conventional gate electrode forming step.
s is a cross-sectional view of a semiconductor substrate.

FIG. 10 is a sectional view of a GaAs semiconductor substrate in each step of a conventional drain electrode and source electrode forming step.

FIG. 11 is a sectional view of a GaAs semiconductor substrate in each step of a conventional drain electrode and source electrode forming step.

[Explanation of symbols]

10 channel layer 11 drain region 12 source region 13 GaAs semiconductor substrate 14 SiO ₂ film 15 resist 16 first opening 17 SiO ₂ film 18 second opening ST10 drain region, source region and channel layer forming step ST20 gate electrode forming step ST21 Inorganic insulating layer deposition step ST22 First resist patterning step ST23 Step ST24 of etching the inorganic insulating layer of the portion exposed by the first opening to a predetermined thickness by dry etching ST24 First resist stripping step ST25 Image reverse patterning Second resist patterning step ST26 by ashing ST27 Step ST28 of etching the remaining insulating layer having a predetermined film thickness in the portion exposed by the first opening by wet etching ST28 Gate electrode metal deposition step ST29 -Off ST30 drain electrode and source electrode forming step

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masaya Takahashi             1-10, Shin-Sayama, Sayama City, Saitama Prefecture             Within Da Engineering Co., Ltd. (72) Inventor Keisuke Shiba             1-10, Shin-Sayama, Sayama City, Saitama Prefecture             Within Da Engineering Co., Ltd. F-term (reference) 5F004 AA06 BA04 BA11 BD01 DB03                 5F102 FA00 GB01 GC01 GD01 GJ05                       GS02 GS04 GV07 GV08 HC11                       HC15 HC16 HC19 HC21

Claims (5)

[Claims] 1. A high impurity concentration active layer forming a drain region which is joined to a drain electrode and a source which is joined to a source electrode, which are formed in a GaAs semiconductor substrate by a plurality of ion implantation steps and at least one annealing step. A high impurity concentration active layer forming a region, a high impurity concentration active layer forming the drain region, and a channel layer connected to a gate electrode interposed between the high impurity concentration active layer forming the source region In the method of manufacturing a semiconductor device, a semiconductor including an inorganic insulating layer as an interlayer film on the high impurity concentration active layer forming the drain region, the high impurity concentration active layer forming the source region, and the channel layer. A step of forming the gate electrode of the device, and a step of forming the drain electrode and the source electrode, The step of forming the gate electrode and the step of forming the drain electrode and the source electrode have a first opening at a location where the gate electrode or the drain electrode and the source electrode are formed on the inorganic insulating layer. Forming a first resist pattern, etching the inorganic insulating layer exposed by the first opening by dry etching to a predetermined thickness, and removing the first resist pattern And a step of forming a second resist pattern having a second opening wider than the first opening at the same position as the position of the first opening of the first resist pattern by image reverse patterning, Etching is performed by wet etching until the inorganic insulating layer having the predetermined film thickness exposed by the first opening is removed. And a step of forming a metal film forming the gate electrode, the drain electrode and the source electrode, and a metal other than the metal forming the gate electrode, the drain electrode and the source electrode is removed by lift-off. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the predetermined film thickness is 300 angstroms or more and 700 angstroms or less. 3. The dry etching is reactive ion etching (RIE).
A method for manufacturing a semiconductor device as described above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the etchant for the wet etching is buffered hydrofluoric acid (BHF). 5. The method of manufacturing a semiconductor device according to claim 1, wherein the inorganic insulating layer is a silicon oxide film or a silicon nitride film.