JP2001308319A - Insulated gate compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form MIS structure where interface level density has been reduced by a method suited for mass production in an insulated gate compound semiconductor device. SOLUTION: A metal oxide film 2 with a metal element other than the components of a compound semiconductor 1 as a component is inserted into the interface between an insulation film 3 and the compound semiconductor 1 for composing this insulated gate compound semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate type compound semiconductor device, and more particularly to a means for reducing an interface state density at an insulating film / compound semiconductor interface in order to achieve high performance. The present invention relates to a certain insulated gate compound semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in a Si device such as a silicon semiconductor integrated circuit device, a MISFET (Meta
l-Insulator-Semiconductor
FET), that is, an insulated gate FET is used. However, in an electronic device using a compound semiconductor such as GaAs which constitutes a high-frequency amplifying element or an ultra-high-speed integrated circuit device, there is a problem of an interface state. (M
et al-Semiconductor FET) or H
EMT (high electron mobility transistor) and the like are used.

[0003] This is a MOSFE using a compound semiconductor.
Case where the T or MISFET, is because due to the interface state existing in an insulating film / compound semiconductor interfaces such as mutual conductance g _m is decreased, no satisfactory device characteristics.

Here, a conventional MISFET using a compound semiconductor will be described with reference to FIG. FIG. 5 is a schematic cross-sectional view of a MISFET. After an n-type GaAs channel layer 32 is grown on a semi-insulating GaAs substrate 31 by MOVPE (metal-organic chemical vapor deposition), An SiO ₂ film 33 serving as a gate insulating film is deposited using a plasma CVD method, and then Si ions are implanted using the gate electrode 34 as a mask to form an n ⁺ -type source / drain region 35. A drain electrode 36 is formed. Reference numeral 37 in the drawing denotes an element isolation region formed by oxygen ion implantation.

In such a MISFET, SiO ₂
On the surface of the n-type GaAs channel layer 32 before the formation of the film 33, a natural oxide film having elements constituting GaAs as elements, that is, Ga ₂ O ₃ , As ₂ O ₃ , As ₂ O ₅ or the like is formed. SiO2 due to these natural oxide films
There is a problem that an interface level which affects device characteristics is formed at the ₂ / GaAs interface.

In order to solve such a problem of the interface state, various methods such as obtaining a good insulating film / compound semiconductor interface while making full use of a semiconductor surface treatment and an in-situ MIS structure forming technique have been used. Attempts have been made to reduce interface state density and achieve good MISFET operation.

For example, before depositing a SiO ₂ film, G
The natural oxide film on the aAs surface is removed, and the defect-fr
A surface treatment technique for forming a SiO ₂ film in the state of ee and passivating the same is known.

In addition, the GaAs surface is not exposed to the atmosphere.
The MIS structure forming technique in situ, that is, thermal cleaning in an ultra-high vacuum
Immediately after cleaning the As surface, a SiO ₂ film is continuously formed in the same reaction chamber to form SiO ₂ / Ga.
Reduction of the interface state density at the As interface has also been performed.

Furthermore, an n-type GaAs is formed on a GaAs substrate.
Immediately after growing the channel layer, ie, as-g
It has also been practiced to reduce the interface state density at the SiO ₂ / GaAs interface by continuously forming an SiO ₂ film on the GaAs surface in the row state.

[0010]

However, although good device operation has been experimentally realized by any of the above-mentioned methods, the method is complicated and expensive. There is a problem that it is difficult to apply to actual mass production.

That is, in the actual mass production stage, it is common that each process is performed in a batch system, and the wafer after each process is stored and moved to the next process.
Since a series of processes must be performed for each wafer as a continuous process without exposing it to the atmosphere, there is a problem that conventional batch processing cannot be performed.

Accordingly, an object of the present invention is to form an MIS structure having a reduced interface state density by a method suitable for mass production.

[0013]

Here, means for solving the problems in the present invention will be described with reference to FIG.
FIG. 1 is a schematic cross-sectional view of a compound semiconductor MISFET, and reference numerals 4, 5, 6, 7, and 8 in the figure.
Represents a gate electrode, a channel region, a source / drain region, a source / drain electrode, and an element isolation region, respectively. See FIG. 1 (1) In the present invention, in an insulated gate compound semiconductor device, a metal oxide film 2 having a metal element other than a constituent element of the compound semiconductor 1 as a constituent element is provided at an interface between the insulating film 3 and the compound semiconductor 1. It is characterized by being inserted.

As described above, by inserting the metal oxide film 2 having a metal element other than the constituent elements of the compound semiconductor 1 at the interface between the insulating film 3 and the compound semiconductor 1, the metal oxide film 2 / compound The interface state density at the interface of the semiconductor 1 can be reduced, and thereby good device characteristics can be realized.

(2) According to the present invention, in the above (1), the metal oxide film 2 is made of a metal oxide having a generation energy larger in absolute value than the generation energy of the oxide of the constituent element of the compound semiconductor 1. It is characterized by that.

As described above, by using a metal oxide having a generation energy larger in absolute value than the generation energy of the oxide of the constituent element of the compound semiconductor 1 as the metal oxide film 2, the natural oxide existing on the surface of the compound semiconductor 1 can be obtained. The oxide film can be reduced, whereby the interface state density due to the native oxide film can be reduced.

(3) In the present invention, in the above (2), when the metal oxide is such that x is 0 <x <1, TiO
_{1 + x} .

As described above, by using TiO _{1 + x} (0 <x <1), Ga _2, which is a natural oxide film of GaAs, is formed.
Since the absolute value of the generation energy of the metal oxide is larger than that of O ₃ , As ₂ O ₃ , or As ₂ O ₅ , the natural oxide film can be reliably reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing steps of the first embodiment of the present invention will be described with reference to FIGS. Each drawing is a schematic cross-sectional view in the process of forming the MISFET. First, an n-type GaAs channel having a thickness of, for example, 100 nm and an impurity concentration of, for example, 5 × 10 ¹⁷ cm ⁻³ is formed on a semi-insulating GaAs substrate 11 by MOVPE. After the layer 12 is grown, a photoresist is applied to the entire surface, and is exposed and developed to form a resist pattern 13 having a shape corresponding to the active area. Then, using the resist pattern 13 as a mask, oxygen ions 14 are formed.
At an acceleration energy of 150 keV, for example, 2 × 1
By implanting ions at a dose of 0 ¹² cm ^-2 ,
For example, the element isolation region 15 having a depth of 200 nm or more is formed.

Next, after the resist pattern 13 is removed, a Ti film 16 is deposited on the entire surface by vacuum evaporation. This Ti
In the step of depositing the film 16, the n-type GaAs channel layer 1
The natural oxide film (not shown) such as Ga ₂ O ₃ , As ₂ O ₃ , or As ₂ O ₅ formed on the surface of
, The natural oxide film disappears. Note that the thickness of the Ti film 16 in this case is uniform T
It is sufficient that the thickness is 1 nm or more, which is the minimum film thickness that can form an i-oxide film. For example, 3 nm of Ti is deposited.

Next, referring to FIG. 2C, the entire surface is exposed to oxygen plasma 17 to
The Ti film 16 is made of a Ti-rich Ti oxide film, that is, TiO.
Replace with _{1 + x} film 18. In this case, the TiO _{1 + x} film 18
Is considered to be in a state where Ti ₃ O ₅ and Ti ₂ O ₃ are mainly mixed, and therefore, x is in the range of 0 <x <1.

In this plasma oxidation step, n-type Ga
The surface of the As channel layer 12 is also oxidized to Ga_TwoO_Three, A
s_TwoO_ThreeOr As_TwoO_FiveEtc. self-oxidized film is formed
Even if_ThreeO_FiveOr Ti_TwoO_ThreeGeneration energy
Is the absolute value of Ga_TwoO_Three, As_TwoO_ThreeOr As_Two
O_FiveIs larger than the absolute value of the generation energy of _Two
O_Three, As_TwoO_ThreeOr As_TwoO_FiveIs Ti_ThreeO_Five
Or Ti_TwoO_ThreeIs immediately reduced by
The oxide film does not remain at the interface.

Here, with reference to Table 1, the relationship between the generated energy ΔH [kJ / mol] will be described.

[Table 1]

As is clear from Table 1, the energy of formation of Ti ₃ O ₅ is −2459.4 kJ / mol, and the energy of formation of Ti ₂ O ₃ is −1520.9 kJ / mol.
mol, and Ga ₂ O ₃ (−1089.1 kJ / mo)
l), As ₂ O ₃ (-169 kJ / mol), or
Since the absolute value is larger than the generation energy of As ₂ O ₅ (−924.9 kJ / mol), the natural oxide film is reduced by Ti ₃ O ₅ or Ti ₂ O ₃ . In addition,
TiO ₂ (−944 kJ / mol) is converted to Ga ₂ O ₃ (−
1089.1 kJ / mol), the absolute value of the generated energy is smaller than that of the Ti film 16 in the oxidation step.
It is necessary to set conditions such as temperature and time so that TiO ₂ is not completely oxidized to form TiO ₂ .

Next, an SiO ₂ film 19 having a thickness of, for example, 30 nm is deposited on the entire surface by using a plasma CVD method, and then a thickness of, for example, 300 nm is formed by using a sputtering method.
WSi ₂ film is deposited, and then the resist pattern 2
The WSi ₂ gate electrode 21 is formed by performing dry etching using 0 as a mask. In this case, the thickness of the SiO ₂ film 19 is a value determined by a scaling rule in consideration of a gate length and the like, including the thickness of the TiO _{1 + x} film 18, and is not limited to 30 nm.

Referring to FIG. 3E, thereafter, a resist pattern 22 having an opening having a shape defining a source / drain region is formed, and the resist pattern 22 and the WSi ₂ gate electrode 2 are formed.
1 as a mask, for example, at an acceleration energy of 50 keV, the Si ions 23 are ion implanted at a dose of 5 × 10 ¹² cm ^-2, and then, after removing the resist pattern 22, an N ₂ gas atmosphere, 800 R at 30 ° C for 30 seconds
TA (Rapid Thermal Annealin)
g) to obtain the n ⁺ type source / drain region 2
4 is formed.

Next, as shown in FIG. 3F, dry etching is performed using a newly provided resist pattern (not shown) having an opening corresponding to a region where a source / drain electrode is to be formed as a mask, thereby forming the SiO ₂ film 19 and After removing the exposed portion of the TiO _{1 + x} film 18 to form a contact hole, the entire surface is AuGe having a thickness of, for example, 30 nm using a vacuum deposition method.
A film and an Au film having a thickness of, for example, 300 nm are sequentially deposited, and then the resist pattern is removed to lift off the AuGe film and the Au film deposited on the resist pattern.

Next, in an N ₂ gas atmosphere, for example, 3
A heat treatment for alloying is performed at 50 ° C. for 5 minutes to form an ohmic AuGe / Au structure source / drain electrode 25, thereby completing the basic structure of the MISFET.

As described above, in the first embodiment of the present invention, first, the natural oxide film is reduced in the step of depositing the Ti film, and the energy generated by the natural oxide film is also reduced in the subsequent plasma oxidation step. Since a Ti-rich Ti oxide film having a generation energy of an absolute value is formed, crystal defects caused by a natural oxide film can be significantly reduced, whereby good device characteristics can be obtained. become.

Next, a manufacturing process according to a second embodiment of the present invention will be described with reference to FIG. Referring to FIG. 4A, an n-type GaAs channel layer 12 is formed on the surface of a semi-insulating GaAs substrate 11 in the same manner as in the first embodiment.
Is formed, an element isolation region 15 is formed around the active region formation planned region.

Referring to FIG. 4B, a TiO _{1 + x} film 26 having a thickness of, for example, 4 nm is deposited by evaporating Ti in an oxygen plasma atmosphere. In this case, the composition of the TiO _{1 + x} film 26 is also T
In order to obtain a Ti-rich state in which i ₃ O ₅ and Ti ₂ O ₃ are mainly mixed, that is, so that x is 0 <x <1,
Set the oxygen plasma conditions.

In the deposition step of the Ti-rich TiO _{1 + x} film 26 and the subsequent heat treatment step, the natural oxide film formed on the surface of the n-type GaAs channel layer 12 is reduced by the difference in generated energy. Become.

Referring to FIG. 4C, thereafter, the thickness is, for example, 30 nm over the entire surface by using the plasma CVD method in the same manner as in the first embodiment.
After depositing the SiO ₂ film 19, a WSi ₂ film having a thickness of, for example, 300 nm is deposited using a sputtering method. Although not shown hereafter, the basic structure of the MISFET is completed by forming the WSi ₂ gate electrode, the n ⁺ -type source / drain regions, and the source / drain electrodes.

As described above, in the second embodiment of the present invention, the TiO _{1 + x} film 26 is directly deposited.
Since the absolute value of the formation energy of the i-rich TiO _{1 + x} film 26 is larger than the formation energy of the natural oxide film of GaAs, the natural oxide film can be reduced, thereby greatly reducing the crystal defects caused by the natural oxide film. , It is possible to obtain good device characteristics.

While the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, in each of the above embodiments, Ti is used as the metal for reducing the natural oxide film or the metal element constituting the metal oxide film. However, the present invention is not limited to Ti. Should be a metal element having a larger absolute value of the generation energy than the GaAs oxide.

For example, as apparent from Table 1 above,
Ta ₂ O ₅ (-2046 kJ / mol), Pr ₂ O
₃ (−1809.6 kJ / mol), HfO ₂ (−11
44.7 kJ / mol) and ZrO ₂ (−110
(0.6 kJ / mol) is larger in absolute value of the generation energy than the GaAs oxide, so that Ta, Pr, Hf, or Zr may be used as the metal element. In addition, Al ₂ O ₃ (−1675.7 kJ / mo)
l) is A, although there is no problem in terms of energy generated.
Since the oxidation of 1 does not easily progress to the middle, when applying the first embodiment, it is necessary to consider oxidation conditions.

In the first embodiment described above, when oxidizing the deposited Ti film using oxygen plasma, it is oxidized using oxygen plasma. However, the present invention is not limited to such a plasma oxidation method. Alternatively, another oxidation method may be used. For example, the heat treatment may be performed at a higher temperature of 150 ° C. or higher in an oxygen atmosphere or air. However, if the temperature is too high, the GaAs surface is thermally damaged.

In the first and second embodiments, the heat treatment is not performed immediately after the formation of the TiO _{1 + x} film, but the reduction of the natural oxide film can be achieved by applying thermal energy. Since the heat treatment is performed effectively, the heat treatment may be performed at a temperature of 600 ° C. or less immediately after forming the TiO _{1 + x} film.

In each of the above embodiments, the gate insulating film is formed with the TiO _{1 + X} / SiO ₂ structure, but the gate insulating film may be formed only by the TiO _{1 + X} film. It is.

In each of the above embodiments, G
Although described as an aAs device, it is not limited to GaAs, but various compound semiconductors, particularly, III-V
Group semiconductors, for example, I
When a MISFET is constituted by nP, In ₂
It is sufficient to use a metal element having an absolute value of the generation energy larger than that of O ₃ , and Ti is a suitable metal element for InP.

In each of the above embodiments, n
Although described as a channel MISFET, the invention is also applied to a p-channel MISFET, and is not limited to a MISFET, but is also applied to a MIS diode.

[0042]

According to the present invention, a MIS structure is formed by inserting a metal oxide film, which is more energy stable than the oxide of the compound semiconductor, on the surface of the compound semiconductor, so that batch processing suitable for mass production is possible. By the simple manufacturing method, it is possible to reduce the interface state density caused by the natural oxide film of the compound semiconductor, and thereby it is possible to obtain good device characteristics.
This greatly contributes to the practical use of the insulated gate compound semiconductor device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 5 is a schematic sectional view of a conventional MIS type compound semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 compound semiconductor 2 metal oxide film 3 insulating film 4 gate electrode 5 channel region 6 source / drain region 7 source / drain electrode 8 element isolation region 11 semi-insulating GaAs substrate 12 n-type GaAs channel layer 13 resist pattern 14 oxygen ion 15 element Isolation region 16 Ti film 17 Oxygen plasma 18 TiO _{1 + x} film 19 SiO ₂ film 20 Resist pattern 21 WSi ₂ gate electrode 22 Resist pattern 23 Si ion 24 n ⁺ type source / drain region 25 Source / drain electrode 26 TiO _{1 + x} Film 27 WSi ₂ film 31 semi-insulating GaAs substrate 32 n-type GaAs channel layer 33 SiO ₂ film 34 gate electrode 35 n ⁺ type source / drain region 36 source / drain electrode 37 element isolation region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA28 CA05 CA09 CA17 DA04 DA12 DA43 DA53 5F040 DA00 DA05 DC03 EB17 EC04 EC09 ED01 ED03 EH02 EK00 FA17 FB04 FC05 FC14 FC25

Claims (3)

[Claims] 1. An insulated gate compound semiconductor device wherein a metal oxide film having a metal element other than a constituent element of the compound semiconductor as a component is inserted at an interface between the insulating film and the compound semiconductor. 2. The insulated gate according to claim 1, wherein said metal oxide film is made of a metal oxide having a generation energy whose absolute value is larger than that of an oxide of a constituent element of said compound semiconductor. Type compound semiconductor device. 3. The insulated gate compound semiconductor device according to claim 2, wherein said metal oxide is TiO _{1 + x} when x is 0 <x <1.