KR101199437B1 - Method for forming silicide of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device suitable for minimizing the gate junction leakage current characteristics by forming a cobalt salicide of uniform thickness by uniform cobalt diffusion, the semiconductor device manufacturing method of the present invention for this Forming a device isolation film including a liner nitride film on the substrate; Forming a gate electrode and a source / drain on the semiconductor substrate; Performing line amorphous ion implantation on the entire surface including the gate electrode and the source / drain; Sequentially forming a cobalt film, a titanium film, and a titanium nitride film along surfaces of the gate electrode and the semiconductor substrate; And annealing to form cobalt silicide on the gate electrode and the source / drain regions.

STI, liner nitride film, cobalt / titanium / titanium nitride (Co / Ti / TiN), silicide, salicide

Description

 Method for forming silicide of semiconductor device {METHOD FOR FORMING SILICIDE OF SEMICONDUCTOR DEVICE}

1A to 1C are cross-sectional views illustrating a silicide forming method of a semiconductor device according to the prior art;

2A to 2D are cross-sectional views illustrating a silicide forming method of a semiconductor device according to an embodiment of the present invention;

Figure 3 is a graph applying the embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

21 silicon substrate 22 trench

23: first oxide film 24: nitride film

25: second oxide film 26: gap fill oxide film

27: gate oxide film 28: gate electrode

29: gate spacer 30: source / drain region

31 Co film 32 Ti film

33 TiN film 34 CoSi ₂ film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming silicide of a semiconductor device.

In the semiconductor manufacturing process, in particular, the operation speed of the device is a very important factor in the manufacturing process of the logic device, so the silicide process is applied to reduce the resistance.

The silicide forming process is to deposit a metal and form a metal silicide film by a thermal process. In a typical silicide process, silicide is formed only on an active region composed of silicon and on top of polysilicon, which is a gate forming material, and other insulating materials. Has adopted a Salicide (Self Aligned Silicide) process in which silicide films are not formed. In particular, as the gate line width decreases to 0.18 μm or less, cobalt silicide having excellent resistance and stability is being applied.

1A to 1C are cross-sectional views illustrating a silicide forming method of a semiconductor device according to the prior art.

As shown in FIG. 1A, after forming the device isolation layer 12 on the silicon substrate 11 by the STI device isolation process, the active region and the field region are separated, a well (not shown) formation process is performed.

Subsequently, the gate oxide film 13 is formed in the active region, the gate electrode 14 is deposited, and the gate is patterned by performing a predetermined photo and etching process. After gate patterning, although not shown, a low concentration of impurity ions are implanted to form a lightly doped drain (LDD) region, a spacer 15 is formed on the sidewall of the gate electrode 14, and then a high concentration of ions is implanted. Source / drain regions 16 are formed.

As shown in FIG. 1B, the wafer surface is cleaned with hydrofluoric acid solution (HF) to remove the oxide film remaining on the silicon substrate 11 for subsequent silicide formation, and then the semiconductor substrate 11 and the gate electrode 14 are removed. Along with the profile, the cobalt film 16 (Co) and titanium film 17 (Ti) to be used as the silicide metal film are sequentially deposited.

As shown in FIG. 1C, a first rapid thermal process (RTP) and a salicide process are performed at a temperature of 500 ° C., so that the source / drain region 16 and the gate electrode 14 are formed. After a part of forms a salicide of the cobalt silicide (CoSi ₂ ) component, the cobalt film / titanium film removal process of the part where the salicide 18 reaction has not occurred is performed.

Subsequently, secondary RTP is performed at a temperature of 750 ° C. to form a salicide 18 of cobalt silicide (CoSi ₂ ) component through a final salicide reaction.

However, in the above-described conventional technique, even if the hydrofluoric acid (HF) cleaning is performed for a long time to remove the natural oxide film present on the surface of the silicon substrate 11 before the cobalt film deposition, several natural oxide films must be thermodynamically present. Nonetheless, this natural oxide film prevents the diffusion of the cobalt film.

Thus, the resulting cobalt silicide (CoSi ₂ ) and the interfacial uniformity of the silicon substrate are not uniform, thereby causing a problem of increased leakage current at the junction. In addition, when oxygen is introduced during the high temperature thermal process after the formation of the STI, the silicon of the STI sidewall is oxidized to generate volume expansion, and thus a compressive stress is applied to the channel portion where the transistor is to be formed so that the leakage current There is a problem that increases.

The present invention has been proposed to solve the above problems of the prior art, to provide a method for manufacturing a semiconductor device suitable for minimizing the gate junction leakage current characteristics by forming a cobalt salicide of uniform thickness by cobalt diffusion is uniform. The purpose is.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming an isolation layer including a liner nitride layer on a semiconductor substrate, and forming a gate electrode and a source / drain on the semiconductor substrate Performing linear amorphous ion implantation on the entire surface including the gate electrode and the source / drain, sequentially forming a cobalt film, a titanium film, and a titanium nitride film along surfaces of the gate electrode and the semiconductor substrate, and annealing And forming cobalt silicide on the gate electrode and the source / drain regions.

By applying the above technique, it is possible to form CoSi ₂ salicide through STI liner nitride film deposition and Co / Ti / TiN triple layer deposition, thereby improving the leakage current characteristics of the junction.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2D are cross-sectional views illustrating a silicide forming method of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, after the trench 22 is formed on the silicon substrate 21 to perform the STI isolation process, the surface of the silicon substrate 21 is oxidized to grow the oxide film 23. The liner nitride film 24 is deposited on the oxide film 23. Subsequently, the CVD oxide film 25 is deposited on the liner nitride film 24 by chemical vapor deposition (hereinafter, referred to as 'CVD').

In this case, when the STI liner nitride film 24 process is applied, stress applied to the active region (a region other than the STI is formed) is reduced, and thus the stress inside the silicon substrate 21. As a result, the occurrence of crystal defects is reduced, and as a result, crystal defects are reduced, resulting in a decrease in junction leakage current due to traps such as crystal defects.

As shown in FIG. 2B, the gap fill oxide layer 26 is deposited on the entire surface of the substrate to fill the trench 22, followed by chemical mechanical polishing (CMP) and full surface etching. The gapfill oxide layer 26, the CVD oxide layer 25a, the liner nitride layer 24a, and the oxide layer 23a are planarized and etched to form an isolation layer until the substrate 21 is exposed to form an active region and a field region.

Subsequently, a well (not shown) process is performed to form a gate oxide film 27 and a gate electrode 28 on the active region of the substrate 21, and low concentration ion implantation is performed to form an LDD region (not shown). After forming, the gate spacer 29 is formed on the side of the gate electrode 28.

Next, high concentration source / drain ion implantation is performed to form source / drain regions 30 on both lower substrates of the gate electrode 28.

Subsequently, a source / drain formation process is performed, and a germanium (Ge) line amorphous ion implantation (PAI) is performed on the entire surface of the substrate 21 by an amorphous process, so that the region where the silicide is to be formed is previously formed. Amorphize.

At this time, the PAI process is carried out for the purpose of homogenizing the thickness of the silicide formed by the subsequent deposition of the metal film and rapid heat treatment by amorphizing the silicon on the substrate 21 or the gate electrode 28 before the deposition of the metal film. It is a process to do it.

On the other hand, the ion implanted during the PAI process is implanted with any one selected from N ₂ , As, or Ar as well as Ge used in the embodiment, the ion implantation energy has a range of 0.1KeV ~ 200KeV, Has a range from 1E12 to 1E16.

As shown in FIG. 2C, the surface of the wafer is removed by using a cleaning solution in which HF and H ₂ O are mixed at a ratio of 1:99 to remove residual oxide films, and then the Co film 31 is disposed on the entire surface of the amorphous substrate 21. ), The Ti film 32 and the TiN film 33 are deposited in this order. At this time, by depositing the TiN film 33, Ti atoms of the Ti film 32 diffuse during the subsequent thermal process to pass through the Co film 31 and exist between the silicon substrate 21 and the Co film 31. It reacts with the natural oxide film and converts it into a porous membrane in the form of Co _x Ti _y O _z (x, y and z are natural numbers). Thereafter, the diffusion of Co through the porous membrane is made undisturbed and thus the interface uniformity of the resulting CoSi ₂ salicide and the silicon substrate 21 becomes more uniform than before, thereby reducing leakage current at the junction. .

On the other hand, the Co film 31 is deposited at a thickness of 100 kPa to 150 kPa, the Ti film 32 is 1 kPa to 200 kPa, and the TiN film 33 is 200 kPa to 350 kPa.

As shown in FIG. 2D, after depositing the triple layers 31, 32, and 33 on the silicon substrate 21, the first rapid thermal annealing (RTA) is performed at a temperature of 500 ° C. FIG. After proceeding to form a salicide of the CoSi component in the source / drain region 30 and the gate electrode, a Co removal process for removing the Co film and the TiN film of the portion where the salicide reaction did not occur, and then the temperature of 750 ℃ Proceeds to the second RTA process to form a salicide 34 of CoSi ₂ component through the final salicide reaction.

Figure 3 is a graph showing the cumulative distribution of the junction leakage current for the present invention and the prior art, the x-axis shows the cumulative distribution of the measurement data (51 points in total), y junction leakage current, the unit is A / μm .

First, A (reference) is a state in which a Co film and a Ti film are deposited after the Ge PAI process, and B (Ge_PAI_Ti_TiN) is a state in which a Co film / Ti film / TiN film is deposited after the Ge PAI process. , C (Ge_PAI_Ti_TiN_STI Liner) is a state in which a Co film / Ti film / TiN film is deposited after applying a liner nitride film, Ge PAI, and the like when forming a device isolation film.

As shown in the graph, in terms of junction leakage current distribution, B has a smaller leakage current value than A, and C, which has previously applied an STI liner nitride film, has a lower leakage current value than B, and thus an improved effect is observed. can do.

As described above, the thickness of the cobalt silicide formed in the active region and the gate electrode is maintained to be constant, thereby reducing the resistance of the gate electrode while eliminating the deterioration of device characteristics due to an increase in the junction leakage current, thereby achieving stable device characteristics.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the present invention described above, the silicon substrate is uniformized by implantation of germanium line amorphous ion before cobalt film deposition during cobalt silicide formation, and the natural oxide film is made into a permeable film using a triple layer of cobalt film / titanium film / titanium nitride film. In other words, the diffusion of cobalt is uniform without disturbing to form a uniform CoSi ₂ salicide, so that the leakage current of the source / drain junction can be minimized.

In addition, when forming the STI, a liner nitride film may be deposited, and germanium line amorphous ion implantation may be performed before cobalt film deposition, and a triple film may be applied to further reduce leakage current than when only a triple film is applied.

By improving the leakage current characteristics of the device, the refresh and operation characteristics of the device are also improved.

Claims (9)

Forming an isolation layer including a liner nitride film on the semiconductor substrate; Forming a gate electrode and a source / drain on the semiconductor substrate; Performing line amorphous ion implantation on the entire surface including the gate electrode and the source / drain; Forming a cobalt film along surfaces of the gate electrode and the semiconductor substrate; Forming a titanium film on the cobalt film; Forming a titanium nitride film on the titanium film; Annealing to form Co _x Ti _y O _z (x, y and z are natural numbers) on the semiconductor substrate; And Forming cobalt silicide on the gate electrode and on the source / drain regions; Silicide forming method of a semiconductor device comprising a. The method of claim 1, The linear amorphous ion implantation method of forming a silicide of a semiconductor device injecting ions selected from Ge, N ₂ , As and Ar. The method of claim 1, Said pre-crystallization ion implantation is a silicide formation method of the semiconductor element which carries out ion implantation energy of 0.1 KeV-200 keV. The method of claim 1, The method for forming silicide of a semiconductor device in which the above-mentioned amorphous ion implantation has a dose of 1E12 to 1E16. The method of claim 1, The titanium film is a silicide forming method of a semiconductor device to form a thickness of 1 ~ 200Å. The method of claim 1, The cobalt film has a thickness of 100 kPa to 150 kPa, and the titanium nitride film has a thickness of 200 kPa to 350 kPa. The method of claim 1, The device isolation film including the liner nitride film is a trench formed after the oxide film, a liner nitride film, and a CVD oxide film is formed by sequentially stacking, silicide formation method of a semiconductor device. The method of claim 1, The step of annealing to form Co _x Ti _y O _z (x, y and z is a natural number) on the semiconductor substrate, And reacting with a natural oxide film present between the semiconductor substrate and the cobalt film. The method of claim 1, Wherein Co _x Ti _y O _z (x, y and z is a natural number) is a silicide forming method of a semiconductor device, characterized in that the porous film.

Images