JP2001332547A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device that has an excellent interface characteristics between a silicon substrate and a metal silicate layer. SOLUTION: This semiconductor device where an active element is formed on a silicon substrate 51 has a metal silicate layer 53 that is formed on the silicon substrate 51, and an electrode layer 54 that is formed on the metal silicon substrate 53. In the metal silicon substrate 53, the concentration of the configuration metal is gradually reduced from the interface between the electrode and metal silicate layers 54 and 53 toward the interface between the silicon substrate 51 and the silicate layer 53.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a metal silicate layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art Higher speed and higher integration of LSIs have been promoted by miniaturization of field effect transistors in accordance with the scaling rule. MOS such as gate insulating film and gate
By simultaneously reducing the height and lateral dimensions of each part of the device, it has been possible to maintain normal device characteristics and increase performance.

According to this scaling rule, the thickness of the gate insulating film of the next generation MIS transistor after 2000 must be about 2 nm or less in terms of an oxide film.
However, when the thickness of the silicon oxide film (SiO ₂ film) is 2 nm or less, the direct tunnel current becomes extremely large, so that the leakage current cannot be suppressed and the power consumption increases.

Therefore, it has been attempted to increase the physical film thickness and suppress the leak current by using a material having a dielectric constant higher than that of SiO ₂ and suppressing the effective silicon oxide film thickness to 2 nm or less.

In the field effect transistor, the interface characteristics between the Si substrate and the gate insulating film are particularly important, while suppressing the leakage current. Therefore, the gate insulating film requires an insulating film material having a high dielectric constant and capable of maintaining good interface characteristics with the Si substrate, and a metal silicate (silicate) film has recently been promising. Began to be reported ("Electrical properties of hafnium sili
cate gate dielectrics deposited directly on silico
n "GCWilk and RMWallace APPLIED PHYSICS LETTER
S VOLUME 74, NUMBER 19, p2854-2856, MAY 1999).

[0006] Such a metal silicate film is formed by forming a metal on a Si substrate by a sputtering method or a vapor deposition method and heat-treating it in an oxygen atmosphere, or by a sputtering method using a silicide target. Have been.

However, in these techniques, it is difficult to control the characteristics of the metal silicate film because the quality of the metal silicate film greatly depends on the amount of introduced oxygen, the heat treatment temperature, or the composition ratio of the target. For example, if the heat treatment or the oxygen treatment is insufficient, the metal silicate film becomes metallic, and if it is excessive, the metal silicate film becomes an SiO ₂ -like metal silicate film. In order to obtain a high dielectric constant, it is necessary to satisfy an intermediate process condition between both metallic and SiO ₂ , and it has been difficult to manufacture easily.

[0008] Further, these methods also have a problem that a large amount of metal elements are distributed at the interface between the Si substrate and the metal silicate layer, which serve as trap sites, and the characteristics of the interface between the Si substrate and the metal silicate layer are deteriorated. there were.

[0009]

As described above, in order to satisfy the scaling rule, it is required to use a metal silicate having a higher dielectric constant than SiO ₂ for the gate insulating film. It is difficult to form a silicate layer with good controllability, and a large amount of metal element is easily distributed at the interface between the silicon substrate and the metal silicate layer.
There is a problem that the interface characteristics between the i-substrate and the metal silicate layer deteriorate.

The present invention has been made in order to solve the above-mentioned conventional problems, and provides a semiconductor device capable of obtaining good interface characteristics between a silicon substrate and a metal silicate layer, and a method of manufacturing the same. The purpose is to do.

[0011]

According to the present invention, there is provided a semiconductor device comprising an active element formed on a silicon substrate, wherein the semiconductor device comprises: a metal silicate layer formed on the silicon substrate; An electrode layer formed on a metal silicate layer, wherein the metal silicate layer has a concentration of constituent metal from an interface between the electrode layer and the metal silicate layer to an interface between the silicon substrate and the metal silicate layer. The semiconductor device is characterized in that it is configured to gradually decrease (semiconductor device A).

Further, according to the present invention, there is provided a semiconductor device in which an active element is formed on a silicon substrate, wherein the semiconductor device comprises a metal silicate layer formed on the silicon substrate, and a metal silicate layer formed on the metal silicate layer. Wherein the concentration of the constituent metal contained in the metal silicate layer is not more than the concentration of the metal in the stoichiometric composition of the metal silicate, and the electrode layer and the metal silicate It is characterized in that the concentration of the constituent metal on the interface side between the silicon substrate and the metal silicate layer is lower than the concentration of the constituent metal on the interface side with the layer ( Semiconductor device B).

In the semiconductor device A or B, the metal constituting the metal silicate layer is Zr (zirconium), Hf
(Hafnium) or La (lanthanum). This is for easily forming the metal silicate. La is preferable for improving the dielectric constant, and Zr or Hf is preferable from the viewpoint of process compatibility.

In the semiconductor device A or B, when the metal constituting the metal silicate layer is Zr, Hf or La, the stoichiometric composition of the metal silicate is ZrSiO
₄ , HfSiO ₄ and La ₂ SiO ₅ , the metal silicate layer has a constituent metal concentration of ZrSi 4.
Less than about 17 atomic percent for O ₄ and HfSiO ₄ ,
Preferably, La ₂ SiO ₅ is configured to be 25 atomic percent or less. More preferably, the metal silicate layer is preferably configured so that the concentration of the constituent metal is 7 atomic percent or less. Furthermore, it is preferable that the concentration of the constituent metal at the interface between the silicon substrate and the metal silicate layer is 1 atomic percent or less.

In the semiconductor device A or B, the metal silicate layer may further contain nitrogen in addition to metal, silicon and oxygen for improving a dielectric constant.

In the semiconductor device A or B, it is preferable that the semiconductor device includes a field-effect transistor, and the metal silicate layer is a gate insulating film of the field-effect transistor.

In the semiconductor device A or B, it is preferable that the metal silicate layer has a thickness of 0.5 nm or more and 4 nm or less.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal silicate layer on an interface between the silicon substrate and the metal oxide film by forming a metal oxide film on a silicon substrate; Selectively removing a metal oxide film on the silicate layer to leave the metal silicate layer (manufacturing method A).

In the manufacturing method A, the step of selectively removing the metal oxide film is preferably performed by using a wet etching method or a sputtering method.

In the manufacturing method A, the metal oxide film is preferably a film containing an amorphous phase. This makes it easier to obtain a difference in etching rate between the metal oxide film and the metal silicate layer.

In the manufacturing method A, defects are recovered and S
Preferably, after the step of selectively removing the metal oxide film, a step of heat-treating the metal silicate layer at a temperature of 800 ° C. or less to suppress iO ₂ growth.
The temperature may be 900 ° C. or less for a short time of 5 minutes or less. Further, more desirably, 300 ° C. to 500 ° C.
° C.

In the manufacturing method A, it is preferable to further include a step of irradiating the metal silicate layer with excited oxygen after the step of selectively removing the metal oxide film because defects can be recovered without raising the temperature. .

In the manufacturing method A, when forming the metal oxide film on the silicon substrate, it is preferable to irradiate with excited oxygen because defects can be recovered without increasing the temperature.

Further, in the method of manufacturing a semiconductor device according to the present invention, there is provided a step of forming a silicon oxide film on a silicon substrate; Forming a metal film or a metal silicide film, and diffusing metal atoms in the metal film or the metal silicide film into the silicon oxide film to form a metal silicate layer (more preferably, remaining without being diffused) Simultaneously forming an electrode by using a metal film or a metal silicide film) (manufacturing method B).

In the manufacturing method A or B, a treatment for introducing nitrogen into the metal silicate layer may be included. At that time, it is preferable to use excited nitrogen.

The manufacturing methods A and B are suitable for the manufacturing method for obtaining the semiconductor devices A and B described above.

Further, the method of manufacturing a semiconductor device according to the present invention comprises forming a semiconductor device on a silicon substrate by vapor deposition using a metal oxide target, sputtering, or laser ablation in a nitrogen atmosphere or under irradiation of excited nitrogen. The method includes a step of forming a metal silicate layer containing nitrogen by forming a film (manufacturing method C).

In the method of manufacturing a semiconductor device according to the present invention, a film is formed on a silicon substrate by a CVD method using a gas containing at least a metal and oxygen in a nitrogen atmosphere or under irradiation of excited nitrogen. Forming a metal silicate layer containing nitrogen (Production method D).

In the production method C or D, it is preferable to further include a step of heat-treating the nitrogen-containing metal silicate layer at a temperature of 800 ° C. or lower in an oxygen atmosphere or irradiating with excited oxygen.

Further, in the method of manufacturing a semiconductor device according to the present invention, a film containing a metal, silicon, and nitrogen (MSiN _x film, M is a metal element) formed on a silicon substrate is 800 ° C. or less in an oxygen atmosphere. (A manufacturing method E) by forming a metal silicate layer containing nitrogen by performing a heat treatment at the temperature described above.

Further, the method of manufacturing a semiconductor device according to the present invention is characterized in that a film (MSiN _x film, M is a metal element) containing metal, silicon and nitrogen formed on a silicon substrate is irradiated with excited oxygen, (Process F) for forming a metal silicate layer containing

In the manufacturing method E or F, using a target containing a metal, silicon and nitrogen, the metal, silicon or nitrogen is deposited by a vapor deposition method, a sputtering method or a laser ablation method.
It is preferable to form a film containing silicon and nitrogen.

Further, in the method of manufacturing a semiconductor device according to the present invention, there is provided a step of forming a metal nitride film on a silicon substrate, and heat-treating the metal nitride film in an oxygen atmosphere at a temperature of 800 ° C. or less to reduce nitrogen. Forming a metal silicate layer to be contained (manufacturing method G).

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a metal nitride film on a silicon substrate and a step of irradiating the metal nitride film with excited oxygen to form a metal silicate layer containing nitrogen. (Production method H).

In the manufacturing methods A to H, the constituent metal of the metal silicate layer is preferably Zr, Hf or La.

In the manufacturing methods A to H, it is preferable that the metal silicate layer is a gate insulating film of a field effect transistor.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) When a metal oxide is formed on a Si substrate, a metal silicate (silicate) layer is formed between the Si substrate and the metal oxide. In the present invention, the metal silicate layer is substantially composed of metal silicate. The metal silicate is of the general formula M _x SiO
_4-δ (M: metal element, 0 <x ≦ 1.0, 3 ≦ δ ≦ 4) However, when the metal element is La, La _x S
iO _5-δ (0 <x <2, 4 ≦ δ ≦ 5). The present inventors have found that this metal silicate layer is formed with a stable structure and composition, and that the electrical characteristics at the Si substrate interface are also very good.

FIG. 1 is a sectional view when a ZrO ₂ film 2 is formed on a Si substrate 1 by a laser ablation method.

As shown in FIG. 1, ZrO
_{When the second} film 2 is formed, a Zr silicate layer 3 is formed at the interface. The dielectric constant of the Zr silicate layer 3 was 14, which was higher than the case where the Zr silicate was oxidized to form a Zr silicate film (up to 12). The metal silicate layer preferably has a thickness of 0.5 nm or more and 4 nm or less. More preferably, 1 nm or more 3
nm or less. Further, when the interface characteristics between the Zr silicate layer 3 and the Si substrate 1 were evaluated, it showed very good electric characteristics, and it was found that the use as a gate insulating film of a field effect transistor was very effective.

The present inventors have attempted to etch the upper ZrO ₂ film 2 using an HF solution in order to use the Zr silicate layer 3 as a gate insulating film.

FIG. 2 shows the ZrO ₂ film 2 and the ZrO formed at the interface when this sample was etched using an HF solution.
FIG. 3 is a diagram illustrating an etching rate of a silicate layer 3.

The black circles indicate the case where the ZrO ₂ film 2 was formed at 450 ° C., and the white circles indicate the case where the ZrO ₂ film was formed at 350 ° C. Before the etching time of 150 seconds, the ZrO ₂ film 2 was used.
Is etched, and after 150 seconds, Zr
This is the case where the silicate layer 3 is being etched. Zr
When the film formation temperature of the O ₂ film 2 is 450 ° C., the etching rate of the ZrO ₂ film 2 is 120 pm / sec and the film formation temperature is 3
At 50 ° C., it was 200 pm / sec. The etching rate of the Zr silicate layer 3 is 2 p in each case.
m / sec.

As described above, it was found that the etching rates of the ZrO ₂ film 2 and the Zr silicate layer 3 were different by 50 times or more. It was also found that the etching rate of the Zr silicate layer 3 formed at the interface was rapidly reduced even when the film thickness and the film forming temperature of the ZrO ₂ film 2 were changed.

This indicates that there is a large difference in the etching rate between the ZrO ₂ film 2 and the Zr silicate layer 3 formed at the interface, and it is sufficiently possible to selectively leave the Zr silicate layer by etching. I have. This is considered to be due to a difference in characteristics between a metal oxide and a material containing a Si element called a metal silicate. As a metal, not only Zr but also a metal such as Hf or La, which forms a silicate layer at an interface, such as Hf or La An oxide can be similarly realized by using an appropriate etching technique.

Based on the above experimental results, the present invention forms a metal oxide film on a Si substrate,
A metal silicate layer is formed at the interface between the i-substrate and the metal oxide film, and then the metal oxide film on the metal silicate layer is selectively peeled off by utilizing a difference in etching rate to leave the metal silicate layer. And a method of manufacturing a field-effect transistor using the same as a high dielectric gate insulating film.

Further, since the metal silicate layer is converted into SiO ₂ when subjected to an excessive heat treatment, the remaining metal silicate layer is selectively irradiated with excited oxygen excellent in defect recovery even at a low temperature in order to recover defects of the metal silicate. For this defect recovery, heat treatment at 800 ° C. or less or heat treatment for 5 minutes or less is also effective.

Further, in order to realize a higher dielectric constant, the metal silicate layer is made to contain nitrogen atoms, so that M
_x SiO _4-δ N _z (M: metal element, 0 <x ≦ 1.0, 3
It is also useful to form ≦ δ ≦ 4, 0 ≦ z ≦ 1).
However, when the metal element is La, La _x SiO _5-δ N
_z (0 <x <2, 4 ≦ δ ≦ 5, 0 ≦ z ≦ 1). In these cases, it should be noted that excessive annealing in an oxygen atmosphere is not performed in order to control the formation of SiO ₂ . In order to introduce nitrogen into the silicate film while suppressing the formation of SiO ₂ , the metal silicate film is nitrided in a nitrogen atmosphere or a film containing metal, silicon, and nitrogen (MSiN _x
Film: M is a metal element) irradiated with excited oxygen or M
A technique of oxidizing the SiN _x film at a low temperature is useful.

FIG. 3 is a sectional view of a field-effect transistor formed according to the present invention. Here, n channel MIS
A transistor was created.

As shown in FIG. 3, a p-type silicon substrate 51
An element isolation region 52 is formed therein. On this p-type silicon substrate 51, a gate insulating film 53 made of metal silicate is formed. A detailed method of forming the gate insulating film 53 will be described later.

On the gate insulating film 53, a gate electrode 54 made of polysilicon is formed. Gate electrode 5
A diffusion layer (source / drain region) 55 into which an n-type impurity is introduced is formed in a silicon substrate 51 sandwiching the semiconductor substrate 4. On the side surfaces of the gate electrode 54 and the gate insulating film 53,
A gate side wall (for example, a CVD silicon nitride film) 56 is formed. These form a field effect transistor.

An interlayer insulating film (for example, a CVD silicon oxide film) 57 is formed on the field effect transistor, and the gate electrode 54 and the source / drain regions are formed through contact holes provided in the interlayer insulating film 57. 55
Is connected to an Al wiring 58.

(Embodiment 1-1) Next, a method of manufacturing the MIS transistor shown in FIG. 3 will be described with reference to FIG.

First, as shown in FIG. 4A, a p-type silicon substrate 5 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm.
On 1, a groove for element isolation is formed by reactive ion etching. Subsequently, for example, an element isolation region 52 is formed by embedding an LP-TEOS film.

Next, as shown in FIG. 4B, a laser ablation film forming method is used, for example, to obtain an oxygen partial pressure of 10P.
a, a substrate temperature of 350 ° C. and a film thickness of 30 nm
ZrO ₂ film containing r and oxygen atoms (metal oxide film) 5
9 is formed on the Si substrate 51. By using the laser ablation film formation method, a metal oxide in which each element has sufficient energy and has a small composition deviation can be formed by the action of light excitation at the time of film formation. As will be described in a later step, in the step of selectively peeling the metal oxide film, the higher the etching rate of the metal oxide, the larger the selectivity with the interface layer, and thus the higher the etching rate of the metal oxide film. Also,
It is preferable to form the film under the condition that the film becomes an amorphous film from the viewpoint of selective peeling.

[0056] At the same time when forming the ZrO ₂ film 59, the interface between the Si substrate 51 and the ZrO ₂ film 59 Zr
A silicate layer 53 is formed. At this point, the Zr, O, and Si elements have sufficient energy in the Zr silicate layer 53 and the composition is unlikely to shift. This means that the high-density Zr silicate layer 5 having a desired composition, few defects,
3 is advantageously formed. By using photoexcitation energy, excessive heating of the substrate is not required, and the formation of SiO _{2 in} the Zr silicate layer 53 can be suppressed, which is advantageous for increasing the dielectric constant of the Zr silicate layer 53. In addition, when the ZrO ₂ film 59 is formed on the silicon substrate 51, a metal oxide with few defects is formed by irradiating with the excited oxygen, so that a better metal silicate layer 53 can be formed. .

In this step, the silicon substrate 51 and ZrO ₂
Between the films 59, Z containing stably Si, Zr and oxygen
The r-silicate layer 53 is formed in a thickness of 0.5 to 4 nm.

Next, as shown in FIG.
Wet etching using the diluted HF solution of about 100 seconds. Then, the ZrO ₂ film 59 is etched, leaving only the Zr silicate layer 53 selectively. At this time, since the etching rate sharply decreases in the Zr silicate layer 53,
Even if the etching time is increased by about 30% to 30%, the film thickness of the Zr silicate layer 59 does not largely change, and only the Zr silicate layer 53 which is easy and has good controllability of the film thickness can be selectively left. A good Zr silicate layer can be left even by using a sputtering method at the time of this etching.

Next, as shown in FIG. 4D, the Zr silicate layer 53 left by the etching is irradiated with excited oxygen by an excited oxygen source 60. In this manner, by irradiating with excited oxygen after etching, defects in the film can be further reduced without converting the Zr silicate layer 53 into SiO ₂ .

To reduce the defects, for example, a heat treatment at 800 ° C. or less or a short heat treatment of 5 minutes or less in an oxygen atmosphere may be performed.

Next, as shown in FIG. 3, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and the polysilicon film is patterned to form a gate electrode 54.
Then, for example 450 ° C., at a pressure 1Pa~10 ⁵ Pa, using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas, for example 5nm~200nm of CVD
A gate sidewall 56 made of a silicon nitride film is formed.

Subsequent steps are the same as the steps for manufacturing a normal MIS transistor. That is, for example, acceleration voltage 2
Arsenic ions are implanted at 0 keV and at a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 55. Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 57 is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by sputtering, and the Al film is patterned by reactive ion etching to form an Al wiring 58.

(Embodiment 1-2) Next, another method of manufacturing the MIS transistor shown in FIG. 3 will be described with reference to FIG.

First, as shown in FIG. 5A, a p-type silicon substrate 5 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used.
On 1, a groove for element isolation is formed by reactive ion etching. Subsequently, for example, an element isolation region 52 is formed by embedding an LP-TEOS film.

Next, as shown in FIG. 5B, the SiO ₂ film 62 is formed on the Si substrate 51 by heating, BOX (combustion oxidation), or CVD in the oxygen atmosphere.

Next, as shown in FIG.
by using the r metal target, for example by vapor deposition, SiO ₂
On the film 62, a metal film 63 having a metal element in an amount equal to or more than the solid solution limit in the SiO ₂ film is deposited. A metal silicide film may be deposited instead of the metal film 63. In this case, a target containing at least metal atoms and silicon atoms may be used.

Next, as shown in FIG. 5D, for example,
A step of diffusing the metal element in the metal film 63 into the SiO ₂ film 62 by heating at 500 to 800 ° C. in vacuum is performed to form at least the metal silicate layer 53 on the silicon substrate 51. Here, Zr was used as the metal element. During the metal film 63, because it contains a metal element in an amount of more than the solubility limit of SiO ₂ film, the inhibition of diffusion due to solubility limit, the metal atom with good controllability, the necessary and sufficient SiO ₂ The metal silicate layer 53 having a high dielectric constant can be formed in the film 62. Similar effects can be obtained when a metal silicide film is used instead of a metal film.

Next, as shown in FIG. 3, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and the polysilicon film is patterned to form a gate electrode 54.
Then, for example 450 ° C., at a pressure 1Pa~10 ⁵ Pa, using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas, for example 5nm~200nm of CVD
A gate sidewall 56 made of a silicon nitride film is formed.

Subsequent steps are the same as the steps for manufacturing a normal MIS transistor. That is, for example, acceleration voltage 2
Arsenic ions are implanted at 0 keV and at a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 55. Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 57 is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by sputtering, and the Al film is patterned by reactive ion etching to form an Al wiring 58.

In the above-described example (examples described with reference to FIGS. 4 and 5), after the metal silicate layer 53 is formed, nitriding the metal silicate layer 53 in a nitrogen atmosphere or by irradiation with excited nitrogen is performed as follows. While preventing the metal silicate layer 53 from being converted into SiO ₂ , defects in the film can be complemented and a high dielectric constant can be realized. The metal silicate film 53 containing nitrogen atoms obtained by nitriding is more preferable as a gate insulating film in terms of characteristics.

(Embodiment 1-3) Next, another method of manufacturing the MIS transistor shown in FIG. 3 will be described with reference to FIG.

First, as shown in FIG. 6A, a p-type silicon substrate 5 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm.
On 1, a groove for element isolation is formed by reactive ion etching. Subsequently, for example, an element isolation region 52 is formed by embedding an LP-TEOS film.

Next, as shown in FIG. 6B, the silicon substrate 51 is placed in a nitrogen gas atmosphere at a pressure of 10 Pa to 10 ⁵ Pa, and for example, Zr atoms and silicon nitride are removed by, for example, a laser ablation method. A target made of at least SiN is irradiated with laser light to deposit an insulating film 64 containing at least Zr atoms and nitrogen atoms on the silicon substrate 51. Other than the laser ablation method, an evaporation method or a sputtering method may be used.

Next, as shown in FIG. 6C, for example, by exposing to an atmosphere of 300 ° C. to 800 ° C. containing oxygen atoms, the insulating film 64 containing at least Zr atoms, nitrogen atoms, and Si atoms contains oxygen. A gate insulating film 53 (metal silicate layer containing nitrogen) into which atoms are introduced is formed. In this case, it is also useful to use heat treatment for a short time of not more than 5 minutes or irradiation with excited oxygen from the excited oxygen source 60.

Next, as shown in FIG. 3, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and the polysilicon film is patterned to form a gate electrode 54.
Then, for example 450 ° C., at a pressure 1Pa~10 ⁵ Pa, using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas, for example 5nm~200nm of CVD
A gate sidewall 56 made of a silicon nitride film is formed.

Subsequent steps are the same as the steps of manufacturing a normal MIS transistor. That is, for example, acceleration voltage 2
Arsenic ions are implanted at 0 keV and at a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 55. Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 57 is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by sputtering, and the Al film is patterned by reactive ion etching to form an Al wiring 58.

(Embodiment 1-4) Next, another method of manufacturing the MIS transistor shown in FIG. 3 will be described with reference to FIG.

First, as shown in FIG. 7A, a p-type silicon substrate 5 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used.
On 1, a groove for element isolation is formed by reactive ion etching. Subsequently, for example, an element isolation region 52 is formed by embedding an LP-TEOS film.

Next, as shown in FIG.
By the VD method, an ammonia gas containing nitrogen and an acid gas containing Zr, such as a mixed gas of ZrCl ₄ gas and NH ₃ gas or a mixed gas of Zr (SO ₄ ) ₂ gas and NH ₃ gas in a nitrogen-diluted atmosphere. Are alternately supplied and evacuated at a pressure of 1 to 10 ⁵ Pa and a flow rate of 1 to 1000 sccm, for example, in a temperature range of room temperature to 800 ° C., for example, a zirconium nitride film, or Zr, nitrogen and Si. A film (ZrSiN _x film) 65 is deposited.

Next, as shown in FIG. 7C, the substrate is exposed to an atmosphere containing oxygen atoms at a temperature of, for example, 200 ° C. to 800 ° C., thereby forming a film 65 containing at least Zr, nitrogen and Si. The metal silicate layer 53 containing nitrogen atoms is formed by introducing oxygen atoms into the metal. This heat treatment may be a heat treatment for a short time of 5 minutes or less or a treatment for irradiating with excited oxygen.

Next, as shown in FIG. 3, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and the polysilicon film is patterned to form a gate electrode 54.
Then, for example 450 ° C., at a pressure 1Pa~10 ⁵ Pa, using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas, for example 5nm~200nm of CVD
A gate sidewall 56 made of a silicon nitride film is formed.

The subsequent steps are the same as the steps for manufacturing a normal MIS transistor. That is, for example, acceleration voltage 2
Arsenic ions are implanted at 0 keV and at a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 55. Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 57 is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by sputtering, and the Al film is patterned by reactive ion etching to form an Al wiring 58.

Although several manufacturing methods of the present invention have been described above, it is also possible to form a nitrogen-containing metal silicate layer by the following method.

For example, using a target (metal oxide target) containing metal atoms and oxygen atoms in a nitrogen atmosphere or while irradiating with excited nitrogen, by a vapor deposition method, a sputtering method, a laser ablation method, or in a nitrogen atmosphere or It is also possible to form a metal silicate layer containing nitrogen by depositing an insulating film on a silicon substrate by a CVD method using a gas containing metal atoms and oxygen atoms while irradiating with excited nitrogen. After depositing such an insulating film, the gate insulating film may be formed by exposure to an oxygen gas atmosphere at 800 ° C. or lower. Instead of exposing to an oxygen gas atmosphere, active oxygen atoms (excited oxygen)
May be applied.

The method of the present embodiment described above uses a damascene gate or a replacement gate (re
It is also effective to apply the present invention to a gate insulating film in a transistor process.

For example, in a normal damascene gate transistor process, after a transistor structure is formed using a dummy gate, TEOS is deposited and polished by CMP, and then the dummy gate is peeled off to form a gate insulating film. Since the step coverage of the gate insulating film to be formed is not good, problems such as non-uniformity of the film thickness occur, and variations and deterioration of device characteristics tend to occur.

Using the method of the present embodiment described above, a metal oxide film is deposited on the entire surface including the surface of the Si substrate exposed after the dummy gate has been peeled off, and the metal silicate layer formed at the interface with the Si substrate is gated. When used as an insulating film, the thickness of the metal silicate layer can be made constant without depending on the thickness of the metal oxide film, so that a gate insulating film having a uniform thickness can be obtained.

(Embodiment 2) Next, a sample prepared in the case where a metal oxide film was formed on a Si substrate by a laser ablation method and a metal silicate layer was formed at an interface between the Si substrate and the metal oxide film. The result of the analysis will be described. Specifically, the cross section was observed with a TEM, and the EDX analysis was performed.

FIG. 8 is a TEM photograph of a cross section of a sample in which a ZrO ₂ film (metal oxide film) is formed on a Si substrate. ZrO
_It can be seen that a Zr silicate layer (interfacial silicate layer: interfacial Zr silicate) is formed at the interface between the _two films and the Si substrate.

FIG. 9 shows a state in which the Si
FIG. 9 shows the result of analyzing the composition of the interface silicate layer toward the substrate.

As shown in FIG. 9, the Zr concentration (atomic percent) gradually decreases from 7% from the upper surface of the interface silicate layer toward the Si substrate (from the circled number 1 to the circled number 6). At the interface between the interface silicate layer and the Si substrate, it is below the detection limit, that is, below 1%. Therefore, by using the silicate interface layer thus obtained, a silicate gate insulating film having a gradient composition structure with a low Zr concentration at the interface with respect to the bulk region can be obtained.

Here, considering the concentration of the interfacial silicate layer thus obtained, the Zr concentration is higher than the concentration in the stoichiometric composition of the Zr silicate layer (interfacial silicate layer), that is, the Zr concentration is about 17%. %, Zr silicide having a Zr-Si bond is formed, so that leak characteristics deteriorate. Therefore, the Zr concentration in the bulk region is preferably 17% or less.

Further, as a metal oxide film, ordinary ZrO
_{When x} ( _x x2) is used, the Zr concentration in the bulk region of the Zr silicate layer reaches a maximum of about 7%, as can be seen from the measurement results in FIG. In this case, the dielectric constant is sufficiently higher than that of SiO ₂ (ε = approximately 7 to 8), and the leak characteristics do not deteriorate. Therefore, the maximum value of the Zr concentration in the bulk region of the Zr silicate layer is preferably 7% or 7% or less.

FIG. 10A shows a MIS capacitor having an Au / interfacial silicate layer (Zr silicate layer) / Si structure in which a ZrO ₂ film is formed by a laser ablation film forming method and an interfacial silicate layer is used as an insulating film. And the results of measuring the CV characteristics thereof. FIG.
(B) shows an Au / Al film formed using a target having the same Zr concentration as the interfacial silicate layer of FIG.
FIG. 4 shows the results of measuring the CV characteristics of a MIS capacitor having a Zr silicate layer / Si structure by a deposition method.

The dielectric constant estimated from the storage capacitance and the film thickness is almost the same as ε = 7 to 8 and is sufficiently higher than that of SiO ₂ . On the other hand, as for the CV curve, the capacitor using the Zr silicate layer formed by the deposition method of FIG.
In the case of (a), no such distortion is observed, and it can be seen that good interface characteristics can be obtained.

As described above, a Zr silicate having a gradient composition structure obtained by the interfacial reaction between a Zr oxide film and Si and having a gradually decreasing Zr concentration from the upper interface to the lower interface of the Zr silicate layer. Layer (from another perspective, the Zr silicate layer at the lower interface
(a Zr silicate layer whose r concentration is lower than the Zr concentration at the upper layer side interface) is used.
At the interface with the substrate, good interface characteristics can be obtained because the Zr concentration is low, and a high dielectric constant can be achieved because the Zr concentration is high in the bulk region of the Zr silicate layer. MIS field-effect transistor having the above characteristics.

Note that Hf or La may be used instead of Zr. In particular, since Hf has the same properties as Zr, the numerical values relating to the Hf concentration are as described above for Zr.
The numerical values for the concentrations apply analogously.

Hereinafter, the MIS having the above-described structure will be described.
The transistor is described. The basic structure is the same as the structure of FIG. 3 shown in the first embodiment, and the basic manufacturing method is the same as the method of FIG. 4 shown in the first embodiment. Here, the manufacturing method will be described with reference to FIG.

First, as shown in FIG. 4A, a p-type silicon substrate 5 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used.
On 1, a groove for element isolation is formed by reactive ion etching. Subsequently, for example, an element isolation region 52 is formed by embedding an LP-TEOS film.

Next, as shown in FIG. 4B, using a laser ablation film forming method, for example, an oxygen partial pressure of about 10
At a substrate temperature of 300 to 600 ° C. in an atmosphere of Pa,
A ZrO ₂ film (metal oxide film) 59 having a thickness of 10 nm is formed on the Si substrate 51. By using the laser ablation film formation method, each element has sufficient energy by the action of light excitation at the time of film formation, so that a film with less composition deviation can be formed.

[0102] Simultaneously with formation of the ZrO ₂ film 59, Zr silicate layer 53 having a thickness of about 2~3nm the interface between the Si substrate 51 and the ZrO ₂ film 59 is formed. The Zr silicate layer 53 formed in this manner forms Zr, O
Since each element of Si and Si has sufficient energy, a composition is unlikely to shift, a desired composition is obtained, and a high-density material having few defects can be obtained. Further, the Zr silicate layer 53 formed in this manner has a structure in which Si,
Since a large amount of Zr is present on the ZrO ₂ film 59 side, a gradient composition structure is obtained in which the Zr concentration gradually decreases toward the Si substrate 51 side. Further, since this is a photoexcitation reaction and does not have excessive kinetic energy, damage to the surface of the Si substrate 51 can be reduced.

[0102] Further, by irradiating the excited oxygen when forming the ZrO ₂ film 59, it is possible to promote the oxidation reaction at the Si substrate interface, close to the SiO ₂ composition, is small defects, graded composition , And a better metal silicate layer 53 can be formed.

Next, as shown in FIG.
When wet etching is performed for about 100 seconds using a dilute HF solution, the ZrO ₂ film 59 is etched, and only the Zr silicate layer 53 remains selectively. At this time, since the etching rate sharply decreases in the Zr silicate layer 53,
Even if the etching time becomes longer by about 30 to 30%, there is no significant change in the film thickness of the Zr silicate layer 53, and only the excellent Zr silicate layer 53 can be selectively left easily and with good film thickness controllability.

Next, as shown in FIG. 4D, excited oxygen is irradiated from the excited oxygen source 60 to the Zr silicate layer 53 left by the etching. RTA treatment may be performed instead of the excitation oxygen irradiation.

Next, as shown in FIG. 3, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and the polysilicon film is patterned to form a gate electrode.
Then, for example 450 ° C., at a pressure 1Pa~10 ⁵ Pa, using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas, for example 5nm~200nm of CVD
A gate sidewall 56 made of a silicon nitride film is formed.

The subsequent steps are the same as the steps for manufacturing a normal MIS transistor. That is, for example, acceleration voltage 2
Arsenic ions are implanted at 0 keV and at a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 55. Subsequently, a CVD silicon oxide film serving as an interlayer insulating film 57 is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by sputtering, and the Al film is patterned by reactive ion etching to form an Al wiring 58.

In this embodiment, in order to obtain a graded composition, a metal film may be further deposited after forming the metal silicate layer, and the metal atoms in the metal film may be diffused into the metal silicate layer by heat treatment. . Further, after forming the metal silicate layer, metal ions may be implanted into the metal silicate layer with low energy.

Also, the present embodiment can be applied to a gate insulating film of a damascene gate or a replacement gate transistor like the first embodiment.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be variously modified and implemented without departing from the gist thereof. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if some constituent elements are deleted from the disclosed constituent elements, they can be extracted as an invention as long as a predetermined effect can be obtained.

[0110]

According to the present invention, a metal silicate layer having a high dielectric constant and excellent interface characteristics with a silicon substrate can be obtained. By using this metal silicate layer as a gate insulating film, the performance of a MIS transistor can be improved. It can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing that a metal silicate layer is formed on an interface between a metal oxide film and a silicon oxide film on a silicon substrate according to an embodiment of the present invention.

FIG. 2 is a diagram showing an etching rate of a metal oxide film and a metal silicate layer according to the embodiment of the present invention.

FIG. 3 is a sectional view showing the structure of the MIS transistor according to the embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing an example of a manufacturing process of the MIS transistor according to the embodiment of the present invention.

FIG. 5 is a process sectional view showing another example of the manufacturing process of the MIS transistor according to the embodiment of the present invention.

FIG. 6 is a process sectional view showing another example of the manufacturing process of the MIS transistor according to the embodiment of the present invention.

FIG. 7 is a process sectional view showing another example of the manufacturing process of the MIS transistor according to the embodiment of the present invention.

FIG. 8 is a micrograph of a cross-sectional structure of a sample in which a metal oxide film is formed on a silicon substrate observed by TEM according to the embodiment of the present invention.

FIG. 9 is a diagram showing the Zr concentration in the metal silicate layer for the sample shown in FIG.

FIG. 10 is a diagram showing CV characteristics of a MIS capacitor obtained by the present invention in comparison with a conventional technology.

[Explanation of symbols]

1 ... silicon substrate 2 ... ZrO ₂ film (metal oxide film) 3 ... Zr silicates layer (metal silicates layer) 51 ... silicon substrate 52 ... isolation region 53 ... gate insulating film (metal silicates layer) 54 ... gate electrode (electrode layer 55, source / drain regions 56, gate side walls 57, interlayer insulating film 58, Al wiring 59, ZrO ₂ film (metal oxide film) 60, oxygen excitation source 62, SiO ₂ film (silicon oxide film) 63, metal film or Metal silicide film 64: an insulating film containing Zr atoms and nitrogen atoms 65: a zirconium nitride film or a film containing Zr, nitrogen and silicon

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/203 H01L 21/203 S Z 21/318 21/318 B 29/78 29/78 301G (72) Inventor Akira Toriumi 1 Toshiba-cho, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture, Japan Inside the Toshiba R & D Center (72) Inventor Shin Fukushima 1-Toshiba-cho, Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa R & D Center Toshiba Corporation F-term (reference) 4K029 AA06 BA52 BB02 BC05 BD01 CA01 CA05 DB05 DB20 FA01 GA01 4K030 AA03 AA13 BA38 BB12 CA04 DA02 DA09 LA02 5F040 DA19 DC01 EC07 ED03 EK05 FA07 FC22 5F058 BA20 BC03 BC11 BC20 BD01 BD05 BF18 BD20 BH03 BH04 BH16 BJ01 BJ10 5F103 AA01 AA08 DD30 LL08 PP03 RR05

Claims (15)

[Claims] 1. A semiconductor device comprising an active element formed on a silicon substrate, the semiconductor device comprising: a metal silicate layer formed on the silicon substrate; and an electrode layer formed on the metal silicate layer. The metal silicate layer is configured so that the concentration of the constituent metal gradually decreases from the interface between the electrode layer and the metal silicate layer toward the interface between the silicon substrate and the metal silicate layer. A semiconductor device characterized by the above-mentioned. 2. A semiconductor device comprising an active element formed on a silicon substrate, the semiconductor device comprising: a metal silicate layer formed on the silicon substrate; and an electrode layer formed on the metal silicate layer. The concentration of the constituent metal contained in the metal silicate layer,
The concentration of the metal in the stoichiometric composition of the metal silicate is less than or equal to the concentration of the constituent metal on the interface side between the electrode layer and the metal silicate layer. A semiconductor device characterized in that the concentration of the constituent metal on the interface side is lower. 3. The metal silicate layer according to claim 1, wherein the metal constituting the metal silicate layer is Zr or Hf, and the metal silicate layer is constituted so that the concentration of the metal constituting the metal silicate layer is 7 atomic percent or less. Or the semiconductor device according to 2. 4. The semiconductor device according to claim 1, wherein the semiconductor device includes a field effect transistor, and the metal silicate layer is a gate insulating film of the field effect transistor.
Or the semiconductor device according to 2. 5. The metal silicate layer has a thickness of 0.5 n.
The semiconductor device according to claim 1, wherein the length is not less than m and not more than 4 nm. 6. A step of forming a metal silicate layer at an interface between the silicon substrate and the metal oxide film by forming a metal oxide film on a silicon substrate; and selecting a metal oxide film on the metal silicate layer. And removing the metal silicate layer by removing the metal silicate layer. 7. The semiconductor device according to claim 6, further comprising, after the step of selectively removing the metal oxide film, a step of heat-treating the metal silicate layer at a temperature of 800 ° C. or less. Production method. 8. A step of forming a silicon oxide film on a silicon substrate, and a step of forming a metal film or a metal silicide film having a metal atom having a solid solution limit or more on the silicon oxide film on the silicon oxide film. Forming a metal silicate layer by diffusing metal atoms in the metal film or the metal silicide film into the silicon oxide film. 9. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of introducing nitrogen into said metal silicate layer. 10. A metal containing nitrogen by forming a film on a silicon substrate by a vapor deposition method, a sputtering method or a laser ablation method using a metal oxide target in a nitrogen atmosphere or under irradiation of excited nitrogen. A method for manufacturing a semiconductor device, comprising a step of forming a silicate layer. 11. A CV using a gas containing at least a metal and oxygen in a nitrogen atmosphere or under irradiation of excited nitrogen.
A method for manufacturing a semiconductor device, comprising a step of forming a metal silicate layer containing nitrogen by forming a film on a silicon substrate by Method D. 12. A process for forming a metal silicate layer containing nitrogen by heat-treating a film containing metal, silicon and nitrogen formed on a silicon substrate in an oxygen atmosphere at a temperature of 800 ° C. or less. A method for manufacturing a semiconductor device, comprising: 13. A method of manufacturing a semiconductor device, comprising: irradiating a film containing metal, silicon and nitrogen formed on a silicon substrate with excited oxygen to form a metal silicate layer containing nitrogen. Method. 14. A step of forming a metal nitride film on a silicon substrate, and a step of heat-treating the metal nitride film at a temperature of 800 ° C. or less in an oxygen atmosphere to form a nitrogen-containing metal silicate layer. A method for manufacturing a semiconductor device, comprising: 15. A semiconductor device comprising: a step of forming a metal nitride film on a silicon substrate; and a step of irradiating the metal nitride film with excited oxygen to form a metal silicate layer containing nitrogen. Manufacturing method.