WO2003003471A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2003003471A1
WO2003003471A1 PCT/JP2002/006032 JP0206032W WO03003471A1 WO 2003003471 A1 WO2003003471 A1 WO 2003003471A1 JP 0206032 W JP0206032 W JP 0206032W WO 03003471 A1 WO03003471 A1 WO 03003471A1
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Prior art keywords
metal element
gate insulating
insulating film
semiconductor device
film
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PCT/JP2002/006032
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French (fr)
Japanese (ja)
Inventor
Masaru Kadoshima
Toshihide Nabatame
Takaaki Suzuki
Yasuhiko Murata
Takashi Naito
Masahiko Hiratani
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Hitachi, Ltd.
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Publication of WO2003003471A1 publication Critical patent/WO2003003471A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a MIS transistor having a gate insulating film.
  • MIS Metal Insulat or Semiconductor
  • MOSFETs Metal a 1-Oxlde-Semiconductor or Field-Effect-Transistor
  • the thickness of the SiO 2 gate insulating film has been reduced.
  • the leakage current increases due to direct tunneling current, the thin film I spoon is predicted that there is a limit.
  • Japanese Patent Application Laid-Open No. 11-135774 discloses a semiconductor device using a silicate dielectric as a high dielectric gate insulating film.
  • Silicate dielectrics solid solution metal oxide S i0 2 has a high thermal stability in the S i, has the advantage of forming a steep gate insulating film / silicon interface. Also, until now, it has been used as a gate insulating film. The advantage of S i 0 2 that has been used can be used as it is. Furthermore, since the silicon dielectric is amorphous, it has excellent leakage current characteristics.
  • the metal elements such as zirconium, cerium, and zinc can be used as the metal elements to be dissolved in the silicate dielectric.
  • the relative dielectric constant of a silicate dielectric can be further improved by making the oxide contain more metal elements having a high relative dielectric constant.
  • metal oxides condense and phase separate within the gate insulating film, causing problems such as an increase in leak current and a failure to obtain the gate capacitance that should be obtained.
  • metal oxides having a high relative dielectric constant generally have a high polarizability, when they form a solid solution in SiO 2, the film becomes coarse at the same time, and the oxygen barrier property is lost. As a result, oxygen diffuses through the gate insulating film, and oxygen and silicon react at the silicon interface. Due to this reaction, a SiO 2 layer having a low dielectric constant grows at the silicon interface, and the relative dielectric constant of the gate insulating film has been effectively reduced.
  • An object of the present invention to suppress aggregation and phase separation of metal oxides in a gate insulating film, maintain oxygen barrier properties, and suppress the formation of a low dielectric constant SiO 2 layer.
  • An object of the present invention is to provide a semiconductor device in which the relative dielectric constant of a film is improved. Disclosure of the invention
  • the gate insulating film is an amorphous composite oxide film containing three kinds of metal elements.
  • the insulating film includes a first metal element having a low relative dielectric constant as a main component, a second metal element having a higher relative dielectric constant than the first metal element and being dissolved in the metal element, and the first metal element.
  • its gate insulation is characterized in that one of the three metal elements is a rare earth element.
  • Amorphous composite Sani ⁇ containing three metal elements it is possible to obtain a high dielectric constant than conventional S i 0 2, further one of the three kinds of metal elements in the rare earth element By doing so, the gate insulating film can be densified, so that aggregation and phase separation of metal oxides in the gate insulating film can be suppressed. At the same time, the oxygen barrier properties are improved.
  • the semiconductor device of the present invention is characterized in that the gate insulating film is an amorphous composite oxide film containing a rare earth element. Densification of the gate insulating film by rare earth elements is most effective when the gate insulating film is an amorphous composite oxide composed of three types of metal elements, but is not necessarily limited to three types. Not something.
  • the gate insulating film preferably has a relative permittivity of 20 or more, preferably 30 to 400, and a first metal element constituting a metal oxide, and has a relative permittivity of less than 20. Or a second metal element constituting a metal oxide of 2 to less than 30; and a third metal for densifying a composite oxide composed of the first metal element and the second metal element. It is an amorphous composite oxide film containing an element.
  • the oxide of the first metal element mainly plays a role in improving the relative dielectric constant of the gate insulating film, and the oxide of the second metal element serves as a gate insulating film for high-temperature heat treatment in a semiconductor device manufacturing process. Plays a role in maintaining an amorphous state.
  • the density changes. This phenomenon is a technique used especially in the field of glass.
  • the oxide dissolves the first metal element having a high relative dielectric constant into the oxide of the second metal element, problems such as agglomeration and phase separation and a decrease in film density occur.
  • the metal element in the composite metal oxide is stabilized by further dissolving the third metal element that densifies the composite oxide composed of the first and second metal elements described above. The solid solution becomes possible, and aggregation and phase separation can be suppressed.
  • the third metal element is preferably a rare earth element. Further, it is preferable that the content of the third metal element is 0.5% or more and 20% or less in element ratio with respect to the total amount of metal elements in the gate insulating film. Within this range, an amorphous composite oxide film can be obtained. However, if the element ratio is less than 0.5%, the effect of densification by the third metal element cannot be obtained, and if the element ratio is more than 20%, solid solution does not occur and phase separation occurs, resulting in relative permittivity. And the leakage current increases.
  • the gate insulating film includes a first metal element forming a metal oxide having a relative dielectric constant of 20 or more and a second metal element forming a metal oxide having a relative dielectric constant of less than 20. Characterized in that it is an amorphous composite oxynitride film to be formed.
  • oxygen atoms are two-coordinate with the metal element and are bonded in a planar manner.
  • the nitrogen atoms take three coordinations and bond sterically. Therefore, by substituting part of the oxygen atoms with nitrogen atoms, the gate insulating film can be densified.
  • the relative dielectric constant can be improved by substituting nitrogen.
  • the relative dielectric constant of the gate insulating film can be further improved.
  • the content of the nitrogen element in the composite oxynitride film is 0.5% or more and 50% or less in element ratio with respect to the total nonmetallic element amount in the gate insulating film. Increasing the amount of nitrogen element is effective in terms of densification of the second metal oxide, but increasing the nitrogen content by more than 50% results in an increase in the leak current of the gate insulating film.
  • the first metal element constituting the gate insulating film of the present invention is preferably at least one of Ba, Nb, W, Ta, Ti, Zr, Hf and Pb.
  • BaO, N b 2 0 5, WO 3, Ta 2 0 5 ⁇ Ti0 2, Zr0 2, 11 0 2 or? 130 is
  • the first metal element preferably has an element ratio of 5 to 30%.
  • the second metal element one or more of Si and A1 are desirable. And against the high temperature heat treatment in the S i 0 2 and A 1 2 0 3 semiconductor device manufacturing process is Sani ⁇ can maintain the amorphous state.
  • the former shows a low relative permittivity of about 3.9 and the latter shows a low relative permittivity of 12.
  • the second metal element preferably has an element ratio of 65 to 95% in a binary system and 65 to 85% in a ternary system.
  • the third metal element includes at least one of Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Ym, Yb, and Ln.
  • the semiconductor device is characterized in that an interface control layer composed of a silicon oxide film or a silicon nitride film is provided at an interface between the gate insulating film and the silicon substrate.
  • an interface control layer composed of a silicon oxide film or a silicon nitride film suppresses oxidation of the silicon interface due to an oxidation process as in the formation of the gate insulating film, and provides an effective relative dielectric constant. The rate can be kept from dropping.
  • the interface control layer also functions as an insulating film, it is necessary to consider a gate capacitance as a stacked gate insulating film structure of the gate insulating film and the interface control layer.
  • FIG. 1 is a schematic diagram of a MIS transistor device according to the present invention.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of the MIS transistor device according to the present invention.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of the MIS transistor device according to the present invention.
  • FIG. 4 is a schematic view of a CVD apparatus for producing a Ba—Si—Gd composite oxide film as a gate insulating film according to the present invention.
  • FIG. 5 shows the physical film in the Ba—Si—Gd composite oxide film that is the gate insulating film of the present invention.
  • FIG. 3 is a diagram showing the relationship between thickness and E 0 T.
  • Figure 6 is a graph showing the relationship of G d 2 0 3 peak intensity ratio Gd / (Gd + Ba + S i) ratio in some Ba-S i-Gd composite oxide film in the gate insulating film of the present invention is there.
  • FIG. 7 is a diagram showing the relationship between the physical film thickness of the Zr—Al—La composite oxide of the present invention and EOT.
  • FIG. 8 is a diagram showing the relationship between the physical film thickness of the Ti—Si composite nitrided oxide film of the present invention and EOT. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a MIS transistor according to the present invention
  • FIGS. 2 and 3 are cross-sectional views showing a method for manufacturing the transistor.
  • the Si single crystal substrate 101 is a substrate with a p-type and (100) plane orientation and a resistivity of 10 to 15 ⁇ ⁇ cm (Fig. 2 (a)).
  • a Ba-Si-Gd composite oxide film to be a 103 gate insulating film was fabricated (Fig. 2 (c)).
  • the first metal element is Ba
  • the second metal element is Si
  • the third metal element for densifying the first and second composite oxide films is Gd.
  • FIG. 4 is a schematic diagram of the CVD apparatus used in this example.
  • Si raw material container 115 and Gd raw material container 116 Enclosed in Si raw material container 115 and Gd raw material container 116. Get enough steam For this purpose, the raw material containers enclosing each raw material were heated to 100 to 250 ° C, and introduced into the thin chamber 111 with argon carrier gas. Argon carrier gas was supplied from Argon cylinder 117. By controlling the flow rate of the argon carrier gas of each raw material to 100 to 500 sccm, the composition of the metal element in the gate insulating layer was adjusted. O 2 gas, which is a reaction gas, was supplied from an oxygen cylinder 118, and the flow rate was set to 100 sccm. The above gases were uniformly supplied onto the Si single crystal substrate 101 by the blade 119.
  • Argon carrier gas was supplied from Argon cylinder 117.
  • the thin-film formation chamber was a hot-wall type, and was heated to 150 ° C by a heater 120 for heating the thin-film formation chamber.
  • the residual gas in the CVD reaction was exhausted by a vacuum pump 122.
  • the pressure in the thin film forming chamber was adjusted to 0.1 t 0 rr by the pressure adjusting valve 121, and the substrate temperature was heated to 300 ° C. or more and 500 ° C. or less by the substrate heating heater 113. With a film formation time of 1 to 5 minutes, a film thickness of 5 to 25 nm was obtained.
  • the elements Ba, Si and Gd were examined by AES (Auer Electron Spectroscopy) analysis, the ratio was 25: 70: 5.
  • XRD X-Ray Diffraction
  • a polycrystalline Si film serving as the gate electrode 104 was formed to a thickness of 30 Onm (FIG. 2 (d)). Thereafter, phosphorus was injected into the n-channel region, and boron was injected into the p-channel region, and activated by heat treatment in a nitrogen atmosphere at 800 ° C. and 10 to 30 min.
  • the gate electrode 104 was formed by patterning a polycrystalline Si film using a normal photolithography method and etching it by RIE in a self-aligned line (FIG. 2 (e)). Similarly, the gate insulating film 103 was formed by processing.
  • a SiO 2 protective film 106 was formed by the CVD method (FIG. 3 (g)). Create a through hole on the source / drain 105 After fabrication, a W-plug electrode 107 was fabricated by CVD (Fig. 3 (h)). Finally, A1 wiring 108 was fabricated on the W-plug 107 to fabricate a MIS transistor device (Fig. 3 (i)).
  • the semiconductor device (MIS transistor element) of this embodiment is formed on a silicon single crystal substrate, an element isolation insulating film, a gate insulating film, and a gate insulating film.
  • a gate electrode, source and drain regions formed on both sides of the gate insulating film between the device isolation insulating film and the gate insulating film, and a gate insulating film with the device isolation insulating film.
  • a protective film for protecting the film, the gate electrode, the source and drain regions, a plug electrode formed in contact with each of the source and drain regions and penetrating the protective film, and formed on the protective film in contact with the plug electrode This is a configuration having the interconnects provided.
  • the gate electrode 104 - 2 ⁇ 2V EOT than C one V characteristics in the case of changing (Si0 2 in terms of thickness) was calculated.
  • Figure 5 summarizes the results.
  • the gradient determined by the least squares method between 5 and 25 nm thickness means the dielectric constant and was about 18.
  • the leak current density was measured for the 5 nm film, it was 4 ⁇ 10 4 A / cm 2 when the voltage of IV was applied.
  • the EOT was about 0.2 nm when the physical film thickness was zero, and the formation of a low dielectric constant SiO 2 layer at the interface between the 103 gate insulating film and the 101 Si single crystal substrate could be suppressed. Furthermore, when the same C-V characteristics were evaluated after being left in the air for 100 hours, no deterioration of the characteristics was observed.
  • a Ba—Si composite oxide film that does not dissolve Gd was prepared.
  • the production conditions were the same except that the supply of the Gd (d pm) 3 raw material was stopped. With a film formation time of 15 minutes, a film thickness of 5 to 25 nm was obtained.
  • the ratio was 25:75.
  • Figure 5 also shows the results of calculating EOT from the same C-V measurement. The dielectric constant was about 13, which was lower than that when Gd was dissolved.
  • the leakage current density was measured for a 5 nm film, 1 When a voltage of V was applied, it was 2 ⁇ 10—iA / cm 2 . This was due to the phase separation of BaO. This indicates that BaO phase separation can be suppressed by the solid solution of Gd.
  • the solid solution of Gd in the Ba—Si composite oxide film can suppress the deterioration accompanying the aggregation of BaO and the precipitation due to the moisture absorption reaction.
  • the B a- S i composite Sani ⁇ there is shown the case where a solid solution of Gd as a third metal element, Y, La, Ce, Pr 5 Nd, Pm, Sm, Eu, Tb, Dy, H The same effect can be obtained with any element of o, Er, Tm and Yb.
  • any metal element of Nb, W, Pb, Ta, Ti, Zr, and Hf, which has a high relative dielectric constant, may be used as the first metal element.
  • a CVD method is used as a method for forming a gate insulating film, but any method such as an electron beam evaporation method or a sputtering method may be used as long as a good thin film can be manufactured.
  • a polycrystalline S i as a gate electrode
  • a metal which does not react with the dielectric material for example W, Mo, T iN, may be used T i S i 2, and the like.
  • phosphorus may be doped into the polycrystalline Si.
  • a low-resistance metal material may be used.
  • a Cu material may be used.
  • a Ba_Si—Gd composite oxide film to be the gate insulating film 103 was formed by a CVD method.
  • a Ba-Si-Gd composite oxide film with a solid solution amount of Gd (Gd / (Gd + Ba + Si)) of 0, 0.5, 5, 20, and 30% was prepared at an elemental ratio of about 100 nm. .
  • XRD analysis was performed on the crystallinity of this film.
  • the Gd 2 0 3 the diffraction peak intensity when Gd solid solution amount of 30% to 100%, indicating Gd 2 0 3 diffraction peak intensity for the solid solution of Gd in FIG.
  • the amorphous composite oxide film of the present invention can be obtained without phase separation by setting the Gd solid solution amount to 0.5% or more and 20% or less in element ratio. Make sure ⁇ L, L / L o
  • a Zr—A1-La composite oxide film in which Zr is selected as the first metal element, A1 is selected as the second metal element, and La is set as the third metal element, is used.
  • the MIS transistor used for the gate insulating film was fabricated.
  • the device isolation region 102 is formed on the Si single crystal substrate 101 with a groove having a depth of about 0.4 ⁇ m, and then a SiO 2 film is entirely formed by the CVD method. It was manufactured by flattening with CMP.
  • Example 1 the SiO 2 film on the substrate surface was removed by dilute HF treatment.
  • a film at 100 ° C in an inert atmosphere a 21 «_81-1 ⁇ composite oxide film with a physical film thickness of 3 to 1511111 is obtained.
  • a post heat treatment was performed at 800 ° C. in a nitrogen atmosphere.
  • a MIS transistor element was manufactured in the same manner as in Example 1.
  • EOT was calculated from the C-V characteristic when one A1 wiring 108 was grounded and the gate electrode 1 ⁇ 4 was changed by 2 to 2 V.
  • Figure 7 shows the results.
  • the gradient obtained from the least squares method between 3 and 15 nm thickness means the dielectric constant and was about 17.
  • the EOT was about 0.2 nm, and the formation of a low dielectric constant SiO 2 layer at the interface between the gate insulating film 103 and the Si single crystal substrate 101 could be suppressed.
  • the C-V characteristics were evaluated after being left in the air for 100 hours, no deterioration of the characteristics was observed.
  • EOT was calculated from the same CV characteristics. The results are summarized in FIG.
  • the dielectric constant was about 12 between 3 and 15 nm thickness. Also, the physical thickness is E 0 T is approximately 0.6nm in the case of zero, S i 0 2 layers of 0. 6 nm to 31 interface was formed. Thus, it was found that the relative dielectric constant and the oxygen barrier property were smaller than when La was dissolved.
  • a MIS transistor using Ti as the first metal element and Si as the second metal element, and using a Ti—Si composite oxide film as a gate insulating film is described. Created.
  • Example 1 the element isolation region 102 by the CVD method after forming a groove having a depth of about 0. 4 zm to S i monocrystalline substrate 101, the entire surface forming a Si0 2 film, then with CM P It was manufactured by flattening.
  • the Si 02 film on the substrate surface was removed by dilute HF treatment.
  • a Ti—Si composite oxide film was first produced by a CVD method. Isopropoxide 'titanium (Ti (OiPr) 2 ) and Si (0-iPr) 4 raw materials were used as Ti and Si raw materials, respectively.
  • the Ti—Si composite oxide film is subjected to a nitriding treatment at 700 ° C. in an ammonia gas atmosphere to obtain a Ti-Si composite acid film as the gate insulating film 103 of the present invention.
  • a film was prepared. The film thickness was 5 to 25 nm.
  • the nitrogen content was measured by AES. The nitrogen content was about 22% of the elemental amounts of oxygen and nitrogen.
  • Example 8 shows the results.
  • the gradient determined by the least squares method between the film thicknesses of 5 to 25 nm means the dielectric constant and was about 15. Further, when the physical film thickness is zero, the EOT is about 0.3 nm, and the formation of a low dielectric constant SiO 2 layer at the interface between the gate insulating film 103 and the Si single crystal substrate 101 can be suppressed. Furthermore, when the C-V characteristics were evaluated after being left in the air for 100 hours, no deterioration of the characteristics was observed.
  • EOT was calculated from the similar C—V characteristics of the Ti—Si composite oxide film before performing the nitriding treatment. The results are summarized in FIG.
  • the dielectric constant was about 12 between 5 and 25 nm thickness.
  • the physical thickness is EOT of about 0. 5 nm in the case of zero, S i 0 2 layers of 0. 5 nm to Si interface formed.
  • an amorphous composite oxide film composed of Hf as the first metal element, Si as the second metal element, and Nd as the third metal element is used for the gate insulating film.
  • the device isolation region 102 is formed by forming a groove having a depth of about 0.4 / m in the Si single crystal substrate 101, and then forming an entire SiO 2 film by a CVD method. It was manufactured by flattening with CMP.
  • a silicon nitride film was formed on the silicon substrate surface by a heat treatment at 700 ° C. for 30 seconds in NH 3 gas.
  • a mixed layer composed of Hf, Si, and Nd was formed.
  • the film was formed using a ternary ion beam sputtering method.
  • the Hf target, the Si gate, and the Nd gate were set, and three ion sources were used simultaneously.
  • a mixed layer with an Hf: Si: Nd element ratio of 10: 85: 5 was fabricated.
  • the obtained mixed layer was heat-treated at 350 ° C. in an oxygen atmosphere to produce a gate insulating film 103 made of an amorphous Hf—Si—Nd composite oxide film.
  • a MIS transistor element was manufactured.
  • the EOT Si02 equivalent film thickness
  • the EOT was calculated from the C-V characteristics when one of the aluminum wirings 109 was used as a ground and a voltage of ⁇ 2 to 2 V was applied to the gate electrode 105.
  • An evaluation was performed on a gate insulating film having a thickness of 10 to 4 Onm.
  • the relative dielectric constant of the amorphous Hf—Si—Nd composite oxide film was found to be about 16.
  • the EOT was about 0.2 nm when the physical film thickness was zero.
  • a good gate insulating film could be obtained by forming a mixed layer composed of Hf, Si, and Nd and oxidizing the mixed layer to form a gate insulating film.
  • silicon nitride is located between the amorphous Hf—Si—Nd composite oxide film and the silicon substrate. It was also confirmed that the oxidation of the silicon substrate could be suppressed by adopting a structure sandwiching the oxide film.
  • an amorphous composite oxide film composed of three kinds of metal elements is used as a gate insulating film,
  • a dense gate insulating film can be obtained.
  • a semiconductor device in which the deterioration of the film quality due to the phase separation of the first metal element oxide was suppressed and the oxygen barrier property was improved. Further, by using the gate insulating film formed according to the present invention, a MIS transistor having a gate length of 0.1 m or less could be provided.

Abstract

A MIS transistor device using a silicon single crystal substrate as a base and a semiconductor device having an amorphous gate insulating film of high relative dielectric constant are disclosed. A semiconductor device having a dense gate insulating film of high relative dielectric constant, especially a MIS transistor device, is fabricated by forming an amorphous composite oxide film composed of three metallic elements as a gate insulating film on a silicon single crystal substrate.

Description

技術分野 Technical field
本発明は、 半導体装置に係わり、 特にゲート絶縁膜を有する MI S型トランジ ス夕素子に関する。 明  The present invention relates to a semiconductor device, and more particularly to a MIS transistor having a gate insulating film. Light
Height
 Fine
MI S (Metal Insulat or Semiconduct or)型半 導体装置はさまざまな電子部品に利用されており、 高集積化 ·低コスト化のため にその最小加工寸法の縮小が進められている。 近年では、 MOSFET (Met a 1― Ox l d e― Semiconduct or Field— Ef f ect— T r ans i s t o r) の微細化は、 く 0. 1〃mのゲート長まで目前に迫って いる状況である。 これに伴い、 S i02ゲート絶縁膜の薄膜化が進められてきた。 しかし、 Si02薄膜の膜厚が 1.5nm以下になると、 直接トンネル電流に起因 してリーク電流が増大するため、 薄膜ィ匕には限界があると予測されている。 MIS (Metal Insulat or Semiconductor) type semiconductor devices are used for various electronic components, and the minimum processing size is being reduced in order to achieve higher integration and lower cost. In recent years, the miniaturization of MOSFETs (Met a 1-Oxlde-Semiconductor or Field-Effect-Transistor) is about to reach the gate length of 0.1 く m. Along with this, the thickness of the SiO 2 gate insulating film has been reduced. However, when the thickness of the Si0 2 film is 1.5nm or less, the leakage current increases due to direct tunneling current, the thin film I spoon is predicted that there is a limit.
そこで、 ゲート絶縁膜を従来材 S i02 (比誘電率 3.9) より誘電率の高い誘 電体材料に置き換えるという試みがなされている。 高誘電体材料を用いると、 物 理膜厚を厚くしたまま、 S i02と同一のゲート容量を得ることができる。 この ため、 スケーリング則に従って素子を微細化した場合にも、 ゲート絶縁膜中の直 接トンネリングによるゲート電極/シリコン基板間のリ一ク電流を抑えられると 考えられている。 Therefore, attempt has been made is replaced with a gate insulating film dielectrics material having a dielectric constant than conventional materials S i0 2 (relative dielectric constant 3.9). With high dielectric material, while thicker objects RimakuAtsu, it is possible to obtain the same gate capacitance and S i0 2. For this reason, it is considered that the leakage current between the gate electrode and the silicon substrate due to direct tunneling in the gate insulating film can be suppressed even when the element is miniaturized according to the scaling law.
特開平 11— 135774号報において、 高誘電体ゲ一ト絶縁膜としてシリケ ート誘電体を用いた半導体装置が開示されている。 S i02に金属酸化物を固溶 したシリケート誘電体は、 S i上において熱的安定性が高く、 急峻なゲート絶縁 膜/シリコン界面を形成できる利点を有する。 また、 これまでゲート絶縁膜とし て用いてきた S i 02の利点をそのまま利用することが出来る。 さらに、 シリケ 一ト誘電体は非晶質であるためリーク電流特性にも優れている。 Japanese Patent Application Laid-Open No. 11-135774 discloses a semiconductor device using a silicate dielectric as a high dielectric gate insulating film. Silicate dielectrics solid solution metal oxide S i0 2 has a high thermal stability in the S i, has the advantage of forming a steep gate insulating film / silicon interface. Also, until now, it has been used as a gate insulating film. The advantage of S i 0 2 that has been used can be used as it is. Furthermore, since the silicon dielectric is amorphous, it has excellent leakage current characteristics.
シリケート誘電体に固溶させる金属元素には、 ジルコニウム、 セリウム、 亜鉛 など多くの金属元素を用いることが出来る。 一般的に、 酸化物が高い比誘電率を 示す金属元素をより多く含有させることにより、 シリケート誘電体の比誘電率を より向上することが出来る。  Many metal elements such as zirconium, cerium, and zinc can be used as the metal elements to be dissolved in the silicate dielectric. In general, the relative dielectric constant of a silicate dielectric can be further improved by making the oxide contain more metal elements having a high relative dielectric constant.
しかしながら、 S i 02内に他の金属元素を多量に固溶すると、 金属元素は酸 化物として安定に固溶できなくなる。 つまり、 ゲート絶縁膜内で金属酸化物の凝 集や相分離が起こり、 リーク電流の増加や本来得るべきゲート容量が得られない といった問題があった。 However, when a large amount of solid solution of other metal elements S i 0 2, the metal element can not be stably dissolved as oxides. In other words, metal oxides condense and phase separate within the gate insulating film, causing problems such as an increase in leak current and a failure to obtain the gate capacitance that should be obtained.
また、 比誘電率の高い金属酸ィ匕物は一般的に分極率が高いため、 S i 0 2内に 固溶すると、 同時に膜が粗になり、 酸素バリア性が失われてしまう。 その結果、 ゲート絶縁膜中を酸素が拡散し、 シリコン界面で酸素とシリコンが反応する。 こ の反応により、 シリコン界面に低誘電率な S i 02層が成長し、 ゲ一ト絶縁膜の 比誘電率は実効的に低下してしまうことが問題となっていた。 In addition, since metal oxides having a high relative dielectric constant generally have a high polarizability, when they form a solid solution in SiO 2, the film becomes coarse at the same time, and the oxygen barrier property is lost. As a result, oxygen diffuses through the gate insulating film, and oxygen and silicon react at the silicon interface. Due to this reaction, a SiO 2 layer having a low dielectric constant grows at the silicon interface, and the relative dielectric constant of the gate insulating film has been effectively reduced.
本発明の目的は、 ゲート絶縁膜中の金属酸化物の凝集や相分離を抑制し、 かつ 酸素バリア性を保持して、 低誘電率な S i 0 2層の形成を抑制して、 ゲート絶縁 膜の比誘電率を向上させた半導体装置を提供することにある。 発明の開示 SUMMARY OF THE INVENTION It is an object of the present invention to suppress aggregation and phase separation of metal oxides in a gate insulating film, maintain oxygen barrier properties, and suppress the formation of a low dielectric constant SiO 2 layer. An object of the present invention is to provide a semiconductor device in which the relative dielectric constant of a film is improved. Disclosure of the invention
本発明は、 シリコン基板上にゲート絶縁膜を有する半導体装置において、 ゲー ト絶縁膜は、 3種類の金属元素を含む非晶質な複合酸化膜であることを特徴とし、 好ましくはそのゲ一ト絶縁膜は、 比誘電率の低い第 1の金属元素を主成分とし、 該第 1の金属元素より比誘電率が高くその金属元素に固溶する第 2の金属元素と、 前記第 1の金属元素と第 2の金属元素から構成される複合酸化物の相分離を抑制 する第 3の金属元素を含む非晶質な複合酸ィ匕膜からなる。 また、 そのゲート絶縁 膜は、前記 3種類の金属元素のうち 1種類が希土類元素であることを特徴とする。 3種類の金属元素を含む非晶質な複合酸ィ匕物は、 従来の S i 02より高い比誘電 率を得ることができ、 さらに前記 3種類の金属元素のうち 1種類を希土類元素に することで、 ゲート絶縁膜を緻密化することができるため、 ゲート絶縁膜中の金 属酸ィヒ物の凝集や相分離を抑制することができる。 また、 同時に酸素バリア性も 向上する。 According to the present invention, in a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film is an amorphous composite oxide film containing three kinds of metal elements. The insulating film includes a first metal element having a low relative dielectric constant as a main component, a second metal element having a higher relative dielectric constant than the first metal element and being dissolved in the metal element, and the first metal element. An amorphous composite oxide film containing a third metal element for suppressing phase separation of the composite oxide composed of the element and the second metal element. Also, its gate insulation The film is characterized in that one of the three metal elements is a rare earth element. Amorphous composite Sani匕物containing three metal elements, it is possible to obtain a high dielectric constant than conventional S i 0 2, further one of the three kinds of metal elements in the rare earth element By doing so, the gate insulating film can be densified, so that aggregation and phase separation of metal oxides in the gate insulating film can be suppressed. At the same time, the oxygen barrier properties are improved.
本発明の半導体装置は、 ゲート絶縁膜が希土類元素を含む非晶質な複合酸化膜 であることを特徴とする。 希土類元素によるゲート絶縁膜の緻密化は、 ゲート絶 縁膜が 3種類の金属元素から構成される非晶質な複合酸化物である場合に最も効 果的であるが、 必ずしも 3種類に限定されるものではない。  The semiconductor device of the present invention is characterized in that the gate insulating film is an amorphous composite oxide film containing a rare earth element. Densification of the gate insulating film by rare earth elements is most effective when the gate insulating film is an amorphous composite oxide composed of three types of metal elements, but is not necessarily limited to three types. Not something.
本発明の半導体装置は、 ゲート絶縁膜は、 比誘電率 2 0以上、 好ましくは 3 0 〜4 0 0の金属酸化物を構成する第 1の金属元素と、 比誘電率 2 0未満、 好まし くは 2〜 3 0未満の金属酸化物を構成する第 2の金属元素と、 前記第 1の金属元 素と前記第 2の金属元素から構成される複合酸化物を緻密化する第 3の金属元素 とを含む非晶質な複合酸化膜であることを特徴とする。 第 1の金属元素の酸化物 は主にゲート絶縁膜の比誘電率を向上する役割を担い、 第 2の金属元素の酸化物 は、 半導体装置の作製プロセスにおける高温熱処理に対して、 ゲート絶縁膜が非 晶質な状態を維持する役割を担う。  In the semiconductor device of the present invention, the gate insulating film preferably has a relative permittivity of 20 or more, preferably 30 to 400, and a first metal element constituting a metal oxide, and has a relative permittivity of less than 20. Or a second metal element constituting a metal oxide of 2 to less than 30; and a third metal for densifying a composite oxide composed of the first metal element and the second metal element. It is an amorphous composite oxide film containing an element. The oxide of the first metal element mainly plays a role in improving the relative dielectric constant of the gate insulating film, and the oxide of the second metal element serves as a gate insulating film for high-temperature heat treatment in a semiconductor device manufacturing process. Plays a role in maintaining an amorphous state.
非晶質な状態を形成する第 2の金属元素の酸化物に対して、 第 2の金属元素と 異なる金属元素を固溶すると、 密度が変化する。 この現象は特にガラスの分野に おいて利用される技術である。 上述したように、 酸化物が高い比誘電率を示す第 1の金属元素を第 2の金属元素の酸化物に固溶する場合、 凝集 ·相分離や膜密度 の減少が問題となる。 本発明では、 以上で示した第 1と第 2の金属元素から構成 される複合酸化物を緻密化する第 3の金属元素をさらに固溶することによって、 複合金属酸化物中の金属元素が安定に固溶できるようになり、 凝集や相分離の抑 制が可能になる。 前記第 1の金属元素として、 酸化物の比誘電率が 30以上を示す金属元素を選 択すると、ゲート絶縁膜の比誘電率を更に向上することができる点で有利である。 前記第 3の金属元素には希土類元素が好ましい。 また、 前記第 3の金属元素の 含有量は、 ゲート絶縁膜中における全金属元素量に対して元素比で 0. 5%以上 20%以下であることが好ましい。 この条件の範囲内で、 非晶質の複合酸化膜を 得ることができる。 しかし、 元素比で 0. 5%より少ない場合には、 前記第 3の 金属元素による緻密化の効果は得られず、 また 20%より多くなると、 固溶せず 相分離が生じて比誘電率やリ一ク電流の増加が生じる。 When a metal element different from the second metal element is dissolved in an oxide of the second metal element which forms an amorphous state, the density changes. This phenomenon is a technique used especially in the field of glass. As described above, when the oxide dissolves the first metal element having a high relative dielectric constant into the oxide of the second metal element, problems such as agglomeration and phase separation and a decrease in film density occur. In the present invention, the metal element in the composite metal oxide is stabilized by further dissolving the third metal element that densifies the composite oxide composed of the first and second metal elements described above. The solid solution becomes possible, and aggregation and phase separation can be suppressed. It is advantageous to select a metal element whose oxide has a relative dielectric constant of 30 or more as the first metal element, since the relative dielectric constant of the gate insulating film can be further improved. The third metal element is preferably a rare earth element. Further, it is preferable that the content of the third metal element is 0.5% or more and 20% or less in element ratio with respect to the total amount of metal elements in the gate insulating film. Within this range, an amorphous composite oxide film can be obtained. However, if the element ratio is less than 0.5%, the effect of densification by the third metal element cannot be obtained, and if the element ratio is more than 20%, solid solution does not occur and phase separation occurs, resulting in relative permittivity. And the leakage current increases.
本発明の半導体装置は、 ゲート絶縁膜は比誘電率 20以上の金属酸化物を構成 する第 1の金属元素と、 比誘電率 20未満の金属酸化物を構成する第 2の金属元 素から構成される非晶質な複合酸化窒化膜であることを特徴とする。  In the semiconductor device of the present invention, the gate insulating film includes a first metal element forming a metal oxide having a relative dielectric constant of 20 or more and a second metal element forming a metal oxide having a relative dielectric constant of less than 20. Characterized in that it is an amorphous composite oxynitride film to be formed.
非晶質な複合酸ィ匕膜中において、 酸素原子は金属元素に対して 2配位をとり平 面的に結合する。 これに対して、 酸素原子の一部を窒素原子に置換した複合酸化 窒化膜においては、 窒素原子は 3配位をとり立体的に結合する。 ゆえに、 酸素原 子の一部を窒素原子に置換することにより、ゲート絶縁膜の緻密化が可能となる。 また、 窒素の置換により、 比誘電率を向上することができる。  In the amorphous composite oxide film, oxygen atoms are two-coordinate with the metal element and are bonded in a planar manner. On the other hand, in a composite oxynitride film in which part of the oxygen atoms is replaced by nitrogen atoms, the nitrogen atoms take three coordinations and bond sterically. Therefore, by substituting part of the oxygen atoms with nitrogen atoms, the gate insulating film can be densified. In addition, the relative dielectric constant can be improved by substituting nitrogen.
前記第 1の金属元素として、 酸化物の比誘電率が 30以上を示す金属元素を選 択すると、ゲ一ト絶縁膜の比誘電率を更に向上することができる点で有利である。 また、 前記複合酸化窒化膜中の窒素元素含有量が、 ゲート絶縁膜中の全非金属元 素量に対して元素比で 0. 5%以上 50%以下であることが好ましい。 第 2の金 属酸化物の緻密化という点で窒素元素量の増加は効果的であるが、 窒素を元素比 で 50%より多くするとゲ一ト絶縁膜のリーク電流の増加をもたらす。  It is advantageous to select a metal element whose oxide has a relative dielectric constant of 30 or more as the first metal element, since the relative dielectric constant of the gate insulating film can be further improved. Further, it is preferable that the content of the nitrogen element in the composite oxynitride film is 0.5% or more and 50% or less in element ratio with respect to the total nonmetallic element amount in the gate insulating film. Increasing the amount of nitrogen element is effective in terms of densification of the second metal oxide, but increasing the nitrogen content by more than 50% results in an increase in the leak current of the gate insulating film.
ここで、本発明のゲート絶縁膜を構成する第 1の金属元素は、 Ba、 Nb、 W、 Ta、 Ti、 Zr、 Hf及び Pbの 1種以上であることが好ましい。 BaO、 N b205、 WO 3、 Ta205ヽ Ti02、 Zr02、 11 02又は?130は Here, the first metal element constituting the gate insulating film of the present invention is preferably at least one of Ba, Nb, W, Ta, Ti, Zr, Hf and Pb. BaO, N b 2 0 5, WO 3, Ta 2 0 5ヽ Ti0 2, Zr0 2, 11 0 2 or? 130 is
それそれ約 34、 約 50、 約 300、 25 - 50, 20 - 80、 約 25、 約 30 又は約 43の高い比誘電率を示す。 第 1の金属元素は、 元素比で 5〜 30 %が好 ましい。 It about 34, about 50, about 300, 25-50, 20-80, about 25, about 30 Or a high relative dielectric constant of about 43. The first metal element preferably has an element ratio of 5 to 30%.
また、 第 2の金属元素としては、 S i及び A 1の 1種以上が望ましい。 酸ィ匕物 である S i 02及び A 1203半導体装置の製造プロセスにおける高温熱処理に対 して、 非晶質な状態を維持することができる。 前者が約 3. 9及び後者が 12の 低い比誘電率を示す。 第 2の金属元素は、 2元系では元素比で 65〜 95 %、 3 元系では 65〜 85 %が好ましい。 Further, as the second metal element, one or more of Si and A1 are desirable. And against the high temperature heat treatment in the S i 0 2 and A 1 2 0 3 semiconductor device manufacturing process is Sani匕物can maintain the amorphous state. The former shows a low relative permittivity of about 3.9 and the latter shows a low relative permittivity of 12. The second metal element preferably has an element ratio of 65 to 95% in a binary system and 65 to 85% in a ternary system.
第 3の金属元素としては、 Y, Ce, Pr, Nd、 Pm、 Sm, Eu, Gd, Tb, Dy, Ho, E r, Ym, Yb及び L nの 1種以上からなる。  The third metal element includes at least one of Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Ym, Yb, and Ln.
本発明の半導体装置は、 前記ゲ一ト絶縁膜とシリコン基板との界面に、 シリコ ン酸化膜又はシリコン窒ィ匕膜から構成される界面制御層を具備することを特徴と する。 シリコン酸化膜又はシリコン窒化膜から構成される界面制御層を具備する ことにより、 前記ゲ一ト絶縁膜の成膜時のような酸化プロセスによるシリコン界 面の酸化を抑制し、 実効的な比誘電率の低下を抑えることができる。 なお、 本構 造では、 界面制御層も絶縁膜として機能するため、 前記ゲート絶縁膜と界面制御 層の積層ゲート絶縁膜構造として、 ゲート容量を考慮する必要がある。 図面の簡単な説明  The semiconductor device according to the present invention is characterized in that an interface control layer composed of a silicon oxide film or a silicon nitride film is provided at an interface between the gate insulating film and the silicon substrate. Providing an interface control layer composed of a silicon oxide film or a silicon nitride film suppresses oxidation of the silicon interface due to an oxidation process as in the formation of the gate insulating film, and provides an effective relative dielectric constant. The rate can be kept from dropping. In this structure, since the interface control layer also functions as an insulating film, it is necessary to consider a gate capacitance as a stacked gate insulating film structure of the gate insulating film and the interface control layer. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明に係る MI S型トランジスタ素子の概略図である。  FIG. 1 is a schematic diagram of a MIS transistor device according to the present invention.
図 2は、 本発明に係る MI S型トランジスタ素子の製造工程を示す断面図であ る。  FIG. 2 is a cross-sectional view showing a manufacturing process of the MIS transistor device according to the present invention.
図 3は、 本発明に係る MI S型トランジスタ素子の製造工程を示す断面図であ る。  FIG. 3 is a cross-sectional view showing a manufacturing process of the MIS transistor device according to the present invention.
図 4は、 本発明に係るゲ一ト絶縁膜である B a— S i— Gd複合酸ィ匕膜を作製 する CVD装置の概略図である。  FIG. 4 is a schematic view of a CVD apparatus for producing a Ba—Si—Gd composite oxide film as a gate insulating film according to the present invention.
図 5は、 本発明のゲート絶縁膜である B a— S i— G d複合酸化膜中の物理膜 厚と E 0 Tとの関係を示す線図である。 FIG. 5 shows the physical film in the Ba—Si—Gd composite oxide film that is the gate insulating film of the present invention. FIG. 3 is a diagram showing the relationship between thickness and E 0 T.
図 6は、 本発明のゲート絶縁膜である Ba— S i— Gd複合酸化膜中の Gd/ (Gd + Ba + S i)比に対する G d 203ピーク強度比の関係を示す線図である。 図 7は、 本発明の Z r—Al— La複合酸化物の物理膜厚と EOTとの関係を 示す線図である。 Figure 6 is a graph showing the relationship of G d 2 0 3 peak intensity ratio Gd / (Gd + Ba + S i) ratio in some Ba-S i-Gd composite oxide film in the gate insulating film of the present invention is there. FIG. 7 is a diagram showing the relationship between the physical film thickness of the Zr—Al—La composite oxide of the present invention and EOT.
図 8は、 本発明の T i— S i複合酸化窒ィ匕膜の物理膜厚と EOTとの関係を示 す線図である。 発明を実施するための最良の形態  FIG. 8 is a diagram showing the relationship between the physical film thickness of the Ti—Si composite nitrided oxide film of the present invention and EOT. BEST MODE FOR CARRYING OUT THE INVENTION
(実施例 1 )  (Example 1)
図 1は本発明に係る MI S型トランジスタであり、 図 2及び図 3はその製造方 法を示す断面図である。 S i単結晶基板 101は p— t ypeで ( 100)面方 位、 抵抗率 10〜15 Ω · cmの基板である (図 2 (a))。 素子分離領域 102 は S i単結晶基板 101に深さ約 0. 4〃mの溝を形成した後に CVD (Che mi c a 1 Va or D e p o s i t i o n)法により、 Si02膜を全面 成 ^臭して、 次に CMP (Chemical Mechanical Pol is hing) で平坦化させて作製した (図 2 (b))。 FIG. 1 shows a MIS transistor according to the present invention, and FIGS. 2 and 3 are cross-sectional views showing a method for manufacturing the transistor. The Si single crystal substrate 101 is a substrate with a p-type and (100) plane orientation and a resistivity of 10 to 15 Ω · cm (Fig. 2 (a)). Isolation regions 102 by CVD (Che mi ca 1 Va or D eposition) process after forming the groove having a depth of about 0.5 4〃M to S i monocrystalline substrate 101, and the entire surface formed ^ smell the Si0 2 film Then, it was flattened by CMP (Chemical Mechanical Polishing) (Fig. 2 (b)).
次に、 希 HF処理により基板表面の S i02膜を除去した後、 CVD法によりNext, after removing the SiO 2 film on the substrate surface by dilute HF treatment,
103ゲート絶縁膜となる B a— S i— Gd複合酸化膜を作製した(図 2 (c))。 この場合、 第 1の金属元素は Ba、 第 2の金属元素は Si、 第 1と第 2の複合酸 化膜を緻密化する第 3の金属元素は G dである。 A Ba-Si-Gd composite oxide film to be a 103 gate insulating film was fabricated (Fig. 2 (c)). In this case, the first metal element is Ba, the second metal element is Si, and the third metal element for densifying the first and second composite oxide films is Gd.
図 4は、 本実施例に用いた CVD装置の概略図である。 B a原料としてジピバ ロイルメ夕ナ一ト 'バリウム (Ba (dpm) 2)、 S i原料としてシリコン 'ィ ソプロポキサイド (Si (0— iPr) 4)及び Gd原料としてジピバロィルメ 夕ナ一ト 'ガドリニウム (Gd (dpm) 3)、 を用い、 それそれ Ba原料容器 1FIG. 4 is a schematic diagram of the CVD apparatus used in this example. Barium (Ba (dpm) 2 ) as a raw material for silicon, silicon (isopropoxide) (Si (0-iPr) 4 ) as a raw material for Si, and gadolinium (Gd) as a raw material for dipivaloylme (Gd) (dpm) 3 ), each using Ba raw material container 1
14、 S i原料容器 115及び Gd原料容器 116に封入した。 十分な蒸気を得 るために、 各原料を封入した原料容器を 100〜250°Cに加熱し、 アルゴンキ ャリアガスにより薄莫形成室 111に導入した。 アルゴンキャリアガスはァルゴ ンボンべ 117より供給した。 各原料のアルゴンキャリアガスの流量を 100〜 500 s c cmに制御して、 ゲート絶縁莫中の金属元素の組成を調整した。 反応ガスである 02ガスは酸素ボンべ 118から供給し、 その流量を 100 s c cmとした。 以上のガスは、 シャヮへヅド 119により均一に S i単結晶基板 101上へと供給した。 薄膜形成室はホットウォール型で、 薄膜形成室加熱用ヒ —夕 120により 150°Cに加熱した。 CVD反応における残留ガスは真空ボン プ 122により排気した。 圧力調整バルブ 121で薄膜形成室の圧力を 0. 1 t 0 r rに調整し、 基板加熱用ヒー夕 113により基板温度を 300 °C以上 50 0°C以下に加熱した。 成膜時間を 1〜5分として、 膜厚 5~25nmを得た。 A ES (Au er Elect ron S p e c t r o s c o p y)分析によつ て、 Ba、 S i及び Gd、 の元素を調べたところ、 25 : 70 : 5であった。 X RD (X— Ray D i f f r a c t i o n)分析を行った結果、 作製した膜か らはピークは同定されず、 非晶質な膜であることが分かった。 14. Enclosed in Si raw material container 115 and Gd raw material container 116. Get enough steam For this purpose, the raw material containers enclosing each raw material were heated to 100 to 250 ° C, and introduced into the thin chamber 111 with argon carrier gas. Argon carrier gas was supplied from Argon cylinder 117. By controlling the flow rate of the argon carrier gas of each raw material to 100 to 500 sccm, the composition of the metal element in the gate insulating layer was adjusted. O 2 gas, which is a reaction gas, was supplied from an oxygen cylinder 118, and the flow rate was set to 100 sccm. The above gases were uniformly supplied onto the Si single crystal substrate 101 by the blade 119. The thin-film formation chamber was a hot-wall type, and was heated to 150 ° C by a heater 120 for heating the thin-film formation chamber. The residual gas in the CVD reaction was exhausted by a vacuum pump 122. The pressure in the thin film forming chamber was adjusted to 0.1 t 0 rr by the pressure adjusting valve 121, and the substrate temperature was heated to 300 ° C. or more and 500 ° C. or less by the substrate heating heater 113. With a film formation time of 1 to 5 minutes, a film thickness of 5 to 25 nm was obtained. When the elements Ba, Si and Gd were examined by AES (Auer Electron Spectroscopy) analysis, the ratio was 25: 70: 5. As a result of XRD (X-Ray Diffraction) analysis, no peak was identified from the prepared film, indicating that the film was an amorphous film.
次にゲ一ト電極 104となる多結晶 S i膜を 30 Onm成膜した(図 2 (d))。 その後 nチャンネル領域にはリンを、 pチャンネル領域にはボロンをそれそれ注 入し、 800°C、 10〜30m inの窒素雰囲気中熱処理して活性化した。 ゲ一 ト電極 104は多結晶 S i膜を通常のホトリソグラフィ一法を用いてパ夕一ニン グし、 セルファラインにて RIEによりェヅチングして形成した(図 2 (e))。ま た同様にゲート絶縁膜 103を加工して形成した。  Next, a polycrystalline Si film serving as the gate electrode 104 was formed to a thickness of 30 Onm (FIG. 2 (d)). Thereafter, phosphorus was injected into the n-channel region, and boron was injected into the p-channel region, and activated by heat treatment in a nitrogen atmosphere at 800 ° C. and 10 to 30 min. The gate electrode 104 was formed by patterning a polycrystalline Si film using a normal photolithography method and etching it by RIE in a self-aligned line (FIG. 2 (e)). Similarly, the gate insulating film 103 was formed by processing.
次にゲート電極 104をマスクしてソース/ドレイン領域 105に周期率表の 第 5族の原子 (P, As, Sb)或いは第 3族の原子 (B, Al, Ga, In) のイオン注入を行い、 800°C;、 30 s e cの Ar中熱処理を施す事により低抵 杭の拡散領域を形成した (図 3 (f))。 次に CVD法により S i02保護膜 10 6を形成した(図 3 (g))。さらにソース/ドレイン 105上にスルーホールを作 製した後、 CVD法により W—プラグ電極 107を作製した (図 3 (h))。 最後 に A1配線 108を W—プラグ 107上に作製して MI S型トランジスタ素子を 作製した (図 3 (i))。 Next, using the gate electrode 104 as a mask, ion implantation of atoms of group 5 (P, As, Sb) or atoms of group 3 (B, Al, Ga, In) of the periodic table into the source / drain region 105 is performed. Then, a low-pile diffusion region was formed by heat treatment in Ar at 800 ° C for 30 sec (Fig. 3 (f)). Next, a SiO 2 protective film 106 was formed by the CVD method (FIG. 3 (g)). Create a through hole on the source / drain 105 After fabrication, a W-plug electrode 107 was fabricated by CVD (Fig. 3 (h)). Finally, A1 wiring 108 was fabricated on the W-plug 107 to fabricate a MIS transistor device (Fig. 3 (i)).
図 3 (i) に示したように、 本実施例の半導体装置 (MIS型トランジスタ素 子) は、 シリコン単結晶基板上に、 素子分離絶縁膜と、 ゲート絶縁膜と、 ゲート 絶縁膜上に形成されたゲート電極と、 前記素子分離絶縁膜と前記ゲ一ト絶縁膜と の間で前記ゲート絶縁膜を挟んで両側に形成されたソース及びドレイン領域と、 前記素子分離絶縁膜とゲ一ト絶縁膜とゲート電極とソース及びドレイン領域とを 保護する保護膜と、 ソース及びドレイン領域の各々に接して前記保護膜を貫通し て形成されたプラグ電極と、 プラグ電極に接して保護膜上に形成された配線とを 有する構成となる。  As shown in FIG. 3 (i), the semiconductor device (MIS transistor element) of this embodiment is formed on a silicon single crystal substrate, an element isolation insulating film, a gate insulating film, and a gate insulating film. A gate electrode, source and drain regions formed on both sides of the gate insulating film between the device isolation insulating film and the gate insulating film, and a gate insulating film with the device isolation insulating film. A protective film for protecting the film, the gate electrode, the source and drain regions, a plug electrode formed in contact with each of the source and drain regions and penetrating the protective film, and formed on the protective film in contact with the plug electrode This is a configuration having the interconnects provided.
片方の A1配線 108をアースにして、 ゲート電極 104に— 2〜2V変化さ せた場合の C一 V特性より EOT (Si02換算膜厚) を算出した。 その結果を 図 5にまとめて示す。 5— 25 nm膜厚間で最小 2乗法から求めた勾配は誘電率 を意味し、 約 18であった。 5nmの膜に対して、 リーク電流密度を測定したと ころ、 IVの電圧印加時に 4 X 10— 4 A/cm2であった。 In the grounded one of the A1 wiring 108, the gate electrode 104 - 2~2V EOT than C one V characteristics in the case of changing (Si0 2 in terms of thickness) was calculated. Figure 5 summarizes the results. The gradient determined by the least squares method between 5 and 25 nm thickness means the dielectric constant and was about 18. When the leak current density was measured for the 5 nm film, it was 4 × 10 4 A / cm 2 when the voltage of IV was applied.
また、物理膜厚がゼロの場合に EOTが約 0.2 nmであり、 103ゲート絶縁 膜と 101 S i単結晶基板界面に低誘電率な S i02層の形成を薄く抑えること ができた。 さらに、 100時間大気中に放置した後に同様の C— V特性を評価し たところ、 特性の劣化は認められなかった。 The EOT was about 0.2 nm when the physical film thickness was zero, and the formation of a low dielectric constant SiO 2 layer at the interface between the 103 gate insulating film and the 101 Si single crystal substrate could be suppressed. Furthermore, when the same C-V characteristics were evaluated after being left in the air for 100 hours, no deterioration of the characteristics was observed.
比較のために、 Gdを固溶しない B a— S i複合酸化膜を作製した。 Gd (d pm) 3原料の供給を停止した以外は、 作製条件を同じにした。 成膜時間を 1 5分として、 膜厚 5— 25 nmを得た。 AES分析によって、 B a及び Siの元 素を調べたところ、 25 : 75であった。 同様の C— V測定から EOTを算出し た結果を図 5に併記した。 誘電率は約 13であり、 Gdを固溶した場合と比較し て低下した。 また、 5 nmの膜に対して、 リーク電流密度を測定したところ、 1 Vの電圧印加時に 2 x 10— iA/cm2であった。 これは、 BaOが相分離した ことによるものであった。 このことから、 Gdの固溶により BaOの相分離を抑 制できることがわかった。 For comparison, a Ba—Si composite oxide film that does not dissolve Gd was prepared. The production conditions were the same except that the supply of the Gd (d pm) 3 raw material was stopped. With a film formation time of 15 minutes, a film thickness of 5 to 25 nm was obtained. When the elements of Ba and Si were examined by AES analysis, the ratio was 25:75. Figure 5 also shows the results of calculating EOT from the same C-V measurement. The dielectric constant was about 13, which was lower than that when Gd was dissolved. When the leakage current density was measured for a 5 nm film, 1 When a voltage of V was applied, it was 2 × 10—iA / cm 2 . This was due to the phase separation of BaO. This indicates that BaO phase separation can be suppressed by the solid solution of Gd.
また、物理膜厚がゼ口の場合に E 0 Tが約 0.7 n mであり、 G dを固溶した場 合と比較して S i界面に形成する S i 02の膜厚は増加した。 この結果から、 B a— S i複合酸化膜へ Gdを固溶することにより、 酸素バリア性が向上し、 低誘 電率な S i02の形成を抑制できることが分かった。 In addition, when the physical film thickness was Eguchi, E 0 T was about 0.7 nm, and the film thickness of Si 0 2 formed at the Si interface increased as compared with the case where Gd was dissolved. From these results, it was found that by forming a solid solution of Gd into the Ba—Si composite oxide film, the oxygen barrier property was improved, and the formation of Si 2 with a low dielectric constant could be suppressed.
更に、 100時間大気中に放置した後に同様の C一 V特性を評価したところ、 比誘電率は約 7まで低下した。 これは、 凝集した BaOが大気中の水と反応し、 Ba (OH) 2等が形成したことによるものである。. Gdの固溶により、 B aO が相分離に伴う吸湿反応も抑制できることが分かった。 Further, when the same C-V characteristics were evaluated after being left in the air for 100 hours, the relative dielectric constant was reduced to about 7. This is because the agglomerated BaO reacted with the water in the atmosphere to form Ba (OH) 2 and the like. It was found that the solid solution of Gd can also suppress the moisture absorption reaction of BaO due to phase separation.
以上のように、本実施例より、 B a— S i複合酸ィ匕膜に Gdを固溶することで、 BaOの凝集や吸湿反応による析出にともなう劣化を抑制できることを確認した c ここで、 B a— S i複合酸ィ匕膜に、 第 3の金属元素として Gdを固溶した場合 を示したが、 Y、 La, Ce, Pr5 Nd, Pm, Sm, Eu, Tb, Dy, H o, Er, Tm及び Ybのいずれの元素であっても、 同様の効果を得ることが出 し o As described above, from the present example, it was confirmed that the solid solution of Gd in the Ba—Si composite oxide film can suppress the deterioration accompanying the aggregation of BaO and the precipitation due to the moisture absorption reaction. the B a- S i composite Sani匕膜, there is shown the case where a solid solution of Gd as a third metal element, Y, La, Ce, Pr 5 Nd, Pm, Sm, Eu, Tb, Dy, H The same effect can be obtained with any element of o, Er, Tm and Yb.
また、 第 1の金属元素として B a以外に、 酸化物が高い比誘電率を示す Nb、 W、 Pb、 Ta、 T i、 Z r、 H fのいずれ金属元素を用いてもよい。  Further, other than Ba, any metal element of Nb, W, Pb, Ta, Ti, Zr, and Hf, which has a high relative dielectric constant, may be used as the first metal element.
本実施例において、 ゲート絶縁膜の作製方法として CVD法を用いたが、 電子 ビーム蒸着法やスパッ夕法など良好な薄膜を作製できる方法であれば、 何れの方 法を用いても良い。  In this embodiment, a CVD method is used as a method for forming a gate insulating film, but any method such as an electron beam evaporation method or a sputtering method may be used as long as a good thin film can be manufactured.
また、 ゲート電極として多結晶 S iを用いているが、 上記誘電体材料と反応し ない金属、 例えば W, Mo, T iN, T i S i2等を用いてもよい。 さらに、 多 結晶 S iにリンをド一プしてもよい。 A1配線を説明したが、 低抵抗な金属材料 ならよく、 例えば Cu材料を用いてもよい。 (実施例 2) Further, although a polycrystalline S i as a gate electrode, a metal which does not react with the dielectric material, for example W, Mo, T iN, may be used T i S i 2, and the like. Further, phosphorus may be doped into the polycrystalline Si. Although the A1 wiring has been described, a low-resistance metal material may be used. For example, a Cu material may be used. (Example 2)
実施例 1と同様に、 CVD法によりゲート絶縁膜 103となる Ba_S i— G d複合酸化膜を作製した。 Gdの固溶量(Gd/ (Gd + Ba + S i))を元素比 で 0、 0. 5、 5、 20、 30%とした Ba— S i— Gd複合酸化膜を約 100 nm作製した。この膜の結晶性について、 XRD分析を行った。 Gd固溶量 30% 時の Gd203回折ピーク強度を 100%として、 Gdの固溶量に対する Gd203 回折ピーク強度を図 6に示した。 In the same manner as in Example 1, a Ba_Si—Gd composite oxide film to be the gate insulating film 103 was formed by a CVD method. A Ba-Si-Gd composite oxide film with a solid solution amount of Gd (Gd / (Gd + Ba + Si)) of 0, 0.5, 5, 20, and 30% was prepared at an elemental ratio of about 100 nm. . XRD analysis was performed on the crystallinity of this film. The Gd 2 0 3 the diffraction peak intensity when Gd solid solution amount of 30% to 100%, indicating Gd 2 0 3 diffraction peak intensity for the solid solution of Gd in FIG.
20%以下の Gd固溶量において、 作製した膜が非晶質であるために、 ピーク は認められなかった。 これに対して、 Gdの固溶量 30%では、 立方晶 Gd203 のピークが同定でき、相分離していることが分かった。また、 Gdの固溶量が 0% のときに、 BaOピークが同定され、 B a 0が相分離していることが分かった。 以上のように、 本実施例より、 Gd固溶量を元素比で 0. 5%以上 20%以下 とすることで、 相分離せずに、 本発明の非晶質な複合酸化膜が得られることを確 §ゑ、し/ L o At a Gd solid solution amount of 20% or less, no peak was observed because the formed film was amorphous. In contrast, in solid solution amount of 30% of Gd, it is identified peaks of cubic Gd 2 0 3 was found to be phase-separated. When the solid solution amount of Gd was 0%, the BaO peak was identified, and it was found that Ba 0 was phase-separated. As described above, according to this example, the amorphous composite oxide film of the present invention can be obtained without phase separation by setting the Gd solid solution amount to 0.5% or more and 20% or less in element ratio. Make sure § L, L / L o
(実施例 3)  (Example 3)
本実施例では、第 1の金属元素として Z r、第 2の金属元素として A 1を選び、 第 3の金属元素として L aとした、 Z r— A 1— L a複合酸化膜をゲ一ト絶縁膜 に用いた MI S型トランジスタを作成した。  In this embodiment, a Zr—A1-La composite oxide film, in which Zr is selected as the first metal element, A1 is selected as the second metal element, and La is set as the third metal element, is used. The MIS transistor used for the gate insulating film was fabricated.
実施例 1と同様に、 素子分離領域 102は S i単結晶基板 101に深さ約 0. 4〃mの溝を形成した後に CVD法により、 S i 02膜を全面成膜し、 次に CM Pで平坦化させて作製した。 As in the first embodiment, the device isolation region 102 is formed on the Si single crystal substrate 101 with a groove having a depth of about 0.4 μm, and then a SiO 2 film is entirely formed by the CVD method. It was manufactured by flattening with CMP.
また、 実施例 1と同様に、 希 HF処理により基板表面の S i02膜を除去した。 ゲ一卜絶縁膜 103である Zr— Al— L a複合酸ィ匕膜をスパヅ夕法により作製 した。 スパヅ夕夕一ゲヅトには、 組成比を Z r: Al : La=17 : 80 : 3と した Zr— A 1— La複合酸ィ匕物焼結体を用いた。 不活性雰囲気中、 100°Cで 成膜することにより、 物理膜厚 3〜1511111の21«_八1ー1^複合酸化膜を得 た。 なお、 成膜後には、 窒素雰囲気中、 800°Cでの後熱処理を行った。 Further, as in Example 1, the SiO 2 film on the substrate surface was removed by dilute HF treatment. A Zr—Al—La composite oxide film, which was the gate insulating film 103, was formed by a sputtering method. For the gate of the spa, a Zr-A1-La composite sintered body having a composition ratio of Zr: Al: La = 17: 80: 3 was used. By forming a film at 100 ° C in an inert atmosphere, a 21 «_81-1 ^^ composite oxide film with a physical film thickness of 3 to 1511111 is obtained. Was. After the film formation, a post heat treatment was performed at 800 ° C. in a nitrogen atmosphere.
次に、 実施例 1と同様にして、 MI S型トランジスタ素子を作製した。 片方の A1配線 108をアースにして、 ゲート電極 1◦ 4に— 2〜2 V変化させた場合 の C— V特性より EOTを算出した。 その結果を図 7に示す。 3〜15nm膜厚 間で最小 2乗法から求めた勾配は誘電率を意味し、 約 17であった。 また物理膜 厚がゼロの場合に EOTが約 0.2 nmであり、ゲート絶縁膜 103と S i単結晶 基板 101界面に低誘電率な S i02層の形成を薄く抑えることができた。 さら に、 100時間大気中に放置した後に C— V特性を評価したところ、 特性の劣化 は認められなかった。 Next, a MIS transistor element was manufactured in the same manner as in Example 1. EOT was calculated from the C-V characteristic when one A1 wiring 108 was grounded and the gate electrode 1◦4 was changed by 2 to 2 V. Figure 7 shows the results. The gradient obtained from the least squares method between 3 and 15 nm thickness means the dielectric constant and was about 17. In addition, when the physical film thickness was zero, the EOT was about 0.2 nm, and the formation of a low dielectric constant SiO 2 layer at the interface between the gate insulating film 103 and the Si single crystal substrate 101 could be suppressed. Furthermore, when the C-V characteristics were evaluated after being left in the air for 100 hours, no deterioration of the characteristics was observed.
比較例として、 組成比を Zr : Al = 20 : 80とした Z r— A 1複合酸化物 焼結体を夕一ゲットとして成膜した Z r— A 1複合酸ィ匕膜 3〜 15 nmに対して、 同様の C— V特性より EOTを算出した。 その結果を図 7にまとめて示す。 3〜 15 nm膜厚間で誘電率は約 12であった。 また、 物理膜厚がゼロの場合に E 0 Tが約 0.6nmであり、 31界面に0. 6 nmの S i 02層が形成した。 このよ うに、 Laを固溶した場合と比較して、 比誘電率及び酸素バリア性は小さいこと が分かった。 As a comparative example, a Zr—A1 composite oxide film having a composition ratio of Zr: Al = 20: 80 and a sintered body of Zr—A1 composite oxide film formed as an overnight getter was formed to 3 to 15 nm. On the other hand, EOT was calculated from the same CV characteristics. The results are summarized in FIG. The dielectric constant was about 12 between 3 and 15 nm thickness. Also, the physical thickness is E 0 T is approximately 0.6nm in the case of zero, S i 0 2 layers of 0. 6 nm to 31 interface was formed. Thus, it was found that the relative dielectric constant and the oxygen barrier property were smaller than when La was dissolved.
以上のように、 Z r— A 1複合酸化膜中に L aを固溶することによって膜を緻 密化した結果、 ゲート絶縁膜として良好な特性が得られることが確認できた。  As described above, as a result of densifying the film by dissolving La in the Zr—A1 composite oxide film, it was confirmed that good characteristics as a gate insulating film were obtained.
(実施例 4)  (Example 4)
本実施例では、第 1の金属元素として T i、第 2の金属元素として S iを選び、 T i— S i複合酸ィ匕窒ィ匕膜をゲート絶縁膜に用いた MI S型トランジスタを作成 した。  In the present embodiment, a MIS transistor using Ti as the first metal element and Si as the second metal element, and using a Ti—Si composite oxide film as a gate insulating film is described. Created.
実施例 1と同様に、 素子分離領域 102は S i単結晶基板 101に深さ約 0. 4 zmの溝を形成した後に CVD法により、 Si02膜を全面成膜し、 次に CM Pで平坦化させて作製した。 As in Example 1, the element isolation region 102 by the CVD method after forming a groove having a depth of about 0. 4 zm to S i monocrystalline substrate 101, the entire surface forming a Si0 2 film, then with CM P It was manufactured by flattening.
また、実施例 1と同様に、希 HF処理により基板表面の S i 02膜を除去した。 ゲ一ト絶縁膜 103である Ti— S i複合酸ィ匕窒ィ匕膜を作成する上で、 まず T i — S i複合酸ィ匕膜を CVD法により作製した。 Ti及び Si原料には、 それそれ イソプロポキサイド 'チタニウム (Ti (O-i Pr) 2)及び Si (0— i P r) 4原料を用いた。 T i— S i複合酸化膜の組成は Τ i : Si = 10 : 90と した。 Further, as in Example 1, the Si 02 film on the substrate surface was removed by dilute HF treatment. In forming the Ti—Si composite oxide film as the gate insulating film 103, a Ti—Si composite oxide film was first produced by a CVD method. Isopropoxide 'titanium (Ti (OiPr) 2 ) and Si (0-iPr) 4 raw materials were used as Ti and Si raw materials, respectively. The composition of the Ti—Si composite oxide film was Τ i: Si = 10: 90.
サンプルを大気中に暴露する前に、 T i— S i複合酸ィ匕膜をアンモニアガス雰 囲気中 700°Cの窒化処理を行い、 本発明のゲート絶縁膜 103である Ti一 S i複合酸ィ匕窒ィ匕膜を作成した。 膜厚は 5〜25nmとした。 AESにより、 窒素 の含有量を測定したところ、 酸素と窒素の元素量に対して窒素は約 22%であつ た。  Before exposing the sample to the atmosphere, the Ti—Si composite oxide film is subjected to a nitriding treatment at 700 ° C. in an ammonia gas atmosphere to obtain a Ti-Si composite acid film as the gate insulating film 103 of the present invention. A film was prepared. The film thickness was 5 to 25 nm. The nitrogen content was measured by AES. The nitrogen content was about 22% of the elemental amounts of oxygen and nitrogen.
次に、 実施例 1及び実施例 3と同様にして MI S型トランジスタ素子を作製し た。 片方の A 1配線 108をアースにして、 ゲート電極 104に _2〜2 V変化 させた場合の C一 V特性より EOTを算出した。 その結果を図 8に示す。 5〜2 5 nm膜厚間で最小 2乗法から求めた勾配は誘電率を意味し、 約 15であった。 また物理膜厚がゼロの場合に EOTが約 0.3nmであり、ゲート絶縁膜 103と S i単結晶基板 101界面に低誘電率な S i02層の形成を薄く抑えることがで きた。 さらに、 100時間大気中に放置した後に C一 V特性を評価したところ、 特性の劣化は認められなかつた。 Next, a MIS transistor device was manufactured in the same manner as in Example 1 and Example 3. EOT was calculated from the C-V characteristic when one of the A1 wirings 108 was grounded and the gate electrode 104 was changed by _2 to 2 V. Figure 8 shows the results. The gradient determined by the least squares method between the film thicknesses of 5 to 25 nm means the dielectric constant and was about 15. Further, when the physical film thickness is zero, the EOT is about 0.3 nm, and the formation of a low dielectric constant SiO 2 layer at the interface between the gate insulating film 103 and the Si single crystal substrate 101 can be suppressed. Furthermore, when the C-V characteristics were evaluated after being left in the air for 100 hours, no deterioration of the characteristics was observed.
比較例として、 窒化処理を行う前の T i— S i複合酸化膜に対して、 同様の C —V特性より EOTを算出した。 その結果を図 8にまとめて示す。 5〜25nm 膜厚間で誘電率は約 12であった。また、物理膜厚がゼロの場合に EOTが約 0. 5nmであり、 Si界面に 0. 5 nmの S i 02層が形成した。 このように、 窒 素を固溶した場合と比較して、 比誘電率及び酸素バリア性は小さいことが分かつAs a comparative example, EOT was calculated from the similar C—V characteristics of the Ti—Si composite oxide film before performing the nitriding treatment. The results are summarized in FIG. The dielectric constant was about 12 between 5 and 25 nm thickness. Also, the physical thickness is EOT of about 0. 5 nm in the case of zero, S i 0 2 layers of 0. 5 nm to Si interface formed. Thus, it is clear that the relative permittivity and oxygen barrier properties are smaller than when nitrogen is dissolved.
Ί o Ί o
以上のように、 T i一 S i複合酸ィ匕膜中の酸素を窒素に置換することで膜を緻 密化した結果、 ゲ一ト絶縁膜として良好な特性が得られることが確認できた。 (実施例 5 ) As described above, it was confirmed that as a result of densifying the film by replacing oxygen in the Ti-Si composite oxide film with nitrogen, good characteristics as a gate insulating film were obtained. . (Example 5)
本実施例では、 第 1の金属元素として Hf、 第 2の金属元素として S i、 及び 第 3の金属元素として N dから構成される非晶質な複合酸化膜をゲ一ト絶縁膜に 用いた MI S型トランジスタを作成した  In this embodiment, an amorphous composite oxide film composed of Hf as the first metal element, Si as the second metal element, and Nd as the third metal element is used for the gate insulating film. MIS type transistor was created
実施例 1と同様に、 素子分離領域 102は S i単結晶基板 101に深さ約 0. 4 /mの溝を形成した後に CVD法により、 S i02膜を全面成膜して、 次に CM Pで平坦化させて作製した。 As in Example 1, the device isolation region 102 is formed by forming a groove having a depth of about 0.4 / m in the Si single crystal substrate 101, and then forming an entire SiO 2 film by a CVD method. It was manufactured by flattening with CMP.
希 H F処理により基板表面のシリコン酸化膜を除去した後、 N H 3ガス中 70 0°C30秒の熱処理によって、 シリコン基板表面にシリコン窒化膜を形成した。 次に、 Hf と S iと Ndからなる混合層を成膜した。 成膜には、 3元系イオン ビ一ムスパッ夕法を用いて行った。 Hfターゲット、 Si夕一ゲヅト及び Nd夕 —ゲヅトをセットし、 3つのイオン源を同時に使用し形成した。 ターゲットを照 射するイオンビームの出力を変化させることによって、 Hf : Si: Ndの元素 比が 10 : 85 : 5である混合層を作製した。得られた混合層を、酸素雰囲気中、 350°Cで熱処理を行い、 非晶質な Hf— S i— Nd複合酸ィ匕膜からなるゲート 絶縁膜 103を作製した。  After removing the silicon oxide film on the substrate surface by dilute HF treatment, a silicon nitride film was formed on the silicon substrate surface by a heat treatment at 700 ° C. for 30 seconds in NH 3 gas. Next, a mixed layer composed of Hf, Si, and Nd was formed. The film was formed using a ternary ion beam sputtering method. The Hf target, the Si gate, and the Nd gate were set, and three ion sources were used simultaneously. By changing the output of the ion beam irradiating the target, a mixed layer with an Hf: Si: Nd element ratio of 10: 85: 5 was fabricated. The obtained mixed layer was heat-treated at 350 ° C. in an oxygen atmosphere to produce a gate insulating film 103 made of an amorphous Hf—Si—Nd composite oxide film.
以下、 実施例 1と同様にして、 MI S型トランジスタ素子を作製した。 片方の アルミ配線 109をァ一スにして、 ゲート電極 105に— 2〜2Vの電圧を変化 させた場合の C— V特性より EOT (Si02換算膜厚) を算出した。 膜厚 10 〜4 Onmのゲート絶縁膜に対して評価を行った。 非晶質な H f— S i— N d複 合酸化膜の比誘電率を求めた結果、 約 16であった。 また、 物理膜厚がゼロの場 合に EOTが約 0.2 nmであった。  Thereafter, in the same manner as in Example 1, a MIS transistor element was manufactured. The EOT (Si02 equivalent film thickness) was calculated from the C-V characteristics when one of the aluminum wirings 109 was used as a ground and a voltage of −2 to 2 V was applied to the gate electrode 105. An evaluation was performed on a gate insulating film having a thickness of 10 to 4 Onm. The relative dielectric constant of the amorphous Hf—Si—Nd composite oxide film was found to be about 16. The EOT was about 0.2 nm when the physical film thickness was zero.
本実施例より、 Hfと Siと Ndからなる混合層を形成し、 前記混合層を酸化 したゲート絶縁膜を作製することによって、 良好なゲート絶縁膜が得られること を確認した。  From this example, it was confirmed that a good gate insulating film could be obtained by forming a mixed layer composed of Hf, Si, and Nd and oxidizing the mixed layer to form a gate insulating film.
また、 非晶質な H f— S i— N d複合酸化膜とシリコン基板の間にシリコン窒 化膜を挟んだ構造にすることで、 シリコン基板の酸化を抑制できることも確認し In addition, silicon nitride is located between the amorphous Hf—Si—Nd composite oxide film and the silicon substrate. It was also confirmed that the oxidation of the silicon substrate could be suppressed by adopting a structure sandwiching the oxide film.
産業上の利用可能性 Industrial applicability
以上のように、 本発明によれば、 シリコン単結晶基板を母材とした M I S型ト ランジス夕素子において、 ゲート絶縁膜として、 3種類の金属元素から構成され る非晶質な複合酸化膜、 特に、 比誘電率 2 0以上の金属酸化物を構成する第 1の 金属元素と、 比誘電率 2 0未満の金属酸化物を構成する第 2の金属元素と、 前記 第 1の金属元素と前記第 2の金属元素から構成される複合酸化物を緻密化する第 3の金属元素から構成される非晶質な複合酸ィ匕膜とすることで、 緻密化したゲ一 ト絶縁膜が得られるために、 第 1の金属元素酸化物の相分離に伴う膜質の劣化を 抑制し、かつ酸素バリア性を向上した半導体装置を提供することができた。また、 本発明によって形成したゲート絶縁膜を用いることで、 ゲート長 0 . l ^m以下 の M I Sトランジスタを提供することができた。  As described above, according to the present invention, in a MIS type transistor device using a silicon single crystal substrate as a base material, an amorphous composite oxide film composed of three kinds of metal elements is used as a gate insulating film, In particular, a first metal element constituting a metal oxide having a relative permittivity of 20 or more, a second metal element constituting a metal oxide having a relative permittivity of less than 20; the first metal element; By forming an amorphous composite oxide film composed of the third metal element that densifies the composite oxide composed of the second metal element, a dense gate insulating film can be obtained. As a result, it was possible to provide a semiconductor device in which the deterioration of the film quality due to the phase separation of the first metal element oxide was suppressed and the oxygen barrier property was improved. Further, by using the gate insulating film formed according to the present invention, a MIS transistor having a gate length of 0.1 m or less could be provided.

Claims

請 求 の 範 囲 The scope of the claims
1 . シリコン基板上にゲ一ト絶縁膜を有する半導体装置において、 前記ゲ一ト 絶縁膜は、 比誘電率の低い第 1の金属元素を主成分とし、 該第 1の金属元素より 比誘電率が高くその金属元素に固溶する第 2の金属元素と、 前記第 1の金属元素 と第 2の金属元素から構成される複合酸化物の相分離を抑制する第 3の金属元素 を含む非晶質な複合酸ィ匕膜であることを特徴とする半導体装置。 1. In a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film mainly includes a first metal element having a low relative dielectric constant, and has a relative dielectric constant higher than that of the first metal element. Containing a second metal element which is highly soluble in the metal element and a third metal element which suppresses phase separation of a composite oxide composed of the first metal element and the second metal element A semiconductor device characterized by a high quality composite oxide film.
2 . シリコン基板上にゲ一ト絶縁膜を有する半導体装置において、 前記ゲ一ト 絶縁膜は、 比誘電率 2 0以上の金属酸化物を構成する第 1の金属元素と、 比誘電 率 2 0未満の金属酸化物を構成する第 2の金属元素と、 前記第 1の金属元素と前 記第 2の金属元素から構成される複合酸化物を緻密化する第 3の金属元素とを含 む非晶質な複合酸ィ匕膜であることを特徴とする半導体装置。  2. In a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film includes a first metal element constituting a metal oxide having a relative dielectric constant of 20 or more, and a relative dielectric constant of 20. A second metal element constituting a metal oxide less than, and a third metal element for densifying a composite oxide composed of the first metal element and the second metal element. A semiconductor device comprising a crystalline composite oxide film.
3 . シリコン基板上にゲート絶縁膜を有する半導体装置において、 前記ゲ一ト 絶縁膜は、 比誘電率 3 0以上の金属酸化物を構成する第 1の金属元素と、 比誘電 率 3 0未満の金属酸化物を構成する第 2の金属元素と、 前記第 1の金属元素と前 記第 2の金属元素から構成される複合酸化物を緻密化する第 3の金属元素とを含 む非晶質な複合酸ィ匕膜であることを特徴とする半導体装置。  3. In a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film comprises a first metal element forming a metal oxide having a relative dielectric constant of 30 or more, and a relative dielectric constant of less than 30. An amorphous material containing a second metal element constituting a metal oxide, and a third metal element for densifying a composite oxide composed of the first metal element and the second metal element A semiconductor device characterized by a complex oxide film.
4 . シリコン基板上にゲ一ト絶縁膜を有する半導体装置において、 前記ゲ一ト 絶縁膜は比誘電率 2 0以上の金属酸化物を構成する第 1の金属元素と、 比誘電率 2 0未満の金属酸ィ匕物を構成する第 2の金属元素とを含む非晶質な複合酸化窒化 膜であることを特徴とする半導体装置。  4. In a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film has a relative permittivity of less than 20 and a first metal element constituting a metal oxide having a relative permittivity of 20 or more. A semiconductor device characterized by being an amorphous composite oxynitride film containing the second metal element constituting the metal oxide film.
5 . シリコン基板上にゲ一ト絶縁膜を有する半導体装置において、 前記ゲ一ト 絶縁膜は比誘電率 3 0以上の金属酸化物を構成する第 1の金属元素と、 比誘電率 3 0未満の金属酸化物を構成する第 2の金属元素とを含む非晶質な複合酸化窒ィ匕 膜であることを特徴とする半導体装置。 5. In a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film has a relative permittivity of less than 30 and a first metal element constituting a metal oxide having a relative permittivity of 30 or more. A semiconductor device comprising an amorphous composite nitrided oxide film containing a second metal element constituting the metal oxide.
6. 請求項 4又は 5において、 前記複合酸化窒化膜中の窒素元素含有量が、 前 記ゲート絶縁膜中の全非金属元素量に対して元素比で 0. 5〜50%であること を特徴とする半導体装置。 6. The method according to claim 4, wherein the nitrogen element content in the composite oxynitride film is 0.5 to 50% in element ratio with respect to the total nonmetallic element amount in the gate insulating film. Characteristic semiconductor device.
7. 請求項 1〜6のいずれかにおいて、 前記第 1の金属元素が、 Ba、 Nb、 W、 Ta、 Ti、 Zr、 H f及び P bの 1種以上であることを特徴とする半導体  7. The semiconductor according to any one of claims 1 to 6, wherein the first metal element is one or more of Ba, Nb, W, Ta, Ti, Zr, Hf, and Pb.
8. 請求項 1〜7のいずれかにおいて、 前記第 2の金属元素が、 Si及び A1 の 1種以上であることを特徴とする半導体装置。 8. The semiconductor device according to claim 1, wherein the second metal element is at least one of Si and A1.
9. 請求項 1〜3、 7、 8のいずれかにおいて、 前記第 3の金属元素が希土類 元素であることを特徴とする半導体装置。  9. The semiconductor device according to any one of claims 1 to 3, 7, and 8, wherein the third metal element is a rare earth element.
10. 請求項 9において、 前記第 3の金属元素の含有量が、 前記ゲート絶縁膜 中の全金属元素量に対して元素比で 0. 5〜20%であることを特徴とする半導  10. The semiconductor according to claim 9, wherein the content of the third metal element is 0.5 to 20% in element ratio with respect to the total metal element content in the gate insulating film.
11. シリコン基板上にゲ一ト絶縁膜を有する半導体装置において、 前記ゲ一 ト絶縁膜は、 元素比で 0. 5〜20%の希土類元素を含む非晶質な複合酸化膜で あることを特徴とする半導体装置。 11. In a semiconductor device having a gate insulating film on a silicon substrate, the gate insulating film is an amorphous composite oxide film containing a rare earth element having an element ratio of 0.5 to 20%. Characteristic semiconductor device.
12. 請求項 1〜3、 7〜11のいずれかにおいて、 前記希土類元素が、 Y, Ce, P r , Nd、 Pm、 Sm, Eu, Gd, Tb, Dy, Ho, E r3 Ym, Yb及び Lnの 1種以上からなることを特徴とする半導体装置。 12. claims 1-3, in any of 7-11, wherein the rare earth element, Y, Ce, P r, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, E r 3 Ym, Yb And a semiconductor device comprising at least one of Ln.
13. 請求項 1〜 12のいずれかにおいて、 前記ゲ一ト絶縁膜と前記シリコン基 板との界面に、 シリコン酸化膜又はシリコン窒化膜から構成される界面制御層を 具備することを特徴とする半導体装置。  13. The method according to claim 1, further comprising an interface control layer formed of a silicon oxide film or a silicon nitride film at an interface between the gate insulating film and the silicon substrate. Semiconductor device.
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