JP2002299607A - Misfet and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MISFET(metal insulator semiconductor field effect transistor) which is capable of preventing the diffusion of impurities and metal atoms from a gate electrode even if a metal oxide which can earn a physical film thickness is used as a gate insulation film, and is also capable of suppressing the decrease in flat band voltage shift and mobility, and also to provide a method of manufacturing the same. SOLUTION: The MISFET comprises a silicon substrate 101, a gate insulation film 103 which is formed of a metal oxide and includes nitrogen at least in a part of it and is formed on the silicon substrate 101, and a gate electrode 104 formed on the gate insulation film 103. In the gate insulation film 103, the content of nitrogen near an interface with the silicon substrate is higher than that in the other parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MIS field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Up to now, high speed and high integration of a semiconductor integrated circuit (LSI) have been promoted by miniaturization of a MIS field effect transistor according to a scaling rule. The scaling rule is to simultaneously reduce the height and lateral dimensions of the device, such as the insulating film and gate length of the MIS field-effect transistor, to maintain normal switching characteristics, and to increase the speed and integration. It is a method of aiming.

According to this scaling rule, the year 200
In the next generation MIS field effect transistor after one year,
A capacitance equivalent to a gate insulating film capacitance of ₂ nm or less in terms of SiO ₂ is required. However, in the case of SiO ₂ which has been conventionally used as a gate insulating film, a tunnel current flows directly at a thickness of 2 nm or less, so that a leak current cannot be suppressed and a problem such as an increase in power consumption occurs.

Therefore, in the next-generation MIS type field effect transistor, a material having a higher dielectric constant than SiO ₂ is used as the gate insulating film, and the physical film thickness is increased while the equivalent silicon oxide film effective film thickness is suppressed to 2 nm or less. Attempts have been made to reduce leakage current.

In addition, the MIS field-effect transistor has a problem of a penetration voltage in addition to suppressing a leakage current. The penetration voltage means that when polycrystalline silicon is used for a gate electrode, impurities such as phosphorus (P) and boron (B), which are dopants of polycrystalline silicon, penetrate through a gate insulating film and diffuse into a channel region. The problem is that the threshold voltage fluctuates due to the This phenomenon has a problem in that since heat is generated during operation of the element, the impurities are diffused with time and the threshold value is changed, thereby deteriorating the reliability.

As a method of solving the problem of the penetration voltage and a means of reducing the resistance of the gate electrode,
In the next generation MIS transistor, the use of metal for the gate electrode is being studied. However, when a metal is used for the gate electrode, metal atoms diffuse from the gate electrode into the gate insulating film or the interface with the silicon substrate, generating fixed charges in the gate insulating film, causing a flat band voltage shift or movement. Degradation is a problem. In particular, when a metal oxide is used for the gate insulating film, the metal oxide is SiO ₂
Since the degree of diffusion of metal atoms is much higher than that, a large amount of fixed charges are generated in the gate insulating film, which is a very serious problem.

[0007]

As described above, the next-generation MIS field-effect transistor has various problems that must be solved in order to advance the miniaturization.

The present invention has been made in view of this problem, and it is possible to prevent diffusion of impurities and metal atoms from a gate electrode even when a metal oxide which increases the physical film thickness is used as a gate insulating film. An object of the present invention is to provide a MIS field-effect transistor capable of suppressing a flat band voltage shift and a decrease in mobility, and a method for manufacturing the same.

[0009]

According to the present invention, the metal oxide in the gate insulating film contains nitrogen to prevent diffusion of impurities and metal from the gate electrode, and at the same time, to form nitrogen at the interface with the silicon substrate. Is not contained, thereby improving the electrical characteristics of the transistor.

Accordingly, the present invention provides a silicon substrate, a gate insulating film formed on the silicon substrate and comprising a metal oxide film or a metal oxynitride film containing nitrogen at least in part, and the gate insulating film. A gate electrode formed thereon, wherein the nitrogen content of the metal oxide film or the metal oxynitride film in the vicinity of the interface with the silicon substrate is lower than other portions of the gate insulating film. A featured MIS field-effect transistor is provided.

At this time, the nitrogen content of the gate insulating film near the interface with the silicon substrate is 0.1 atomic%.
The following is preferred.

It is preferable that a portion of the gate insulating film near the interface with the silicon substrate has a thickness of 0.6 nm or less from the silicon substrate.

The nitrogen content of the gate insulating film having a thickness of 0.6 nm or less from the interface with the gate electrode is 1%.
It is preferably 0 atomic% or more.

According to the present invention, there is provided a silicon substrate, a gate insulating film formed on the silicon substrate and made of a metal oxide containing nitrogen at least partially, and a gate electrode formed on the gate insulating film. A thickness of 0.6 from the interface with the silicon substrate in the gate insulating film.
The nitrogen content in a region of nm is 0.1 atomic% or less, and the nitrogen content in a region of the gate insulating film having a thickness of at least 0.6 nm from an interface with the gate electrode is 10 atomic% or more. A MIS field-effect transistor is provided.

At this time, it is preferable that the gate insulating film contains silicon.

Further, the present invention provides a silicon substrate, a gate insulating film made of a metal oxide formed on the silicon substrate, a silicon nitride film formed on the gate insulating film, and a silicon nitride film formed on the silicon nitride film. And a gate electrode formed on the MIS-type field effect transistor.

At this time, the metal oxide is Zr, Hf,
It is preferable to contain any of La, Ce, Ti, Al, Y, Mg, Ta, and Bi. Particularly desirable is Zr, H
f, La, Ce, Y, Mg, Ta, or Bi.

Preferably, nitrogen is introduced into the metal oxide by heat treatment in a nitrogen atmosphere or exposure to excited nitrogen.

Preferably, before forming the gate electrode, nitrogen is introduced into the metal oxide by heat treatment in a nitrogen atmosphere or exposure to excited nitrogen.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION First, A
The diffusion degree of boron (B) as an impurity in Al ₂ O ₃ and AlN which is an insulating film containing nitrogen is shown at 800 ° C. to 1200 ° C. Degree of diffusion of B in Al ₂ O ₃ film (800 ° C. to 1200 ° C.) =
2-6 × 10 ⁻⁵ B diffusivity in AlN film (800 ° C. to 1200 ° C.) = 1
To 6 × 10 ^-6 insulating film containing such a nitrogen, compared with the insulating film not containing nitrogen, diffusion of the impurity is sufficiently small.

Al ₂ O ₃ as a metal oxide and Al ³⁺ as a metal atom in AlN as a metal oxynitride
1 shows the diffusion coefficient at 1700 ° C. Diffusion coefficient of Al ³⁺ in Al ₂ O ₃ film (1700 ° C.) =
1.4 × 10 ⁻¹¹ Diffusion coefficient of Al ^{3+ in} the AlN film (1700 ° C.) = 4 ×
10 ^-13 As described above, it can be seen that the nitrogen-containing insulating film has a sufficiently small diffusion degree of metal atoms as compared with the nitrogen-free insulating film. Therefore, in the present invention, diffusion of elements (impurities and metal atoms) constituting a gate electrode is prevented by forming a layer containing nitrogen in a part of a gate insulating film made of a metal oxide film or a metal oxynitride film. It was used as a diffusion barrier layer.

It has also been found that when the nitrogen concentration in the metal oxide film or the metal oxynitride film is increased, the degree of diffusion of impurities and metal atoms is reduced, and the diffusion barrier property is improved. However, when nitrogen is present in the vicinity of the silicon substrate interface of the gate insulating film, a defect is easily formed, and the charge trapped by the defect tends to deteriorate the silicon substrate interface characteristic.

Therefore, it is necessary to make the concentration of nitrogen extremely low on the surface of the silicon substrate. Experiments from this viewpoint have revealed that the nitrogen content must be lower than the detection limit of a general analyzer such as XPS in order not to cause deterioration of the interface characteristics. Therefore, in the present invention, the nitrogen content in the vicinity of the interface with the silicon substrate in the gate insulating film made of a metal oxide film or a metal oxynitride film containing nitrogen needs to be 0.1 atomic% or less. More preferably, it is 0.01 atomic% or less. Further, when the improvement of the interface characteristics is required, the content is desirably 0.001 atomic% or less.

Further, the range from the interface between the gate insulating film and the silicon substrate where nitrogen affects the interface was examined.

FIG. 1 shows that a gate insulating film made of a zirconium oxide film containing nitrogen is formed on a silicon substrate, and a horizontal axis represents a distance from the surface of the silicon substrate to a position where the nitrogen content exceeds 0.1 atomic%. It is the figure which made the average coordination number in the interface structure of the silicon substrate and gate insulating film of 100) plane the vertical axis | shaft.

As is clear from FIG. 1, when the position where the nitrogen content exceeds 0.1 atomic% is 0.6 nm or more away from the silicon substrate surface, the average coordination number starts to decrease gradually. This is due to the theory of Philips that the closer the average coordination number (NaV.) Is to 2.76, the more stable it is [J. Vac. Sci. Tech B17 (4) p1
803 (1999)]. If the average coordination number is 2.9 or more, the interface structure becomes unstable and an interface state is generated. Therefore, in the present invention, in a gate insulating film made of a metal oxide film or a metal oxynitride film containing nitrogen, when the thickness is 0.6 nm from the interface with the silicon substrate, the nitrogen content is 0.1 atomic% or less. Is desirable. In addition, the region where the nitrogen content is 0.1 atomic% or less is preferable when the thickness is 1 nm or more from the interface with the silicon substrate, because the average coordination number starts to decrease more gradually. Further, when the distance is 1.5 nm or more, the average coordination number does not change at the minimum value. Therefore, the distance is more preferably 1.5 nm or more.

FIG. 2 shows a metal oxide film (Z
rO ₂ ) and a gate insulating film made of a metal nitride film (ZrN) formed on the metal oxide film. The horizontal axis represents the distance from the silicon substrate surface to the interface between the metal nitride film and the metal oxide film. , The vertical axis represents the average coordination number in the interface structure between the silicon substrate and the metal oxide film on the (100) plane.

As shown in FIG. 2, the distance between the interface between the silicon substrate and the metal oxide film and the interface between the metal oxide film and the metal nitride film starts to decrease gradually at 0.6 nm or more, and gradually decreases at 1 nm or more. At first, if the nitrided layer is separated by 1.5 nm or more, it hardly changes. Therefore, in the case of this laminated structure,
It is sufficient that the distance between the interface between the silicon substrate and the metal oxide film and the interface between the metal oxide film and the metal nitride film is 0.6 nm or more. Further, when the thickness is desirably 1 nm or more, more desirably 1.5 nm or more, a stable structure can be obtained and good interface characteristics can be obtained.

FIG. 3 shows (a) a CV of a capacitor structure composed of a metal oxide film (Al ₂ O ₃ ) formed on a p-type silicon substrate and polysilicon formed on the metal oxide film.
Characteristics, (b) a metal oxide film (Al ₂ O ₃ ) formed on a p-type silicon substrate, a metal nitride film (AlN) formed on the metal oxide film, and a poly film formed on the metal nitride film 5 is a CV characteristic of a capacitor structure made of silicon.

As can be seen from FIG. 3, the one not containing nitrogen shown in (a) has a flat band shift (ΔVf
b) is about 0.68V. On the other hand, in the case where the diffusion barrier layer containing nitrogen shown in (b) exists, the flat band shift (ΔVfb) was about 0.15 V, and the flat band shift was a sufficiently small value. This is a result of suppressing the diffusion of phosphorus (P) contained in polysilicon by the diffusion barrier layer containing nitrogen, which indicates that a sufficient diffusion barrier property is obtained.

As described above, by providing a diffusion barrier layer made of a metal oxide containing nitrogen in the vicinity of an interface with a gate electrode in a gate insulating film made of a metal oxide, flat band shift can be reduced and good Silicon interface characteristics can be realized.

Further, after silicon is contained in the gate insulating film, a nitriding treatment is performed and nitrogen is added.
Due to the strong bond of -N, Si in the gate insulating film is absorbed, and the silicon content near the interface with the silicon substrate relatively increases. In this manner, in the vicinity of the interface with the silicon substrate, a metal oxide having good electrical characteristics and a high silicon content is obtained, and in the vicinity of the interface with the gate electrode, a metal oxide having a high nitrogen content for preventing diffusion is obtained. .

FIG. 4 is a cross-sectional view of a MIS field-effect transistor having a gate structure according to an embodiment of the present invention.

This MIS type field effect transistor has p
A silicon substrate 101, a gate insulating film 103 made of a metal oxide film containing nitrogen formed on the silicon substrate 101, and a gate electrode made of polysilicon formed on the gate insulating film. I have. The nitrogen content in the gate insulating film 103 at a thickness of 0.6 nm from the interface with the silicon substrate 101 is 0.1 atomic% or less. Further, the gate electrode 104 in the gate insulating film 103
The nitrogen content at a thickness of 0.6 nm from the interface with
atomic%. The gate electrode 104 is made of TiN, TaN, W, Nb, Z instead of polysilicon.
An electrode containing a metal such as r, Ru, and Ru oxide may be used.

Source / drain regions 105, which are diffusion layers into which n-type impurities have been introduced, are formed in the silicon substrate 101 at positions sandwiching the gate electrode 104.
A gate sidewall 106 made of a silicon nitride film is formed on a sidewall of the gate electrode 104. Reference numeral 107 denotes an interlayer insulating film made of a silicon oxide film, and an Al wiring 108 is connected to the gate electrode 104 and the source / drain region 105 through a contact hole provided in the interlayer insulating film 107. The formed MIS field-effect transistors are separated from each other by the element separation region 102.

The MIS field effect transistor was formed with a gate length of 50 nm, and its operation was confirmed.
The leakage current was suppressed, the flat band voltage shift was small, and the mobility was high.

FIG. 5 is a cross-sectional view for explaining a specific method of forming the gate insulating film 103 of the MIS field effect transistor shown in FIG.

First, as shown in FIG. 5A, a p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm.
A groove for element isolation is formed on the substrate 01 by reactive ion etching. Subsequently, for example, an element isolation region 102 is formed by embedding an LP (low pressure) -TEOS film.

Next, for example, as shown in FIG.
Using a laser ablation film forming method, for example, in an atmosphere with an oxygen partial pressure of 1 × 10 ⁴ Pa, a substrate temperature of 400 ° C. and Hf
A metal oxide 109 made of O ₂ is formed on the silicon substrate 101 with a thickness of 5 nm. By using a laser ablation film formation method, a film can be formed by photoexcitation of a source gas, in which each element has sufficient energy and the composition ratio between metal atoms and oxygen atoms is small. If there is no deviation in the composition ratio, dangling bonds hardly occur, which is advantageous for forming an insulating film with few defects.

In place of the laser ablation film forming method, the metal oxide 109 may be formed by using a sputter film forming method. In this case, for example, an oxygen partial pressure of 40 mtorr
r, at a substrate temperature of 300 ° C., a metal oxide 109 made of HfO ₂ was deposited to a thickness of 3 nm on a silicon substrate 101.
After being deposited thereon, it is desirable to densify the metal oxide 109 by annealing in an oxygen atmosphere at 600 ° C. to 800 ° C.

Further, the metal oxide 109 may be formed by an evaporation method. In this case, for example, the substrate temperature is 200 ° C.
Then, after depositing a metal oxide made of HfO ₂ to a thickness of 4 nm on the silicon substrate 101, it is desirable to densify the metal oxide 109 by annealing in an oxygen atmosphere at 600 ° C. to 800 ° C.

Further, the metal oxide 1 is formed by using the CVD film forming method.
09 may be formed. In this case, for example, C ₁₆ H
₃₆ Mixed gas of HfO ₄ gas and oxygen gas or HfCl
Mixed gas of ₄ gases, NH ₃ gas and oxygen gas or Hf
A mixed gas of Hf-containing gas and oxygen gas, such as a mixed gas of (SO ₄ ) ₂ gas, NH ₃ gas and oxygen gas, is 1 Pa to
The substrate is supplied and evacuated at a pressure of 10 ⁴ Pa and a flow rate of 1 sccm to 1000 sccm, and the substrate temperature is set to room temperature 800 ° C.
It is preferable that the metal oxide 109 is densified by annealing in an oxygen atmosphere at 600 ° C. to 900 ° C. after the deposition in a temperature range of the order.

Next, as shown in FIG.
By heating in an atmosphere of O gas and NH ₃ gas, the vicinity of the surface of the metal oxide 109 is nitrided to form a diffusion barrier layer 116. At this time, the nitrogen content of the diffusion barrier layer 116 was about 10 atomic%.

As a method of forming the diffusion barrier layer 116 made of a metal oxide containing nitrogen, nitrogen atoms are implanted only into the surface of the metal oxide 109 using a nitrogen implant, and the nitrogen is implanted by rapid heating (RTA). Atomic stabilization may be performed.

The surface of the metal oxide 109 may be irradiated with excited (radical) nitrogen to form the diffusion barrier layer 116. The method of irradiating with excited nitrogen is particularly effective when it is desirable to nitride only the surface layer because nitriding tends to proceed from the surface of the metal oxide 109 in particular.

As shown in FIG. 5D, instead of forming the diffusion barrier layer 116 made of a metal oxide containing nitrogen, 300 ° C. to 500 ° C. and a pressure of 1 Pa to 104 ° C.
In Pa, SiH ₄ gas diluted with nitrogen gas and NH
Using a mixed gas of _three gases, for example, a film thickness of 1 nm to ₃ nm
May be deposited as a diffusion barrier layer. At this time, the silicon nitride film 111
Is also effective in that nitrogen is diffused only to the surface of the metal oxide 109 by using rapid overheating (RTA) to cause segregation.

Further, a metal oxide such as HfN may be deposited instead of the silicon nitride film 111 by using sputtering, vapor deposition, laser ablation, or the like, and this may be used as a diffusion barrier layer.

Next, polysilicon is deposited by chemical vapor deposition.
A polysilicon film is deposited on the entire surface, and the polysilicon film is patterned.
To form a gate electrode 104. Then, for example, 4
At 50 ° C. and a pressure of 1 Pa to 104 Pa, with nitrogen gas
Diluted SiH₄Gas and NH ₃Using a gas mixture
For example, a CVD silicon nitride film of 5 nm to 200 nm
Is deposited.

The subsequent steps are performed, for example, at an accelerating voltage of 20 K in the same manner as in the manufacturing process of a normal MIS type field effect transistor.
Arsenic ions are implanted at an eV and a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 105. Subsequently, an interlayer insulating film 107 made of silicon oxide is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching to form a wiring 108. Through such steps, the MIS field effect transistor shown in FIG. 4 can be formed.

Next, referring to FIG. 6, the MIS shown in FIG.
Another manufacturing method for the gate insulating film 103 of the field effect transistor will be described. Here, silicon is contained in the metal oxide described with reference to FIG.

First, as shown in FIG. 6A, a p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm.
A groove for element isolation is formed on the substrate 01 by reactive ion etching. Subsequently, for example, an element isolation region 102 is formed by embedding an LP (low pressure) -TEOS film.

Next, as shown in FIG. 6B, for example,
Using a laser ablation film forming method, for example, in an atmosphere with an oxygen partial pressure of 1 × 10 ⁴ Pa, at a substrate temperature of 400 ° C.,
Using a target composed of f, Si, and oxygen atoms,
An Hf silicate oxide 113 is formed on the silicon substrate 101 with a thickness of 5 nm. By using a laser ablation film forming method, by optically exciting the source gas,
A film in which each element has sufficient energy and the composition ratio of metal atoms to oxygen atoms is small can be formed. If there is no deviation in the composition ratio, dangling bonds hardly occur, which is advantageous for forming an insulating film with few defects.

The metal silicate oxide 113 may be formed by a sputtering film forming method instead of the laser ablation film forming method. In this case, for example, oxygen partial pressure 4
After depositing Hf metal or Hf silicide or Hr silicate on the silicon substrate 101 at a substrate temperature of 300 ° C. in an atmosphere of 0 mtorr, annealing is performed in an oxygen atmosphere of 600 ° C. to 800 ° C. to form the Hf silicate oxide 11.
3 can be formed.

Further, the metal silicate oxide 113 may be formed by using an evaporation method. In this case, for example, at a substrate temperature of 200 ° C., Hf metal or Hf silicide is
m, deposited on the silicon substrate 101 at 600 ° C. to 8
Annealing is performed in an oxygen atmosphere at 00 ° C. to form the Hf silicate oxide 113.

Further, the metal silicate oxide 113 may be formed by using a CVD film forming method. In this case, for example,
A mixed gas of C ₁₆ H ₃₆ HfO ₄ gas, monosilane (SiH ₄ ) gas and nitrogen gas, or HfCl ₄ gas and NH ₃
Mixed gas of gas and monosilane (SiH ₄ ) gas or Hf (SO ₄ ) ₂ gas, NH ₃ gas and monosilane (Si
A mixed gas of a gas containing Hf and a gas containing silicon, such as a mixed gas of H ₄ ) gas, is applied at a pressure of 1 Pa to 10 ⁴ Pa,
supplied at a flow rate of sccm to 1000 sccm,
After evacuation and deposition at a substrate temperature in a temperature range of about 800 ° C., annealing is performed in an oxygen atmosphere at 600 ° C. to 900 ° C. to form the metal silicate oxide 113.

As another method of forming the metal silicate oxide film 113, as shown in FIG. 6C, the silicon substrate 101 is heated in an oxygen atmosphere, or BOX (combustion oxidation) or CVD is used. An SiO ₂ film having a thickness of about ₁ nm to ₄ nm is formed thereon. next,
For example, a film containing a metal element is deposited on the silicon substrate 101 by an evaporation method using an Hf metal target or a target containing at least Hf metal atoms and silicon atoms.

Thereafter, for example, a step of diffusing at least the metal element into the SiO ₂ film by heating at 400 ° C. to 900 ° C. in vacuum or nitrogen is performed, and at least Hf atom, silicon atom, oxygen The metal silicate oxide film 113 containing atoms may be formed.

After the metal silicate oxide film 113 is formed by the above steps, as shown in FIG. 6C, the metal silicate oxide film 113 is heated in an atmosphere of, for example, NO gas or NH ₃ gas. The diffusion barrier layer 116 is formed by nitriding the vicinity of the surface. At this time, the diffusion barrier layer 116
Had a nitrogen content of about 10 atomic%.

As a method for forming the diffusion barrier layer 116 made of a metal silicate oxide containing nitrogen,
Using nitrogen implantation, nitrogen atoms may be implanted only into the surface of the metal silicate oxide 113, and the nitrogen atoms may be stabilized by rapid heating (RTA).

Further, the surface of the metal silicate oxide 113 is irradiated with excited (radical) nitrogen to form the diffusion barrier layer 11.
6 may be formed. The method of irradiating with excited nitrogen is particularly effective when it is desirable to nitride only the surface layer because nitriding tends to proceed from the surface of the metal silicate oxide 113 in particular.

As shown in FIG. 6D, the diffusion barrier layer 11 made of a metal silicate oxide containing nitrogen is used.
6 instead of 300-500 ° C., pressure 1P
a to 104 Pa, SiH ₄ diluted with nitrogen gas
For example, using a mixed gas of gas and NH ₃ gas,
An m to 3 nm CVD silicon nitride film 111 may be deposited and used as a diffusion barrier layer. At this time, it is also effective to use a method in which nitrogen is diffused only into the surface of the metal silicate oxide 113 by using the rapid overheating (RTA) in the silicon nitride film 111 to cause segregation.

Further, a metal oxide such as HfN may be deposited instead of the silicon nitride film 111 by using sputtering, vapor deposition, laser ablation, or the like, and this may be used as a diffusion barrier layer.

Next, polysilicon is deposited by chemical vapor deposition.
A polysilicon film is deposited on the entire surface, and the polysilicon film is patterned.
To form a gate electrode 104. Then, for example, 4
At 50 ° C. and a pressure of 1 Pa to 104 Pa, with nitrogen gas
Diluted SiH₄Gas and NH ₃Using a gas mixture
For example, a CVD silicon nitride film of 5 nm to 200 nm
Is deposited.

The subsequent steps are performed, for example, at an accelerating voltage of 20 K, in the same manner as in a normal MIS type field effect transistor manufacturing process.
Arsenic ions are implanted at an eV and a dose of 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 105. Subsequently, an interlayer insulating film 107 made of silicon oxide is deposited on the entire surface by a chemical vapor deposition method.
A contact hole is opened at the bottom. Subsequently, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching to form a wiring 108. Through such steps, the MIS field effect transistor shown in FIG. 4 can be formed.

Although several embodiments of the present invention have been described above, the present invention is not limited to the above-described range.

For example, an insulating film is deposited by vapor deposition or sputtering using a target containing metal atoms and oxygen atoms while irradiating with excited oxygen, and then exposed to an atmosphere containing nitrogen atoms so that the surface of the gate insulating film is exposed to nitrogen. May be permeated.

Further, by forming a metal nitride film or a metal oxynitride film and ion-implanting oxygen at the interface with the silicon substrate and heating, the silicon substrate surface has a SiO ₂ / Si interface structure containing no nitrogen or A silicate / Si interface structure may be formed.

[0068]

As described above, according to the present invention, by forming a diffusion barrier layer containing nitrogen in a part of a gate insulating film made of a metal oxide, diffusion of impurities and metal atoms from a gate electrode can be achieved. MIS field effect transistor capable of preventing the occurrence of a flat band voltage shift and a decrease in mobility, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 shows a (100) plane in which a gate insulating film made of a zirconium oxide film containing nitrogen is formed on a silicon substrate, and a distance from a surface of the silicon substrate to a position where the nitrogen content exceeds 0.1 atomic% is abscissa. The vertical axis represents the average coordination number in the interface structure between the silicon substrate and the gate insulating film.

FIG. 2 shows a metal oxide film (ZrO ₂ ) on a silicon substrate
And a metal nitride film (Zr) formed on the metal oxide film.
N), a horizontal axis represents the distance from the surface of the silicon substrate to the interface between the metal nitride film and the metal oxide film, and the average in the interface structure between the (100) plane silicon substrate and the metal oxide film. The figure which made a coordinate number into a vertical axis | shaft.

FIG. 3A shows a CV characteristic of a metal oxide film (Al ₂ O ₃ ) formed on a p-type silicon substrate and a capacitor structure formed of polysilicon formed on the metal oxide film;
(B) Metal oxide film (Al) formed on p-type silicon substrate
₂ O ₃ ), a diagram showing CV characteristics of a capacitor structure composed of a metal nitride film (AlN) formed on the metal oxide film and polysilicon formed on the metal nitride film.

FIG. 4 is a cross-sectional view of a MIS field-effect transistor having a gate structure according to an embodiment of the present invention.

FIG. 5 is a sectional view for explaining a specific method for forming a gate insulating film of the MIS field-effect transistor according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the MIS field-effect transistor according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 102 ... Element isolation region 103 ... Gate insulating film 104 ... Gate electrode 105 ... Source / drain region 106 ... Metal oxide film containing nitrogen 107 ... Interlayer insulating film 108 ... Al wiring 109 ... Metal oxide film 111 ... film containing metal silicate oxide film 113 ... metal silicate oxide film 114 ... SiO ₂ film 115 ... gold containing a nitrogen-containing

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shin Fukushima 1 Tokoba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture F-term (reference) 4T104 5F058 BA01 BC02 BC03 BC04 BF02 BF12 BF17 BF22 BF23 BF24 BF27 BF29 BF30 BH03 BH04 5F140 AA06 AA19 AA24 AA28 AA39 BA01 BA20 BD01 BD04 BD07 BD11 BD12 BD15 BD17 BE05 BE09 BE10 BE13 BG BF BF BF BF BF BF BF BG BK25 BK29 CB04 CC03 CC12

Claims (10)

[Claims] 1. A silicon substrate, a gate insulating film formed of a metal oxide film or a metal oxynitride film containing nitrogen at least in part formed on the silicon substrate, and formed on the gate insulating film. A MIS comprising a gate electrode having a lower nitrogen content in the vicinity of the interface with the silicon substrate in the metal oxide film or the metal oxynitride film than in other portions of the gate insulating film. Type field effect transistor. 2. The MIS field-effect transistor according to claim 1, wherein the nitrogen content of the gate insulating film near the interface with the silicon substrate is 0.1 atomic% or less. 3. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of 0.6 n from the silicon substrate in the vicinity of the interface with the silicon substrate.
2. The MIS type field effect transistor according to claim 1, wherein m is equal to or less than m. 4. The method according to claim 1, wherein a nitrogen content of 0.6 nm or less in the gate insulating film from the interface with the gate electrode is 10 atom.
2. The MIS according to claim 1, wherein the MIS is not less than ic%.
Type field effect transistor. 5. A semiconductor device, comprising: a silicon substrate; a gate insulating film formed on the silicon substrate, the gate insulating film being made of a metal oxide containing nitrogen at least in part; and a gate electrode formed on the gate insulating film. The nitrogen content in the region of 0.6 nm in thickness from the interface with the silicon substrate in the gate insulating film is 0.1 atomic%.
And a nitrogen content of at least 10 atomic% in a region of the gate insulating film having a thickness of at least 0.6 nm from an interface with the gate electrode in the gate insulating film.
IS type field effect transistor. 6. The MIS field effect transistor according to claim 1, wherein said gate insulating film contains silicon. 7. A silicon substrate, a gate insulating film made of a metal oxide formed on the silicon substrate, a silicon nitride film formed on the gate insulating film, and a silicon nitride film formed on the silicon nitride film A MIS field-effect transistor comprising a gate electrode. 8. The method according to claim 1, wherein the metal oxide is Zr, Hf, La, C
8. The MIS field-effect transistor according to claim 1, comprising any one of e, Ti, Al, Y, Mg, Ta, and Bi. 9. The MIS type electric field according to claim 1, wherein nitrogen is introduced into said metal oxide by heat treatment in a nitrogen atmosphere or exposure to excited nitrogen. Method for manufacturing effect transistor. 10. The method according to claim 1, wherein before the gate electrode is formed, nitrogen is introduced into the metal oxide by heat treatment in a nitrogen atmosphere or exposure to excited nitrogen. The method for manufacturing a MIS field effect transistor according to any one of the above.