JP3637325B2 - Field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MIS field effect transistor using a silicate (silicate) made of silicon dioxide and a metal oxide as a gate insulating film.
[0002]
[Prior art]
High speed and high integration of LSI have been promoted by miniaturization of MOS devices according to the scaling rule. This scaling rule keeps the element characteristics normal and fine in miniaturization by simultaneously reducing the height and lateral dimensions of each part of the MOS device, such as the thickness of the insulating film and the gate length. It is possible to raise.
[0003]
In the next-generation MOS transistor, a film thickness of 2 nm or less is required as the SiO ₂ gate insulating film because of the required gate insulating film capacitance. However, SiO ₂ that has been conventionally used as a gate insulating film has such a thickness that a tunnel current starts to flow directly in this film thickness region, so that leakage current cannot be suppressed and problems such as increase in power consumption cannot be avoided. . Therefore, recently, in the next generation MOS transistor, a material having a dielectric constant higher than that of SiO ₂ is used for the gate insulating film, and the effective film thickness in terms of silicon oxide film is suppressed to 2 nm or less, and the physical film thickness is increased to increase the leakage current. Attempts have been made to suppress this.
[0004]
Alternatively the insulating film material of SiO _2, silicate of SiO ₂ and metal oxides (silicates) material have been studied. However, in this type of material, fine crystals are precipitated in the gate insulating film made of silicate in a high temperature heat treatment process essential for a normal transistor manufacturing process, such as an impurity activation process of a diffusion layer, and the gate. There is a concern that the dielectric constant of the insulating film becomes non-uniform depending on the location.
[0005]
FIG. 8 is an electron micrograph before and after performing heat treatment at 1000 ° C. for 30 seconds necessary for impurity activation treatment of the diffusion layer of the transistor using Zr silicate for the gate insulating film. FIG. 8A is a cross-sectional structure photograph before the heat treatment, and is a homogeneous film before the heat treatment. On the other hand, FIG. 8B is a photograph of the cross-sectional structure after the heat treatment, and it can be seen that after the heat treatment, fine crystal grains are clearly precipitated and the composition is separated to form a heterogeneous film. FIG. 8C is a planar structure photograph after the heat treatment, and the dark portion indicates that the Zr concentration is high and crystalline, and the dielectric constant is high. The light-colored portion indicates that the Zr concentration is low and the dielectric constant is low. Each size is distributed in the order of 10 to 30 nm, and is close to the size of the gate region of the next-generation transistor to which these silicate materials are applied. Such inhomogeneity of the composition causes significant variation in transistor characteristics. It is thought to cause deterioration.
[0006]
[Problems to be solved by the invention]
In this way, when a silicate with a high dielectric constant is used for the gate insulating film, fine crystal grains are precipitated by heat treatment during the transistor manufacturing process, resulting in a heterogeneous composition of the gate insulating film, yield deterioration, and transistor characteristics. There was a problem that caused deterioration and dispersion.
[0007]
The present invention has been made in consideration of the above circumstances, and the purpose thereof is to make the composition of the gate insulating film inhomogeneous and to precipitate fine crystal grains even when silicate is used for the gate insulating film. It is an object of the present invention to provide a field effect transistor capable of suppressing the above-described problems and contributing to improvement in yield and characteristics.
[0008]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0009]
That is, the present invention relates to a field effect transistor in which a gate electrode is provided on a silicon substrate via a gate insulating film made of silicate containing at least one of Zr, Hf, La, Ce, Y, Bi, and Pr. It is characterized in that at least one of Mg, Ca, and Mn is added to the silicate constituting the above.
[0010]
Here, preferred embodiments of the present invention include the following.
[0011]
(1) The concentration of the metal element constituting the silicate is 17 at% or less (more desirably 10 at% or less), the concentration of the metal element added to the silicate is 1 at% or more, and the concentration of the metal element constituting the silicate is Also low.
(2) The concentration of the metal element added to the silicate must be ½ or less of the concentration of the metal element constituting the silicate.
[0012]
(3) The gate insulating film must be amorphous.
(4) The gate insulating film contains nitrogen.
[0013]
(5) When Mg or Mn is used as the metal element to be added to the silicate, the concentration of Mg or Mn is 1 at% or more (more preferably 2 at% or more).
(6) When Ca is used as the metal element to be added to the silicate, the Ca concentration must be 2 at% or more.
[0014]
(Function)
According to the present invention, the dielectric constant of the gate insulating film can be increased by using at least one of Zr, Hf, La, Ce, Y, Bi, and Pr as the main metal constituting the silicate. In addition, the viscosity of the gate insulating film can be increased by adding at least one of Mg, Ca, and Mn as a specific metal element to the silicate. When the viscosity of the gate insulating film is increased, the metal element in the silicate becomes difficult to move during the heat treatment in the transistor manufacturing process, and phase separation of the metal element is suppressed. Accordingly, it is possible to suppress the deterioration of characteristics due to the heterogeneity of the composition of the gate insulating film made of silicate, the precipitation of fine crystal grains, and the like, and it is possible to contribute to the improvement of the yield and the characteristics of the field effect transistor.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The details of the present invention will be described below with reference to the illustrated embodiments.
[0016]
(Embodiment)
FIG. 1 is a cross-sectional view showing a schematic structure of a MIS transistor according to an embodiment of the present invention.
[0017]
In the figure, 101 is a p-type silicon substrate, 102 is an element isolation region, and a gate electrode 104 is formed on the element formation region surrounded by the element isolation region 102 of the silicon substrate 101 via a gate insulating film 103. ing. The gate insulating film 103 is a high dielectric constant silicate composed of HfO ₂ and SiO ₂ , and Mg is added to the silicate. The gate electrode 104 is a polysilicon film, but a metal electrode such as TiN, TaN, W, Nb, Ru, or Ru oxide may be used instead.
[0018]
An n-type impurity layer 105 is formed on the surface layer of the substrate 101 with the gate electrode 104 interposed therebetween. The impurity layer 105 is a diffusion layer (source / drain region) introduced shallowly from the surface by, for example, ion implantation of As with an energy of 40 KeV and a surface density of about 5 × 10 ¹⁵ , and Ni, Co, or the like is formed on the surface. The silicide layer 106 is formed. Sidewall insulating films 107 made of SiON are formed on the sides of the gate insulating film 103 and the gate electrode 104.
[0019]
An interlayer insulating film 108 made of a CVD silicon oxide film or the like is formed on the substrate surface on which each of the above portions is formed. The interlayer insulating film 108 is provided with contact holes for connection to the gate and the source / drain. An Al wiring 109 is provided so as to connect to the gate electrode 104 and the silicide layer 106 in the source / drain region 105.
[0020]
Next, a manufacturing process of the MIS field effect transistor of this embodiment will be described with reference to FIG.
[0021]
First, as shown in FIG. 2A, a trench for element isolation is formed by reactive ion etching on a p-type silicon substrate 101 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm. Subsequently, for example, an element isolation region 102 is formed by embedding an LP (low pressure) -TEOS (Tetra ethyl orthosilicate) film. In the figure, the element isolation region 102 protrudes above the substrate surface, but the upper surface of the element separation region 103 may be the same height as the substrate surface.
[0022]
Next, as shown in FIG. 2B, for example, a laser ablation film forming method is used to form a gate made of silicate having a film thickness of 5 nm and a substrate temperature of room temperature to 300 ° C. in an atmosphere having an oxygen partial pressure of 1 to 100 Pa. An insulating film 103 is formed. This gate insulating film 103 is obtained by slightly adding Mg to Hf silicate composed of HfO ₂ and SiO ₂ . In this embodiment, for example, the concentration of Hf in the silicate is 10 at%, and the concentration of Mg is 5 at%.
[0023]
In this step, a sputter film forming method is used to form Hf metal, Hf silicide, or Hf silicate having a film thickness of 3 nm and a silicon substrate at a substrate temperature of room temperature to 300 ° C., for example, in an atmosphere having an oxygen partial pressure of 1 to 5 Pa. Hf silicate containing Mg may be formed by depositing on 101 and simultaneously or subsequently sputtering Mg and annealing at a temperature of 400 to 1000 ° C. in an oxygen or nitrogen atmosphere.
[0024]
Further, Hf metal or Hf silicide with a substrate temperature of room temperature to 300 ° C. and a film thickness of 4 nm is deposited on the silicon substrate 101 by vapor deposition, and Mg is deposited at the same time or subsequently, in an oxygen or nitrogen atmosphere. Among them, annealing may be performed at a temperature of 600 to 1000 ° C. to form Hf silicate containing Mg.
[0025]
Further, as shown in FIG. 2 (c), a CVD film forming method is used to mix C ₁₆ H ₃₆ HfO ₄ gas, monosilane (SiH ₄ ) gas, nitrogen gas, HfCl ₄ gas in an oxygen atmosphere. NH ₃ gas and the SiH ₄ gas mixed gas, or the Hf (SO _{4) 2} gas and the NH ₃ gas and SiH ₄ gas mixture containing Hf of mixed gas of the gas, a further gas containing Mg, such as MgSO ₄ gas For example, the substrate is deposited in a temperature range of room temperature to 800 ° C. at a pressure of 1 to 10 ⁴ Pa at a flow rate of 1 to 1000 sccm, and annealed in an oxygen atmosphere at 600 to 1000 ° C. after the deposition. Hf silicate containing Mg may be formed.
[0026]
Further, as shown in FIG. 2D, an SiO ₂ film 114 of about 1 to 4 nm is formed on the silicon substrate 101 by heating the silicon substrate 101 in an oxygen atmosphere, BOX (combustion oxidation), or by CVD. Subsequently, a film 115 having a metal element is deposited on the silicon substrate 101 by, for example, vapor deposition using, for example, a Hf metal target or a target containing at least Hf metal atoms and Si atoms and added with Mg. To do. Thereafter, for example, at least a metal element is diffused into the SiO ₂ film by heating at 400 to 900 ° C. in vacuum or nitrogen, and contains at least Mg atoms, Hf atoms, Si atoms, and oxygen atoms on the silicon substrate 101. A silicate may be formed.
[0027]
Next, as shown in FIG. 2E, a polysilicon film is deposited on the entire surface by chemical vapor deposition, and, for example, phosphorus oxychloride (POCl ₃ ) is used in the polysilicon film at 850 ° C. for 30 minutes. Phosphorus diffusion treatment is performed to reduce the resistance of the polysilicon film. The addition of impurities to the polysilicon film may be performed in a later step by using ion implantation at the same time as the addition of impurities to the diffusion layer. Further, instead of the polysilicon film, a polysilicon film doped with Ge may be used.
[0028]
Next, as shown in FIG. 3F, the gate electrode 104 is formed by patterning the polysilicon film. At this time, it is preferable that the gate insulating film 103 be patterned at the same time as the gate electrode 104, but the side surfaces of the gate electrode 104 and the gate insulating film 103 do not necessarily coincide with each other. A shape in which the gate insulating film 103 is concave as compared with the gate electrode 104 as shown in FIG. 3F, or a shape where the gate insulating film 103 is convex as compared with the gate electrode 104 as shown in FIG. The shape may be sufficient, and even if the whole is inclined, there is no problem.
[0029]
Next, as shown in FIG. 3H, a sidewall insulating film 107 is formed on the sidewall of the gate portion by depositing a SiON film on the entire surface and then etching back. Next, as shown in FIG. 3 (j), arsenic As ions are implanted into the entire surface, for example, at an acceleration voltage of 70 KeV and a dose amount of 1 × 10 ¹⁵ cm ⁻² , and thereafter, for example, 900 ° C., 30 minutes or 1000 ° C., 30 A second heat treatment is performed to diffuse and activate arsenic in the silicon substrate 101 to form the source and drain regions 105. At this time, when the gate insulating film 103 made of silicate contains Mg, it is possible to suppress inhomogeneous composition of the silicate and precipitation of microcrystals. Furthermore, it is desirable to form a silicide layer 106 by depositing Ni or Co on the diffusion layer 105 and heat-treating it, thereby reducing the resistance of the diffusion layer.
[0030]
Note that the order of the step of forming the side wall in FIG. 3H and the step of performing ion implantation in FIG. 3I may be interchanged as necessary.
[0031]
The subsequent steps are in accordance with a normal MIS transistor manufacturing process. A silicon oxide film to be an interlayer insulating film 108 is deposited on the entire surface by chemical vapor deposition, and contact holes are opened in the interlayer insulating film 108. Subsequently, an Al film 109 is deposited on the entire surface by sputtering, and the Al film 109 is patterned by reactive ion etching, thereby completing the MIS transistor having the structure shown in FIG.
[0032]
As described above, according to the present embodiment, the gate insulating film 103 made of silicate has a homogeneous composition even when high-temperature heat treatment is performed, and a high dielectric constant gate insulating film in which fine precipitates do not appear is used. The conventional MIS transistor can be realized.
[0033]
FIG. 4 (a) is a planar structure photograph after heat treatment of Hf silicate with a HfO ₂ concentration of 50% at 900 ° C., clearly showing that fine crystal grains are precipitated and the composition is separated. The On the other hand, FIG. 4B is a structural photograph after heat treatment of a film in which 5% of MgO is added to the Hf silicate, and it can be seen that the precipitation of microcrystals is clearly suppressed. At this time, the viscosity of the sample to which MgO is added is about 5 times that before the addition. Thus, the suppression of the precipitation of fine crystal grains by adding MgO is the same for Zr silicate and shows a marked improvement.
[0034]
FIG. 5 is a diagram showing the composition dependency of the viscosity when MgO, MnO, and CaO are added to the silicate. It can be seen that the viscosity increases remarkably depending on the composition from 1 at% or more. This increase in viscosity makes it difficult for the constituent elements of the silicate to diffuse and aggregate. As a result, as shown in FIG. 4, it is possible to suppress the precipitation of fine crystal grains, and the effective additive composition is 2 at% or more when MgO is taken as an example (Mg concentration is 1 at% or more). ) Is effective. Desirably, the effect can be expected more significantly when the concentration is 4 at% or more (Mg concentration is 2 at% or more).
[0035]
FIG. 6 is a graph showing the dependence of the surface tension (energy) of the SiO ₂ mixture on the ion concentration (ion radius / ion valence). Here, the value of Si is the standard, and the surface energy when Si is added to SiO ₂ is the standard, and a mixture of a material (for example, Mg, Ca, Mn, etc.) showing a larger value and SiO ₂ is the surface. Since energy increases, there is a tendency to gather together in order to reduce the surface area.
[0036]
On the other hand, a mixture of a material having a value smaller than the value of Si, such as Ti, and SiO ₂ has a small surface energy and can be dispersed in a small lump. Therefore, by adding a material such as Mg, Ca, or Mn that shows a larger value than Si, it is possible to form a mixture with SiO _2, which tends to be a lump mixture. From these tendencies, it can be seen that it is effective to add an additive such as Mg to suppress the precipitation of microcrystals which are small lumps in the silicate.
Further, when the concentration of the metal element in the silicate is increased, Coulomb scattering due to the fixed charges caused by the metal element is caused, and the electron mobility of the transistor is deteriorated. For example, as shown in FIG. 7, in the case of the Zr element, when the concentration exceeds 17 at%, the mobility is remarkably deteriorated particularly on the low electric field side. This was the same not only for the Zr element but also for the Hf element. Therefore, the concentration of the metal element in the entire silicate is desirably 17 at% or less. When considering application to a logic device or the like that requires higher speed operation, the concentration of the metal element in the entire silicate is desirably 10 at% or less.
[0037]
Furthermore, since the dielectric constant of the silicate is determined by the concentration ratio of the dielectric constant of the contained metal oxide and the dielectric constant of SiO ₂ , it is desirable that the contained metal oxide has a higher dielectric constant. For example, since MgO has a lower dielectric constant than ZrO ₂ , it is desirable that the concentration of Mg to be added be lower than that of Zr in order to keep the dielectric constant of the silicate high. Further, since the dielectric constants of ZrO ₂ and MgO are approximately εZrO ₂ : εMgO˜2: 1, the Mg concentration is desirably ½ or less of the Zr concentration in order to keep the dielectric constant high.
[0038]
(Modification)
In addition, this invention is not limited to embodiment mentioned above. The metal added to suppress the precipitation of microcrystals in the silicate is not limited to Mg, and Ca or Mn may be used. Furthermore, instead of a simple substance such as Mg, a plurality of elements such as Mg, Ca, and Mn may be combined as necessary. In order to further improve the viscosity, elements such as nitrogen, argon, krypton, and xenon with large molecular radii are added or added simultaneously with elements such as Mg, thereby suppressing atom migration and precipitation of microcrystals. It is possible to suppress this. The concentration to be added can also be changed to an appropriate value according to the physical properties of the silicate or the heat treatment conditions. As described above, as long as it is used as a barrier film that suppresses scattering of constituent elements of the insulating film without departing from the spirit of the present invention, it can be used as the technique of the present invention in various forms.
[0039]
In addition, various modifications can be made without departing from the scope of the present invention.
[0040]
【The invention's effect】
As described above in detail, according to the present invention, in a field effect transistor using a silicate gate insulating film, by adding at least one of Mg, Ca, and Mn, a minute amount is formed in the gate insulating film during the heat treatment. The precipitation of simple crystals can be suppressed. As a result, even through a conventional manufacturing process that requires high-temperature heat treatment, a high dielectric constant and homogeneous gate insulating film can be realized, and high integration and high performance of the field effect transistor can be achieved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a schematic structure of a MIS transistor according to a first embodiment.
FIG. 2 is a cross-sectional view showing a manufacturing process of the MIS transistor according to the first embodiment.
FIG. 3 is a cross-sectional view showing a manufacturing process of the MIS transistor according to the first embodiment.
FIG. 4 is an electron micrograph showing the structural change before and after silicate heat treatment by addition of Mg.
FIG. 5 is a graph showing the composition dependency of viscosity when MgO, MnO, and CaO are added to a silicate.
FIG. 6 is a graph showing the cation concentration dependence of the surface tension by adding an element to SiO ₂ .
FIG. 7 is a graph showing the relationship between the concentration of metal elements in silicate and the mobility of electrons.
FIG. 8 is an electron micrograph showing a cross-sectional state and a surface state before and after heat treatment when Zr silicate is used for a gate insulating film.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 102 ... Element isolation region 103 ... Gate insulating film 104 made of Hf silicate ... Gate electrode 105 ... Source / drain region 106 ... Silicide layer 107 ... Side wall insulating film 108 ... Interlayer insulating film 109 ... Al wiring 110 ... Resist 114 ... SiO ₂ insulating film 115 ... Metal thin film such as Hf and Zr

Claims (5)

A silicon substrate;
A gate insulating film formed by adding at least one of magnesium, calcium , and manganese to a silicate including at least one of zirconium, hafnium, lanthanum, cerium, yttrium, bismuth, and praseodymium formed on the silicon substrate;
A gate electrode formed on the gate insulating film;
A field effect transistor comprising: The concentration of the metal element constituting the silicate is 17 at% or less, the concentration of the metal element added to the silicate is 1 at% or more, and lower than the concentration of the metal element constituting the silicate. Item 1. The field effect transistor according to Item 1. 3. The field effect transistor according to claim 2, wherein the concentration of the metal element constituting the silicate is 10 at% or less. 4. The field effect transistor according to claim 2, wherein the concentration of the metal element added to the silicate is ½ or less of the concentration of the metal element constituting the silicate. The field effect transistor according to claim 1, wherein the gate insulating film is amorphous.

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