JP5633346B2 - Field effect transistor, semiconductor memory, display element, image display apparatus and system - Google Patents

Description

  The present invention relates to a field effect transistor, a semiconductor memory, a display element, an image display device, and a system, and more particularly, to a field effect transistor having an insulating film made of a dielectric oxide, and the field effect transistor. The present invention relates to a semiconductor memory, a display element, an image display device, and a system.

  A field effect transistor (FET), which is a kind of semiconductor element, is based on the principle of applying a voltage to a gate electrode and providing a gate (gate) for the flow of electrons or holes by the electric field of the channel. It is a transistor that controls the current between the electrodes.

  FETs are used as switching elements and amplifying elements because of their characteristics. In addition to a low gate current, the FET has a planar structure, and thus can be easily manufactured and integrated as compared with a bipolar transistor. Therefore, it is an indispensable element in an integrated circuit used in current electronic equipment.

  Electronic devices using FETs based on the MIS (Metal Insulator Semiconductor) structure, such as switching elements, memories, logic circuits, or LSI (Large Scale Integrated Circuit) integrated with these, AM-TFT (Active Matrix Thin Film Transistor) ) And the like, silicon oxide, oxynitride, and nitride have long been used as the gate and capacitor insulating film. These silicon-based insulating films are not only excellent as insulating films but also have a high affinity with the MIS process.

However, in recent years, a demand for further higher integration and lower power consumption of these electronic devices has increased, and a technique using a so-called High-k insulating film having a dielectric constant much higher than that of SiO ₂ as an insulating film has been proposed. Yes.

For example, in a fine MOS (Metal Oxide Semiconductor) device having a gate length of 0.1 μm or less, the film thickness must be 2 nm or less when the gate insulating layer of the FET is made of SiO ₂ from the scaling law. However, in this case, the gate leakage current due to the tunnel current becomes a big problem. As a countermeasure, it has been studied to reduce the gate leakage current by using a high-k insulating film for the gate insulating layer and increasing the thickness of the gate insulating layer.

  As a semiconductor device using a field effect transistor, there is a volatile / nonvolatile semiconductor memory.

In the volatile memory, the drain electrode of the field-effect transistor and the capacitor are connected in series, and a high-k insulating film is used for the dielectric layer of the capacitor, so that low power consumption and high integration can be achieved. At present, the dielectric layer of the capacitor is mainly a laminate of SiO ₂ / SiNx / SiO ₂ , and an insulating film having a higher relative dielectric constant is desired.

In the nonvolatile semiconductor memory, when the insulating film between the semiconductor layer and the floating gate electrode is the first gate insulating layer and the insulating film between the floating gate electrode and the gate electrode is the second gate insulating layer, the second gate insulating layer is formed. By using a high-k insulating film to increase the coupling ratio, the write / erase voltage can be reduced. At present, the second gate insulating layer is mainly a laminate of SiO ₂ / SiNx / SiO ₂ , and an insulating film having a higher relative dielectric constant is desired.

  In addition, in an AM-TFT used for a display or the like, a high saturation current can be obtained by using a high-k insulating film as a gate insulating layer, and ON / OFF control can be performed with a lower gate voltage. Low power consumption is possible.

Generally, as a high-k insulating film material, metal oxides such as Hf, Zr, Al, Y, and Ta, that is, HfO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O _{5 are used.} These silicates (HfSiO, ZrSiO), their aluminates (HfAlO, ZrAlO), their oxynitrides (HfON, ZrON, HfSiON, ZrSiON, HfAlON, ZrAlON) and the like have been studied.

On the other hand, perovskite structures and related substances have been studied in relation to ferroelectric memory materials. The perovskite structure is represented by ABO ₃ and is typically a combination of a divalent metal ion (A site) and a tetravalent metal ion, or a combination of trivalent metal ions at both the A site and B site. For example, SrTiO ₃ , BaZrO ₃ , CaSnO ₃ , LaAlO ₃ and the like. In addition, there are many crystals in which the B site is composed of two types of ions, such as SrBi _0.5 Ta _0.5 O ₃ and BaSc _0.5 Nb _0.5 O ₃ .

Furthermore, there is a series of crystals called layered perovskite structures. This is represented by (AO) _m (BO ₂ ) _n and has a structure in which m AO layers and n BO ₂ layers are laminated. For example, with respect to SrTiO ₃ (m = n = 1) which is the basic structure, Sr ₂ TiO ₄ , Sr ₃ Ti ₂ O ₇ , Sr ₄ Ti ₃ O ₁₀ and the like. Due to the presence of these crystal structures, the composition ratio of A ions and B ions can be varied, and a great variety of crystal groups appear together with the solid solution of the B site ions described above. In the present application, the “perovskite structure-related crystal” means a crystal having a perovskite structure and a layered perovskite structure.

  By the way, when a polycrystalline material is used for the gate insulating layer, a large leakage current flows at the interface of the crystal grain boundary, which deteriorates the function as the gate insulating layer, and the crystal system has anisotropy. Has a problem of causing variation in transistor characteristics due to dielectric anisotropy.

  For this reason, Patent Documents 1 and 2 disclose a method of suppressing leakage current in a gate insulating layer by using an amorphous insulating film made of a high dielectric constant silicate as a gate insulating layer.

Patent Document 3 discloses a method of suppressing leakage current in a gate insulating layer by using an amorphous insulating film mainly composed of A ₂ B ₂ O ₇ having a pyrochlore structure as a gate insulating layer.

  Patent Documents 4, 5, and 6 disclose a method of suppressing a leakage current of a gate insulating layer by using a laminated film including a high dielectric constant film as a gate insulating layer. Patent Document 7 discloses an epitaxial growth method. A method of suppressing leakage current of a gate insulating layer by forming a high dielectric constant film on a substrate and then mixing the element of the substrate and the metal oxide element in the gate insulating layer by performing heat treatment is disclosed. Yes.

  Further, Patent Document 8 discloses a TFT device having a structure in which a laminated film of an inorganic oxide film having a high dielectric constant and an organic polymer film is used as a gate insulating layer.

However, the insulating films disclosed in Patent Documents 1 and ₂ have a problem that the relative dielectric constant cannot be sufficiently increased because of the large amount of SiO ₂ components.

  Further, in the material disclosed in Patent Document 3, the gate insulating layer may be formed to include a crystal phase, and the process margin for forming the amorphous phase is extremely narrow, which has a manufacturing problem. .

  Further, the methods disclosed in Patent Documents 4 to 8 have a problem that the manufacturing process becomes complicated and the manufacturing cost increases.

  The present invention has been made in view of the above, and includes a field effect transistor, a semiconductor memory, a display element, an image display device, and a system that use an insulating film that has a simple, low cost, high dielectric constant, and low leakage current. It is intended to provide.

The present invention
A substrate,
A source electrode, a drain electrode, and a gate electrode formed on the substrate;
A semiconductor layer in which a channel is formed between a source electrode and a drain electrode by applying a predetermined voltage to the gate electrode;
A gate insulating layer between the gate electrode and the semiconductor layer;
With
The gate insulating layer includes one or more elements selected from alkaline earth metals and one or more elements selected from lanthanoids excluding Ga, Sc, Y, and Ce. A field effect transistor characterized in that it is formed of an amorphous composite metal oxide insulating film (excluding those containing Si and Al) .

The present invention also provides:
The semiconductor layer is a field effect transistor which is an oxide semiconductor.

The present invention also provides:
The substrate is a field effect transistor characterized in that the substrate is an insulating substrate.

The present invention also provides:
The substrate is a semiconductor substrate, and is a field effect transistor.

The present invention also provides:
The field effect transistor;
A first capacitor electrode connected to the drain electrode;
A second capacitor electrode;
A capacitor dielectric layer provided between the first capacitor electrode and the second capacitor electrode;
A volatile semiconductor memory.

The present invention also provides:
The capacitor dielectric layer comprises:
Amorphous composite metal oxidation comprising one or more elements selected from alkaline earth metals and one or more elements selected from lanthanoids excluding Ga, Sc, Y, and Ce The volatile semiconductor memory is formed of a material insulating film.

The present invention also provides:
In the field effect transistor,
The nonvolatile semiconductor memory further includes a second gate insulating layer and a floating gate electrode between the semiconductor layer and the gate insulating layer.

The present invention also provides:
A light control element whose light output is controlled according to a drive signal;
A drive circuit including the field effect transistor according to any one of claims 1 to 3, which drives the light control element;
It is a display element characterized by comprising.

The present invention also provides:
The light control element is a display element including an organic electroluminescence element.

The present invention also provides:
The light control element is a display element including a liquid crystal element.

The present invention also provides:
The light control element is a display element including an electrochromic element.

The present invention also provides:
The light control element includes an electrophoretic element. It is a display element.
The light control element includes an electrowetting element. It is a display element.
An image display device that displays an image according to image data,
A plurality of the display elements arranged in a matrix;
A plurality of wirings for individually applying a gate voltage to each field effect transistor in the plurality of display elements;
In accordance with the image data, a display control device that individually controls the gate voltage of each field effect transistor via the plurality of wirings;
An image display apparatus comprising:

The present invention also provides:
A system comprising: the image display device described above; and an image data creation device that creates image data based on image information to be displayed and outputs the image data to the image display device.

  According to the present invention, since an insulating film having a high relative dielectric constant and a small leakage current can be obtained, a field effect transistor, a semiconductor memory, a display element, and an image display device that can be driven at a low voltage and can be highly integrated. And the system can be provided at low cost.

Structure diagram of field effect transistor according to first embodiment Structural diagram (1) of a field effect transistor of another configuration according to the first embodiment Structural diagram (2) of a field effect transistor of another configuration according to the first embodiment Structural diagram of field-effect transistor of other configuration in first embodiment (3) Structural diagram of field effect transistor according to second embodiment Structure diagram of volatile memory in the third embodiment Structural diagram of volatile memory of other configuration in the third embodiment (1) Structural diagram (2) of volatile memory of other configuration in the third embodiment Structural diagram of volatile memory of other configuration in third embodiment (3) Structure diagram of volatile memory in the fourth embodiment Structure diagram of nonvolatile semiconductor memory according to fifth embodiment Structural diagram (1) of nonvolatile semiconductor memory of other configuration in the fifth embodiment Structural diagram (2) of the nonvolatile semiconductor memory of another configuration in the fifth embodiment Structural diagram (3) of nonvolatile semiconductor memory of other configuration in the fifth embodiment Structure diagram of nonvolatile semiconductor memory in sixth embodiment Structural drawing of organic electroluminescence display element in seventh embodiment Structural drawing of organic electroluminescence display element of other configuration in seventh embodiment Structure diagram of liquid crystal element used for display element in seventh embodiment Structure diagram of electrochromic element used for display element in seventh embodiment Structure diagram of electrophoretic element used for display element in seventh embodiment Structural diagram of electrowetting element used for display element in seventh embodiment (1) Structural diagram of electrowetting element used for display element in seventh embodiment (2) FIG. 9 is a block diagram illustrating a configuration of a television device according to an eighth embodiment. Explanatory drawing (1) of the television apparatus in 8th Embodiment. Explanatory drawing (2) of the television apparatus in 8th Embodiment. Explanatory drawing (3) of the television apparatus in 8th Embodiment Explanatory drawing of the display element in 8th Embodiment Explanatory drawing of organic EL in 8th Embodiment Explanatory drawing (4) of the television apparatus in 8th Embodiment. Explanatory drawing (1) of the other display element in 8th Embodiment. Explanatory drawing (2) of the other display element in 8th Embodiment Characteristics diagram of field effect transistor in Example 1 and Comparative Example 1 Structure diagram of volatile memory in Embodiment 3 Flowchart of manufacturing method of organic EL display element in Example 7

  The form for implementing this invention is demonstrated below.

  The inventors of the present invention have found an insulator material made of an oxide that is a single layer film, has a high dielectric constant, and a low leakage current, and has found an electronic device using the insulator material. This is based on the fact that it could be manufactured.

  That is, one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra) and lanthanoids (La, Pr, Nd) excluding Ga, Sc, Y, and Ce. , Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The composite metal oxide film containing one or more elements selected from the group consisting of This is based on the finding that

  Alkaline earth oxides easily react with moisture and carbon dioxide in the atmosphere and easily change to hydroxides and carbonates, and are not suitable for application to electronic devices alone. In addition, simple oxides such as lanthanoids excluding Ga, Sc, Y, and Ce are easily crystallized, and leakage current becomes a problem as described above. However, the inventors have found that a complex oxide system of an alkaline earth metal and a lanthanoid other than Ga, Sc, Y, and Ce is stable in the atmosphere and can form an amorphous film in a wide composition range. Ce is specifically tetravalent among lanthanoids and forms crystals with a perovskite structure with an alkaline earth metal. Therefore, in order to obtain an amorphous phase, lanthanoids other than Ce are preferable.

  A crystal phase such as a spinel structure exists between the alkaline earth metal and the Ga oxide, but these crystals do not precipitate (generally 1000 ° C. or more) unless the temperature is very high as compared with the perovskite structure crystal. In addition, the existence of a stable crystal phase has not been reported between alkaline earth metal oxides and oxides composed of lanthanoids excluding Sc, Y, and Ce. Crystal precipitation is rare. Furthermore, when a complex oxide of an alkaline earth metal and a lanthanoid excluding Ga, Sc, Y, and Ce is composed of three or more kinds of metal elements, the amorphous phase is further stabilized.

  From the viewpoint of producing a high dielectric constant film, it is preferable to increase the composition ratio of elements such as Ba, Sr, Lu, and La.

Since the composite metal oxide film of the present invention can form an amorphous film in a wide composition range, the physical properties can also be controlled widely. For example, although the relative dielectric constant is about 6 to 20 and is sufficiently higher than that of SiO ₂ , it can be adjusted to an appropriate value according to the application by selecting the composition.

Further, the thermal expansion coefficient is equivalent to that of general wiring materials and semiconductor materials having 10 ⁻⁶ to 10 ⁻⁵ , and even if the heating process is repeated as compared with SiO ₂ having a thermal expansion coefficient of 10 ⁻⁷ units, the film There are few troubles such as peeling. In particular, a favorable interface is formed with an oxide semiconductor such as a-IGZO.

  Therefore, a high performance semiconductor device can be obtained by using it for insulating films, such as FET.

The above-mentioned composite metal oxide film can be formed by a vacuum film formation process such as a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a sputtering method, etc. It can be formed as an amorphous film.
[First Embodiment]
Based on FIG. 1, the field effect transistor (first aspect) in the present embodiment will be described.
The field effect transistor (first aspect) in this embodiment includes an insulating substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, and a semiconductor layer 16.

  First, the insulating substrate 11 is prepared. As materials, for example, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc. in addition to alkali-free glass and silica glass that are already widely used for flat panel displays. Plastic substrates can also be used as appropriate. In order to clean the surface and improve adhesion, it is preferable to perform pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning.

  Next, the gate electrode 12 is formed on the substrate 11. Various materials and processes are available. Examples of the material that can be used include metals and alloys such as Mo, Al, and Cu, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI). As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. is there.

  Next, the gate insulating film 13 is formed. In the present embodiment, the gate insulating layer 13 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, And a lanthanoid other than Ce and one or two or more elements selected from lanthanoids.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

Next, source / drain electrodes 14 and 15 are formed. Again, various materials and processes are available. Examples of the material that can be used include metals and alloys such as Mo, Al, and Ag, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI).
As a process, for example, a film can be patterned by a photolithography method after film formation by sputtering, spin coating, dip coating, or the like, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. .

  Next, a semiconductor layer 16 for forming a channel between the source electrode 14 and the drain electrode 15 is formed. The material is not particularly limited, and for example, an oxide semiconductor such as polycrystalline silicon (p-Si), amorphous silicon (a-Si), In-Ga-Zn-O, and an organic semiconductor such as pentacene can be used as appropriate. . Among these, an oxide semiconductor is preferable from the viewpoint of stability at the interface between the gate insulating layer 13 and the semiconductor layer 16.

  The process is not particularly limited. For example, a film is formed by a vacuum process such as a sputtering method, a pulsed laser deposition (PLD) method, a CVD method, an ALD method, or a solution process such as spin coating / dip coating, and then a pattern is formed by a photolithography method. It is also possible to directly form a desired shape by a printing process such as ink jet, nanoimprint, or gravure.

  Through these steps, a field effect transistor is formed.

In the field effect transistor in this embodiment, the composite metal oxide insulating film forming the gate insulating layer 13 is amorphous and has a relative dielectric constant of 6 or higher, which is higher than that of SiO _2. The field effect transistor can be driven at a low voltage.

  The field effect transistor shown in FIG. 1 is a so-called bottom gate / bottom contact type. However, the field effect transistor in this embodiment is not limited to this, for example, the bottom gate / top contact type shown in FIG. The top gate / bottom contact type shown in FIG. 3 and the top gate / top contact type shown in FIG. 4 may be used.

  Specifically, in the bottom gate / top contact type shown in FIG. 2, a gate electrode 22 made of a metal material or the like is formed on an insulating substrate 21, and further gate insulation is performed so as to cover the gate electrode 22. A layer 23 is formed, a semiconductor layer 24 is formed over the gate insulating layer 23, and a source electrode 25 and a drain electrode 26 are formed so that a channel is formed in the semiconductor layer 24.

  In the top gate / bottom contact type shown in FIG. 3, a semiconductor for forming a source electrode 32 and a drain electrode 33 on an insulating substrate 31 and forming a channel between the source electrode 32 and the drain electrode 33. A layer 34 is formed, a gate insulating layer 35 is formed so as to cover the source electrode 32, the drain electrode 33, and the semiconductor layer 34, and a gate electrode 36 is formed on the gate insulating layer 35.

  In the top gate / top contact type shown in FIG. 4, a semiconductor layer 42 is formed on an insulating substrate 41, and a source electrode 43 and a drain electrode 44 are formed so that a channel is formed in the semiconductor layer 42. The gate insulating layer 45 is formed so as to cover the source electrode 43, the drain electrode 44, and the semiconductor layer 42, and the gate electrode 46 is formed on the gate insulating layer 45.

Note that the field-effect transistor in this embodiment can be used for a drive circuit or the like in a semiconductor memory, a TFT, a display (display element), or the like.
[Second Embodiment]
Based on FIG. 5, the field effect transistor (second aspect) in the second embodiment will be described.

  The field effect transistor (second embodiment) in this embodiment includes a semiconductor substrate 51, a gate insulating layer 52, a gate electrode 53, a gate sidewall insulating film 54, a source region 55, a drain region 56, an interlayer insulating film 57, and a source. An electrode 58 and a drain electrode 59 are provided.

  First, the semiconductor substrate 51 is prepared. The material is not particularly limited as long as it is a semiconductor material, and materials such as Si (silicon) and Ge (germanium) to which a desired impurity is added can be appropriately used.

  Next, a gate insulating layer 52 is formed on the semiconductor substrate 51. In this embodiment, the gate insulating layer 52 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, And a composite metal oxide insulating film containing one or more elements selected from lanthanoids excluding Ce.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  Next, the gate electrode 53 is formed. There are no particular limitations on the material and process, and as the material, for example, a metal material such as polysilicon or Al, and a laminate of these and a barrier metal such as TiN or TaN can be used. A vacuum film formation method such as a sputtering method can be used. Although not shown, a silicide layer such as Ni, Co, or Ti may be formed on the surface of the gate electrode 53 in order to reduce the resistance.

  The patterning method of the gate insulating layer 52 and the gate electrode 53 is not particularly limited. For example, a mask is formed using a photoresist, and the gate insulating layer 52 or the gate is not covered with the mask by a dry etching method. A photolithography method for removing the electrode 53 can be used.

Next, a gate sidewall insulating film 54 is formed on the side surfaces of the gate insulating layer 52 and the gate electrode 53. The material and process are not particularly limited, and as the material, for example, an insulator such as SiON or SiO ₂ can be used. For the process, a vacuum film forming method such as a CVD method or a sputtering method can be used. The patterning method is not particularly limited. For example, a method of forming the material of the gate sidewall insulating film 54 on the entire surface of the substrate and then etching the entire surface by dry etching may be used.

  Next, the source region 55 and the drain region 56 are formed by selectively implanting ions into the semiconductor substrate 51. Although not shown, silicide layers such as Ni, Co, and Ti may be formed on the surfaces of the source region 55 and the drain region 56 in order to reduce the resistance.

Next, an interlayer insulating film 57 is formed. The material and process are not particularly limited, and as the material, for example, an insulator such as SiON or SiO ₂ can be used. For the process, a vacuum film forming method such as a CVD method or a sputtering method can be used. The patterning method is not particularly limited, and a desired pattern can be obtained by a photolithography method or the like. For example, a through hole as shown in FIG. 5 can be formed.

  Next, the source electrode 58 and the drain electrode 59 are formed. The source electrode 58 and the drain electrode 59 are formed so as to fill the through holes formed in the interlayer insulating film 57 and connect to the source region 55 and the drain region 56.

  The material and process are not particularly limited, and a metal material such as Al or Cu can be used as the material. As for the process, for example, a method of patterning by a photolithography method after filling a through hole by a vacuum film forming method such as a sputtering method, or a method of CMP (Chemical Mechanical Polishing) after filling a through hole by a CVD method or a plating method is used. A flattening method or the like can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably. Alternatively, a W plug in which through holes are filled with W may be used by using the CVD method.

Through the above steps, a field effect transistor is formed. In the field-effect transistor in this embodiment, the composite metal oxide insulating film that forms the gate insulating layer 52 is amorphous and has a relative dielectric constant of 6 or higher, which is higher than that of SiO _2. Thus, the field effect transistor can be driven at a low voltage and highly integrated.

  In the field effect transistor of the second mode illustrated in FIG. 5, the semiconductor layer forming a channel between the source region 55 and the drain region 56 corresponds to the semiconductor substrate 51.

  Although not shown, a semiconductor layer such as SiGe may be formed between the semiconductor substrate 51 made of Si and the gate insulating layer 52. 5 shows a top gate structure, the gate insulating layer 52 described above can also be used in a so-called double gate structure or a fin-type FET.

Note that the field-effect transistor in this embodiment can be used for a semiconductor memory or the like.
[Third Embodiment]
Next, a volatile semiconductor memory element (first aspect) in the third embodiment will be described with reference to FIG.

  The volatile semiconductor memory element (first aspect) in this embodiment includes an insulating substrate 61, a gate electrode 62, a gate insulating layer 63, a source electrode 64, a drain electrode 65, a semiconductor layer 66, and a first capacitor electrode 67. A capacitor dielectric layer 68 and a second capacitor electrode 69.

  First, the insulating substrate 61 is prepared. The material is the same as that of the substrate 11 in the first embodiment.

  Next, the gate electrode 62 is formed on the substrate 61. The materials and processes are the same as those of the gate electrode 12 in the first embodiment.

  Next, the second capacitor electrode 69 is formed. Various materials and processes can be used for the second capacitor electrode 69. Examples of materials that can be used include metals and alloys such as Mo, Al, Cu, and Ru, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI). . As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. is there.

  If the material and process of the gate electrode 62 and the second capacitor electrode 69 are the same, they may be formed simultaneously.

  Next, the gate insulating layer 63 is formed. In the present embodiment, the gate insulating layer 63 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, And a lanthanoid other than Ce and one or two or more elements selected from lanthanoids.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  Next, a capacitor dielectric layer 68 is formed on the second capacitor electrode 69. The material of the capacitor dielectric layer 68 is not particularly limited. For example, a high dielectric constant oxide material containing Hf oxide, Ta oxide, La oxide, etc., lead zirconate titanate (PZT), strontium bismuth tantalate, etc. A ferroelectric material typified by (SBT) can be used. Among them, the insulating film according to the present invention, that is, one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, and It is preferably formed of a composite metal oxide insulating film containing one or more elements selected from lanthanoids other than Ce.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  If the materials and processes of the gate insulating layer 68 and the capacitor dielectric layer 68 are the same, they may be formed simultaneously.

  Next, the source electrode 64 and the drain electrode 65 are formed. The materials and processes are the same as those of the source electrode 14 and the drain electrode 15 in the first embodiment.

  Next, the first capacitor electrode 67 is formed. Various materials and processes can be used for the first capacitor electrode 67. Examples of materials that can be used include metals and alloys such as Mo, Al, Cu, and Ru, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI). . As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. is there.

  Alternatively, the source electrode 64 and the drain electrode 65 may be formed at the same time as long as the materials and processes of the first capacitor electrode 67 are the same.

  Next, the semiconductor layer 66 is formed. The material is not particularly limited, and for example, an oxide semiconductor such as polycrystalline silicon (p-Si), amorphous silicon (a-Si), In-Ga-Zn-O, and an organic semiconductor such as pentacene can be used as appropriate. . Among these, an oxide semiconductor is preferable from the viewpoint of stability at the interface between the gate insulating layer 63 and the semiconductor layer 66. The process is not particularly limited. For example, a film is formed by a vacuum process such as a sputtering method, a pulsed laser deposition (PLD) method, a CVD method, an ALD method, or a solution process such as spin coating / dip coating, and then a pattern is formed by a photolithography method. It is also possible to directly form a desired shape by a printing process such as ink jet, nanoimprint, or gravure.

  Through the above steps, a volatile memory is manufactured.

From the first viewpoint, in the volatile memory according to the present embodiment, the composite metal oxide insulating film forming the gate insulating layer 63 is amorphous, and the relative dielectric constant is 6 or higher, which is higher than that of SiO _2. Therefore, the leakage current can be kept low, and the volatile memory can be driven at a low voltage.

From the second point of view, in the volatile memory according to the present embodiment, the composite metal oxide insulating film forming the gate insulating layer 63 and the capacitor dielectric layer 68 is amorphous and has a relative dielectric constant of 6 or more and SiO _2. Therefore, the leakage current can be kept low, and the volatile memory can be driven at a low voltage.

  The positional relationship among the gate electrode 62, the gate insulating layer 63, the source electrode 64, the drain electrode 65, and the semiconductor layer 66 in the volatile memory (first aspect) shown in FIG. 6 is a so-called bottom gate / bottom contact type. However, the volatile memory in this embodiment is not limited to this. For example, the bottom gate / top contact type shown in FIG. 7, the top gate / bottom contact type shown in FIG. 8, and the top gate / top contact type shown in FIG. But you can.

In addition, the first capacitor electrode 67, the capacitor dielectric layer 68, and the second capacitor electrode 69 in the volatile memory (first mode) shown in FIG. 6 have a planar structure. The capacitance of the capacitor may be increased by a method such as.
[Fourth Embodiment]
Next, a volatile semiconductor memory element (second aspect) in the fourth embodiment will be described with reference to FIG.

  The volatile semiconductor memory element (second aspect) in the present embodiment includes a semiconductor substrate 71, a gate insulating layer 72, a gate electrode 73, a gate sidewall insulating film 74, a source region 75, a drain region 76, and a first interlayer insulation. A film 77, a bit line electrode 78, a second interlayer insulating film 79, a first capacitor electrode 80, a capacitor dielectric layer 81, and a second capacitor electrode 82 are provided.

  Regarding the semiconductor substrate 71, the gate insulating layer 72, the gate electrode 73, the gate sidewall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77, the semiconductor substrate 51, the gate in the second embodiment The insulating layer 52, the gate electrode 53, the gate sidewall insulating film 54, the source region 55, the drain region 56, and the interlayer insulating film 57 can be formed by the same materials and processes.

  In the present embodiment, the gate insulating layer 72 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, And a composite metal oxide insulating film containing one or more elements selected from lanthanoids excluding Ce.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  As described above, after forming the gate insulating layer 72, the gate electrode 73, the gate sidewall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 on the semiconductor substrate 71, the bit line electrode 78 is formed. Form. The material and process are not particularly limited, and for example, Al or Cu can be used as the material. As for the process, for example, a through hole is filled by a vacuum film formation method such as a sputtering method or a CVD method, and then patterning is performed by a photolithography method, or a through hole is filled by a CVD method or a plating method and then CMP (Chemical Mechanical) is performed. A method of flattening by a polishing method can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably. Alternatively, a W plug in which through holes are filled with W may be used by using the CVD method.

  Next, a second interlayer insulating film 79 is formed. The materials and processes are the same as those of the interlayer insulating film 57 in the second embodiment.

  Next, the first capacitor electrode 80 is formed. There are no particular limitations on the material and process, and for example, a metal material such as Al, Cu, or Ru, or polysilicon can be used. As for the process, for example, a through hole is filled by a vacuum film forming method such as a sputtering method or a CVD method, and then patterning is performed by a photolithography method, or a CMP (Chemical Mechanical Polishing) is performed after filling the through hole by a CVD method or a plating method. The method of flattening by the method can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably. Alternatively, a W plug in which through holes are filled with W may be used by using the CVD method.

  Next, a capacitor dielectric layer 81 is formed. The material of the capacitor dielectric layer 81 is not particularly limited. For example, a high dielectric constant oxide material including Hf oxide, Ta oxide, La oxide, lead zirconate titanate (PZT), strontium bismuth tantalate, and the like. A ferroelectric material typified by (SBT) can be used. Among them, the insulating film according to the present invention, that is, one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, and It is preferably formed of a composite metal oxide insulating film containing one or more elements selected from lanthanoids other than Ce.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  Next, a second capacitor electrode 82 is formed. The material and process are not particularly limited, and for example, a metal material such as Al, Cu, or Ru, or polysilicon can be used. For the process, for example, a method of patterning by a photolithography method after film formation by a vacuum film formation method such as a CVD method or a sputtering method can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably.

  Through the above steps, a volatile memory is manufactured.

From the first viewpoint, in the volatile memory according to the present embodiment, the composite metal oxide insulating film forming the gate insulating layer 72 is amorphous, and the relative dielectric constant is 6 or higher, which is higher than that of SiO _2. Therefore, the leakage current can be kept low, and the volatile memory can be highly integrated and driven at a low voltage.

From the second viewpoint, in the volatile memory according to the present embodiment, the composite metal oxide insulating film forming the gate insulating layer 72 and the capacitor dielectric layer 81 is amorphous, and the relative dielectric constant is 6 or more and SiO _2. Therefore, the leakage current can be kept low, and the volatile memory can be highly integrated and driven at a low voltage.

  Note that in this embodiment mode, a volatile memory having a stack structure in which a capacitor is disposed above a field effect transistor has been described; however, the present invention is not limited to this. For example, although not shown, a trench-type volatile memory in which a trench is formed in a semiconductor substrate and a capacitor is disposed below the field-effect transistor may be used.

The first capacitor electrode 80, the capacitor dielectric layer 81, and the second capacitor electrode 82 in the volatile memory shown in FIG. 10 have a planar structure. The capacity may be increased.
[Fifth Embodiment]
Based on FIG. 11, a nonvolatile semiconductor memory (first aspect) in the fifth embodiment will be described.

  The nonvolatile semiconductor memory (first aspect) in this embodiment includes an insulating substrate 91, a gate electrode 92, a first gate insulating layer 93, a floating gate electrode 94, a second gate insulating layer 95, and a source electrode 96. A drain electrode 97 and a semiconductor layer 98.

  The first gate insulating layer 93 is called a so-called gate electrode insulating layer, the second gate insulating layer 95 is called a so-called tunnel insulating layer, and the gate electrode 92 is called a so-called control gate electrode. Depending on the voltage application conditions to the source electrode 96, the drain electrode 97, and the gate electrode 92, electrons can be transferred into and out of the floating gate electrode 94 through the second gate insulating film, which is a tunnel insulating layer, by the tunnel effect. Function as.

  A method for manufacturing a nonvolatile semiconductor memory in this embodiment will be described.

  First, the insulating substrate 91 is prepared. The material is the same as that of the substrate 11 in the first embodiment.

  Next, a gate electrode 92 is formed on the substrate 91. The materials and processes are the same as those of the gate electrode 12 in the first embodiment.

  Next, a first gate insulating layer 93 is formed so as to cover the gate electrode 92. In the present embodiment, the first gate insulating layer 93 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc , Y, and Ce are formed of a composite metal oxide insulating film containing one or more elements selected from lanthanoids.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained. The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  Next, a floating gate electrode 94 is formed on the first gate insulating layer 93. Various materials and processes are available. Examples of the material that can be used include metals and alloys such as Mo, Al, and Cu, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI). As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. is there.

Next, a second gate insulating layer 95 is formed so as to cover the floating gate electrode 94. There is no restriction | limiting in particular about material, The optimal material can be selected suitably. Among them, in order to improve the coupling ratio, a low dielectric constant insulating material such as SiO ₂ or a fluorine-based polymer is preferable. The process is not particularly limited. For example, a vacuum film formation method such as sputtering, CVD, ALD, or a coating solution containing a metal alkoxide / metal complex, spin coating using a coating solution containing a polymer, Solution processes such as die coating, nozzle coating, and ink jet can be used as appropriate, and a desired pattern can be formed by using a photolithography method or directly drawing by a printing method.

  Next, a source electrode 96 and a drain electrode 97 are formed over the second gate insulating layer. The materials and processes are the same as those of the source electrode 14 and the drain electrode 15 in the first embodiment.

  Next, the semiconductor layer 98 is formed. The material is not particularly limited, and for example, an oxide semiconductor such as polycrystalline silicon (p-Si), amorphous silicon (a-Si), In-Ga-Zn-O, and an organic semiconductor such as pentacene can be used as appropriate. . Among these, an oxide semiconductor is preferable. The process is not particularly limited. For example, a film is formed by a vacuum process such as a sputtering method, a pulsed laser deposition (PLD) method, a CVD method, an ALD method, or a solution process such as spin coating / dip coating, and then a pattern is formed by a photolithography method. It is also possible to directly form a desired shape by a printing process such as ink jet, nanoimprint, or gravure.

  From the above steps, the nonvolatile memory (first aspect) is manufactured.

In the nonvolatile semiconductor memory according to the present embodiment, the composite metal oxide insulating film forming the first gate insulating layer 93 is amorphous and has a relative dielectric constant of 6 or higher, which is higher than that of SiO _2. The current can be kept low, and the write / erase voltage can be reduced.

  In the nonvolatile memory (first embodiment) shown in FIG. 11, the positional relationship among the gate electrode 92, the source electrode 96, the drain electrode 97, and the semiconductor layer 98 is a so-called bottom gate / bottom contact type. The nonvolatile memory in the embodiment is not limited to this, and may be, for example, a bottom gate / top contact type shown in FIG. 12, a top gate / bottom contact type shown in FIG. 13, and a top gate / top contact type shown in FIG.

11-14, the gate electrode 92, the first gate insulating layer 93, and the floating gate electrode 94 have a planar structure. For example, the capacitance of the capacitor can be increased by a three-dimensional structure. May be.
[Sixth Embodiment]
Next, the nonvolatile semiconductor memory element (second aspect) in the sixth exemplary embodiment will be described with reference to FIG.

  The nonvolatile semiconductor memory element (second aspect) in this embodiment includes a semiconductor substrate 101, a first gate insulating layer 102, a gate electrode 103, a second gate insulating film 104, a floating gate electrode 105, and gate sidewall insulation. A film 106, a source region 107, and a drain region 108 are included.

  The first gate insulating layer 102 is called a so-called inter-gate electrode insulating layer, the second gate insulating layer 104 is called a so-called tunnel insulating layer, and the gate electrode 103 is called a so-called control gate electrode. Depending on the voltage application conditions to the source region 107, the drain region 108, and the gate electrode 103, electrons can be taken into and out of the floating gate electrode 105 through the second gate insulating layer 104 that is a tunnel insulating layer by a tunnel effect. Functions as a memory.

  A manufacturing method will be described.

  First, the semiconductor substrate 101 is prepared. The material is the same as that of the semiconductor substrate 11 in the first embodiment.

Next, a second gate insulating film 104 is formed. The material is not particularly limited, but is preferably a low dielectric constant insulating material such as SiO ₂ . The process is not particularly limited, and for example, a vacuum oxidation method such as a thermal oxidation method, a sputtering method, a chemical CVD method, or an ALD method can be used.

  Next, the floating gate electrode 105 is formed. There are no particular limitations on the material and process, and as the material, for example, a metal material such as polysilicon or AL, and a laminate of these and a barrier metal such as TiN or TaN can be used. A vacuum film forming method such as a sputtering method can be used.

  Next, a first gate insulating film 102 is formed. In this embodiment, the first gate insulating film 102 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, and the like. , Y, and Ce are formed of a complex metal oxide insulating film containing one or more elements selected from lanthanoids.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained. The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  Next, the gate electrode 103 is formed. The material and process are the same as those of the gate insulating layer 53 in the second embodiment.

  The patterning of the first gate insulating layer 102, the gate electrode 103, the second gate insulating film 104, and the floating gate electrode 105 is not particularly limited, but a desired pattern can be obtained by, for example, photolithography. .

  Next, a gate sidewall insulating film 106 is formed. The materials and processes are the same as those of the gate sidewall insulating film 54 in the first embodiment. Next, the source region 107 and the drain region 108 are formed by selectively implanting ions into the semiconductor substrate 101. Although not shown, a silicide layer such as Ni, Co, Ti or the like may be formed on the surfaces of the source region 107 and the drain region 108 in order to reduce the resistance.

From the above steps, a nonvolatile memory (second aspect) is formed. In the nonvolatile semiconductor memory in this embodiment, the composite metal oxide insulating film forming the first gate insulating layer 102 is amorphous and has a relative dielectric constant of 6 or higher, which is higher than that of SiO _2. The current can be kept low, and the write / erase voltage can be reduced.

In FIG. 15, the first gate insulating layer 102, the gate electrode 103, and the floating gate electrode 105 have a planar structure. However, even if the capacitance of the capacitor is increased by, for example, a three-dimensional structure method. good.
[Seventh Embodiment]
Next, the display element in 7th Embodiment is demonstrated based on FIGS. The display element according to the present embodiment is an organic electroluminescence (organic EL) display element.

  Based on FIG. 16, the organic EL display element in this Embodiment is demonstrated. The organic EL display element in this embodiment includes an insulating substrate 201, a first gate electrode 202, a second gate electrode 203, a gate insulating layer 204, a first source electrode 205, a first drain electrode 206, a first 2 source electrode 207, second drain electrode 208, first semiconductor layer 209, second semiconductor layer 210, first protective layer 211, second protective layer 212, partition 213, organic EL layer 214, upper part An electrode 215, a sealing layer 216, an adhesive layer 217, and a counter insulating substrate 218 are included.

  The organic EL display element in the present embodiment has an organic EL element 250 as a light control element, and a drive circuit 280 having a first field effect transistor 260 and a second field effect transistor 270. The first field effect transistor 260 includes a first gate electrode 202, a gate insulating layer 204, a first source electrode 205, a first drain electrode 206, a first semiconductor layer 209, and a first protective layer 211. The second field-effect transistor 270 includes a second gate electrode 203, a gate insulating layer 204, a second source electrode 207, a second drain electrode 208, a second semiconductor layer 210, and a second protective layer. It consists of 212.

  The driver circuit 280 has a structure of two transistors and one capacitor, and the first drain electrode 206 and the second gate electrode 203 are connected to each other. In FIG. 16, a capacitor is formed between the second source electrode 207 and the second gate electrode 203 for convenience, but the location where the capacitor is formed is not limited in practice, and a capacitor having a necessary capacity is appropriately provided. Can be designed and formed.

  Next, a method for manufacturing the organic EL display element in the present embodiment will be described.

  The first field-effect transistor 260 and the second field-effect transistor 270 can be manufactured by the same material and process as the field-effect transistor in the first embodiment.

  In this embodiment, the gate insulating layer 204 includes one or more elements selected from alkaline earth metals (Be, Mg, Ca, Sr, Ba, Ra), Ga, Sc, Y, And a lanthanoid other than Ce and one or two or more elements selected from lanthanoids.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but more preferably selected from each element group so as to obtain a composition capable of taking a stable amorphous state. It is preferable that the metal element contained is contained.

  The process is not particularly limited, and a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

Various materials and processes can be used for the first protective layer 211 and the second protective layer 212. As the material, for example, an inorganic oxide such as SiO ₂ , SiON, or SiNx, or an insulating material such as a fluorine polymer can be used. Regarding the process, for example, after film formation by a sputtering method, spin coating method, or the like, patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure.

Various materials and processes can be used for the partition 213 as well. As the material, for example, an inorganic oxide such as SiO ₂ , SiON, or SiNx, or an insulating material such as acrylic or polyimide can be used. Regarding the process, for example, after film formation by a sputtering method, spin coating method, or the like, patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure.

  Next, the organic EL element 250 will be described. The organic EL element in this embodiment has an organic EL layer 214, an upper electrode 215, and a second drain electrode (lower electrode) 208.

For example, ITO is used for the second drain electrode 208. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, a silver (Ag) -neodymium (Nd) alloy, or the like may be used.

  The organic EL layer 214 has an electron transport layer, a light emitting layer, and a hole transport layer. The upper electrode 215 is connected to the electron transport layer, and the second drain electrode 208 is connected to the hole transport layer. When a predetermined voltage is applied between the second drain electrode 208 and the upper electrode 215, holes and electrons injected from the second drain electrode 208 and the upper electrode 215 are recombined in the organic EL layer 214, and The light emitting layer emits light by the excited energy.

  For example, aluminum (Al) is used for the upper electrode 215. A magnesium (Mg) -silver (Ag) alloy, an aluminum (Al) -lithium (Li) alloy, ITO (Indium Tin Oxide), or the like may be used.

  In addition, it does not specifically limit about the manufacturing method of an organic EL element, It is possible to use the existing technique, for example, vacuum film-forming methods, such as a vacuum evaporation method and a sputtering method, and solution processes, such as an inkjet and a nozzle coat, suitably Can be used.

After forming the driving device 280 and the organic EL element 250, the sealing layer 216 is formed. Various materials and processes can be used for the sealing layer 216. As the material, for example SiO ₂ and SiON, inorganic oxides such as SiNx can be used. For the process, for example, a vacuum film forming method such as a CVD method or a sputtering method can be used.

  Finally, it is bonded to the counter insulating substrate 218 through an adhesive layer 217 made of a material such as an epoxy resin or an acrylic resin to complete an organic EL display element.

In the organic EL display element in the present embodiment, when the first and second field effect transistors described above are turned on, light is emitted from the organic EL layer 214 and an image is displayed from the insulating substrate 201 side indicated by the arrow A. Is something that can be done. In this case, the insulating property 201, the second drain electrode 208, and the gate insulating layer 204 are required to be made of a transparent material (ITO, SiO ₂ or the like).

  In this embodiment, the case of so-called “bottom emission” in which light emission is extracted from the substrate side has been described. However, the present invention is not limited to this. For example, a high-reflectance electrode such as a silver (Ag) -neodymium (Nd) alloy is used for the second drain electrode 208, and a semi-transparent electrode such as a magnesium (Mg) -silver (Ag) alloy is used for the upper electrode 215. It is also possible to use so-called “top emission” in which light emission is extracted from the opposite insulating substrate side opposite to A.

  In this embodiment, the case where the organic EL element 250 is arranged beside the drive circuit 280 has been described, but the present invention is not limited to this. For example, as shown in FIG. 17, the organic EL element 250 may be disposed above the drive circuit 280.

  The organic EL display element in FIG. 17 includes a first gate electrode 222, a gate insulating layer 224, a first source electrode 225, a first drain electrode 226, a first semiconductor layer 229, and a first gate on an insulating substrate 221. A first field-effect transistor 260 including one protective layer 231, a second gate electrode 223, a gate insulating layer 224, a second source electrode 227, a second drain electrode 228, a second semiconductor layer 230, An interlayer insulating film 233 is formed so as to cover the second field effect transistor 270 including the two protective layers 232, and a partition wall 234 is formed on the interlayer insulating film 233. On the other hand, the organic EL element formed above the drive circuit 280 composed of the first field effect transistor 260 and the second field effect transistor 270 includes a lower electrode 235, an organic EL layer 236, and an upper electrode 237. The second drain electrode 228 and the lower electrode 235 are connected by a through hole formed in the interlayer insulating film 233. The sealing layer 238, the adhesive layer 239, and the counter insulating substrate 240 are the same as the sealing layer 216, the adhesive layer 217, and the counter insulating substrate 218 in FIG.

  In the present embodiment, the case where the organic EL layer is composed of an electron transport layer, a light emitting layer, and a hole transport layer has been described, but the present invention is not limited to this. For example, the electron transport layer and the light emitting layer may be one layer. Further, an electron injection layer may be provided between the electron transport layer and the upper electrode 215. Furthermore, a hole injection layer may be provided between the hole transport layer and the second drain electrode.

In the organic EL display element in the present embodiment, the composite metal oxide insulating film forming the gate insulating layer 204 is amorphous and has a relative dielectric constant of 6 or higher and a value higher than that of SiO _2. Thus, the power consumption of the organic EL display element can be reduced.

  In the above description, the driving circuit for driving the display element has a two-transistor one-capacitor structure, but the present invention is not limited to this. it can.

  In the above description, an organic EL display element using an organic EL element as a light control element has been described. However, a liquid crystal display device can be formed by using a liquid crystal element as the light control element. As an example, as shown in FIG. 18, the liquid crystal element includes a polarizing plate 302, a glass substrate 303, a transparent electrode 304, an alignment film 305, an alignment film 307, a transparent electrode 308, a color filter 309, a glass substrate 310, and a polarizing plate 311. The backlight system 301 is provided in an element including a liquid crystal layer 306 filled with a liquid crystal material. A display element is obtained by controlling the orientation of the liquid crystal material by a voltage applied between the transparent electrode 304 and the transparent electrode 308 by the power source 312 or the like and controlling the transmittance of light incident from the backlight system 301.

  In this embodiment mode, a reflective display device can be obtained by using an electrochromic element, an electrophoretic element, or an electrowetting element as the light control element (display element).

  For example, as shown in FIG. 19 as an example, the electrochromic element includes a glass substrate 321, a lower electrode 322, a white reflective layer 323, an electrolyte solution or solid electrolyte 324, an electrochromic layer 325, an upper transparent electrode 326, and a glass substrate 327. Consists of. When a predetermined voltage is applied between the lower electrode 322 and the upper transparent electrode 326 by the power source 328 or the like, the electrochromic material is reversibly oxidized or reduced, and the display element is formed by coloring or decoloring.

  For example, the electrophoretic element includes a glass substrate 331, a lower electrode 332, a display layer 333, an upper transparent electrode 334, and a glass substrate 335, as shown in FIG. 20 as an example. The display layer 333 is a layer in which charged white particles and black particles are dispersed in a solvent. When a predetermined voltage is applied between the lower electrode 332 and the upper transparent electrode 334 by a power source 336 or the like, the charged particles are converted into an electric field. It becomes a display element by moving by.

  Further, for example, as shown in FIG. 21, as an example, the electrowetting element includes a white substrate 341, a lower transparent electrode 342, a hydrophobic insulating layer 343, an oil layer 344, an aqueous solution layer 345, an upper transparent electrode 346, a glass substrate. 347. Here, the oil layer 344 is colored, and the aqueous solution layer 345 is in a transparent state. In the off state, since the aqueous solution layer 345 is a light-transmitting layer, oil coloring is displayed. After that, as shown in FIG. 22, when a predetermined voltage is applied between the lower transparent electrode 342 and the upper transparent electrode 346 by the power source 348 or the like, charges are generated on the surface of the hydrophobic insulating layer 343, and hydrophilicity is generated. It changes to the surface. That is, the affinity of the hydrophobic insulating layer 343 decreases with the oil layer 344, and the affinity with the aqueous solution layer 345 increases, so that the oil layer 344 contacts the hydrophobic insulating layer 343 in order to reduce the overall energy. Move in the direction that minimizes the area. Then, the color of the white substrate 341 is displayed. Based on such a principle, the electrowetting element functions as a display element.

The electrochromic element, electrophoretic element, and electrowetting element may be combined with a color filter as appropriate to form a reflective color display.
[Eighth Embodiment]
Next, an image display apparatus and system according to the eighth embodiment will be described with reference to FIGS. FIG. 23 shows a schematic configuration of a television device 500 as a system according to an embodiment of the present invention. Note that the connection lines in FIG. 23 represent typical signals and information flows, and do not represent the entire connection relationship of each block.

  The television apparatus 500 in this embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, a DA converter (DAC) 512, an audio Output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541, hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500 and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code readable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a preset channel broadcast from the broadcast waves received by the antenna 610.

  The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information.

  The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 and separates audio information and video information.

  The audio decoder 511 decodes the audio information from the TS decoder 506.

  The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514.

  The video decoder 521 decodes the video information from the TS decoder 506.

  The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524.

  The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and a signal including display information in response to an instruction from the operation device 532 or the IR light receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like.

  The operating device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main controller 501 of various information input by the user.

  The drive IF 541 is a bi-directional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk and a driving device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk.

  The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and notifies the main controller 501 of it.

  The communication control device 552 controls communication with the Internet. Various information can be acquired via the Internet.

  As shown in FIG. 24 as an example, the image display device 524 includes a display 700 and a display control device 780.

  As shown in FIG. 25 as an example, the display 700 includes a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

  In addition, as shown in FIG. 26 as an example, the display 710 includes n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at equal intervals along the line. The display element 702 can be specified by the scan line and the data line.

  As shown in FIG. 27 as an example, each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

  As an example, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714, as shown in FIG.

  Aluminum (Al) is used for the cathode 712. A magnesium (Mg) -silver (Ag) alloy, an aluminum (Al) -lithium (Li) alloy, ITO (Indium Tin Oxide), or the like may be used.

ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, a silver (Ag) -neodymium (Nd) alloy, or the like may be used.

  The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. A cathode 712 is connected to the electron transport layer 742, and an anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  As shown in FIG. 27, the drive circuit 720 includes two field effect transistors 810 and 820 and a capacitor 830.

  The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 810 is turned on, the organic EL element 750 is driven by the field effect transistor 820.

  As an example, the display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG.

  The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523.

  The scanning line driving circuit 784 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 782.

  The data line driving circuit 786 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 782.

  As is apparent from the above description, in the television device 500 according to the present embodiment, the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525 constitute an image data creation device. Yes.

  In the above description, the light control element is an organic EL element. However, the present invention is not limited to this, and may be a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 30, the current supply line in the display element 703 is not necessary.

  In this case, as shown in FIG. 31 as an example, the drive circuit 730 is configured by only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can do. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 31 denote a counter electrode (common electrode) of the capacitor 760 and the liquid crystal element 770, respectively.

  The field effect transistors 810, 820, and 840 in this embodiment are the field effect transistors in the first embodiment. Thus, in this embodiment, a high-performance television device with low power consumption can be obtained.

  In addition, the field effect transistor in the first embodiment and the volatile memory in the third embodiment are the image data processing circuit 782, the scanning line driving circuit 784, and the data line driving included in the display control device 780. The circuit 786 can be used. Thus, the display 700 including the display 710 in which the display elements 702 are arranged in a matrix and the display control device 780 can be formed on the same plane, and a low-cost television device can be obtained. .

  Moreover, although the said embodiment demonstrated the case where a system was a television apparatus, it is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 524 are connected may be used.

  In addition, an image display device 524 is provided as a display unit in a portable information device such as a mobile phone, a portable music player, a portable video player, an electronic BOOK, or a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 524 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

  The field effect transistors, volatile memories, and nonvolatile memories according to the first to sixth embodiments can be used for devices other than display elements and image display devices (for example, IC cards and ID tags).

Example 1
Next, as Example 1, a field effect transistor according to the present invention will be described. Based on FIG. 2 which is a block diagram of the field effect transistor manufactured in Example 1, the manufacturing method of the field effect transistor in Example 1 is demonstrated.

  First, molybdenum (Mo) was formed to 100 nm as a gate electrode 22 on a substrate 21 made of alkali-free glass by a DC sputtering method through a metal mask. Next, La (thd) 3, Mg (thd) 2 (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) were used as solvents in tetraethylene glycol dimethyl ether (tetraglyme) and tetrahydrofuran (THF), respectively. A dissolved material was used as a raw material, and a magnesium lanthanum composite oxide insulating film was formed to a thickness of 200 nm by a CVD method to form a gate insulating layer 23.

Next, argon (Ar) and oxygen (O ₂ ) gas is introduced into the chamber, and a DC sputtering method is performed at room temperature using an MgIn ₂ O ₄ sintered body target, whereby Mg − that becomes the semiconductor layer 24 is formed. An In-based oxide film was formed. The semiconductor layer 24 was formed only in a predetermined region by performing film formation using a metal mask having an opening in the region to be formed. The film thickness of the deposited semiconductor layer 24 was about 100 nm.

  Next, the source electrode 25 and the drain electrode 26 were formed by vacuum deposition using aluminum (Al) as a deposition source. Note that the source electrode 25 and the drain electrode 26 were formed only in a predetermined region by performing film formation using a metal mask having an opening in the region to be formed. The film thickness of the formed source electrode 25 and drain electrode 26 was about 100 nm, the formed channel length was about 50 μm, and the channel width was about 400 μm.

  Next, the semiconductor layer 24 was heat-treated in the atmosphere at 300 ° C. for 1 hour.

  Thereby, the field effect transistor in Example 1 was produced.

(Comparative Example 1)
Next, a field effect transistor having a conventional structure will be described as Comparative Example 1 with reference to FIG. The field effect transistors in Example 1 and Comparative Example 1 differ only in the manufacturing method of the gate insulating layer 23, and the other layers were manufactured by the same manufacturing methods and materials.

After forming the gate electrode 22 on the substrate 21 by the same method as in Example 1, 200 nm of SiO ₂ was formed by RF sputtering to form the gate insulating layer 23. Then, the semiconductor layer 24, the source electrode 25, and the drain electrode 26 were formed by the same method as Example 1, and the field effect transistor in the comparative example 1 was produced.

(Example 1 and Comparative Example 1)
FIG. 32 shows transistor characteristics of the field-effect transistor of Example 1 and the field-effect transistor of Comparative Example 1. The field effect transistor of Example 1 and the field effect transistor of Comparative Example 1 both have an ON / OFF ratio, which is the current ratio between the current flowing in the ON state and the current flowing in the OFF state, of 7 digits or more, and the switching operation is It was good. Further, in the field effect transistor of Example 1, like the field effect transistor of Comparative Example 1, the current Id starts to increase when the gate voltage Vg is about 0 V. The field effect transistor of Example 1 is It was confirmed that good transistor characteristics were exhibited. Further, as described above, the field effect transistor of Example 1 has a higher dielectric constant of the gate insulating layer than the field effect transistor of Comparative Example 1, and therefore the current Id flowing in the ON state is The field effect transistor of Example 1 showed a higher value than the field effect transistor of Comparative Example 1.

The magnesium lanthanum composite oxide constituting the gate insulating layer 23 formed in Example 1 has a relative dielectric constant of about 9, and the relative dielectric constant of the SiO ₂ film formed by thermal oxidation in Comparative Example 1 The value was higher than the rate value of about 3.9. Moreover, it was confirmed that it has a low leakage current characteristic. Further, even when the gate insulating layer 23 was heated at 600 ° C. for 1 hour, no diffraction peak was observed in the X-ray diffraction experiment, and it was confirmed to be in an amorphous state.

(Example 2)
A field effect transistor (MOS-FET) in the second embodiment will be described with reference to FIG. In this example, La (thd) ₃ and Sr (thd) ₂ (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) were respectively added to a p-type Si substrate 51 by tetraethylene glycol dimethyl ether (tetraglyme). ) And tetrahydrofuran (THF) were used as liquid raw materials, and a strontium lanthanum composite oxide insulating film was formed to a thickness of 5 nm by the CVD method. Further, after forming a polycrystalline silicon film by a CVD method, the polycrystalline silicon film and the lanthanum strontium complex oxide insulating film are patterned by a photolithography process, thereby forming a gate insulating film 52 and a gate electrode 53. Next, after depositing SiON by the CVD method, the entire surface was dry etched to form a gate sidewall insulating film 54. Next, phosphorus ions were implanted into the p-type Si substrate 51 using the gate electrode 53 and the gate sidewall insulating film 54 as a self-alignment mask, and a source region 55 and a drain region 56 were formed by ion diffusion. Next, SiO ₂ was deposited by CVD, and an interlayer insulating film 57 having contact holes opened was formed by a photolithography process. Finally, an Al layer was deposited by sputtering, a contact hole was filled, and patterning was performed by a photolithography process to form a source electrode 58 and a drain electrode 59. Through the above steps, a field effect transistor (MOS-FET) was manufactured.

  The field effect transistor produced in this example showed good transistor characteristics and low leakage current characteristics.

  It should be noted that the strontium lanthanum composite oxide constituting the gate insulating layer 52 formed in this example has a relative dielectric constant of about 10 and is confirmed to have low leakage current characteristics. Further, it was confirmed by an X-ray diffraction experiment that the film was in an amorphous state.

Example 3
Next, as Example 3, a volatile memory according to this embodiment will be described.

  A manufacturing method of the volatile memory manufactured in Example 3 will be described with reference to FIG.

  First, the gate electrode 112 and the second capacitor electrode 113 were formed on the substrate 111 made of alkali-free glass. Specifically, a molybdenum (Mo) film was formed on the glass substrate 111 by DC sputtering so as to have a thickness of about 100 nm. Thereafter, a photoresist is applied, and a resist pattern similar to the pattern of the gate electrode 112 and the second capacitor electrode 113 to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, RIE (Reactive Ion) Etching) removed the molybdenum film in the region where the resist pattern was not formed, and then removed the resist pattern, thereby forming the gate electrode 112 and the second capacitor electrode 113.

Next, the gate insulating layer 114 was formed. Specifically, La (thd) ₃ and Ba (thd) ₂ (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) are respectively formed on the gate electrode 112 and the glass substrate 111 with tetraethylene glycol. A barium lanthanum complex oxide insulating film having a thickness of about 200 nm was formed by a CVD method using a liquid source material dissolved in dimethyl ether (tetraglyme) and tetrahydrofuran (THF). Thereafter, a photoresist is applied, a resist pattern similar to the pattern of the gate insulating film 114 to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, the resist pattern is formed by RIE (Reactive Ion Etching). The gate insulating layer 114 was formed by removing the barium lanthanum complex oxide insulating film in the region where it was not formed, and then removing the resist pattern.

Next, a capacitor dielectric layer 115 was formed. Specifically, on the second capacitor electrode 123, La (thd) ₃ and Ba (thd) ₂ (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) are respectively tetraethylene glycol dimethyl ether. (Tetraglyme) dissolved in tetrahydrofuran (THF) was used as a liquid raw material, and a barium lanthanum composite oxide insulating film was formed to a thickness of about 50 nm by CVD. Thereafter, a photoresist is applied, a resist pattern similar to the pattern of the capacitor dielectric layer 115 to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, the resist pattern is formed by RIE (Reactive Ion Etching). The capacitor dielectric layer 115 was formed by removing the barium lanthanum complex oxide insulating film in the unformed region and then removing the resist pattern.

  Next, the source electrode 116 and the drain electrode 117 were formed. In this example, the drain electrode 117 also serves as the first capacitor electrode in the third embodiment, and forms a capacitor together with the capacitor dielectric layer 115 and the second capacitor electrode.

  Specifically, an ITO film, which is a transparent conductive film, is formed on the gate insulating layer 114 and the capacitor dielectric layer 115 by a DC sputtering method so that the film thickness becomes about 100 nm, and then, on the ITO film, A resist pattern similar to the pattern of the source electrode 116 and the drain electrode 117 to be formed is formed by applying a photoresist, pre-baking, exposure by an exposure apparatus, and development, and further, an area in which no resist pattern is formed by RIE The ITO film was removed, and then the resist pattern was also removed to form the source electrode 116 and the drain electrode 117 made of the ITO film.

  Next, the semiconductor layer 118 was formed. Specifically, an Mg—In based oxide film is formed to a thickness of about 100 nm by DC sputtering, and then a photoresist is applied on the Mg—In based oxide film, A resist pattern similar to the pattern of the semiconductor layer 118 to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, the Mg-In oxide film in a region where the resist pattern is not formed is removed by RIE. Then, the semiconductor layer 118 was formed by removing the resist pattern. Thus, the semiconductor layer 118 was formed so that a channel was formed between the source electrode 116 and the drain electrode 117.

  A volatile memory was manufactured through the above steps. The barium lanthanum composite oxide constituting the gate insulating layer 114 and the capacitor dielectric layer 115 of the volatile memory manufactured in this example has a relative dielectric constant of about 11, and is confirmed to have low leakage current characteristics. It was done. Further, it was confirmed by an X-ray diffraction experiment that the film was in an amorphous state.

Example 4
Next, the volatile semiconductor memory in Example 4 is demonstrated based on FIG. In this example, Y (thd) 3 and Sr (thd) 2 (thd = 2,2,6,6-tetramethyl-3,5-heptanionato) are respectively formed on a p-type Si substrate 71 by tetraethylene glycol dimethyl ether ( tetraglyme), tetrahydrofuran (THF) dissolved in a solvent as a raw material, and a strontium yttrium composite oxide insulating film was formed to a thickness of 5 nm by CVD. Next, after forming polycrystalline silicon by the CVD method, the gate insulating layer 72 and the gate electrode 73 are formed by patterning the polycrystalline silicon film and the barium yttrium composite oxide insulating film by a photolithography method by a photolithography process. . Next, after depositing SiON by the CVD method, the gate sidewall insulating film 74 was formed by dry etching the entire surface. Next, using the gate electrode 73 and the gate sidewall insulating film 74 as a self-alignment mask, phosphorus ions are implanted into the p-type Si substrate 71 and ion diffusion is performed, thereby forming a source region 75 and a drain region 76. Next, SiO ₂ was deposited by CVD, and an interlayer insulating film 77 having contact holes opened was formed by a photolithography process. A polycrystalline silicon film was deposited by CVD, a contact hole was buried, and a bit line electrode 78 was formed by a photolithography process. Next, SiO ₂ was deposited by CVD, and an interlayer insulating film 79 having contact holes opened was formed on the drain region 76 by a photolithography process. Next, a polycrystalline silicon film was formed by a CVD method, and a capacitor lower electrode 80 was formed by a photolithography process. Next, Y (thd) 3, Sr (thd) 2 (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) were used as solvents in tetraethylene glycol dimethyl ether (tetraglyme) and tetrahydrofuran (THF), respectively. The dissolved material is used as a raw material, a strontium yttrium composite oxide insulating film is formed to a thickness of 30 nm by CVD, a capacitor dielectric layer 81 is formed, a polycrystalline silicon film is formed by CVD, and a capacitor upper electrode 82 is formed. . Through these steps, a volatile semiconductor memory element was produced.

  A volatile memory was manufactured through the above steps. The strontium yttrium composite oxide insulating film constituting the gate insulating layer 72 and the capacitor dielectric layer 81 of the volatile memory manufactured in this example has a relative dielectric constant of about 7 and low leakage current characteristics. Was confirmed. Further, it was confirmed by an X-ray diffraction experiment that the film was in an amorphous state.

(Example 5)
Next, as Example 5, a nonvolatile memory according to this embodiment will be described.

  Based on FIG. 11, which is a configuration diagram of a volatile memory manufactured in Example 5, a method for manufacturing a nonvolatile memory in Example 5 will be described.

  First, the gate electrode 92 was formed on the substrate 91 made of alkali-free glass. Specifically, a molybdenum (Mo) film was formed on the glass substrate 91 by DC sputtering so as to have a thickness of about 30 nm. After that, a photoresist is applied, a resist pattern similar to the pattern of the gate electrode 92 to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, a resist pattern is formed by RIE (Reactive Ion Etching) The molybdenum film in the region that was not formed was removed, and then the resist pattern was also removed, thereby forming the gate electrode 92.

Next, the gate insulating layer 93 was formed. Specifically, on the gate electrode 92 and the glass substrate 91, La (thd) ₃ and Ca (thd) ₂ (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) are respectively tetraethylene glycol. A material dissolved in dimethyl ether (tetraglyme) and tetrahydrofuran (THF) was used as a liquid raw material, and a calcium lanthanum composite oxide insulating film was formed to a thickness of about 100 nm by a CVD method to form a gate insulating layer 93.

  Next, a floating gate electrode 94 was formed. Specifically, Mo (molybdenum) was deposited on the gate insulating layer 93 by DC sputtering so as to have a thickness of about 15 nm. Thereafter, a photoresist is applied, a resist pattern similar to the pattern of the gate electrode 94 to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, a resist pattern is formed by RIE (Reactive Ion Etching) The molybdenum film in the region that was not formed was removed, and then the resist pattern was also removed, thereby forming the gate electrode 94.

Next, a second gate insulating layer 95 was formed. More specifically, the gate insulating layer 93, on top of the floating gate electrode 94, was formed to a thickness of 50nm of SiO ₂ by CVD method to form a second gate insulating layer 95.

  Next, the source electrode 96 and the drain electrode 97 were formed. Specifically, an ITO film, which is a transparent conductive film, is formed on the second gate insulating layer 95 by DC sputtering so as to have a film thickness of about 100 nm, and then a photoresist is formed on the ITO film. The resist pattern similar to the pattern of the source electrode 96 and the drain electrode 97 to be formed is formed by coating, pre-baking, exposure by an exposure apparatus, and development, and further, the ITO film in the region where the resist pattern is not formed by RIE Thereafter, the resist pattern is also removed, thereby forming a source electrode 96 and a drain electrode 97 made of an ITO film.

  Next, the semiconductor layer 98 was formed. Specifically, an Mg—In based oxide film is formed to a thickness of about 100 nm by DC sputtering, and then a photoresist is applied on the Mg—In based oxide film, A resist pattern similar to the pattern of the semiconductor layer 98 to be formed is formed by pre-baking, exposure with an exposure apparatus, and development, and further, RIE removes the Mg-In oxide film in the region where the resist pattern is not formed. Then, the semiconductor layer 98 was formed by removing the resist pattern. As a result, the semiconductor layer 98 was formed so that a channel was formed between the source electrode 96 and the drain electrode 97.

  Through the above steps, a nonvolatile memory was manufactured. The calcium lanthanum composite oxide insulating film constituting the gate insulating layer 93 of the nonvolatile memory manufactured in this example has a relative dielectric constant of about 8 and is confirmed to have low leakage current characteristics. Further, it was confirmed by an X-ray diffraction experiment that the film was in an amorphous state.

(Example 6)
Next, the non-volatile semiconductor memory in Example 6 is demonstrated based on FIG. In this example, a surface of the p-type Si substrate 101 was thermally oxidized to form a SiO ₂ film having a thickness of 5 nm, and then a tunnel insulating film 104 as a second gate insulating layer was formed by a photolithography process. Next, a polycrystalline silicon film was formed by a CVD method, and a floating gate electrode 105 was formed by a photolithography process. Next, a mixed powder of Y (thd) 3, Sr (thd) 2 (thd = 2,2,6,6-tetramethyl-3,5-heptanedionato) is mixed with tetrahydrofuran (THF) and ethylene glycol dimethyl ether (DME). A material dissolved in a solvent was used as a raw material, a strontium barium composite oxide insulating film was formed to a thickness of 25 nm by a CVD method, and a gate insulating layer 102 was formed by a photolithography process. Next, a polycrystalline silicon film was formed by a CVD method, and a gate electrode 103 was formed by a photolithography process.

  Next, after depositing SiON by the CVD method, the gate sidewall insulating film 106 was formed by dry etching the entire surface. Next, using the gate electrode 103 and the gate sidewall insulating film 106 as a self-alignment mask, phosphorus ions are implanted into the p-type Si substrate 101 and ion diffusion is performed, thereby forming the source region 107 and the drain region 108.

  Through the above steps, a nonvolatile memory was manufactured. The strontium yttrium composite oxide insulating film constituting the gate insulating layer 102 of the nonvolatile memory manufactured in this example has a relative dielectric constant of about 7, and it was confirmed that it has low leakage current characteristics. Further, it was confirmed by an X-ray diffraction experiment that the film was in an amorphous state.

(Example 7)
Next, as Example 7, a display element according to the present invention will be described in detail. The display element in Example 7 is an organic EL display element having the configuration shown in FIG. 16, and a method for manufacturing the organic EL display element in Example 7 will be described based on FIG.

  First, in step 102 (S102), the first gate electrode 202 and the second gate electrode 203 were formed. Specifically, a molybdenum (Mo) film was formed on a glass substrate 201 made of alkali-free glass by a DC sputtering method so as to have a thickness of about 100 nm. Thereafter, a photoresist is applied, a resist pattern similar to the pattern to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, an area where no resist pattern is formed by RIE (Reactive Ion Etching) The aluminum film was removed, and then the resist pattern was also removed, whereby the first gate electrode 202 and the second gate electrode 203 were formed.

Next, in step 104 (S104), the gate insulating layer 204 was formed. Specifically, on the first gate electrode 202, the second gate electrode 203, and the glass substrate 201, La (thd) ₃ , Mg (thd) ₂ (thd = 2,2,6,6-tetramethyl-3 , 5-heptanedionato) dissolved in tetraethylene glycol dimethyl ether (tetraglyme) and tetrahydrofuran (THF) as liquid raw materials, a magnesium lanthanum composite oxide insulating film was formed to a thickness of about 200 nm by CVD. Thereafter, a photoresist is applied, a resist pattern similar to the pattern to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, an area where no resist pattern is formed by RIE (Reactive Ion Etching) The magnesium lanthanum composite oxide insulating film was removed, and then the resist pattern was also removed. Thus, the gate insulating layer 204 having a through hole was formed over the second gate electrode 203.

  Next, in step 106 (S106), first and second source electrodes 205 and 207 and first and second drain electrodes 206 and 208 were formed. Specifically, an ITO film, which is a transparent conductive film, is formed on the gate insulating layer 204 by DC sputtering so that the film thickness becomes about 100 nm, and then a photoresist is applied on the ITO film, A resist pattern similar to the pattern to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, the ITO film in a region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed. As a result, first and second source electrodes 205 and 207 made of an ITO film and first and second drain electrodes 206 and 208 were formed. As a result, the first drain electrode 206 and the first gate electrode 203 were connected.

  Next, in step 108 (S108), the first semiconductor layer 209 and the second semiconductor layer 210 were formed. Specifically, an Mg—In based oxide film is formed to a thickness of about 100 nm by DC sputtering, and then a photoresist is applied on the Mg—In based oxide film, A resist pattern similar to the pattern to be formed is formed by pre-baking, exposure by an exposure apparatus, and development, and further, the RIE removes the Mg—In-based oxide film in the region where the resist pattern is not formed. The first semiconductor layer 209 and the second semiconductor layer 210 were formed by removing the resist pattern. Accordingly, the first semiconductor layer 209 is formed between the second source electrode 207 and the second drain electrode 208 so that a channel is formed between the first source electrode 205 and the first drain electrode 206. The second semiconductor layer 210 was formed so that a channel was formed therebetween.

  Next, in step 110 (S110), a first protective film 211 and a second protective layer 212 were formed. Specifically, a photosensitive fluororesin was applied to the entire surface of the substrate, and a desired pattern was obtained by pre-baking, exposure using an exposure apparatus, and development, and then post-baking. The film thickness of the first protective film 211 and the second protective layer 212 thus formed was about 400 nm.

  Next, in step 112 (S112), the partition wall 213 was formed. Specifically, a photosensitive polyimide material was applied to the entire surface of the substrate, and a desired pattern was obtained by pre-baking, exposure using an exposure apparatus, and development, and then post-baking. The film thickness of the partition wall 213 formed in this way was about 1 μm.

  Next, in step 114 (S114), the organic EL layer 214 was formed in a region where the partition wall 213 was not formed using an ink jet apparatus.

  Next, in step 116 (S116), the upper electrode 215 was formed. Specifically, the upper electrode 215 was formed by vacuum vapor deposition of MgAg.

Next, in step 118 (S118), the sealing layer 216 was formed. Specifically, the sealing layer 216 was formed by forming a SiO ₂ film with a thickness of about 2 μm by CVD.

  Next, in step 120 (S120), the counter substrate 218 was bonded. Specifically, an adhesive layer 217 was formed over the sealing layer 216, and a counter substrate 218 made of non-alkali glass was bonded thereto. Thus, a display panel of the organic EL display device in Example 7 having the configuration shown in FIG. 16 was produced.

  Next, in step 122 (S122), a display control device was connected. Specifically, a display control device (not shown) is connected to the display panel so that an image can be displayed on the display panel. This produced the image display system of the organic EL display element.

  The organic EL display device fabricated in Example 7 can be driven at a low voltage, and the power consumption of the image display system can be suppressed to a low level.

  As mentioned above, although the form which concerns on implementation of this invention was demonstrated, the said content shows embodiment of this invention and does not limit the content of invention.

11 Insulating substrate 12 Gate electrode 13 Gate insulating film 14 Source electrode 15 Drain electrode 16 Semiconductor layer

JP-A-11-135774 Japanese Patent No. 3637325 Japanese Patent Laid-Open No. 2002-270828 JP 2002-134737 A Japanese Patent No. 3773448 JP 2003-258243 A Japanese Patent No. 3831764 JP 2008-16807 A

Claims (15)

A substrate,
A source electrode, a drain electrode, and a gate electrode formed on the substrate;
A semiconductor layer in which a channel is formed between a source electrode and a drain electrode by applying a predetermined voltage to the gate electrode;
A gate insulating layer between the gate electrode and the semiconductor layer;
With
The gate insulating layer includes one or more elements selected from alkaline earth metals and one or more elements selected from lanthanoids excluding Ga, Sc, Y, and Ce. A field effect transistor characterized in that it is formed of an amorphous composite metal oxide insulating film containing silicon (excluding those containing Si and Al) .   The field effect transistor according to claim 1, wherein the semiconductor layer is an oxide semiconductor.   The field effect transistor according to claim 1, wherein the substrate is an insulating substrate.   The field effect transistor according to claim 1, wherein the substrate is a semiconductor substrate. The field effect transistor according to any one of claims 1 to 4,
A first capacitor electrode connected to the drain electrode;
A second capacitor electrode;
A capacitor dielectric layer provided between the first capacitor electrode and the second capacitor electrode;
Volatile semiconductor memory comprising: The capacitor dielectric layer comprises:
Amorphous composite metal oxidation comprising one or more elements selected from alkaline earth metals and one or more elements selected from lanthanoids excluding Ga, Sc, Y, and Ce 6. The volatile semiconductor memory according to claim 5, wherein the volatile semiconductor memory is formed of a material insulating film. In the field effect transistor according to any one of claims 1 to 4,
A non-volatile semiconductor memory, further comprising a second gate insulating layer and a floating gate electrode between the semiconductor layer and the gate insulating layer. A light control element whose light output is controlled according to a drive signal;
A drive circuit including the field effect transistor according to any one of claims 1 to 3, which drives the light control element;
A display element comprising:   The display device according to claim 8, wherein the light control element includes an organic electroluminescence element.   The display element according to claim 8, wherein the light control element includes a liquid crystal element.   The display element according to claim 8, wherein the light control element includes an electrochromic element. The display element according to claim 8, wherein the light control element includes an electrophoretic element.   The display element according to claim 8, wherein the light control element includes an electrowetting element. An image display device that displays an image according to image data,
A plurality of display elements according to any one of claims 8 to 13 arranged in a matrix,
A plurality of wirings for individually applying a gate voltage to each field effect transistor in the plurality of display elements;
In accordance with the image data, a display control device that individually controls the gate voltage of each field effect transistor via the plurality of wirings;
An image display device comprising: An image display device according to claim 14,
Creating image data based on image information to be displayed, and outputting the image data to the image display device;
A system comprising:

Images