JP6855848B2 - Field-effect transistor manufacturing method, volatile semiconductor memory device manufacturing method, non-volatile semiconductor memory device manufacturing method, display element manufacturing method, image display device manufacturing method, system manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a field effect transistor, a method for manufacturing a volatile semiconductor memory element, a method for manufacturing a non-volatile semiconductor memory device, a method for manufacturing a display element, a method for manufacturing an image display device, and a method for manufacturing a system.

A field effect transistor (FET), which is a type of semiconductor element, applies a voltage to the gate electrode and creates a gate for the flow of electrons or holes by the electric current of the channel. It is a transistor that controls the current between the electrodes.

FETs are used as switching elements and amplification elements because of their characteristics. In addition to having a low gate current, the structure is flat, so that it is easier to manufacture and integrate than a bipolar transistor. Therefore, FET has become an indispensable element in integrated circuits used in current electronic devices.

Conventionally, a silicon-based insulating film has been widely used for the gate insulating layer of a field-effect transistor. However, in recent years, there has been an increasing demand for higher integration and lower power consumption of field-effect transistors, and a so-called high-k insulating film having a significantly higher relative permittivity than a silicon-based insulating film is used for the gate insulating layer. Technology is being considered. For example, field-effect transistors and semiconductor memories have been proposed in which an oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid is used as a gate insulating layer (for example, a patent). Reference 1).

Further, since the oxide containing the alkaline earth metal and the rare earth element (Sc, Y, lanthanoid) has a high barrier property, the oxide containing the alkaline earth metal and the rare earth element is used as a passivation layer. A provided electric field effect type transistor has been proposed (see, for example, Patent Document 2).

As a method for patterning an oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid, Patent Document 1 discloses a photolithography process using dry etching. Dry etching is not preferable because it has disadvantages such as high risk of gas used, heavy environmental load, and expensive equipment used, and patterning by a photolithography process using wet etching is preferable.

_{By the way, the silicon-based insulating film (SiO 2} or SiON) that has been widely used in the gate insulating layer and the passivation layer can be wet-etched with a hydrofluoric acid-based etching solution. However, there is no report on a solution capable of wet-etching an oxide containing an alkaline earth metal and a rare earth element, and among alkaline earth metals and Ga, Sc, Y, and lanthanoids in the gate insulating layer or the passivation layer. When an oxide containing a selected element was used, patterning by a photolithography process using wet etching was difficult.

Therefore, in the manufacturing process of a field effect transistor in which an oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid is used as a gate insulating layer or a passivation layer, the gate insulating layer is used. Alternatively, it is desired that the passivation layer be formed by a photolithography process using wet etching.

The present invention relates to a field effect transistor in which at least one of a gate insulating layer and a passivation layer is formed of a first oxide containing an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanoid. In the production method, it is an object to pattern a layer formed from a first oxide by wet etching.

The method for manufacturing the electric field effect type transistor is a method for manufacturing an electric field effect type transistor having a gate insulating layer, an active layer, and a passivation layer, and is a first step for forming the gate insulating layer and the passivation. Including a second step of forming a layer, at least one of the first step and the second step comprises an alkaline earth metal and at least one of Ga, Sc, Y, and lanthanoid. The step of forming the first oxide containing the oxide, and etching the first oxide with a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide solution. It is a requirement to include the process to be performed.

According to the disclosed technique, an electric field effect formed from a first oxide in which at least one of the gate insulating layer and the passivation layer contains an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanoid. In the method for manufacturing a type transistor, the layer formed from the first oxide can be patterned by wet etching.

It is sectional drawing which illustrates the field effect transistor which concerns on 1st Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is a figure (the 2) which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 1st Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on 2nd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the organic EL display element which concerns on 3rd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the organic EL display element which concerns on the modification of 3rd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the field effect transistor which concerns on 4th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the volatile semiconductor memory element which concerns on 5th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the volatile semiconductor memory element which concerns on 6th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the non-volatile semiconductor memory element which concerns on 7th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the non-volatile semiconductor memory element which concerns on 8th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on 9th Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the field effect transistor which concerns on 9th Embodiment. It is a figure (the 2) which illustrates the manufacturing process of the field effect transistor which concerns on 9th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of the 9th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on 10th Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the field effect transistor which concerns on tenth embodiment. It is a figure (No. 2) which illustrates the manufacturing process of the field effect transistor which concerns on tenth embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of the tenth embodiment. FIG. 1 is a cross-sectional view (No. 1) for explaining the structure and manufacturing method of the organic EL display element according to the eleventh embodiment. FIG. 2 is a cross-sectional view (No. 2) for explaining the structure and manufacturing method of the organic EL display element according to the eleventh embodiment. It is a block diagram which shows the structure of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 1) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 2) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 3) of the television apparatus which concerns on the twelfth embodiment. It is explanatory drawing of the display element which concerns on 12th Embodiment. It is explanatory drawing of the organic EL which concerns on 12th Embodiment. It is explanatory drawing (the 4) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 1) of the other display element which concerns on 12th Embodiment. It is explanatory drawing (the 2) of the other display element which concerns on 12th Embodiment. It is a figure which shows the Vgs-Ids characteristic change before and after the BTS test. It is a figure which shows the change amount (ΔVth) of the threshold voltage with respect to a stress time.

Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.

The inventors have prepared a first oxide containing an element A, which is an alkaline earth metal, and an element B, which is at least one of Ga, Sc, Y, and a lanthanoid, in hydrochloric acid, oxalic acid, nitric acid, and the like. It has been found that etching is possible by contacting with a first solution containing at least one of phosphoric acid, acetic acid, sulfuric acid and aqueous hydrogen peroxide. Each of the following embodiments is based on the above findings of the inventors.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating the field effect transistor according to the first embodiment. Referring to FIG. 1, the field effect transistor 10 has a substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, an active layer 16, and a passivation layer 17. It is a bottom gate / bottom contact type field effect transistor. The field effect transistor 10 is a typical example of the semiconductor device according to the present invention.

Further, one of the functions of the passivation layer in the present invention is a layer having a function of isolating and protecting at least the active layer (semiconductor layer) from moisture, oxygen, hydrogen and the like in the atmosphere. Further, the passivation layer in the present invention may protect not only the active layer but also other components of the field effect transistor (for example, the gate insulating layer, the source electrode, the drain electrode, and the gate electrode). Good. One of the functions of the passivation layer in the present invention is to protect (at least a part of) the field effect transistor from the material of the layer formed on the field effect transistor and the formation process thereof.

Further, the passivation layer of the field-effect transistor may be physically separated from other components of the field-effect transistor via, for example, an EL (Electro Luminescence) element, regardless of where it is formed. However, it is one of the components of the field effect transistor. That is, for example, the passivation layer formed after forming the EL element or the like or the passivation layer provided in the vicinity of the interlayer insulating film is also used as the passivation layer of the field effect type tongue star.

The passivation layer is also sometimes called a protective layer.

In the field effect transistor 10, the gate electrode 12 is formed on the insulating substrate 11, and the gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, the source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13, and the active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are formed at predetermined intervals that serve as channel regions of the active layer 16. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16. Hereinafter, each component of the field effect transistor 10 will be described in detail.

In the present embodiment, for convenience, the passivation layer 17 side is the upper side or one side, and the substrate 11 side is the lower side or the other side. Further, the surface on the passivation layer 17 side of each portion is defined as the upper surface or one surface, and the surface on the substrate 11 side is defined as the lower surface or the other surface. However, the field-effect transistor 10 can be used in an upside-down state, or can be arranged at an arbitrary angle. Further, the plan view means that the object is viewed from the normal direction of the upper surface of the substrate 11, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the substrate 11.

The shape, structure, and size of the substrate 11 are not particularly limited and may be appropriately selected depending on the intended purpose. The material of the substrate 11 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a glass substrate, a ceramic substrate, a plastic substrate, a film substrate and the like can be used.

The glass base material is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include non-alkali glass and silica glass. The plastic base material and the film base material are not particularly limited and may be appropriately selected depending on the intended purpose. For example, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate, etc. (PEN) and the like.

The gate electrode 12 is formed in a predetermined region on the substrate 11. The gate electrode 12 is an electrode for applying a gate voltage. The material of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag). ), Copper (Cu), Zinc (Zn), Nickel (Ni), Chromium (Cr), Tantal (Ta), Molybdenum (Mo), Titanium (Ti) and other metals, alloys of these, mixtures of these metals, etc. Can be used. Further, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide and niobium oxide, composite compounds thereof, and mixtures thereof may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. The average film thickness of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 10 nm to 1 μm, more preferably 50 nm to 300 nm.

The gate insulating layer 13 is provided between the gate electrode 12 and the active layer 16 and is a layer for insulating the gate electrode 12 and the active layer 16. The average film thickness of the gate insulating layer 13 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 50 nm to 3 μm, more preferably 100 nm to 1 μm.

The source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13. The source electrode 14 and the drain electrode 15 are formed at predetermined intervals. The source electrode 14 and the drain electrode 15 are electrodes for extracting a current in response to application of a gate voltage to the gate electrode 12. In addition to the source electrode 14 and the drain electrode 15, the wiring connected to the source electrode 14 and the drain electrode 15 may be formed in the same layer.

The materials of the source electrode 14 and the drain electrode 15 are not particularly limited and may be appropriately selected depending on the intended purpose. For example, aluminum (Al), platinum (Pt), palladium (Pd), and gold (Au). , Silver (Ag), Copper (Cu), Zinc (Zn), Nickel (Ni), Chromium (Cr), Tantal (Ta), Molybdenum (Mo), Titanium (Ti) and other metals, Alloys of these, These metals A mixture of the above can be used.

Further, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide and niobium oxide, composite compounds thereof, and mixtures thereof may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. The average film thickness of the source electrode 14 and the drain electrode 15 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 10 nm to 1 μm, more preferably 50 nm to 300 nm.

The active layer 16 is formed on the gate insulating layer 13 so as to cover a part of the source electrode 14 and the drain electrode 15. The active layer 16 located between the source electrode 14 and the drain electrode 15 serves as a channel region. The average film thickness of the active layer 16 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 5 nm to 1 μm, more preferably 10 nm to 0.5 μm.

The material of the active layer 16 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), In-Ga-Zn- Examples thereof include oxide semiconductors such as O and organic semiconductors such as pentacene. Among these, it is preferable to use an oxide semiconductor from the viewpoint of the stability of the interface between the gate insulating layer 13 and the passivation layer 17.

The passivation layer 17 is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16. The average film thickness of the passivation layer 17 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 50 nm to 3 μm, more preferably 100 nm to 1 μm. In FIG. 1, the planar shape of the passivation layer 17 matches the planar shape of the gate insulating layer 13, but the present invention is not limited to this. For example, the planar shape of the passivation layer 17 may be smaller than the planar shape of the gate insulating layer 13. Alternatively, the planar shape of the passivation layer 17 may be made larger than the planar shape of the gate insulating layer 13 to cover the side surface of the gate insulating layer 13.

At least one of the gate insulating layer 13 and the passivation layer 17 is an oxide. The oxide used in the present embodiment (hereinafter referred to as the first oxide) includes element A, which is an alkaline earth metal, gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid. At least one of the above elements B is contained, and if necessary, other components are contained. The alkaline earth metal contained in the first oxide may be one kind or two or more kinds.

Examples of the alkaline earth metal include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and radium (Ra).

Lantanoids include lanthanum (La), cerium (Ce), placeodim (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), and dysprosium. (Dy), holmium (Ho), erybium (Er), turium (Tm), ytterbium (Yb), lutetium (Lu) can be mentioned.

The first oxide is preferably a normal dielectric amorphous oxide. The normal dielectric amorphous oxide is stable in the atmosphere and can stably form an amorphous structure in a wide composition range. However, crystals may be contained in a part of the first oxide.

The fact that the gate insulating layer 13 is made of an amorphous material is a preferable form in terms of improving the characteristics of the transistor. This is because if the gate insulating layer 13 is made of a crystalline material, the leakage current due to the grain boundaries cannot be suppressed low, which leads to deterioration of the transistor characteristics.

Further, it is necessary that the gate insulating layer 13 is a normal dielectric material in order to reduce hysteresis in the transfer characteristics of the transistor. With the exception of special cases where the transistor is used for applications such as memory, it is not preferable that hysteresis is present in a device that normally utilizes the switching characteristics of the transistor.

A normal dielectric is a dielectric other than a piezoelectric body, a pyroelectric body, or a ferroelectric substance, that is, a dielectric material that is not polarized by pressure or has spontaneous polarization in the absence of an external electric field. Point to. Further, the piezoelectric body, the pyroelectric body and the ferroelectric body need to be crystals in order to exhibit their characteristics. That is, when the gate insulating layer 13 is formed of an amorphous material, the gate insulating layer 13 is inevitably a normal dielectric material.

Alkaline earth metal oxides easily react with moisture and carbon dioxide in the atmosphere and easily change to hydroxides and carbonates, so they are not suitable for application to electronic devices by themselves. In addition, simple oxides such as Ga, Sc, Y, and lanthanoids are easily crystallized, and leakage current becomes a problem. However, the first oxide is suitable for the gate insulating layer 13 because it is stable in the atmosphere and can form an isoelectric amorphous film in a wide composition region.

Since Ce is specifically tetravalent among lanthanoids and forms crystals having a perovskite structure with alkaline earth metals, it is preferable that the B element is not Ce in order to obtain an amorphous phase.

Crystal phases such as spinel structure exist between alkaline earth metal oxide and Ga oxide, but these crystals do not precipitate unless the temperature is very high compared to perovskite structure crystals (generally 1000 ° C or higher). ). In addition, the existence of a stable crystal phase has not been reported between the alkaline earth metal oxide and the oxide composed of Sc, Y, and lanthanoid, and crystal precipitation from the amorphous phase even after a high temperature post-step. Is rare. Further, when the alkali earth metal and the oxide containing Ga, Sc, Y, and lanthanoid are composed of three or more kinds of metal elements, the amorphous phase is further stabilized.

From the viewpoint of producing a high dielectric constant film, it is preferable to increase the composition ratio of elements such as Ba, Sr, Lu, and La. Further, since the first oxide has an excellent barrier property against moisture and oxygen in the atmosphere, it can also be used as a material for the passivation layer 17.

The first oxide preferably further contains element C, which is at least one of Al, Ti, Zr, Hf, Nb, and Ta. As a result, the amorphous phase can be further stabilized, and the thermal stability, heat resistance, and denseness can be further improved.

The composition ratio of the element A, which is an alkaline earth metal in the first oxide, and the element B, which is at least one of Ga, Sc, Y, and a lanthanoid, is not particularly limited and depends on the purpose. It can be appropriately selected, but it is preferably in the following range.

In the first oxide, as a composition ratio (element A: element B) of element A, which is an alkaline earth metal, and element B, which is at least one of Ga, Sc, Y, and lanthanoid. Oxides (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , In _{terms of Lu 2} O ₃ ), 10.0 mol% to 67.0 mol%: preferably 33.0 mol% to 90.0 mol%.

The element A, which is an alkaline earth metal in the first oxide, the element B, which is at least one of Ga, Sc, Y, and a lanthanoid, and Al, Ti, Zr, Hf, Nb, and Ta. The composition ratio with at least one of the C elements is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably in the following range.

In the first oxide, an element A which is an alkaline earth metal, an element B which is at least one of Ga, Sc, Y, and a lanthanoid, and Al, Ti, Zr, Hf, Nb, and Ta. As the composition ratio (element A: element B: element C) with at least one of the above elements, oxides (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TIO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ ) In terms of conversion, 5.0 mol% to 22.0 mol%: 33.0 mol% to 90.0 mol: 5.0 mol% to 45.0 mol% is preferable.

Oxides in the first oxide (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , The proportions of Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ ) are, for example, fluorescent X-ray analysis, electron beam micro-analysis ( It can be calculated by analyzing the cation element of the oxide by EPMA), dielectric coupled plasma emission spectroscopic analysis (ICP-AES), or the like.

When the first oxide is used for the gate insulating layer 13, the material of the passivation layer 17 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN can be used. Similarly, when the first oxide is used for the passivation layer 17, the material of the gate insulating layer 13 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can. However, the first oxide may be used for both the gate insulating layer 13 and the passivation layer 17. In this case, the interface between the gate insulating layer 13 and the passivation layer 17 is stable, and more reliable characteristics can be easily obtained.

When the first oxide is used for both the gate insulating layer 13 and the passivation layer 17, the gate insulating layer 13 and the passivation layer 17 do not have to be the same material. For example, when the gate insulating layer 13 is an oxide containing Mg, Ba as an element A and La as an element B, the passivation layer 17 is gate-insulated with an oxide containing Ca, Sr as an element A and Gd as an element B. A first oxide different from layer 13 can be used.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field-effect transistor shown in FIG. 1 will be described. 2 and 3 are diagrams illustrating a manufacturing process of the field effect transistor according to the first embodiment.

First, in the step shown in FIG. 2A, the substrate 11 is prepared. Then, a conductive film is formed on the substrate 11 by a vacuum vapor deposition method or the like, and the formed conductive film is patterned by photolithography and etching to form a gate electrode 12 having a predetermined shape. From the viewpoint of cleaning the surface of the substrate 11 and improving the adhesion, it is preferable that pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning is performed before forming the gate electrode 12. The material and thickness of the substrate 11 and the gate electrode 12 can be appropriately selected as described above.

The method for forming the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, after film formation by a sputtering method, a vacuum vapor deposition method, a dip coating method, a spin coating method, a die coating method or the like, A method of patterning by photolithography can be mentioned. Another example is a method of directly forming a desired shape by a printing process such as inkjet, nanoimprint, or gravure.

Next, in the step shown in FIG. 2B, an insulating layer 130 (a layer that finally becomes the gate insulating layer 13) that covers the gate electrode 12 is formed on the entire surface of the substrate 11. The method for forming the insulating layer 130 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a sputtering method, a pulse laser deposit (PLD) method, a chemical vapor deposition (CVD) method, or an atomic layer Examples thereof include a film forming step by a vacuum process such as a vapor deposition (ALD) method and a solution process such as dip coating, spin coating, and die coating. Other examples include printing processes such as inkjet, nanoimprint, and gravure. The material and thickness of the insulating layer 130 are as described for the gate insulating layer 13.

Next, in the step shown in FIG. 2C, the insulating layer 130 formed on the entire surface of the substrate 11 is patterned by photolithography and wet etching to form a predetermined shape to form the gate insulating layer 13. Specifically, first, a mask for etching is formed on the insulating layer 130. The mask for etching is not particularly limited, but can be formed, for example, by spin coating, prebaking, exposing, developing, or post-baking a general-purpose resist material. Alternatively, a metal pattern or an oxide pattern formed by a photolithography process can be used as a mask.

After forming the mask, the insulating layer 130 is etched to form the gate insulating layer 13. The first oxide constituting the gate insulating layer 13 is a solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide solution (hereinafter referred to as the first solution). It can be etched by contacting it. Specifically, a method in which the first oxide is immersed in the first solution for etching, or a method in which the first solution is dropped onto the first oxide and the substrate 11 is rotated. An example is a method of etching.

The concentration of hydrochloric acid is preferably 0.001 mol / L to 6 mol / L, more preferably 0.01 mol / L to 1 mol / L. The concentration of oxalic acid is preferably 0.1 to 10%, more preferably 1 to 5%. The concentration of nitric acid is preferably 0.1 to 40%, more preferably 1 to 20%. The concentration of phosphoric acid is preferably 1 to 90%, more preferably 10 to 80%. The concentration of acetic acid is preferably 0.1 to 80%, more preferably 1 to 50%. The concentration of sulfuric acid is preferably 0.1 to 50%, more preferably 1 to 20%. The concentration of the hydrogen peroxide solution is preferably 0.1 to 20%, more preferably 1 to 10%. Among these solutions, hydrochloric acid and a mixed solution of phosphoric acid and nitric acid are preferable because of the high solubility of the first oxide.

After the insulating layer 130 is etched to form the gate insulating layer 13, the mask is removed. The mask removing step is not particularly limited, but can be removed, for example, by immersing the mask material in a soluble solution.

Next, in the step shown in FIG. 2D, a source electrode 14 and a drain electrode 15 having a predetermined shape are formed on the gate insulating layer 13. From the viewpoint of cleaning the surface of the gate insulating layer 13 and improving the adhesion, it is preferable that pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning is performed before forming the source electrode 14 and the drain electrode 15.

The method for forming the source electrode 14 and the drain electrode 15 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a sputtering method, a vacuum vapor deposition method, a dip coating method, a spin coating method, a die coating method or the like can be used. After the film formation, a method of patterning by photolithography can be mentioned. Another example is a method of directly forming a desired shape by a printing process such as inkjet, nanoimprint, or gravure. The material and thickness of the source electrode 14 and the drain electrode 15 can be appropriately selected as described above.

Next, in the step shown in FIG. 3A, an active layer 16 having a predetermined shape is formed on the gate insulating layer 13. The method for forming the active layer 16 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, after film formation by a sputtering method, a vacuum vapor deposition method, a dip coating method, a spin coating method, a die coating method or the like, A method of patterning by photolithography can be mentioned. Another example is a method of directly forming a desired shape by a printing process such as inkjet, nanoimprint, or gravure. The material and thickness of the active layer 16 can be appropriately selected as described above.

Next, in the step shown in FIG. 3B, the insulating layer 170 (finally, the passivation layer) that covers the source electrode 14, the drain electrode 15, and the active layer 16 on the entire surface of the substrate 11 and the gate insulating layer 13. 17 layers) are formed. The method for forming the insulating layer 170 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a sputtering method, a pulse laser deposit (PLD) method, a chemical vapor deposition (CVD) method, or an atomic layer Examples thereof include a film forming step by a vacuum process such as a vapor deposition (ALD) method and a solution process such as dip coating, spin coating and die coating. Other examples include printing processes such as inkjet, nanoimprint, and gravure. The material and thickness of the insulating layer 170 are as described for the passivation layer 17.

Next, in the step shown in FIG. 3C, the insulating layer 170 formed on the entire surface of the substrate 11 and the gate insulating layer 13 is patterned by photolithography and wet etching to form a predetermined shape to form the passivation layer 17. To do. The specific method is the same as the method of forming the gate insulating layer 13 from the insulating layer 130 in FIG. 2 (c).

Through the above steps, a bottom gate / bottom contact type field effect transistor 10 can be manufactured.

As described above, in the present embodiment, at least one of the gate insulating layer 13 and the passivation layer 17 is the element A, which is an alkaline earth metal, and at least one of Ga, Sc, Y, and a lanthanoid. It is an oxide containing element B. Then, the first oxide is wet-etched with a solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide solution (the first solution) to form a predetermined shape. Patterning.

By using the first solution, the gate insulating layer 13 and the passivation layer 17 can be suitably wet-etched. Since it is not necessary to use a conventional dry etching process, no high-risk gas is used, and there are no problems such as environmental load and the price of the equipment used.

Further, since the relative permittivity of the first oxide is about 6 to 20, which _{is higher than that of the SiO 2} film, the use of the first oxide in the gate insulating layer lowers the field effect transistor. Voltage drive (low power consumption) is possible. Further, since the first oxide has a high barrier property, the use of the first oxide in the passivation layer 17 makes it possible to improve the reliability of the field effect transistor.

That is, a high-performance (low power consumption, high reliability) electric field is obtained by using the first oxide in at least one of the gate insulating layer 13 and the passivation layer 17 and wet-etching the first oxide. Effective transistors can be manufactured at low cost, high safety, and low environmental load.

<Modified example of the first embodiment>
A modification of the first embodiment shows an example of a field effect transistor having a layer structure different from that of the first embodiment. In the modified example of the first embodiment, the description of the same component as that of the above-described embodiment may be omitted.

FIG. 4 is a cross-sectional view illustrating the field effect transistor according to the modified example of the first embodiment. Each field-effect transistor shown in FIG. 4 is a typical example of the semiconductor device according to the present invention.

The field-effect transistor 10A shown in FIG. 4A is a bottom-gate / top-contact field-effect transistor. In the field effect transistor 10A, the gate electrode 12 is formed on the insulating substrate 11, and the gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, an active layer 16 is formed on the gate insulating layer 13, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 at predetermined intervals which are channel regions of the active layer 16. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16.

The field-effect transistor 10B shown in FIG. 4B is a top-gate / bottom-contact field-effect transistor. In the field effect transistor 10B, the source electrode 14 and the drain electrode 15 are formed on the insulating substrate 11, and the active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the gate electrode 12.

The field-effect transistor 10C shown in FIG. 4C is a top-gate / top-contact field-effect transistor. In the field-effect transistor 10C, the active layer 16 is formed on the insulating substrate 11, and the source electrode 14 and the drain electrode 15 are separated on the active layer 16 by a predetermined interval which becomes a channel region of the active layer 16. It is formed. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the gate electrode 12.

As described above, the layer structure of the field-effect transistor according to the present invention is not particularly limited, and the structures shown in FIGS. 1 and 4 can be appropriately selected depending on the intended purpose. Regarding the field effect transistors 10A, 10B, and 10C shown in FIG. 4, at least one of the gate insulating layer 13 and the passivation layer 17 is the first oxide, and the gate insulating layer 13 and the passivation layer 17 are electric fields. It can be manufactured by the same manufacturing method as the effect transistor 10. Therefore, the field effect transistors 10A, 10B, and 10C also have the same effect as the field effect transistors 10.

<Second Embodiment>
In the second embodiment, a method of manufacturing the field effect transistor shown in FIG. 5 will be described. In the second embodiment, the description of the same components as those in the above-described embodiment may be omitted.

FIG. 5 is a cross-sectional view illustrating the field effect transistor according to the second embodiment. Each field-effect transistor shown in FIG. 5 is a typical example of the semiconductor device according to the present invention.

The field-effect transistor 120 shown in FIG. 5 is a top-gate self-aligned field-effect transistor. The active layer 122 is formed on the insulating substrate 121, the gate insulating layer 123 is formed on the active layer 122, and the gate electrode 124 is further formed on the gate insulating layer 123. An interlayer insulating film 127 is formed so as to cover the substrate 121, the active layer 122, and the gate electrode 124. Note that 122a indicates a source region and 122b indicates a drain region.

Further, a source electrode 125 and a drain electrode 126 are formed on the interlayer insulating film 127. The source electrode 125 and the drain electrode 126 are connected to the active layer 122 via through holes formed in the interlayer insulating film 127. A passivation layer 128 is formed so as to cover the interlayer insulating film 127, the source electrode 125, and the drain electrode 126.

In the top gate self-aligned field effect transistor 120, since there is no region (overlap region) in which the gate electrode 124, the source electrode 125, and the drain electrode 126 overlap, FIGS. 1, 4 (a), and 4 are Compared with the structures of (b) and 4 (c), the parasitic capacitance can be reduced, and a field effect transistor operating at a higher speed can be obtained.

At least one of the gate insulating layer 123 and the passivation layer 128 is the same oxide as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. Can be used.

When the first oxide is used for the gate insulating layer 123, the material of the passivation layer 128 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 128, the material of the gate insulating layer 123 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can. However, the first oxide may be used for both the gate insulating layer 123 and the passivation layer 128. In this case, the interface between the gate insulating layer 123 and the passivation layer 128 is stable, and more reliable characteristics can be easily obtained.

The substrate 121, the active layer 122, the gate electrode 124, the source electrode 125, and the drain electrode 126 are, for example, the same as the substrate 11, the active layer 16, the gate electrode 12, the source electrode 14, and the drain electrode 15 of the first embodiment. The material can be applied.

The material of the interlayer insulating film 127 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN can be used.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field effect transistor 120 will be described. As an example, a method for manufacturing a field-effect transistor having a configuration in which both the gate insulating layer 123 and the passivation layer 128 use the first oxide will be described, but the present invention is not limited thereto.

First, the active layer 122, the gate insulating layer 123, and the gate electrode 124 are formed on the substrate 121. Specifically, for example, the active layer 122 is formed on the substrate 121, the gate insulating layer 123 is formed, the gate electrode 124 is formed, and the gate electrode 124 and the gate insulating layer 123 are formed by a photolithography method. It can be formed by sequentially etching.

As the film forming process of the gate insulating layer 123 and the gate electrode 124, the same process as in the first embodiment can be used. As the mask used in the etching process of the gate insulating layer 123, the mask used in the etching process of the gate electrode 124 may be used, or the pattern of the gate electrode itself may be used as a mask.

Further, when the gate electrode 124 is a material that can be wet-etched by the first solution, the gate insulating layer 123 and the gate electrode 124 can be etched at once, and the process can be further simplified. For example, the gate electrode 124 is a single layer or a laminate of Al, Al alloy, Mo, and Mo alloy, and a mixed aqueous solution of nitric acid, phosphoric acid, and acetic acid is used as the etching solution to collectively combine the gate electrode 124 and the gate insulating layer 123. It is possible to etch with.

Further, the gate electrode 124 may be formed and patterned after the gate insulating layer 123 is formed and patterned on the substrate 121.

Next, the interlayer insulating film 127 is formed. The material and process are not particularly limited, and as the material, for example, _{an insulator such as SiON or SiO 2} can be used, and for the process, a vacuum film forming method such as a CVD method or a sputtering method can be used. The patterning method is also not particularly limited, and a desired pattern can be obtained by a photolithography method or the like, and through holes can be formed as appropriate.

Before forming the interlayer insulating film 127, the resistance of the source region 122a and the drain region 122b in FIG. 5 may be reduced by, for example, Ar plasma treatment.

Next, the source electrode 125 and the drain electrode 126 are formed. The source electrode 125 and the drain electrode 126 are formed on the through holes formed in the interlayer insulating film 127 and are connected to the active layer 122 (source region 122a, drain region 122b). As the process, the same process as that of the first embodiment can be applied.

Finally, the passivation layer 128 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the field effect transistor 120 is formed.

As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the first oxide is patterned by wet etching in a low-cost process similar to that of the first embodiment. It is possible to realize a high-performance (low power consumption, high reliability) field-effect transistor.

<Third embodiment>
In the third embodiment, an example of an organic electroluminescence (organic EL) display element is shown. In the third embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of organic EL display element]
FIG. 6 is a cross-sectional view illustrating the structure and manufacturing method of the organic EL display element according to the third embodiment. With reference to FIG. 6, the organic EL display element 200 includes a drive circuit 210, an interlayer insulating film 220, an organic EL element 230, a partition wall 240, a sealing layer 250, an adhesive layer 260, and a facing insulating substrate. It has 270 and.

The drive circuit 210 is composed of a first field-effect transistor 20 and a second field-effect transistor 30. The first field effect transistor 20 includes a first gate electrode 22, a gate insulating layer 23, a first source electrode 24, a first drain electrode 25, and a first gate electrode 22 formed on a substrate 21 which is an insulating substrate. It has one active layer 26 and a first passivation layer 27. Further, the second field effect transistor 30 has a second gate electrode 32, a gate insulating layer 23, a second source electrode 34, a second drain electrode 35, and a second activity formed on the substrate 21. It has a layer 36 and a second passivation layer 37. At least one of the gate insulating layer 23, the first passivation layer 27, and the second passivation layer 37 is used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. The same oxide as the first oxide can be used.

In the drive circuit 210, a through hole in which the first drain electrode 25 of the first field-effect transistor 20 and the second gate electrode 32 of the second field-effect transistor 30 are formed in the gate insulating layer 23. It has a structure of two transistors and one capacitor connected via. In the case of FIG. 6, a capacitor is formed between the second gate electrode 32 and the second source electrode 34, but the capacitor forming location is not limited, and a capacitor having an appropriately required capacity is required. Can be designed and formed in various places.

The interlayer insulating film 220 is formed so as to cover the first field effect transistor 20 and the second field effect transistor 30 of the drive circuit 210, and the organic EL element 230 and the partition wall 240 are formed on the interlayer insulating film 220. Is formed.

The organic EL element 230 is an optical control element having a lower electrode 231, an organic EL layer 232, and an upper electrode 233. The lower electrode 231 of the organic EL element 230 is connected to the second drain electrode 35 of the second field effect transistor 30 via a through hole 220x formed in the interlayer insulating film 220.

As in the organic EL display element 200A shown in FIG. 7, the first passivation layer 27 and the second passivation layer 37 may be integrally formed to form the passivation layer 27A. In this case, the lower electrode 231 of the organic EL element 230 is the second field effect transistor 30 via the through holes 220y formed in the interlayer insulating film 220 and the through holes 220z formed in the passivation layer 27A. It is connected to the second drain electrode 35.

In the organic EL element 230, the lower electrode 231 includes, for example, a conductive oxide such as ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, or a silver (Ag) -neodymium (Nd) alloy. Etc. can be used. For the upper electrode 233, for example, aluminum (Al), magnesium (Mg) -silver (Ag) alloy, aluminum (Al) -lithium (Li) alloy, ITO or the like can be used.

The organic EL layer 232 has an electron transport layer, a light emitting layer, and a hole transport layer. Then, the upper electrode 233 is connected to the electron transport layer, and the lower electrode 231 is connected to the hole transport layer. When a predetermined voltage is applied between the lower electrode 231 and the upper electrode 233, the holes and electrons injected from the lower electrode 231 and the upper electrode 233 are recombined in the organic EL layer 232 and emit light by the excited energy. The layer emits light. That is, when the first field-effect transistor 20 and the second field-effect transistor 30 are turned on, the organic EL element 230 emits light.

A sealing layer 250, an adhesive layer 260, and a counter-insulating substrate 270 are sequentially laminated on the organic EL element 230.

[Manufacturing method of organic EL display element]
Next, a method of manufacturing the organic EL display element 200 will be described. The first field-effect transistor 20 and the second field-effect transistor 30 can be manufactured by the same materials and processes as the field-effect transistor according to the first embodiment.

When the first oxide is used as the passivation layer 27A in FIG. 7, in order to form the through holes 220z, for example, after the passivation layer 27A is formed and before the interlayer insulating film 220 is formed, the passivation layer is formed. A mask is provided on 27A to open the portion forming the through hole 220z. Then, the passivation layer 27A may be etched with the first solution via a mask.

Alternatively, after the passivation layer 27A and the interlayer insulating film 220 are continuously formed, a through hole 220y is formed in the interlayer insulating film 220, and the interlayer insulating film 220 in which the through hole 220y is formed is used as a mask with the first solution. Through holes 220z may be formed in the passivation layer 27A by etching.

Various materials and processes can be used to form the interlayer insulating film 220 and the partition wall 240. As the material, for example, _{an inorganic oxide such as SiO 2} , SiON, SiN _x , or an insulating material such as acrylic or polyimide can be used. As for the process, for example, after film formation by a sputtering method or spin coating method, patterning can be performed by a photolithography method, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure.

The method for producing the organic EL element 230 is not particularly limited, and existing techniques can be used. For example, a vacuum film forming method such as a vacuum vapor deposition method or a sputtering method, or a solution process such as inkjet or nozzle coating can be appropriately performed. It can be used.

Various materials and processes can be used to form the sealing layer 250. As the material, for example, inorganic oxides such as _{SiO 2} , SiON, and SiN _{x can be used.} As for the process, for example, a vacuum film forming method such as a CVD method or a sputtering method can be used.

After forming the sealing layer 250, for example, the facing insulating substrate 270 is bonded to the adhesive layer 260 made of a material such as epoxy resin or acrylic resin to complete the organic EL display element 200.

As described above, high performance (low power consumption, high power consumption) is achieved by a low-cost process in which the first oxide is used as at least one of the gate insulating layer and the passivation layer and the first oxide is patterned by wet etching. (Reliability) organic EL display element can be realized.

The display element according to the present embodiment has at least an optical control element and a drive circuit for driving the optical control element, and further includes other members, if necessary. The optical control element is not particularly limited as long as it is an element that controls the optical output according to the drive signal, and can be appropriately selected according to the purpose. In the above example, an example of a display element using an organic EL element as an optical control element has been described, but as an optical control element, a liquid crystal element, an electrochromic element, an electrophoresis element, or an electrowetting element can be used instead of the organic EL element. It is also possible to realize a display element using the above.

The drive circuit is not particularly limited as long as it has the field-effect transistor according to the first embodiment, and can be appropriately selected depending on the intended purpose. The other members are not particularly limited and may be appropriately selected depending on the intended purpose.

<Fourth Embodiment>
In the fourth embodiment, another example of the field effect transistor is shown. In the fourth embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of field effect transistor]
FIG. 8 is a cross-sectional view illustrating the structure and manufacturing method of the field effect transistor according to the fourth embodiment. Referring to FIG. 8, the field effect transistor 50 includes a substrate 51, a gate electrode 52, a gate insulating layer 53, a gate side wall insulating film 54, a source region 55, a drain region 56, and an interlayer insulating film 57. The source electrode 58, the drain electrode 59, and the passivation layer 111 are provided. The field-effect transistor 50 is a typical example of the field-effect transistor according to the present invention.

At least one of the gate insulating layer 53 and the passivation layer 111 is the same oxide as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. Can be used.

When the first oxide is used for the gate insulating layer 53, the material of the passivation layer 111 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 111, the material of the gate insulating layer 53 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can. However, the first oxide may be used for both the gate insulating layer 53 and the passivation layer 111. In this case, the interface between the gate insulating layer 53 and the passivation layer 111 is stable, and more reliable characteristics can be easily obtained.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field effect transistor 50 will be described. As an example, a method for manufacturing a field-effect transistor having a configuration in which both the gate insulating layer 53 and the passivation layer 111 use the first oxide will be described, but the present invention is not limited thereto.

In order to manufacture the field effect transistor 50, first, a substrate 51, which is a semiconductor substrate, is prepared. The material is not particularly limited as long as it is a semiconductor material, and materials such as Si (silicon) and Ge (germanium) to which desired impurities are added can be appropriately used.

Next, the gate insulating layer 53 is formed on the substrate 51. The process is not particularly limited, and for example, a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film forming method such as a CVD method, an ALD method, or a sputtering method. It can be formed as an amorphous film by any film forming method.

Next, the gate electrode 52 is formed. The material and process are not particularly limited, and as the material, for example, a metal material such as polysilicon or Al, or a laminate of these and a barrier metal such as TiN or TaN can be used. As for the process, for example, a vacuum film forming method such as a CVD method or a sputtering method can be used. Further, in order to reduce the resistance, for example, a VDD layer of Ni, Co, Ti or the like may be formed on the surface of the gate electrode 52.

The patterning method of the gate electrode 52 is also not particularly limited, but for example, photolithography in which a mask is formed using a photoresist and the gate insulating layer 53 or the gate electrode 52 in a region not covered by the mask is removed by a dry etching method. The law is available.

The process of the gate insulating layer 53 is the same as that of the gate insulating layer 13 according to the first embodiment. The mask material for wet etching of the gate insulating layer 53 is not particularly limited, but for example, the pattern of the gate electrode 52 can be used as a mask.

Next, the gate side wall insulating film 54 is formed on the side surfaces of the gate insulating layer 53 and the gate electrode 52. The material and process are not particularly limited, and as the material, for example, _{an insulator such as SiON or SiO 2} can be used, and for the process, a vacuum film forming method such as a CVD method or a sputtering method can be used. The patterning method is also not particularly limited, and for example, a method of forming the material of the gate side wall insulating film 54 on the entire surface of the substrate and then etching-baging the entire surface by a dry etching method can be used.

Next, the source region 55 and the drain region 56 are formed by selectively ion-implanting the substrate 51. In order to reduce the resistance, for example, a silicide layer of Ni, Co, Ti or the like may be formed on the surfaces of the source region 55 and the drain region 56.

Next, the interlayer insulating film 57 is formed. The material and process are not particularly limited, and as the material, for example, _{an insulator such as SiON or SiO 2} can be used, and for the process, a vacuum film forming method such as a CVD method or a sputtering method can be used. The patterning method is also not particularly limited, and a desired pattern can be obtained by a photolithography method or the like, and through holes can be formed as appropriate.

Next, the source electrode 58 and the drain electrode 59 are formed. The source electrode 58 and the drain electrode 59 are formed so as to embed a through hole formed in the interlayer insulating film 57 and connect to the source region 55 and the drain region 56.

The material and process are not particularly limited, and as the material, for example, a metal material such as Al or Cu can be used. Regarding the process, for example, a method of embedding through holes by a vacuum film forming method such as a sputtering method and then patterning by a photolithography method, or a method of embedding through holes by a CVD method or a plating method and then using a CMP (Chemical Mechanical Polishing) method. A flattening method or the like can be used. Further, it may be appropriately formed as a laminate with a barrier metal layer such as TiN or TaN. Alternatively, a W plug in which a through hole is embedded by W may be used by using the CVD method.

Finally, the passivation layer 111 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, a field effect transistor is formed.

For the field effect transistor 50, the active layer forming a channel between the source region 55 and the drain region 56 corresponds to the substrate 51. Further, an active layer such as SiGe may be formed between the substrate 51 made of Si and the gate insulating layer 53. Further, although FIG. 8 shows a top gate structure, the above-mentioned gate insulating layer 53 can also be used in a so-called double gate structure or a fin type FET.

As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the first oxide is patterned by wet etching in a low-cost process similar to that of the first embodiment. It is possible to realize a high-performance (low power consumption, high reliability) field-effect transistor.

<Fifth Embodiment>
In the fifth embodiment, an example of a volatile semiconductor memory device is shown. In the fifth embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of volatile semiconductor memory element]
FIG. 9 is a cross-sectional view illustrating the structure and manufacturing method of the volatile semiconductor memory element according to the fifth embodiment. With reference to FIG. 9, the volatile semiconductor memory element 60 includes a substrate 61 which is an insulating substrate, a gate electrode 62, a gate insulating layer 63, a source electrode 64, a drain electrode 65, an active layer 66, and the like. It has a first capacitor electrode 67, a capacitor dielectric layer 68, a second capacitor electrode 69, and a passion layer 112. The volatile semiconductor memory element 60 is a typical example of the semiconductor device according to the present invention.

At least one of the gate insulating layer 63 and the passivation layer 112 has the same oxidation as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. You can use things.

When the first oxide is used for the gate insulating layer 63, the material of the passivation layer 112 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 112, the material of the gate insulating layer 63 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can. However, the first oxide may be used for both the gate insulating layer 63 and the passivation layer 112. In this case, the interface between the gate insulating layer 63 and the passivation layer 112 is stable, and more reliable characteristics can be easily obtained.

The capacitor dielectric layer 68 is also preferably the first oxide.

[Manufacturing method of volatile semiconductor memory element]
Next, a method of manufacturing the volatile semiconductor memory element 60 will be described. As an example, a method for manufacturing a volatile semiconductor memory device having a configuration in which both the gate insulating layer 63 and the passivation layer 112 use the first oxide will be described, but the present invention is not limited thereto.

To manufacture the volatile semiconductor memory element 60, first, the substrate 61 is prepared. The material is the same as that of the substrate 11 according to the first embodiment. Next, the gate electrode 62 is formed on the substrate 61. The materials and processes are the same as those of the gate electrode 12 according to the first embodiment.

Next, the second capacitor electrode 69 is formed. Various materials and processes can be used for the second capacitor electrode 69. As the material, for example, metals and alloys such as Mo, Al, Cu and Ru, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylene dioxythiophene (PEDOT) and polyaniline (PANI) are used. it can. As a process, for example, after film formation by a sputtering method, spin coating, dip coating, etc., patterning can be performed by a photolithography method, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure. Is.

If the materials and processes of the gate electrode 62 and the second capacitor electrode 69 are the same, they may be formed at the same time.

Next, the gate insulating layer 63 made of the first oxide is formed. The process is the same as that of the gate insulating layer 13 according to the first embodiment.

Next, the capacitor dielectric layer 68 is formed on the second capacitor electrode 69. The material of the capacitor dielectric layer 68 is not particularly limited, and for example, a high dielectric constant oxide material containing Hf oxide, Ta oxide, La oxide, etc., lead zirconate titanate (PZT), strontium tantarate, etc. Ferroelectric materials such as bismuth (SBT) can be used. Above all, it is preferable to form the capacitor dielectric layer 68 from the first oxide.

The process is not particularly limited, and for example, a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film forming method such as a CVD method, an ALD method, or a sputtering method. It can be formed as an amorphous film by any film forming method.

If the materials and processes of the gate insulating layer 63 and the capacitor dielectric layer 68 are the same, they may be formed at the same time.

Next, the source electrode 64 and the drain electrode 65 are formed. The materials and processes are the same as those of the source electrode 14 and the drain electrode 15 according to the first embodiment.

Next, the first capacitor electrode 67 is formed. Various materials and processes can be used for the first capacitor electrode 67. As the material, for example, metals and alloys such as Mo, Al, Cu and Ru, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylene dioxythiophene (PEDOT) and polyaniline (PANI) are used. it can. As a process, for example, after film formation by a sputtering method, spin coating, dip coating, etc., patterning can be performed by a photolithography method, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure. Is.

Further, if the materials and processes of the source electrode 64 and the drain electrode 65 and the first capacitor electrode 67 are the same, they may be formed at the same time.

Next, the active layer 66 is formed. The material is not particularly limited, and for example, an oxide semiconductor such as polycrystalline silicon (p-Si), amorphous silicon (a-Si), In-Ga-Zn-O, and an organic semiconductor such as pentacene are appropriately used. it can. Above all, an oxide semiconductor is preferable from the viewpoint of stability of the interface between the gate insulating layer 63 and the active layer 66. The process is not particularly limited, and for example, after forming a film by a vacuum process such as a sputtering method, a pulse laser deposit (PLD) method, a CVD method, or an ALD method, or a solution process such as spin coating or dip coating, a photolithography method is used. It is also possible to directly form a desired shape by patterning or by a printing process such as inkjet, nanoimprint, or gravure.

Finally, the passivation layer 112 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. By the above steps, the volatile semiconductor memory element 60 is manufactured.

In the volatile semiconductor memory element 60, the positional relationship between the gate electrode 62, the gate insulating layer 63, the source electrode 64, the drain electrode 65, and the active layer 66 is a so-called bottom gate / bottom contact type. The volatile semiconductor memory element is not limited to this, and may be, for example, a bottom gate / top contact type, a top gate / bottom contact type, or a top gate / top contact type.

Further, although the first capacitor electrode 67, the capacitor dielectric layer 68, and the second capacitor electrode 69 in the volatile semiconductor memory element 60 have a planar structure, for example, a capacitor may be formed by a method such as a three-dimensional structure. You may increase the capacity of.

As described above, high performance (low power consumption, high power consumption) is achieved by a low-cost process in which the first oxide is used as at least one of the gate insulating layer and the passivation layer and the first oxide is patterned by wet etching. (Reliability) volatile semiconductor memory elements can be realized. Further, when the first oxide is used for the capacitor dielectric layer in addition to the gate insulating layer, the power consumption can be further reduced, which is preferable.

<Sixth Embodiment>
In the sixth embodiment, another example of the volatile semiconductor memory device is shown. In the sixth embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of volatile semiconductor memory element]
FIG. 10 is a cross-sectional view illustrating the structure and manufacturing method of the volatile semiconductor memory element according to the sixth embodiment. With reference to FIG. 10, the volatile semiconductor memory element 70 includes a substrate 71 which is a semiconductor substrate, a gate electrode 72, a gate insulating layer 73, a gate sidewall insulating film 74, a source region 75, and a drain region 76. , The first interlayer insulating film 77, the bit wire electrode 78, the second interlayer insulating film 79, the second capacitor electrode 80, the capacitor dielectric layer 81, the first capacitor electrode 82, and the passion layer 113. And have. The volatile semiconductor memory element 70 is a typical example of the semiconductor device according to the present invention.

At least one of the gate insulating layer 73 and the passivation layer 113 has the same oxidation as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. You can use things.

When the first oxide is used for the gate insulating layer 73, the material of the passivation layer 113 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 113, the material of the gate insulating layer 73 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can. However, the first oxide may be used for both the gate insulating layer 73 and the passivation layer 113. In this case, the interface between the gate insulating layer 73 and the passivation layer 113 is stable, and more reliable characteristics can be easily obtained.

The capacitor dielectric layer 81 is also preferably the first oxide.

[Manufacturing method of volatile semiconductor memory element]
Next, a method of manufacturing the volatile semiconductor memory element 70 will be described. As an example, a method for manufacturing a volatile semiconductor memory device having a structure in which both the gate insulating layer 73 and the passivation layer 113 use the first oxide will be described, but the present invention is not limited thereto.

In the volatile semiconductor memory element 70, the substrate 71, the gate electrode 72, the gate insulating layer 73, the gate side wall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 are the fourth embodiments. It can be formed by the same materials and processes as the substrate 51, the gate electrode 52, the gate insulating layer 53, the gate side wall insulating film 54, the source region 55, the drain region 56, and the interlayer insulating film 57.

After forming the gate insulating layer 73, the gate electrode 72, the gate side wall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 on the substrate 71, the bit wire electrode 78 is formed. The material and process are not particularly limited, and as the material, for example, Al, Cu, or the like can be used. Regarding the process, for example, a method of embedding through holes by a vacuum film forming method such as a sputtering method or a CVD method and then patterning by a photolithography method, or a method of embedding through holes by a CVD method or a plating method and then flattening by a CMP method. You can use the method to do it. Further, it may be appropriately formed as a laminate with a barrier metal layer such as TiN or TaN. Alternatively, a W plug in which a through hole is embedded by W may be used by using the CVD method.

Next, the second interlayer insulating film 79 is formed. The material and process are the same as those of the interlayer insulating film 57 according to the fourth embodiment.

Next, the second capacitor electrode 80 is formed. The material and process are not particularly limited, and as the material, for example, a metal material such as Al, Cu, or Ru, or polysilicon can be used. Regarding the process, for example, a method of embedding through holes by a vacuum film forming method such as a sputtering method or a CVD method and then patterning by a photolithography method, or a method of embedding through holes by a CVD method or a plating method and then flattening by a CMP method. You can use the method to do it. Further, it may be appropriately formed as a laminate with a barrier metal layer such as TiN or TaN. Alternatively, a W plug in which a through hole is embedded by W may be used by using the CVD method.

Next, the capacitor dielectric layer 81 is formed. The material of the capacitor dielectric layer 81 is not particularly limited, and for example, a high dielectric constant oxide material containing Hf oxide, Ta oxide, La oxide, etc., lead zirconate titanate (PZT), strontium tantarate, etc. Ferroelectric materials such as bismuth (SBT) can be used. Above all, it is preferable to form the capacitor dielectric layer 81 from the first oxide.

The process is not particularly limited, and for example, a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film forming method such as a CVD method, an ALD method, or a sputtering method. It can be formed as an amorphous film by any film forming method. When the first oxide is used for the capacitor dielectric layer 81, the same process as the gate insulating layer 13 according to the first embodiment can be used.

Next, the first capacitor electrode 82 is formed. The material and process are not particularly limited, and as the material, for example, metal materials such as Al, Cu, and Ru, and polysilicon can be used. As for the process, for example, a method of forming a film by a vacuum film forming method such as a CVD method or a sputtering method and then patterning by a photolithography method can be used. Further, it may be appropriately formed as a laminate with a barrier metal layer such as TiN or TaN.

Finally, the passivation layer 113 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. By the above steps, the volatile semiconductor memory element 70 is manufactured.

In the volatile semiconductor memory element 70, a volatile semiconductor memory element having a stack type structure in which a capacitor is arranged above a field effect transistor has been described, but the present invention is not limited to this. For example, a volatile semiconductor memory element having a trench-type structure in which a groove is dug in a semiconductor substrate and a capacitor is arranged below the field-effect transistor may be used.

Further, although the second capacitor electrode 80, the capacitor dielectric layer 81, and the first capacitor electrode 82 in the volatile semiconductor memory element 70 have a planar structure, for example, a capacitor may be formed by a method such as a three-dimensional structure. You may increase the capacity of.

As described above, high performance (low power consumption, high power consumption) is achieved by a low-cost process in which the first oxide is used as at least one of the gate insulating layer and the passivation layer and the first oxide is patterned by wet etching. (Reliability) volatile semiconductor memory elements can be realized. Further, when the first oxide is used for the capacitor dielectric layer in addition to the gate insulating layer, the power consumption can be further reduced, which is preferable.

<Seventh Embodiment>
In the seventh embodiment, an example of a non-volatile semiconductor memory element is shown. In the seventh embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of non-volatile semiconductor memory element]
FIG. 11 is a cross-sectional view illustrating the structure and manufacturing method of the non-volatile semiconductor memory element according to the seventh embodiment. With reference to FIG. 11, the non-volatile semiconductor memory element 90 includes a substrate 91 which is an insulating substrate, a gate electrode 92, a first gate insulating layer 93, a floating gate electrode 94, and a second gate insulating layer. It has 95, a source electrode 96, a drain electrode 97, an active layer 98, and a passion layer 114. The non-volatile semiconductor memory element 90 is a typical example of the semiconductor device according to the present invention.

At least one of the first gate insulating layer 93 and the passivation layer 114 is the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. The same oxides as can be used.

When the first oxide is used for the first gate insulating layer 93, the material of the passivation layer 114 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can.

Similarly, when the first oxide is used for the passivation layer 114, the material of the first gate insulating layer 93 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, SiN or the like is used. Can be used. However, the first oxide may be used for both the first gate insulating layer 93 and the passivation layer 114. In this case, the interface between the first gate insulating layer 93 and the passivation layer 114 is stable, and more reliable characteristics can be easily obtained.

The first gate insulating layer 93 is a so-called inter-gate electrode insulating layer, the second gate insulating layer 95 is a so-called tunnel insulating layer, and the gate electrode 92 is a so-called control gate electrode. Depending on the voltage application conditions to the source electrode 96, the drain electrode 97, and the gate electrode 92, electrons can be taken in and out of the floating gate electrode 94 through the second gate insulating layer, which is a tunnel insulating layer, due to the tunnel effect. Functions as.

[Manufacturing method of non-volatile semiconductor memory element]
Next, a method of manufacturing the non-volatile semiconductor memory element 90 will be described. As an example, a method for manufacturing a non-volatile semiconductor memory device having a configuration in which both the first gate insulating layer 93 and the passivation layer 114 use the first oxide will be described, but the present invention is not limited thereto.

To manufacture the non-volatile semiconductor memory element 90, first, the substrate 91 is prepared. The material is the same as that of the substrate 11 according to the first embodiment.

Next, the gate electrode 92 is formed on the substrate 91. The materials and processes are the same as those of the gate electrode 12 according to the first embodiment.

Next, the first gate insulating layer 93 made of the first oxide is formed so as to cover the gate electrode 92. The process is the same as that of the gate insulating layer 13 according to the first embodiment.

Next, the floating gate electrode 94 is formed on the first gate insulating layer 93. Various materials and processes are available. As the material, for example, metals and alloys such as Mo, Al and Cu, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylene dioxythiophene (PEDOT) and polyaniline (PANI) can be used. As a process, for example, after film formation by a sputtering method, spin coating, dip coating, etc., patterning can be performed by a photolithography method, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure. Is.

Next, the second gate insulating layer 95 is formed so as to cover the floating gate electrode 94. The material is not particularly limited, and the optimum material can be appropriately selected. Above all, in order to improve the coupling ratio, for example, _{a low dielectric constant insulating material such as SiO 2} or a fluorine-based polymer is preferable. The process is not particularly limited, and for example, a vacuum film forming method such as a sputtering method, a CVD method, or an ALD method, a coating solution containing a metal alkoxide / metal complex, or a spin coating using a coating solution containing a polymer is used. , Die-coating, nozzle-coating, inkjet and other solution processes can be appropriately used, and a desired pattern can be formed by using a photolithography method or directly drawing by a printing method.

Next, the source electrode 96 and the drain electrode 97 are formed on the second gate insulating layer 95. The materials and processes are the same as those of the source electrode 14 and the drain electrode 15 according to the first embodiment.

Next, the active layer 98 is formed. The material is not particularly limited, and for example, an oxide semiconductor such as polycrystalline silicon (p-Si), amorphous silicon (a-Si), In-Ga-Zn-O, and an organic semiconductor such as pentacene are appropriately used. it can. Of these, oxide semiconductors are preferable. The process is not particularly limited, and for example, a vacuum process such as a sputtering method, a pulse laser deposit (PLD) method, a CVD method, or an ALD method, or a solution process such as spin coating / dip coating is used to form a film, and then a photolithography method is used. It is also possible to directly form a desired shape by patterning or by a printing process such as inkjet, nanoimprint, or gravure.

Finally, the passivation layer 114 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. The non-volatile semiconductor memory element 90 is manufactured by the above steps.

In the non-volatile semiconductor memory element 90, the positional relationship between the gate electrode 92, the source electrode 96, the drain electrode 97, and the active layer 98 is a so-called bottom gate / bottom contact type, but the non-volatile semiconductor memory according to the present embodiment. The element is not limited to this, and may be, for example, a bottom gate / top contact type, a top gate / bottom contact type, or a top gate / top contact type.

Further, in the non-volatile semiconductor memory element 90, the gate electrode 92, the first gate insulating layer 93, and the floating gate electrode 94 have a planar structure. You may increase the capacity of.

As described above, a low-cost process in which the first oxide is used as at least one of the first gate insulating layer and the passivation layer and the first oxide is patterned by wet etching has high performance (low consumption). It is possible to realize a non-volatile semiconductor memory element (power, high reliability). That is, it is possible to suppress the leakage current to a low level, reduce the write / erase voltage, and make the device have a longer life.

<Eighth Embodiment>
In the eighth embodiment, another example of the non-volatile semiconductor memory device is shown. In the eighth embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of non-volatile semiconductor memory element]
FIG. 12 is a cross-sectional view illustrating the structure and manufacturing method of the non-volatile semiconductor memory element according to the eighth embodiment. With reference to FIG. 12, the non-volatile semiconductor memory element 100 includes a substrate 101 which is a semiconductor substrate, a first gate insulating layer 102, a gate electrode 103, a second gate insulating layer 104, a floating gate electrode 105, and a gate side wall insulation. It has a film 106, a source region 107, a drain region 108, and a passivation layer 115. The non-volatile semiconductor memory element 100 is a typical example of the semiconductor device according to the present invention.

At least one of the first gate insulating layer 102 and the passivation layer 115 is the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. The same oxides as can be used.

When the first oxide is used for the first gate insulating layer 102, the material of the passivation layer 115 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, or SiN may be used. it can.

Similarly, when the first oxide is used for the passivation layer 115, the material of the first gate insulating layer 102 is not particularly limited, and for example _{, an inorganic oxide film such as SiO 2} , SiON, SiN or the like is used. Can be used. However, the first oxide may be used for both the first gate insulating layer 102 and the passivation layer 115. In this case, the interface between the first gate insulating layer 102 and the passivation layer 115 is stable, and more reliable characteristics can be easily obtained.

The first gate insulating layer 102 is a so-called inter-gate electrode insulating layer, the second gate insulating layer 104 is a so-called tunnel insulating layer, and the gate electrode 103 is a so-called control gate electrode. Depending on the voltage application conditions to the source region 107, the drain region 108, and the gate electrode 103, electrons can be taken in and out of the floating gate electrode 105 through the second gate insulating layer 104, which is a tunnel insulating layer, due to the tunnel effect. Functions as memory.

[Manufacturing method of non-volatile semiconductor memory element]
Next, a method of manufacturing the non-volatile semiconductor memory element 100 will be described. As an example, a method for manufacturing a non-volatile semiconductor memory device having a configuration in which both the first gate insulating layer 102 and the passivation layer 115 use the first oxide will be described, but the present invention is not limited thereto.

To manufacture the non-volatile semiconductor memory element 100, first, the substrate 101 is prepared. The material is the same as that of the substrate 51 in the fourth embodiment.

Next, the second gate insulating layer 104 is formed. The material is not particularly limited, but for example, a low dielectric constant insulating material such as _{SiO 2 is preferable.} The process is not particularly limited, and for example, a vacuum film forming method such as a thermal oxidation method, a sputtering method, a chemical CVD method, or an ALD method can be used.

Next, the floating gate electrode 105 is formed. The material and process are not particularly limited, and as the material, for example, a metal material such as polysilicon or AL, or a laminate of these and a barrier metal such as TiN or TaN can be used, and the process is a CVD method. , Vacuum film formation methods such as sputtering can be used.

Next, the first gate insulating layer 102 made of the first oxide is formed. The process is the same as that of the gate insulating layer 13 according to the first embodiment.

Next, the gate electrode 103 is formed. The material and process are the same as those of the gate insulating layer 53 according to the fourth embodiment.

The patterning of the first gate insulating layer 102, the gate electrode 103, the second gate insulating layer 104, and the floating gate electrode 105 is not particularly limited, but a desired pattern can be obtained by, for example, a photolithography method.

Next, the gate side wall insulating film 106 is formed. The material and process are the same as those of the gate sidewall insulating film 54 in the fourth embodiment. Next, the source region 107 and the drain region 108 are formed by selectively ion-implanting the substrate 101. In order to reduce the resistance, for example, a silicide layer of Ni, Co, Ti or the like may be formed on the surfaces of the source region 107 and the drain region 108.

Finally, the passivation layer 115 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. The non-volatile semiconductor memory element 100 is formed by the above steps.

In the non-volatile semiconductor memory element 100, the first gate insulating layer 102, the gate electrode 103, and the floating gate electrode 105 have a planar structure. You may increase the capacity of.

As described above, a low-cost process in which the first oxide is used as at least one of the first gate insulating layer and the passivation layer and the first oxide is patterned by wet etching has high performance (low consumption). It is possible to realize a non-volatile semiconductor memory element (power, high reliability). That is, it is possible to suppress the leakage current to a low level, reduce the write / erase voltage, and make the device have a longer life.

<9th embodiment>
In the ninth embodiment, an example of a field effect transistor having a plurality of passivation layers is shown. In the ninth embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of field effect transistor]
FIG. 13 is a cross-sectional view illustrating the field effect transistor according to the ninth embodiment. Referring to FIG. 13, the field effect transistor 110 includes a substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, an active layer 16, and a first passivation layer 17a. And a bottom gate / bottom contact type field effect transistor having a second passivation layer 17b. The field effect transistor 110 is a typical example of the semiconductor device according to the present invention.

In the field effect transistor 110, the gate electrode 12 is formed on the insulating substrate 11, and the gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, the source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13, and the active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are formed at predetermined intervals that serve as channel regions of the active layer 16. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second passivation layer 17b is further formed on the first passivation layer 17a. Is formed.

The passivation layer is usually formed above the substrate 11. The passivation layer has a first passivation layer 17a and a second passivation layer 17b arranged in contact with the first passivation layer 17a. In FIG. 13, as an example, the first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16.

The arrangement of the first passivation layer 17a and the second passivation layer 17b in the passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose. As shown in FIG. 13, the first passivation layer 17a May be arranged on the active layer 16 side of the second passivation layer 17b, or conversely, the second passivation layer 17b may be arranged on the active layer 16 rather than the first passivation layer 17a. Good. Further, the second passivation layer 17b may be arranged so as to cover the upper surface and the side surface of the first passivation layer 17a, or the first passivation layer may cover the upper surface and the side surface of the second passivation layer 17b. 17a may be arranged.

− First passivation layer 17a−
The first passivation layer 17a is preferably a second oxide.

-Second oxide-
The second oxide contains Si (silicon) and an alkaline earth metal, preferably at least one of Al (aluminum) and B (boron), and if necessary, other oxides. Contains ingredients.

In the second oxide, SiO ₂ formed of Si forms an amorphous structure. Further, the alkaline earth metal has a function of breaking the Si—O bond. Therefore, it is possible to control the relative permittivity and the coefficient of linear expansion of the second oxide formed by the composition ratio of Si and the alkaline earth metal.

The second oxide preferably contains at least one of Al and B. _Al 2 _{O 3} formed by Al, and _B 2 _{O 3} formed by B, in order to form a similarly amorphous structure and SiO _2, wherein in the second oxide, and more stable amorphous structure It is possible to obtain a more uniform insulating film. Further, since the alkaline earth metal changes the coordination structures of Al and B depending on its composition ratio, it is possible to control the relative permittivity and the coefficient of linear expansion of the second oxide formed. ..

In the second oxide, examples of the alkaline earth metal include Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium). These may be used alone or in combination of two or more.

The composition ratio of Si in the second oxide and the alkaline earth metal is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably in the following range.

In the second oxide, the composition ratio (Si: alkaline earth metal) of Si and the alkaline earth metal is _{50 in terms of oxides (SiO 2} , BeO, MgO, CaO, SrO, BaO). It is preferably 0.0 mol% to 90.0 mol%: 10.0 mol% to 50.0 mol%.

The composition ratio of Si in the second oxide, the alkaline earth metal, and at least one of Al and B is not particularly limited and may be appropriately selected depending on the intended purpose, but within the following range. It is preferable to have.

In the second oxide, the composition ratio of Si, the alkaline earth metal, and at least one of Al and B (Si: alkaline earth metal: at least one of Al and B) is an oxide (SiO). ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) In terms of 50.0 mol% to 90.0 mol%: 5.0 mol% to 20.0 mol%: 5.0 mol% to 30.0 mol% is preferable.

The proportion of oxides (SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) in the second oxide is, for example, fluorescent X-ray analysis, electron beam micro-analysis (EPMA). ), Inductively coupled plasma emission spectroscopy (ICP-AES), etc., can be calculated by analyzing the cation element of the oxide.

The relative permittivity of the first passivation layer 17a is not particularly limited and may be appropriately selected depending on the intended purpose.

The relative permittivity of the first passivation layer 17a can be measured, for example, by producing a capacitor in which a lower electrode, a dielectric layer (first passivation layer), and an upper electrode are laminated, and using an LCR meter or the like. ..

The coefficient of linear expansion of the first passivation layer 17a is not particularly limited and may be appropriately selected depending on the intended purpose.

The coefficient of linear expansion of the first passivation layer 17a can be measured using, for example, a thermomechanical analyzer. In this measurement, the coefficient of linear expansion can be measured by separately preparing and measuring a measurement sample having the same composition as that of the first passivation layer 17a without producing a field effect transistor.

-Second passivation layer 17b-
The second passivation layer 17b contains the first oxide. As the first oxide, the oxide exemplified as the material of the gate insulating layer 13 or the passivation layer 17 in the first embodiment can be used. That is, the first oxide contains at least element A, which is an alkaline earth metal, and element B, which is at least one of gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid. And, if necessary, it contains other ingredients.

The relative permittivity of the second passivation layer 17b is not particularly limited and may be appropriately selected depending on the intended purpose. The relative permittivity of the second passivation layer 17b can be measured, for example, by the same method as the relative permittivity of the first passivation layer 17a.

The coefficient of linear expansion of the second passivation layer 17b is not particularly limited and may be appropriately selected depending on the intended purpose. The coefficient of linear expansion of the second passivation layer 17b can be measured, for example, by the same method as the coefficient of linear expansion of the first passivation layer 17a.

The inventors have described the passivation layer as a first passivation layer 17a containing the second oxide and a second passivation layer containing the first oxide (for example, an amorphous amorphous oxide). It has been found that the laminated structure of 17b exhibits excellent barrier properties against atmospheric moisture, oxygen and nitrogen. Therefore, the field-effect transistor containing the passivation layer has a small fluctuation amount of the threshold voltage with respect to the BTS (Bias Temperature Stress) test, and can provide a field-effect transistor exhibiting high reliability.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field-effect transistor shown in FIG. 13 will be described. 14 and 15 are diagrams illustrating a manufacturing process of the field effect transistor according to the ninth embodiment.

First, after executing the same steps as in FIGS. 2 (a) to 3 (a) of the first embodiment, in the step shown in FIG. 14 (a), the entire surface on the substrate 11 and the gate insulating layer 13 is covered. , A first passivation layer 170a (a layer that is etched to become a first passivation layer 17a) that covers the source electrode 14, the drain electrode 15, and the active layer 16 is formed. Then, a second passivation layer 170b (a layer that is etched to become a second passivation layer 17b) is formed on the entire surface of the first passivation layer 170a.

The method for forming the first passivation layer 170a and the second passivation layer 170b is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a sputtering method, a pulse laser deposition (PLD) method, or chemistry. Examples thereof include film formation by a vacuum process such as a vapor deposition (CVD) method and an atomic layer deposition (ALD) method.

Further, in the first passivation layer 170a, a coating liquid containing the precursor of the second oxide (coating liquid for forming the first passivation layer) is prepared, and the coating liquid is coated or printed on the object to be coated. A film can also be formed by firing this under appropriate conditions. Similarly, in the second passivation layer 170b, a coating liquid containing the precursor of the first oxide (coating liquid for forming a second passivation layer) is prepared, and the coating liquid is applied or printed on the object to be coated. However, a film can also be formed by firing this under appropriate conditions.

The average film thickness of the first passivation layer 170a is preferably 10 to 1,000 nm, more preferably 20 to 500 nm. The average film thickness of the second passivation layer 170b is preferably 10 to 1,000 nm, more preferably 20 to 500 nm.

--A coating liquid for forming the first passivation layer ---
The coating liquid for forming the first passivation layer contains at least a silicon-containing compound, an alkaline earth metal compound, and a solvent, preferably at least one of an aluminum-containing compound and a boron-containing compound, and further. Contains other ingredients as needed.

--- Silicon-containing compound ---
Examples of the silicon-containing compound include an inorganic silicon compound and an organosilicon compound.

Examples of the inorganic silicon compound include tetrachlorosilane, tetrabromosilane, tetraiodosilane and the like.

The organosilicon compound is not particularly limited as long as it is a compound having silicon and an organic group, and can be appropriately selected depending on the intended purpose. Silicon and an organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have an acyloxy group and a phenyl group which may have a substituent. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms.

Examples of the organosilicon compound include tetramethoxysilane, tetraethoxysilane, tetraisopropoxysilane, tetrabutoxysilane, 1,1,1,3,3,3-hexamethyldisilazane (HMDS), and bis (trimethylsilyl) acetylene. , Triphenylsilane, silicon 2-ethylhexanate, tetraacetoxysilane and the like.

The content of the silicon-containing compound in the coating liquid for forming the first passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Alkaline earth metal-containing compound ---
Examples of the alkaline earth metal-containing compound include an inorganic alkaline earth metal compound and an organic alkaline earth metal compound. Examples of the alkaline earth metal in the alkaline earth metal-containing compound include Be (berylium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

Examples of the inorganic alkaline earth metal compound include alkaline earth metal nitrate, alkaline earth metal sulfate, alkaline earth metal chloride, alkaline earth metal fluoride, alkaline earth metal bromide, and alkaline earth metal iodide. And so on.

Examples of the alkaline earth metal nitrate include magnesium nitrate, calcium nitrate, strontium nitrate, barium nitrate and the like.

Examples of the alkaline earth metal sulfate include magnesium sulfate, calcium sulfate, strontium sulfate, barium sulfate and the like.

Examples of the alkaline earth metal chloride include magnesium chloride, calcium chloride, strontium chloride, barium chloride and the like.

Examples of the alkaline earth metal fluoride include magnesium fluoride, calcium fluoride, strontium fluoride, barium fluoride and the like.

Examples of the alkaline earth metal bromide include magnesium bromide, calcium bromide, strontium bromide, barium bromide and the like.

Examples of the alkaline earth metal iodide include magnesium iodide, calcium iodide, strontium iodide, barium iodide and the like.

The organic alkaline earth metal compound is not particularly limited as long as it is a compound having an alkaline earth metal and an organic group, and can be appropriately selected depending on the intended purpose. The alkaline earth metal and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have a substituent, a phenyl group which may have a substituent, an acetylacetonate group which may have a substituent, a sulfonic acid group which may have a substituent, and the like. Be done. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, and Shu. Examples thereof include an acid and an acyloxy group having two or more carbonyl groups such as citric acid.

Examples of the organic alkaline earth metal compound include magnesium methoxydo, magnesium ethoxide, diethyl magnesium, magnesium acetate, magnesium formate, magnesium acetylacetone, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, magnesium citrate, and salicylic acid. Magnesium, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium methoxydo, calcium ethoxydo, calcium acetate, calcium formate, acetylacetone calcium, calcium dipivaloylmethanate, calcium 2-ethylhexanoate, calcium lactate , Calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, calcium benzoate, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetylacetone strontium, strontium 2-ethylhexanoate, strontium lactate, naphthenic acid Strontium, strontium salicylate, strontium oxalate, barium ethoxide, barium isopoxide, barium acetate, barium formate, acetylacetone barium, barium 2-ethylhexanoate, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, benzoate Examples thereof include barium acid, barium trifluoromethanesulfonate, and bis (acetylacetonate) berylium.

The content of the alkaline earth metal-containing compound in the coating liquid for forming the first passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Aluminum-containing compound ---
Examples of the aluminum-containing compound include inorganic aluminum compounds and organoaluminum compounds.

Examples of the inorganic aluminum compound include aluminum chloride, aluminum nitrate, aluminum bromide, aluminum hydroxide, aluminum borate, aluminum trifluoride, aluminum sulfate, aluminum sulfate, aluminum phosphate, ammonium aluminum sulfate and the like.

The organoaluminum compound is not particularly limited as long as it is a compound having aluminum and an organic group, and can be appropriately selected depending on the intended purpose. Aluminum and an organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have a substituent, an acetylacetonate group which may have a substituent, a sulfonic acid group which may have a substituent, and the like. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, and Shu. Examples thereof include an acid and an acyloxy group having two or more carbonyl groups such as citric acid.

Examples of the organic aluminum compound include aluminum isopropoxide, aluminum-sec-butoxide, triethylaluminum, diethylaluminum ethoxide, aluminum acetate, acetylacetone aluminum, hexafluoroacetylacetone aluminum, aluminum 2-ethylhexanoate, aluminum lactate, and scent. Examples thereof include aluminum acid, aluminum di (s-butoxide) acetoacetate chelate, and aluminum trifluoromethanesulfonate.

The content of the aluminum-containing compound in the coating liquid for forming the first passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Boron-containing compound ---
Examples of the boron-containing compound include an inorganic boron compound and an organic boron compound.

Examples of the inorganic boron compound include orthoboric acid, boron oxide, boron tribromide, tetrafluoroboric acid, ammonium borate, magnesium borate and the like. Examples of boron oxide include diboron dioxide, diboron trioxide, tetraboron trioxide, tetraboron pentoxide and the like.

The organic boron compound is not particularly limited as long as it is a compound having boron and an organic group, and can be appropriately selected depending on the intended purpose. Boron and an organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have a substituent, a phenyl group which may have a substituent, a sulfonic acid group which may have a substituent, and a thiophene group which may have a substituent. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Alkoxy groups also include organic groups that have two or more oxygen atoms and two of the two or more oxygen atoms are bonded to boron and together with boron to form a ring structure. included. It also includes an alkoxy group in which the alkyl group contained in the alkoxy group is replaced with an organic silyl group. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms.

Examples of the organoboron compound include (R) -5,5-diphenyl-2-methyl-3,4-propano-1,3,2-oxazaborolidine, triisopropyl borate, and 2-isopropoxy-4. , 4,5,5-tetramethyl-1,3,2-dioxaborolane, bis (hexyleneglycolato) diboron, 4- (4,5,5-tetramethyl-1,3,2-dioxaborolane-2) -Il) -1H-pyrazole, (4,5,5-tetramethyl-1,3,2-dioxaborolan-2-yl) benzene, tert-butyl-N- [4- (4,4,5,5) 5-Tetramethyl-1,2,3-dioxaborolan-2-yl) phenyl] carbamate, phenylboronic acid, 3-acetylphenylboronic acid, boron trifluoride acetic acid complex, boron trifluoride sulfolane complex, 2-thiophenboron Examples thereof include acid and tris (trimethylsilyl) boronate.

The content of the boron-containing compound in the coating liquid for forming the first passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Solvent ---
The solvent is not particularly limited as long as it is a solvent that stably dissolves or disperses various compounds, and can be appropriately selected depending on the intended purpose. For example, toluene, xylene, mesitylene, simene, pentylbenzene, dodecylbenzene, etc. Bicyclohexyl, cyclohexylbenzene, decane, undecane, dodecane, tridecane, tetradecane, pentadecane, tetralin, decalin, isopropanol, ethyl benzoate, N, N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, mineral spirits, dimethylpropylene urea , 4-Byrolactone, 2-methoxyethanol, propylene glycol, water and the like.

The content of the solvent in the coating liquid for forming the first passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

The composition ratio of the silicon-containing compound and the alkaline earth metal-containing compound in the coating liquid for forming the first passivation layer (silicon-containing compound: alkaline earth metal-containing compound) is not particularly limited and may be appropriately used according to the purpose. It can be selected, but it is preferably in the following range.

In the first passivation layer forming coating liquid, the composition ratio of Si and alkaline earth metal (Si: alkaline earth metal) is _{converted to oxides (SiO 2} , BeO, MgO, CaO, SrO, BaO). 50.0 mol% to 90.0 mol%: 10.0 mol% to 50.0 mol% is preferable.

The composition ratio of the silicon-containing compound, the alkaline earth metal-containing compound, and at least one of the aluminum-containing compound and the boron-containing compound in the coating liquid for forming the first passivation layer (silicon-containing compound: alkaline earth metal-containing compound: aluminum). The compound (at least one of the contained compound and the boron-containing compound) is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably in the following range.

In the first passivation layer forming coating liquid, the composition ratio of Si, alkaline earth metal, and at least one of Al and B (Si: alkaline earth metal: at least one of Al and B) is oxidized. In terms of substances (SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ), 50.0 mol% to 90.0 mol%: 5.0 mol% to 20.0 mol%: 5. It is preferably 0 mol% to 30.0 mol%.

--A coating liquid for forming a second passivation layer ---
The coating liquid for forming the second passivation layer contains at least an alkaline earth metal-containing compound (element A-containing compound), a B-element-containing compound, and a solvent, and preferably at least the C-element-containing compound. Any of them is contained, and if necessary, other components are contained.

--- Alkaline earth metal-containing compound (element A-containing compound) ---
Examples of the alkaline earth metal-containing compound include an inorganic alkaline earth metal compound and an organic alkaline earth metal compound. Examples of the alkaline earth metal in the alkaline earth metal-containing compound include Be (berylium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

Examples of the inorganic alkaline earth metal compound include alkaline earth metal nitrate, alkaline earth metal sulfate, alkaline earth metal chloride, alkaline earth metal fluoride, alkaline earth metal bromide, and alkaline earth metal iodide. And so on.

Examples of the alkaline earth metal nitrate include magnesium nitrate, calcium nitrate, strontium nitrate, barium nitrate and the like.

Examples of the alkaline earth metal sulfate include magnesium sulfate, calcium sulfate, strontium sulfate, barium sulfate and the like.

Examples of the alkaline earth metal chloride include magnesium chloride, calcium chloride, strontium chloride, barium chloride and the like.

Examples of the alkaline earth metal fluoride include magnesium fluoride, calcium fluoride, strontium fluoride, barium fluoride and the like.

Examples of the alkaline earth metal bromide include magnesium bromide, calcium bromide, strontium bromide, barium bromide and the like.

Examples of the alkaline earth metal iodide include magnesium iodide, calcium iodide, strontium iodide, barium iodide and the like.

The organic alkaline earth metal compound is not particularly limited as long as it is a compound having an alkaline earth metal and an organic group, and can be appropriately selected depending on the intended purpose. The alkaline earth metal and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have a substituent, a phenyl group which may have a substituent, an acetylacetonate group which may have a substituent, a sulfonic acid group which may have a substituent, and the like. Be done. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, and Shu. Examples thereof include an acid and an acyloxy group having two or more carbonyl groups such as citric acid.

Examples of the organic alkaline earth metal compound include magnesium methoxydo, magnesium ethoxide, diethyl magnesium, magnesium acetate, magnesium formate, magnesium acetylacetone, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, magnesium citrate, and salicylic acid. Magnesium, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium methoxydo, calcium ethoxydo, calcium acetate, calcium formate, acetylacetone calcium, calcium dipivaloylmethanate, calcium 2-ethylhexanoate, calcium lactate , Calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, calcium benzoate, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetylacetone strontium, strontium 2-ethylhexanoate, strontium lactate, naphthenic acid Strontium, strontium salicylate, strontium oxalate, barium ethoxydo, barium isopropoxide, barium acetate, barium formate, acetylacetone barium, barium 2-ethylhexanoate, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, benzoate Examples thereof include barium acid, barium trifluoromethanesulfonate, and bis (acetylacetonate) berylium.

The content of the alkaline earth metal-containing compound in the coating liquid for forming the second passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Element B-containing compound ---
Rare earth elements in the element B-containing compound include Ga (gallium), Sc (scandium), Y (yttrium), La (lantern), Ce (cerium), Pr (placeodim), Nd (neodymium), and Pm (promethium). , Sm (samarium), Eu (yttrium), Gd (gadrinium), Tb (terbium), Dy (dysprosium), Ho (formium), Er (erbium), Tm (thulium), Yb (yttrium), Lu (lutetium) Can be mentioned.

Examples of the element B-containing compound include an inorganic element B compound and an organic element B compound.

Examples of the inorganic element B compound include nitrate of element B, sulfate of element B, fluoride of element B, chloride of element B, bromide of element B, and iodide of element B. Can be mentioned.

Examples of the nitrate of the second element include gallium nitrate, scandium nitrate, ittium nitrate, lanthanum nitrate, cerium nitrate, placeodium nitrate, neodymium nitrate, samarium nitrate, europium nitrate, gadolinium nitrate, terbium nitrate, displosium nitrate, formium nitrate, and nitrate. Examples thereof include erbium, turium nitrate, itterbium nitrate, and lutetium nitrate.

Examples of the sulfate of the element B include gallium sulfate, scandium sulfate, yttrium sulfate, lanthanum sulfate, cerium sulfate, placeodym sulfate, neodymium sulfate, samarium sulfate, europium sulfate, gadolinium sulfate, terbium sulfate, displosium sulfate, formium sulfate, and the like. Examples thereof include erbium sulfate, turium sulfate, itterbium sulfate, and lutetium sulfate.

Examples of the fluoride of the element B include gallium fluoride, scandium fluoride, ytterbium fluoride, lanthanum fluoride, cerium fluoride, placeodium fluoride, neodymium fluoride, samarium fluoride, uropium fluoride, and gadolinium fluoride. , Terbium fluoride, dysprosium fluoride, formium fluoride, elbium fluoride, thulium fluoride, ytterbium fluoride, lutetium fluoride and the like.

Examples of the chloride of the element B include gallium chloride, scandium chloride, yttrium chloride, lanthanum chloride, cerium chloride, placeodym chloride, neodymium chloride, samarium chloride, europium chloride, gadolinium chloride, terbium chloride, displosium chloride, formium chloride, and the like. Examples thereof include erbium chloride, turium chloride, itterbium chloride, and lutetium chloride.

Examples of the bromide of the element B include gallium bromide, scandium bromide, ytterbium bromide, lantern bromide, cerium bromide, praseodymium bromide, neodymium bromide, samarium bromide, europium bromide, and gadolinium bromide. Examples thereof include terbium bromide, dysprosium bromide, holmium bromide, erbium bromide, thulium bromide, ytterbium bromide, lutetium bromide and the like.

Examples of the element B iodide include gallium iodide, scandium iodide, ytterbium iodide, lanthanum iodide, cerium iodide, praseodymium iodide, neodymium iodide, samarium iodide, uropyum iodide, and gadolinium iodide. Examples thereof include terbium iodide, dysprosium iodide, holmium iodide, elbium iodide, thulium iodide, ytterbium iodide, and lutetium iodide.

The organic element B compound is not particularly limited as long as it is a compound having the element B and an organic group, and can be appropriately selected depending on the intended purpose. The element B and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have a substituent, an acetylacetonate group which may have a substituent, a cyclopentadienyl group which may have a substituent, and the like. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms.

Examples of the organic element B compound include tris (cyclopentadienyl) gallium, scandium isopropoxide, scandium acetate, tris (cyclopentadienyl) scandium, ittrium isopropoxide, yttrium 2-ethylhexanoate, and tris ( Acetylacetonate) ittrium, tris (cyclopentadienyl) ittrium, lanthanum isopropoxide, lanthanum 2-ethylhexanoate, tris (acetylacetonate) lantern, tris (cyclopentadienyl) lantern, cerium 2-ethylhexanoate , Tris (acetylacetonate) cerium, tris (cyclopentadienyl) cerium, praseodymium isopropoxide, praseodymium oxalate, tris (acetylacetonate) praseodymium, tris (cyclopentadienyl) praseodymium, neodymium isopropoxide, 2 -Neodymium ethylhexanoate, trifluoroacetylacetonateneodymium, tris (isopropylcyclopentadienyl) neodymium, tris (ethylcyclopentadienyl) promethium, samarium isopropoxide, samarium 2-ethylhexanoate, tris (acetylacetonate) ) Samalium, Tris (cyclopentadienyl) samarium, 2-ethylhexanoate uropium, tris (acetylacetonate) uropium, tris (ethylcyclopentadienyl) uropium, gadrinium isopropoxide, 2-ethylhexanoate gadrinium, tris (Acetylacetonate) gadrinium, tris (cyclopentadienyl) gadrinium, terbium acetate, tris (acetylacetonate) terbium, tris (cyclopentadienyl) terbium, dysprosium isopropoxide, dysprosium acetate, tris (acetylacetonate) Dysprosium, Tris (ethylcyclopentadienyl) dysprosium, formium isopropoxide, formium acetate, tris (cyclopentadienyl) formium, erbium isopropoxide, erbium acetate, tris (acetylacetonate) erbium, tris (cyclopentadi) Enyl) erbium, turium acetate, tris (acetylacetonate) turium, tris (cyclopentadienyl) turium, itterbium isopropoxide, itterbium acetate, tris (acetylacetonate) itterbium, tris (cyclo) Examples thereof include ytterbium (pentadienyl), lutetium oxalate, and tris (ethylcyclopentadienyl) lutetium.

The content of the element B-containing compound in the coating liquid for forming the second passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Element C-containing compound ---
Examples of the C element include Al (aluminum), Ti (titanium), Zr (zirconium), Hf (hafnium), Nb (niobium), and Ta (tantalum).

Examples of the element C-containing compound include an inorganic compound of the C element, an organic compound of the C element, and the like.

Examples of the element C inorganic compound include element C nitrate, element C sulfate, element C fluoride, element C chloride, element C bromide, and element C iodide. And so on.

Examples of the inorganic compound of element C include aluminum nitrate, aluminum sulfate, aluminum fluoride, aluminum chloride, aluminum bromide, aluminum bromide, aluminum hydroxide, aluminum phosphate, ammonium aluminum sulfate, titanium sulfide, and titanium fluoride. , Titanium chloride, titanium bromide, titanium bromide, zirconium sulfate, zirconium carbonate, zirconium fluoride, zirconium chloride, zirconium bromide, zirconium bromide, hafnium sulfate, hafnium fluoride, hafnium chloride, hafnium bromide, hafnium bromide , Niobide fluoride, niobium chloride, niobium bromide, tantalum fluoride, tantalum chloride, tantalum bromide and the like.

The organic compound of the C element is not particularly limited as long as it is a compound having the C element and an organic group, and can be appropriately selected depending on the intended purpose. The element C and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordination bond.

The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent may be selected. Examples thereof include an acyloxy group which may have a substituent, an acetylacetonate group which may have a substituent, a cyclopentadienyl group which may have a substituent, and the like. Examples of the alkyl group include an alkyl group having 1 to 6 carbon atoms. Examples of the alkoxy group include an alkoxy group having 1 to 6 carbon atoms. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms.

Examples of the organic compound of the element C include aluminum isopropoxide, aluminum-sec-butoxide, triethylaluminum, diethylaluminum ethoxide, aluminum acetate, acetylacetonealuminum, aluminum hexafluoroacetylacetoneate, aluminum 2-ethylhexanoate, and lactic acid. Aluminum, aluminum benzoate, aluminum di (s-butoxide) acetoacetate chelate, aluminum trifluoromethanesulfonate, titanium isopropoxide, bis (cyclopentadienyl) titanium chloride, zirconium butoxide, zirconium isopropoxide, bis (2) -Zylzyl oxide (-ethylhexanoic acid), zirconium di (n-butoxide) bisacetyl sweat toner, tetrakis (acetylacetoneic acid) zirconium, tetrakis (cyclopentadienyl) zirconium, hafnium butoxide, hafnium isopropoxide, tetrakis (2-ethylhexane) Acid) hafnium, hafnium di (n-butoxide) bisacetylacetonate, tetrakis (acetylacetoneic acid) hafnium, bis (cyclopentadienyl) dimethylhafnium, niobethoxydo, niobium 2-ethylhexanoate, bis (cyclopentadienyl) Examples thereof include niobium chloride, tantalum ethoxydo, and tetraethoxyacetylacetonate tantalum.

The content of the element C-containing compound in the coating liquid for forming the second passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

--- Solvent ---
The solvent is not particularly limited as long as it is a solvent that stably dissolves or disperses various compounds, and can be appropriately selected depending on the intended purpose. For example, toluene, xylene, mesitylene, simene, pentylbenzene, dodecylbenzene, etc. Bicyclohexyl, cyclohexylbenzene, decane, undecane, dodecane, tridecane, tetradecane, pentadecane, tetralin, decalin, isopropanol, ethyl benzoate, N, N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, mineral spirits, dimethylpropylene urea , 4-Byrolactone, 2-methoxyethanol, propylene glycol, water and the like.

The content of the solvent in the coating liquid for forming the second passivation layer is not particularly limited and may be appropriately selected depending on the intended purpose.

The composition ratio of the alkaline earth metal-containing compound (element A-containing compound) and the element B-containing compound (alkaline earth metal-containing compound: element B-containing compound) in the coating liquid for forming the second passivation layer is The present invention is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably in the following range.

In the coating liquid for forming the second passivation layer, the composition ratio of the element A, which is an alkaline earth metal, and the element B, which is at least one of Ga, Sc, Y, and lanthanoid (element A: element B). Elements) include oxides (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ In _{terms of O 3} , Lu ₂ O ₃ ), 10.0 mol% to 67.0 mol%: preferably 33.0 mol% to 90.0 mol%.

The composition ratio of at least one of the alkaline earth metal-containing compound (element A-containing compound), the element B-containing compound, and the element C-containing compound in the coating liquid for forming the second passivation layer (containing alkaline earth metal). The compound (element B-containing compound: element C-containing compound) is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably in the following range.

In the coating liquid for forming the second passivation layer, the element A, which is an alkaline earth metal, the element B, which is at least one of Ga, Sc, Y, and lanthanoid, and Al, Ti, Zr, Hf, and Nb. , And the composition ratio (element A: element B: element C) with at least one of Ta is an oxide (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TIO ₂ , ZrO ₂ , HfO ₂ , Nb _In terms of 2 O ₅ , Ta ₂ O ₅ ), 5.0 mol% to 22.0 mol%: 33.0 mol% to 90.0 mol: 5.0 mol% to 45.0 mol% is preferable.

--- Method of forming the first passivation layer and the second passivation layer ---
An example of a method of forming a first passivation layer using a coating liquid for forming a first passivation layer and a method of forming a second passivation layer using a coating liquid for forming a second passivation layer will be described. The method for forming the first passivation layer 170a and the second passivation layer 170b includes a coating step and a heat treatment step, and further includes other steps if necessary.

The coating step is not particularly limited as long as it is a step of applying the first passivation layer forming coating solution or the second passivation layer forming coating solution to the object to be coated, and it is appropriately selected according to the purpose. Can be done. The coating method is not particularly limited and may be appropriately selected depending on the intended purpose. For example, it is desired by a method of patterning by photolithography after film formation by a solution process, or a printing method such as inkjet, nanoimprint, or gravure. Examples thereof include a method of directly forming a film of the shape of. Examples of the solution process include dip coating, spin coating, die coating, nozzle printing and the like.

The heat treatment step is not particularly limited as long as it is a step of heat-treating the first passivation layer forming coating liquid or the second passivation layer forming coating liquid applied to the object to be coated, and is appropriately used according to the purpose. You can choose. At the time of heat treatment, the first passivation layer forming coating liquid or the second passivation layer forming coating liquid applied to the object to be coated may be dried by natural drying or the like. By the heat treatment, the solvent is dried, an oxide (the first oxide or the second oxide) is produced, and the like.

In the heat treatment step, the drying of the solvent (hereinafter, referred to as “drying treatment”) and the formation of the first oxide or the second oxide (hereinafter, referred to as “formation treatment”) are different. It is preferable to carry out at temperature. That is, it is preferable to dry the solvent and then raise the temperature to produce the first oxide or the second oxide. During the formation of the second oxide, for example, decomposition of at least one of a silicon-containing compound, an alkaline earth metal-containing compound, an aluminum-containing compound, and a boron-containing compound occurs. During the formation of the first oxide, for example, decomposition of at least one of an alkaline earth metal-containing compound (element A-containing compound), a element B-containing compound, and an element C-containing compound occurs.

The temperature of the drying treatment is not particularly limited and may be appropriately selected depending on the solvent contained therein, and examples thereof include 80 ° C. to 180 ° C. In drying, it is effective to use a decompression oven or the like for lowering the temperature. The time of the drying treatment is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include 1 minute to 1 hour.

The temperature of the production treatment is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 100 ° C. or higher and lower than 550 ° C., more preferably 200 ° C. to 500 ° C. The time of the generation process is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include 1 hour to 5 hours.

In the heat treatment step, the drying treatment and the production treatment may be continuously carried out, or may be divided into a plurality of steps and carried out.

The heat treatment method is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include a method of heating an object to be coated. The atmosphere in the heat treatment is not particularly limited and may be appropriately selected depending on the intended purpose, but an oxygen atmosphere is preferable. By performing the heat treatment in an oxygen atmosphere, the decomposition product can be rapidly discharged to the outside of the system, and the formation of the first oxide or the second oxide can be promoted.

During the heat treatment, it is effective to irradiate the substance after the drying treatment with ultraviolet light having a wavelength of 400 nm or less in order to accelerate the reaction of the production treatment. By irradiating with ultraviolet light having a wavelength of 400 nm or less, chemical bonds such as organic substances contained in the substance after the drying treatment can be cleaved and the organic substances can be decomposed, so that the first oxide or the second oxide can be efficiently decomposed. Oxide can be formed. The ultraviolet light having a wavelength of 400 nm or less is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include ultraviolet light having a wavelength of 222 nm using an excimer lamp. It is also preferable to impart ozone instead of or in combination with irradiation with ultraviolet light. By adding ozone to the material after the drying treatment, the formation of oxides is promoted.

Next, in the step shown in FIG. 14B, the mask 300 is formed in a predetermined region on the second passivation layer 170b. The mask 300 is not particularly limited as long as it is a material that functions as a protective film in the etching process of the first passivation layer 170a and the second passivation layer 170b, and can be appropriately selected depending on the intended purpose. The material of the mask 300 is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include a positive type photoresist and a negative type photoresist.

Next, in the step shown in FIG. 15A, the second passivation layer 170b is etched to form the second passivation layer 17b having a predetermined shape. The second passivation layer 170b can be etched with the first solution. Etching methods include a dip method in which the second passivation layer 170b is immersed in the first solution, a spray method in which the first solution is sprayed onto the second passivation layer 170b, and a second passivation layer 170b. An example is a spin method in which the first solution is dropped and the substrate containing the second passivation layer 170b is rotated.

The concentration of hydrochloric acid in the first solution is preferably 0.04 wt% to 40 wt%. The concentration of oxalic acid in the first solution is preferably 0.1 wt% to 10 wt%. The concentration of nitric acid in the first solution is preferably 0.1 wt% to 40 wt%. The concentration of phosphoric acid in the first solution is preferably 0.1 wt% to 85 wt%. The concentration of acetic acid in the first solution is preferably 1 wt% to 50 wt%. The concentration of sulfuric acid in the first solution is preferably 1 wt% to 20 wt%. The concentration of the hydrogen peroxide solution in the first solution is preferably 1 wt% to 10 wt%. As the first solution, a mixed solution of hydrochloric acid, phosphoric acid and nitric acid, and a mixed solution of phosphoric acid, nitric acid and acetic acid are preferable.

Next, in the step shown in FIG. 15B, the first passivation layer 170a is etched to form the first passivation layer 17a having a predetermined shape. The first passivation layer 170a can be etched with a solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium hydrogen fluoride, and an organic alkali (hereinafter, may be referred to as the second solution). it can. Etching methods include a dip method in which the first passivation layer 170a is immersed in the second solution, a spray method in which the second solution is sprayed onto the first passivation layer 170a, and a first passivation layer 170a. Examples thereof include a spin method in which the second solution is dropped and the substrate containing the first passivation layer 170a is rotated.

In the ninth embodiment, after the second passivation layer is etched in the step shown in FIG. 15 (a), the first passivation layer is continuously etched in the step shown in FIG. 15 (b). .. Therefore, it is not necessary to form a mask on each of the second passivation layer and the first passivation layer, the number of steps for patterning the passivation layer is simplified, productivity is good, and a passivation layer having a desired shape can be obtained. Can be formed.

The concentration of hydrofluoric acid in the second solution is preferably 0.1 to 10 wt%. The concentration of ammonium fluoride in the second solution is preferably 5 to 25 wt%. The concentration of ammonium hydrogen fluoride in the second solution is preferably 1 to 25 wt%. The concentration of the organic alkali in the second solution is preferably 1 to 15 wt%. As the second solution, a solution of hydrofluoric acid, ammonium fluoride and ammonium hydrogen fluoride is preferable.

Next, in the step shown in FIG. 15C, the mask 300 is removed. The method for removing the mask 300 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, when a photoresist is used for the mask 300, the mask 300 can be dissolved and the mask 300 can be removed with a solution such as a resist stripping solution. Further, as the method for removing the mask 300, it is preferable to select a method that does not damage the passivation layer. Through the above steps, a bottom gate / bottom contact type field effect transistor 110 can be manufactured.

As described above, in the field-effect transistor according to the ninth embodiment, the passivation layer includes the first passivation layer containing the second oxide and the second passivation layer containing the first oxide. It is arranged in contact with the passivation layer.

The method for manufacturing the field-effect transistor according to the ninth embodiment includes a step of wet-etching the first passivation layer by bringing it into contact with the second solution, and the first passivation layer. It includes a step of wet etching by contacting with the solution of.

By using the above solution for each passivation layer, each passivation layer can be suitably wet-etched. Since it is not necessary to use a conventional dry etching process, no high-risk gas is used, and there are no problems such as environmental load and the price of the equipment used.

Further, since the passivation layer in which the second oxide and the first oxide are laminated has a high barrier property, the reliability of the field-effect transistor is improved (for example, the fluctuation amount of the threshold voltage with respect to the BTS test is increased. (Small) is possible.

That is, by wet-etching each passivation layer with the above solution, a high-performance (low power consumption, high reliability) field-effect transistor can be manufactured at low cost, high safety, and low environmental load. It becomes possible to do.

<Modified example of the ninth embodiment>
A modification of the ninth embodiment shows an example of a field effect transistor having a layer structure different from that of the ninth embodiment. In the modified example of the ninth embodiment, the description of the same component as that of the above-described embodiment may be omitted.

FIG. 16 is a cross-sectional view illustrating an electric field effect transistor according to a modified example of the ninth embodiment. Each field-effect transistor shown in FIG. 16 is a typical example of the semiconductor device according to the present invention.

The field effect transistor 110A shown in FIG. 16A is a bottom gate / top contact type field effect transistor. In the field effect transistor 110A, the gate electrode 12 is formed on the insulating substrate 11, and the gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, an active layer 16 is formed on the gate insulating layer 13, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 at predetermined intervals which are channel regions of the active layer 16. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second passivation layer 17b is further formed on the first passivation layer 17a. Is formed.

The field effect transistor 110B shown in FIG. 16B is a top gate / bottom contact type field effect transistor. In the field effect transistor 110B, the source electrode 14 and the drain electrode 15 are formed on the insulating substrate 11, and the active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the gate electrode 12, and a second passivation layer 17b is further formed on the first passivation layer 17a.

The field-effect transistor 110C shown in FIG. 16C is a top-gate / top-contact field-effect transistor. In the field effect transistor 110C, the active layer 16 is formed on the insulating substrate 11, and the source electrode 14 and the drain electrode 15 are separated on the active layer 16 by a predetermined interval which becomes a channel region of the active layer 16. It is formed. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the gate electrode 12, and a second passivation layer 17b is further formed on the first passivation layer 17a.

As described above, the layer structure of the field-effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 13 and 16 can be appropriately selected depending on the intended purpose. Regarding the field effect transistors 110A, 110B, and 110C shown in FIG. 16, the first passivation layer 17a and the second passivation layer 17b can be manufactured by the same manufacturing method as the field effect transistor 110. Therefore, the field effect transistors 110A, 110B, and 110C also have the same effect as the field effect transistors 110.

Contrary to FIGS. 16A to 16C, the second passivation layer 17b may be arranged in the active layer 16 rather than the first passivation layer 17a. Further, the second passivation layer 17b may be arranged so as to cover the upper surface and the side surface of the first passivation layer 17a, or the first passivation layer may cover the upper surface and the side surface of the second passivation layer 17b. 17a may be arranged.

<10th Embodiment>
In the tenth embodiment, an example of a field effect transistor provided with a gate insulating layer having a two-layer structure is shown. In the tenth embodiment, the description of the same components as those of the above-described embodiment may be omitted.

[Structure of field effect transistor]
FIG. 17 is a cross-sectional view illustrating the field effect transistor according to the tenth embodiment. With reference to FIG. 17, the field-effect transistor 110D includes a substrate 11, a gate electrode 12, a first gate insulating layer 13a, a second gate insulating layer 13b, a source electrode 14, and a drain electrode 15. , A bottom gate / bottom contact type field effect transistor having an active layer 16 and a first passivation layer 17a. The field effect transistor 110D is a typical example of the semiconductor device according to the present invention.

The field-effect transistor 110D has a two-layer structure in which the gate insulating layer is the first gate insulating layer 13a and the second gate insulating layer 13b, and the passivation layer is only the first passivation layer 17a. The point is different from the field effect transistor 110 (see FIG. 13). However, the passivation layer may be only the second passivation layer 17b, or may have a two-layer structure of the first passivation layer 17a and the second passivation layer 17b as in the field-effect transistor 110.

The arrangement of the first gate insulating layer 13a and the second gate insulating layer 13b in the gate insulating layer is not particularly limited and may be appropriately selected depending on the intended purpose. As shown in FIG. 17, the first gate insulating layer The gate insulating layer 13a may be arranged closer to the gate electrode 12 than the second gate insulating layer 13b, and conversely, the second gate insulating layer 13b is a gate electrode rather than the first gate insulating layer 13a. It may be arranged at 12. Further, the second gate insulating layer 13b may be arranged so as to cover the upper surface and the side surface of the first gate insulating layer 13a, or the first gate insulating layer 13b may be arranged so as to cover the upper surface and the side surface of the second gate insulating layer 13b. The gate insulating layer 13a of the above may be arranged.

The first gate insulating layer 13a can be formed of the same material as the first passivation layer 17a, and the second gate insulating layer 13b can be formed of the same material as the second passivation layer 17b.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field-effect transistor shown in FIG. 17 will be described. 18 and 19 are diagrams illustrating a manufacturing process of the field effect transistor according to the tenth embodiment.

First, in the step shown in FIG. 18A, the gate electrode 12 having a predetermined shape is formed on the substrate 11 in the same manner as in the step shown in FIG. 2A.

Next, in the step shown in FIG. 18B, a first gate insulating layer 130a (a layer that is etched to become the first gate insulating layer 13a) that covers the gate electrode 12 is formed on the entire surface of the substrate 11. To do. Then, a second gate insulating layer 130b (a layer that is etched to become a second gate insulating layer 13b) is formed on the entire surface of the first gate insulating layer 130a.

The first gate insulating layer 130a can be formed of the same material as the first passivation layer 170a, and the second gate insulating layer 130b can be formed of the same material as the second passivation layer 170b. The method for forming the first gate insulating layer 130a is not particularly limited, and various methods exemplified as the method for forming the first passivation layer 170a can be appropriately selected depending on the intended purpose. Similarly, the method for forming the second gate insulating layer 130b is not particularly limited, and various methods exemplified as the method for forming the second passivation layer 170b can be appropriately selected depending on the intended purpose.

Next, in the step shown in FIG. 18C, the mask 310 is formed in a predetermined region on the second gate insulating layer 130b in the same manner as in the step shown in FIG. 14B. Next, in the step shown in FIG. 18D, the second gate insulating layer 130b is etched to form the second gate insulating layer 13b having a predetermined shape in the same manner as in the step shown in FIG. 15A. ..

Next, in the step shown in FIG. 19A, the first gate insulating layer 130a is etched to form the first gate insulating layer 13a having a predetermined shape in the same manner as in the step shown in FIG. 15B. .. Next, in the step shown in FIG. 19B, the mask 310 is removed in the same manner as in the step shown in FIG. 15C.

Next, in the step shown in FIG. 19 (c), the bottom gate / bottom contact type electric field effect is obtained by executing the same steps as in FIGS. 2 (d) to 3 (c) of the first embodiment. A type transistor 110D can be manufactured. However, the passivation layer may be only the first passivation layer 17a, and if necessary, only the second passivation layer 17b, or the first passivation layer 17a and the second passivation as in the field effect transistor 110. It may have a two-layer structure of the layer 17b.

As described above, the electric field effect type transistor according to the tenth embodiment has, as a gate insulating layer, a first gate insulating layer containing the second oxide containing Si and an alkaline earth metal. The second gate insulating layer containing the first oxide containing the element A, which is an alkaline earth metal, and the element B, which is at least one of Ga, Sc, Y, and a lanthanoid. They are placed in contact with each other.

The method for manufacturing the field-effect transistor according to the tenth embodiment includes a step of wet-etching the first gate insulating layer by bringing it into contact with the second solution, and the second gate insulating layer. It includes a step of wet etching by contacting with a first solution.

By using the above solution for each gate insulating layer, each gate insulating layer can be suitably wet-etched. Since it is not necessary to use a conventional dry etching process, no high-risk gas is used, and there are no problems such as environmental load and the price of the equipment used.

Further, since the relative permittivity of the first oxide is about 6 to 20, which _{is higher than that of the SiO 2} film, the use of the first oxide in the gate insulating layer lowers the field effect transistor. Voltage drive (low power consumption) is possible.

That is, by wet-etching each gate insulating layer with the above solution, a high-performance (low power consumption, high reliability) field-effect transistor can be obtained at low cost, high safety, and low environmental load. It becomes possible to manufacture.

<Modified example of the tenth embodiment>
A modification of the tenth embodiment shows an example of a field effect transistor having a layer structure different from that of the tenth embodiment. In the modified example of the tenth embodiment, the description of the same component as that of the above-described embodiment may be omitted.

FIG. 20 is a cross-sectional view illustrating an electric field effect transistor according to a modified example of the tenth embodiment. Each field-effect transistor shown in FIG. 20 is a typical example of the semiconductor device according to the present invention.

The field effect transistor 110E shown in FIG. 20A is a bottom gate / top contact type field effect transistor. In the field effect transistor 110E, the gate electrode 12 is formed on the insulating substrate 11, the first gate insulating layer 13a is formed so as to cover the gate electrode 12, and the first gate insulating layer 13a is further covered with the first gate insulating layer 13a. The gate insulating layer 13b of No. 2 is formed.

Further, the active layer 16 is formed on the second gate insulating layer 13b, and the source electrode 14 and the drain electrode 15 are formed on the active layer 16 at predetermined intervals that serve as channel regions of the active layer 16. There is. A first passivation layer 17a is formed on the second gate insulating layer 13b so as to cover the source electrode 14, the drain electrode 15, and the active layer 16.

The field effect transistor 110F shown in FIG. 20B is a top gate / bottom contact type field effect transistor. In the field effect transistor 110F, the source electrode 14 and the drain electrode 15 are formed on the insulating substrate 11, and the active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a first gate insulating layer 13a is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second gate insulating layer 13b is further formed on the first gate insulating layer 13a. The gate electrode 12 is formed on the second gate insulating layer 13b. Then, a first passivation layer 17a is formed on the second gate insulating layer 13b so as to cover the gate electrode 12.

The field effect transistor 110G shown in FIG. 20 (c) is a top gate / top contact type field effect transistor. In the field effect transistor 110G, the active layer 16 is formed on the insulating substrate 11, and the source electrode 14 and the drain electrode 15 are separated on the active layer 16 by a predetermined interval which becomes a channel region of the active layer 16. It is formed. Further, a first gate insulating layer 13a is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second gate insulating layer 13b is further formed on the first gate insulating layer 13a. The gate electrode 12 is formed on the second gate insulating layer 13b. Then, a first passivation layer 17a is formed on the second gate insulating layer 13b so as to cover the gate electrode 12.

As described above, the layer structure of the field-effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 17 and 20 can be appropriately selected depending on the intended purpose. Regarding the field effect transistors 110E, 110F, and 110G shown in FIG. 20, the first gate insulating layer 13a and the second gate insulating layer 13b can be manufactured by the same manufacturing method as the field effect transistor 110D. Therefore, the field effect transistors 110E, 110F, and 110G also have the same effect as the field effect transistors 110D.

Contrary to FIGS. 20 (a) to 20 (c), the second gate insulating layer 13b may be arranged in the active layer 16 rather than the first gate insulating layer 13a. Further, the second gate insulating layer 13b may be arranged so as to cover the upper surface and the side surface of the first gate insulating layer 13a, or the first gate insulating layer 13b may be arranged so as to cover the upper surface and the side surface of the second gate insulating layer 13b. The gate insulating layer 13a of the above may be arranged. Further, the passivation layer may be only the second passivation layer 17b, or may have a two-layer structure of the first passivation layer 17a and the second passivation layer 17b as in the field effect transistor 110.

<11th Embodiment>
In the eleventh embodiment, an example of an organic electroluminescence (organic EL) display element is shown. In the eleventh embodiment, the description of the same components as those in the above-described embodiment may be omitted.

21 and 22 are cross-sectional views illustrating the structure and manufacturing method of the organic EL display element according to the eleventh embodiment.

The organic EL display element 150 shown in FIG. 21A is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a bottom contact / top gate type field effect transistor.

The organic EL display element 150A shown in FIG. 21B is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a top contact / top gate type field effect transistor.

The organic EL display elements 150 and 150A include a substrate 321, a first gate electrode 322 and a second gate electrode 323, a gate insulating layer 351 and a first source electrode 325 and a second source electrode 326. 1. The drain electrode 327 and the second drain electrode 328, the first active layer 329 and the second active layer 330, the first passion layer 41a and the second passion layer 41b, the interlayer insulating film 43, and the like. It has an organic EL layer 352 and a cathode 45.

The first drain electrode 327 and the second gate electrode 323 are connected to each other via a through hole formed in the gate insulating layer 351. The second drain electrode 328 functions as an anode in the organic EL element 350.

In the case of FIGS. 21 (a) and 21 (b), a capacitor is formed between the second gate electrode 323 and the second drain electrode 328, but the capacitor forming location is not limited. , Capacitors with the required capacity can be designed and formed at the required locations.

Substrate 321, first gate electrode 322 and second gate electrode 323, gate insulating layer 351, first source electrode 325 and second source electrode 326, first drain electrode 327 and second drain electrode 328, Regarding the first active layer 329 and the second active layer 330, the first passivation layer 41a and the second passivation layer 41b, the materials and processes described in the description of the field effect transistor according to the ninth embodiment. Etc. can be formed.

The first passivation layer 41a and the second passivation layer 41b correspond to the first passivation layer 17a and the second passivation layer 17b of the field effect transistor 110 and the like. Further, as in the ninth embodiment, the arrangement of the first passivation layer 41a and the second passivation layer 41b in the passivation layer is not particularly limited and can be appropriately selected according to the purpose. .. Further, the second passivation layer 41b may be arranged so as to cover the upper surface and the side surface of the first passivation layer 41a, or the first passivation layer may cover the upper surface and the side surface of the second passivation layer 41b. 41a may be arranged.

The material of the interlayer insulating film 43 (flattening film) is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include organic materials, inorganic materials and organic-inorganic composite materials.

Examples of the organic material include resins such as polyimide, acrylic resin, fluorine-based resin, non-fluorine-based resin, olefin-based resin, and silicone resin, and photosensitive resins using them.

Examples of the inorganic material include SOG (spin on glass) materials such as Aquamica manufactured by AZ Electronic Materials Co., Ltd.

Examples of the organic-inorganic composite material include an organic-inorganic composite compound composed of a silane compound disclosed in Patent Document (Japanese Unexamined Patent Publication No. 2007-158146).

The interlayer insulating film 43 preferably has a barrier property against moisture, oxygen, and hydrogen in the atmosphere.

The process for forming the interlayer insulating film 43 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, it is desired by spin coating, inkjet printing, slit coating, nozzle printing, gravure printing, dip coating method or the like. Examples include a method of directly forming a film of the shape of the above, and a method of patterning a photosensitive material by a photolithography method.

It is also effective to stabilize the characteristics of the field-effect transistor constituting the display element by performing a heat treatment as a post-process after forming the interlayer insulating film 43.

The method for producing the organic EL layer 352 and the cathode 45 is not particularly limited and may be appropriately selected depending on the intended purpose. The solution process and the like can be mentioned.

This makes it possible to manufacture so-called "bottom emission" organic EL display elements 150 and 150A that extract light emission from the substrate 321 side. In this case, the substrate 321 and the gate insulating layer 351 and the second drain electrode (anode) 38 are required to be transparent.

The organic EL display element 150B shown in FIG. 22A is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a bottom contact / bottom gate type field effect transistor.

The organic EL display element 150C shown in FIG. 22B is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a top contact / bottom gate type field effect transistor.

Unlike the organic EL display elements 150 and 150A, the organic EL display elements 150B and 150C include a first passivation layer 42a and a second passivation layer 42b in addition to the first passivation layer 41a and the second passivation layer 41b. Have. The first passivation layer 42a and the second passivation layer 42b can be formed by the materials, processes and the like described in the description of the field effect transistor according to the ninth embodiment.

The first passivation layer 42a and the second passivation layer 42b correspond to the first passivation layer 17a and the second passivation layer 17b of the field effect transistor 110 and the like. Further, as in the ninth embodiment, the arrangement of the first passivation layer 42a and the second passivation layer 42b in the passivation layer is not particularly limited and can be appropriately selected depending on the intended purpose. .. Further, the second passivation layer 42b may be arranged so as to cover the upper surface and the side surface of the first passivation layer 42a, or the first passivation layer may cover the upper surface and the side surface of the second passivation layer 42b. 42a may be arranged.

Although the configuration in which the organic EL element 350 is arranged next to the drive circuit 320 has been described in FIGS. 21 and 22, the organic EL element 350 may be arranged above the drive circuit 320. Also in this case, it is a so-called "bottom emission" that extracts light emission from the substrate 321 side, and the drive circuit 320 is required to be transparent. The source electrode, drain electrode, and anode are transparent with conductivity such as _{ITO, In 2} O ₃ , SnO ₂ , ZnO with Ga added, ZnO with Al added, SnO _{2 with Sb added, and the like.} It is preferable to use a suitable oxide.

<12th Embodiment>
In the twelfth embodiment, an example of an image display device and a system using the field effect transistor according to the first embodiment is shown. In the twelfth embodiment, the description of the same components as those in the above-described embodiment may be omitted.

FIG. 23 shows a schematic configuration of the television device 500 as a system according to the twelfth embodiment. The connection line in FIG. 23 shows a typical signal or information flow, and does not represent all the connection relationships of each block.

The television device 500 according to the twelfth embodiment includes a main control device 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541. , Hard disk device 542, optical disk device 543, IR receiver 551, communication control device 552, and the like.

The main control device 501 controls the entire television device 500, and is composed of a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code that can be deciphered by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

The tuner 503 selects the broadcast of a preset channel from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

The TS decoder 506 TS-decodes the output signal of the demodulation circuit 505 and separates the audio information and the video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and outputs a signal including display information in response to an instruction from the operation device 532 and the IR receiver 551. Generate.

AV (Audio-Visual) data and the like are temporarily stored in the memory 531. The operation device 532 includes an input medium (not shown) such as a control panel, and notifies the main control device 501 of various information input by the user. The drive IF541 is a bidirectional communication interface, and conforms to ATAPI (AT Attachment Packet Interface) as an example.

The hard disk device 542 is composed of a hard disk, a drive device for driving the hard disk, and the like. The drive device records the data on the hard disk and reproduces the data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, a DVD) and reproduces the data recorded on the optical disk.

The IR receiver 551 receives an optical signal from the remote controller transmitter 620 and notifies the main control device 501. The communication control device 552 controls communication with the Internet. Various information can be obtained via the Internet.

The image display device 524 has a display device 700 and a display control device 780, as shown in FIG. 24 as an example. As shown in FIG. 25 as an example, the display 700 has a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

Further, as shown in FIG. 26 as an example, the display 710 has n scanning lines (X0, X1, X2, X3, ..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction It has m current supply lines (Y0i, Y1i, Y2i, Y3i, ..., Ym-1i) arranged at equal intervals along the line. Then, the display element 702 can be specified by the scanning line and the data line.

As shown in FIG. 27 as an example, each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

As shown in FIG. 28 as an example, the organic EL element 750 has an organic EL thin film layer 740, a cathode 712, and an anode 714.

The organic EL element 750 can be arranged next to the field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same substrate. However, the present invention is not limited to this, and for example, the organic EL element 750 may be arranged on the field effect transistor. In this case, since transparency is required for the gate electrode, ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, and Ga-added ZnO and Al were added to the gate electrode. A transparent oxide having conductivity such as _{SnO 2} to which ZnO and Sb are added is used.

In the organic EL element 750, Al is used for the cathode 712. In addition, Mg-Ag alloy, Al-Li alloy, ITO and the like may be used. ITO is used for the anode 714. In addition, _{conductive oxides such as In 2} O ₃ , SnO ₂ , and ZnO, Ag—Nd alloy, and the like may be used.

The organic EL thin film layer 740 has an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. Then, the cathode 712 is connected to the electron transport layer 742, and the anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

Further, as shown in FIG. 27, the drive circuit 720 has two field effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to one terminal of the capacitor 830.

The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

Therefore, when the field-effect transistor 810 is turned on, the organic EL element 750 is driven by the field-effect transistor 820.

The display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG. 29 as an example.

The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line drive circuit 784 individually applies a voltage to n scanning lines in response to an instruction from the image data processing circuit 782. The data line drive circuit 786 individually applies a voltage to m data lines in response to an instruction from the image data processing circuit 782.

As is clear from the above description, in the television device 500 according to the present embodiment, the image data creation device is configured by the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525. ing.

Further, in the above, the case where the optical control element is an organic EL element has been described, but the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoresis element, or an electrowetting element may be used.

For example, when the optical control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 30, the current supply line in the display element 703 becomes unnecessary.

Further, in this case, as shown in FIG. 31 as an example, the drive circuit 730 is composed of only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. 27. Can be done. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Reference numerals 762 and 772 in FIG. 31 are counter electrodes (common electrodes) of the capacitor 760 and the liquid crystal element 770, respectively.

Further, in the above embodiment, the case where the system is a television device has been described, but the present invention is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, it may be a computer system in which a computer (including a personal computer) and an image display device 524 are connected.

In addition, an image display device 524 is used as a display means in mobile information devices such as mobile phones, portable music playback devices, portable video playback devices, electronic books, PDAs (Personal Digital Assistants), and imaging devices such as still cameras and video cameras. Can be used. Further, the image display device 524 can be used as a display means for displaying various information in a mobile system such as a car, an aircraft, a train, or a ship. Further, the image display device 524 can be used as a display means for displaying various information in the measuring device, the analyzer, the medical device, and the advertising medium.

[Example 1]
In Example 1, the bottom gate / bottom contact type field effect transistor shown in FIG. 1 was manufactured.

(Formation of gate electrode)
First, the gate electrode 12 was formed on the substrate 11. Specifically, a Mo film as a conductive film was formed on a glass substrate 11 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 12 was formed by prebaking, exposure with an exposure apparatus, and development. Further, RIE (Reactive Ion Etching) was used to remove the Mo film in the region where the resist pattern was not formed. After that, the gate electrode 12 was formed by removing the resist pattern as well.

(Formation of gate insulating layer)
Next, the gate insulating layer 13 was formed. First, a coating liquid for forming a gate insulating layer was prepared. Specifically, in 1.2 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, the coating liquid for forming the gate insulating layer was dropped onto the substrate 11 and the gate electrode 12, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the gate insulating layer 13 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then the stripping solution (Tokyo Oka stripping solution 104). The gate insulating layer 13 was formed by immersing it in the water for 2 minutes to remove the resist pattern. By removing a part of the strontium lanthanum zirconium oxide in this step, a part of the gate electrode 12 was exposed so that a voltage could be applied to the gate electrode 12.

(Formation of source electrode and drain electrode)
Next, the source electrode 14 and the drain electrode 15 were formed. Specifically, a Mo film as a conductive film is formed on the gate insulating layer 13 by DC sputtering so that the average film thickness is about 100 nm, and then a photoresist is applied on the Mo film and prebaked. A resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 formed by exposure and development by the exposure apparatus was formed. Furthermore, the Mo film in the region where the resist pattern was not formed was removed by RIE. After that, the resist pattern was also removed to form the source electrode 14 and the drain electrode 15 made of the Mo film.

(Formation of active layer)
Next, the active layer 16 was formed. Specifically, a Mg—In oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Mg-In oxide film, and a resist pattern similar to the pattern of the active layer 16 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mg-In oxide film in the region where the resist pattern was not formed was removed by RIE. After that, the active layer 16 was formed by removing the resist pattern as well. As a result, the active layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

(Formation of passivation layer)
Next, the passivation layer 17 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 17 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 17 was formed by removing the resist pattern as well.

From the above, the bottom gate / bottom contact type field effect transistor was completed.

[Example 2]
In "(Formation of Gate Insulating Layer)" of Example 1, a field-effect transistor is provided in exactly the same manner as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide is an aqueous solution having a oxalic acid concentration of 5%. Made.

[Example 3]
In "(Formation of Gate Insulating Layer)" of Example 1, a field effect transistor was produced by the same method as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a nitric acid concentration of 20%. did.

[Example 4]
In "(Formation of Gate Insulating Layer)" of Example 1, a field-effect transistor was produced by the same method as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a phosphoric acid concentration of 50%. did.

[Example 5]
In "(Formation of Gate Insulating Layer)" of Example 1, the electric field was subjected to the same method as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was 5% acetic acid and the immersion time in the etching solution was 6 minutes. An effect transistor was manufactured.

[Example 6]
In "(Formation of Gate Insulating Layer)" of Example 1, a field effect transistor was produced by the same method as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was 10% sulfuric acid.

[Example 7]
In "(Formation of Gate Insulating Layer)" of Example 1, the method is exactly the same as that of Example 1 except that the etching solution of strontium lanthanum zirconium oxide is a mixed aqueous solution of 20% nitric acid, 60% phosphoric acid, and 20% water. A field effect transistor was manufactured.

[Example 8]
In "(Formation of Gate Insulating Layer)" of Example 1, the etching solution of strontium lanthanum zirconium oxide was the same as that of Example 1 except that the etching solution was a mixed aqueous solution of 5% nitric acid, 80% phosphoric acid, 10% acetic acid, and 5% water. A field effect transistor was manufactured in exactly the same way.

[Example 9]
In "(Formation of Gate Insulating Layer)" of Example 1, a field effect type is used in exactly the same manner as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide is an aqueous solution having a concentration of hydrogen peroxide solution of 5%. A transistor was manufactured.

[Example 10]
In Example 10, the top-gate self-aligned field-effect transistor shown in FIG. 5 was produced.

(Formation of active layer)
First, the active layer 122 was formed on the substrate 121. _{Specifically, an Mg—In oxide (In 2} MgO ₄ ) film was formed on a glass substrate 121 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Mg-In oxide film, and a resist pattern similar to the pattern of the active layer 122 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mg-In oxide film in the region where the resist pattern was not formed was removed by RIE. After that, the resist pattern was also removed to form the active layer 122.

(Formation of gate insulating layer and gate electrode)
Next, the gate insulating layer 123 was formed. The same coating liquid for forming a gate insulating layer as in Example 1 was dropped onto the substrate 121 and the active layer 122, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was.

Next, a Mo / Al / Mo laminated film as a conductive film was formed by DC sputtering so that the average film thickness was about 300 nm (50 nm / 200 nm / 50 nm). After that, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 124 was formed by prebaking, exposure with an exposure apparatus, and development. Next, by immersing in a mixed aqueous solution of 5% nitric acid, 80% phosphoric acid, 10% acetic acid, and 5% water for 30 seconds, the Mo / Al / Mo laminated film in the region where the resist pattern was not formed and the strontium lanthanum zirconium. The oxide was removed. After that, the gate insulating layer 123 and the gate electrode 124 were formed by removing the resist pattern as well.

Next, the interlayer insulating film 127 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film, and a resist pattern similar to the pattern of the interlayer insulating film 127 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the resist pattern was also removed to form the interlayer insulating film 127.

(Formation of source electrode and drain electrode)
Next, the source electrode 125 and the drain electrode 126 were formed. Specifically, a Mo / Al / Mo laminated film as a conductive film is formed on the interlayer insulating film 127 by DC sputtering so that the average film thickness is about 300 nm (50 nm / 200 nm / 50 nm), and then a film is formed. A photoresist was applied, and a resist pattern similar to the pattern of the source electrode 125 and the drain electrode 126 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the Mo / Al / Mo laminated film in the region where the resist pattern was not formed was removed by RIE. After that, the resist pattern was also removed to form the source electrode 125 and the drain electrode 126 made of the Mo / Al / Mo laminated film.

(Formation of passivation layer)
Next, the passivation layer 128 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 128 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 128 was formed by removing the resist pattern as well.

As described above, the top gate self-aligned field effect transistor 120 has been completed.

(Transistor characteristic evaluation)
The transistor characteristics of the field-effect transistor produced in Examples 1 to 10 were evaluated. The transistor characteristics are the voltage between the gate electrode 12 and the source electrode 14 (Vgs) and the current between the source electrode 14 and the drain electrode 15 (Ids) when the voltage between the source electrode 14 and the drain electrode 15 (Vds) = + 10V. The relationship (Vgs-Ids) was measured.

Further, the field effect mobility in the saturation region was calculated from the evaluation result of the transistor characteristics (Vgs-Ids). In addition, the S value was calculated as an index of the sharpness of the rise of Ids with respect to the application of Vgs. Further, the ratio (on / off ratio) of Ids in the on state (for example, Vgs = + 10V) and the off state (for example, Vgs = −10V) of the transistor was calculated. Further, the threshold voltage (Vth) was calculated as the rising voltage value of Ids with respect to the application of Vgs.

As a result of the transistor characteristics, high mobility, high on / off ratio, low S value, and Vth near 0V are expressed as excellent transistor characteristics. Specifically, mobility ^{3 cm} 2 / Vs or more, on / off ratio of 1.0 × 10 ⁸ or more, excellent transistor characteristics that S value is 0.7 or less, Vth is in the range of ± 5V It is expressed as.

At the same time, the capacitance of the gate insulating layer was measured and the relative permittivity was calculated. When the relative permittivity of the gate insulating layer is higher than 6, it is expressed as low power consumption.

Table 1 shows the evaluation results of the transistor characteristics of the field-effect transistor manufactured in Examples 1 to 10. It can be seen that all the field effect transistors manufactured in Examples 1 to 10 show excellent transistor characteristics. Further, the relative permittivity of the gate insulating layer was about 13 in all of Examples 1 to 10, and it was a field effect transistor having low power consumption.

From the above, it was found that a high-performance field-effect transistor can be manufactured by a low-cost process in which the first oxide is used as the gate insulating layer and the first oxide is patterned by wet etching.

［実施例１１］
実施例１１では、図１に示すボトムゲート／ボトムコンタクト型の電界効果型トランジスタを作製した。

[Example 11]
In Example 11, the bottom gate / bottom contact type field effect transistor shown in FIG. 1 was manufactured.

(Formation of gate electrode)
First, the gate electrode 12 was formed on the glass substrate 11 in the same manner as in Example 1.

(Formation of gate insulating layer)
Next, the gate insulating layer 13 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film, and a resist pattern similar to the pattern of the gate insulating layer 13 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the gate insulating layer 13 was formed by removing the resist pattern as well.

(Formation of source electrode and drain electrode)
Next, the source electrode 14 and the drain electrode 15 were formed in the same manner as in Example 1.

(Formation of active layer)
Next, the active layer 16 was formed in the same manner as in Example 1.

(Formation of passivation layer)
Next, the passivation layer 17 was formed. First, a coating liquid for forming a passivation layer was prepared. Specifically, in 1.2 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a passivation layer.

Next, the coating liquid for forming the passivation layer was dropped onto the substrate 11, the gate electrode 12, the gate insulating layer 13, the source electrode 14, the drain electrode 15, and the active layer 16 and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the passivation layer 17 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then put into a stripping solution (Tokyo Oka stripping solution 104). The passivation layer 17 was formed by immersing for 2 minutes and removing the resist pattern. By removing a part of the strontium lanthanum zirconium oxide in this step, a part of the gate electrode 12, the source electrode 14, and the drain electrode 15 were exposed, and a voltage could be applied to each electrode.

[Example 12]
In Example 11 “(Formation of Passivation Layer)”, a field effect transistor was produced by the same method as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a oxalic acid concentration of 5%. ..

[Example 13]
In Example 11 “(Formation of Passivation Layer)”, a field effect transistor was produced by the same method as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a nitric acid concentration of 20%.

[Example 14]
In Example 11 “(Formation of Passivation Layer)”, a field effect transistor was produced by the same method as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a phosphoric acid concentration of 50%.

[Example 15]
In Example 11 “(Formation of Passivation Layer)”, the field effect type is exactly the same as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide is 5% acetic acid and the immersion time in the etching solution is 6 minutes. A transistor was manufactured.

[Example 16]
In Example 11 “(Formation of Passivation Layer)”, a field effect transistor was produced by the same method as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was 10% sulfuric acid.

[Example 17]
In Example 11 “(Formation of Passivation Layer)”, the field effect is exactly the same as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide is a mixed aqueous solution of 20% nitric acid, 60% phosphoric acid, and 20% water. A type transistor was manufactured.

[Example 18]
In Example 11 “(Formation of Passivation Layer)”, the etching solution of strontium lanthanum zirconium oxide is exactly the same as in Example 11 except that it is a mixed aqueous solution of 5% nitric acid, 80% phosphoric acid, 10% acetic acid, and 5% water. An electric field effect transistor was manufactured by the method.

[Example 19]
In Example 11 “(Formation of Passivation Layer)”, the field effect transistor was prepared in exactly the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a concentration of hydrogen peroxide solution of 5%. Made.

(Transistor characteristic evaluation)
For the field effect transistors manufactured in Examples 11 to 19, mobility, on / off ratio, S value, and threshold voltage (Vth) were calculated in the same manner as in Examples 1 to 10. Further, the field effect transistors manufactured in Examples 11 to 19 were subjected to a BTS (Bias Temperature Stress) test for 100 hours in the atmosphere (temperature 50 ° C., relative humidity 50%).

The stress conditions were the following four conditions.
(1) Vgs = + 10V and Vds = 0V
(2) Vgs = + 10V and Vds = + 10V
(3) Vgs = -10V and Vds = 0V
(4) Vgs = -10V and Vds = + 10V
Every time the BTS test elapsed for a certain period of time, the relationship between Vgs and Ids (Vgs-Ids) was measured when Vds = + 10V, and the amount of change in the threshold voltage (ΔVth) in a stress time of 100 hours was evaluated. When the amount of change in the threshold voltage (ΔVth) in a stress time of 100 hours is 3 V or less, it is expressed as high reliability.

Table 2 shows the evaluation results of the transistor characteristics of the field-effect transistor manufactured in Examples 11 to 19. It can be seen that all the field effect transistors manufactured in Examples 11 to 19 show excellent transistor characteristics. Further, it can be seen that the change amount (ΔVth) of the threshold voltage is 1 V or less in all the results, indicating high reliability.

From the above, it was found that a high-performance field-effect transistor can be manufactured by a low-cost process in which the first oxide is used as the passivation layer and the first oxide is patterned by wet etching.

［実施例２０］
実施例２０では、図６に示す有機ＥＬ表示素子２００を作製した。まず、基板２１上に第１のゲート電極２２及び第２のゲート電極３２を形成した。具体的には、無アルカリガラスよりなる基板２１上に、ＤＣスパッタ法によりＭｏ膜を厚さが約１００ｎｍとなるよう成膜した。この後、フォトレジストを塗布し、プリベーク、露光装置による露光、現像により、形成されるパターンと同様のレジストパターンを形成した。更に、ＲＩＥにより、レジストパターンの形成されていない領域のＭｏ膜を除去し、この後、レジストパターンも除去することにより、第１のゲート電極２２及び第２のゲート電極３２を形成した。

[Example 20]
In Example 20, the organic EL display element 200 shown in FIG. 6 was manufactured. First, the first gate electrode 22 and the second gate electrode 32 were formed on the substrate 21. Specifically, a Mo film was formed on a substrate 21 made of non-alkali glass by a DC sputtering method so as to have a thickness of about 100 nm. After that, a photoresist was applied, and a resist pattern similar to the pattern formed was formed by prebaking, exposure with an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the first gate electrode 22 and the second gate electrode 32.

Next, the gate insulating layer 23 was formed on the substrate 21, the first gate electrode 22, and the second gate electrode 32. First, 1 L of a coating liquid for forming a gate insulating layer having the same composition as that of Example 1 was prepared.

Next, a coating liquid for forming a gate insulating layer was applied onto the substrate 21, the first gate electrode 22, and the second gate electrode 32 by the slit coating method. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was.

After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the gate insulating layer 23 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then put into a stripping solution (Tokyo-modified stripping solution 104). By immersing for 2 minutes and removing the resist pattern, a gate insulating layer 23 having a through hole was formed on the second gate electrode 32.

Next, the first source electrode 24, the second source electrode 34, the first drain electrode 25, and the second drain electrode 35 were formed. Specifically, an ITO film as a transparent conductive film was formed on the gate insulating layer 23 by a DC sputtering method so that the film thickness was about 100 nm. After that, a photoresist was applied onto the ITO film, and a resist pattern similar to the pattern formed by prebaking, exposure with an exposure apparatus, and development was formed.

Further, the ITO film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed, so that the first source electrode 24, the second source electrode 34, and the second source electrode 34 made of the ITO film are formed. The drain electrode 25 of 1 and the second drain electrode 35 were formed. As a result, the first drain electrode 25 and the second gate electrode 32 are connected to each other via a through hole formed in the gate insulating layer 23.

Next, the first active layer 26 and the second active layer 36 were formed. Specifically, an Mg-In-based oxide film is formed to have a film thickness of about 100 nm by a DC sputtering method, and then a photoresist is applied onto the Mg-In-based oxide film. A resist pattern similar to the pattern formed was formed by prebaking, exposure by an exposure apparatus, and development. Further, the Mg-In oxide film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed to remove the first active layer 26 and the second active layer 36. Formed.

As a result, the first active layer 26 is formed between the second source electrode 34 and the second drain electrode 35 so that a channel is formed between the first source electrode 24 and the first drain electrode 25. A second active layer 36 was formed so that channels were formed between them.

Next, the first passivation layer 27 and the second passivation layer 37 were formed. First, a coating liquid for forming a passivation layer was prepared. Specifically, in 1.2 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a passivation layer.

Next, the coating liquid for forming the passivation layer is applied to the substrate 21, the first gate electrode 22, the second gate electrode 32, the gate insulating layer 23, the first source electrode 24, the first drain electrode 25, and the second. It was dropped onto the source electrode 34, the second drain electrode 35, the first active layer 26, and the second active layer 36, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) is applied, and a resist pattern similar to the pattern of the first passivation layer 27 and the second passivation layer 37 formed by prebaking, exposure by an exposure apparatus, and development is performed. Was formed.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then put into a stripping solution (Tokyo-modified stripping solution 104). The first passivation layer 27 and the second passivation layer 37 were formed by immersing for 2 minutes and removing the resist pattern. Through the above steps, a drive circuit 210 having a two-transistor, one-capacitor structure was manufactured.

Next, an interlayer insulating film 220 (flattening film) was formed on the drive circuit 210. Specifically, a positive photosensitive organic material (Sumiresin Excel CRC series, manufactured by Sumitomo Bakelite Co., Ltd.) was applied by spin coating, and a desired pattern was obtained by prebaking, exposure with an exposure device, and development. Then, by post-baking at 320 ° C. for 30 minutes, an interlayer insulating film 220 having a through hole 220x was formed on the second drain electrode 35. The average film thickness of the interlayer insulating film 220 formed in this way was about 3 μm.

Next, a lower electrode 231 to be a pixel electrode was formed. Specifically, the Ag-Pd-Cu thin film and the ITO thin film were sequentially formed by DC sputtering so that the average film thickness of each was 100 nm. After that, a photoresist was applied onto the Ag-Pd-Cu thin film and the ITO thin film, and a desired pattern was obtained by prebaking, exposure with an exposure apparatus, and development. Further, the ITO thin film and the Ag-Pd-Cu thin film in the region where the resist pattern was not formed were sequentially removed by RIE. After that, the lower electrode 231 was formed by removing the resist pattern as well.

Next, the partition wall 240 was formed. Specifically, a positive photosensitive polyimide resin (DL-1000, manufactured by Toray Industries, Inc.) was applied by spin coating, and a desired pattern was obtained by prebaking, exposure with an exposure device, and development. Then, the partition wall 240 was formed by post-baking at 230 ° C. for 30 minutes.

Next, using a polymer organic light emitting material, an organic EL layer 232 was formed on the lower electrode 231 by an inkjet device.

Next, the upper electrode 233 was formed. Specifically, the upper electrode 233 was formed on the organic EL layer 232 and the partition wall 240 by vacuum-depositing MgAg.

Next, the sealing layer 250 was formed. Specifically, the sealing layer 250 was formed on the upper electrode 233 by forming a SiN film with an average film thickness of about 2 μm by plasma CVD.

Next, it was bonded to the facing insulating substrate 270. Specifically, an adhesive layer 260 was formed on the sealing layer 250, and a counter-insulating substrate 270 made of a non-alkali glass substrate was bonded.

The organic EL display element 200 produced by these steps exhibited low power consumption and high reliability characteristics.

From the above, it was found that a high-performance organic EL display element can be manufactured by a low-cost process in which the first oxide is used as the gate insulating layer and the passivation layer and the first oxide is patterned by wet etching. ..

[Example 21]
In Example 21, the organic EL display element 200A shown in FIG. 7 was manufactured. Specifically, it is organic in exactly the same manner as in Example 21 except that the first passivation layer 27 and the second passivation layer 37 (FIG. 6) of Example 21 are changed to the integrated passivation layer 27A. An EL display element 200A was manufactured.

The produced organic EL display element 200A exhibited low power consumption and high reliability characteristics.

From the above, it was found that a high-performance organic EL display element can be manufactured by a low-cost process in which the first oxide is used as the gate insulating layer and the passivation layer and the first oxide is patterned by wet etching. ..

[Example 22]
In Example 22, the field effect transistor 50 (MOS-FET) shown in FIG. 8 was manufactured. First, a coating liquid for forming a gate insulating layer for forming a gate insulating layer 53 on a substrate 51 (8 inches) made of p-type Si was prepared. Specifically, in 4.0 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, the coating liquid for forming the gate insulating layer was dropped onto the substrate 51 and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (film thickness 10 nm). It was.

Further, after forming a polycrystalline silicon film by the CVD method, the polycrystalline silicon film was patterned by a photolithography step to obtain a gate electrode 52. Then, using the gate electrode 52 as a mask, the gate insulating layer is immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the gate electrode 52 is not formed. 53 was formed.

Next, after SION was deposited by the CVD method, the entire surface was dry-etched to form the gate side wall insulating film 54. Next, using the gate electrode 52 and the gate sidewall insulating film 54 as a self-aligning mask, phosphorus ions were implanted into the substrate 51, and the source region 55 and the drain region 56 were formed by ion diffusion.

_{Next, SiO 2} was deposited by the CVD method, and an interlayer insulating film 57 having through holes opened was formed by a photolithography step. Finally, an Al layer was deposited by a sputtering method, through holes were embedded, and patterning was performed by a photolithography step to form a source electrode 58 and a drain electrode 59.

Finally, the passivation layer 111 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 111 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 111 was formed by removing the resist pattern as well. Through the above steps, the field effect transistor 50 was manufactured.

The field effect transistor 50 produced in this example showed excellent transistor characteristics. Further, the relative permittivity of the gate insulating layer 53 was 13.3, which was a low power consumption field effect transistor.

From the above, it was found that a high-performance field-effect transistor can be manufactured by a low-cost process in which the first oxide is used as the gate insulating layer and the first oxide is patterned by wet etching.

[Example 23]
In Example 23, the volatile semiconductor memory element 60 shown in FIG. 9 was manufactured. First, a gate electrode 62 and a second capacitor electrode 69 were formed on a substrate 61 made of non-alkali glass. Specifically, a Mo film was formed on the substrate 61 by a DC sputtering method so that the thickness was about 100 nm. After that, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 62 and the second capacitor electrode 69 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the Mo film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the gate electrode 62 and the second capacitor electrode 69.

Next, the gate insulating layer 63 was formed. First, a coating liquid for forming a gate insulating layer was prepared. Specifically, in 1.2 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, the coating liquid for forming the gate insulating layer was dropped onto the substrate 61, the gate electrode 62, and the second capacitor electrode 69, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the gate insulating layer 63 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then it was added to the stripping solution (Tokyo Oka stripping solution 104). The gate insulating layer 63 was formed by immersing for 2 minutes to remove the resist pattern.

Next, the capacitor dielectric layer 68 was formed. The above-mentioned coating liquid for forming a gate insulating layer was dropped onto the substrate 61, the gate electrode 62, the second capacitor electrode 69, and the gate insulating layer 63, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 30 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the capacitor dielectric layer 68 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then it was added to the stripping solution (Tokyo Oka stripping solution 104). The capacitor dielectric layer 68 was formed by immersing for 2 minutes to remove the resist pattern.

Next, the source electrode 64 and the drain electrode 65 were formed. In this embodiment, the drain electrode 65 forms a capacitor together with the capacitor dielectric layer 68 and the second capacitor electrode 69.

Specifically, an ITO film, which is a transparent conductive film, was formed on the gate insulating layer 63 and the capacitor dielectric layer 68 by a DC sputtering method so that the film thickness was about 100 nm. After that, a photoresist was applied onto the ITO film, and a resist pattern similar to the pattern of the source electrode 64 and the drain electrode 65 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the ITO film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the source electrode 64 and the drain electrode 65 made of the ITO film.

Next, the active layer 66 was formed. Specifically, an Mg-In oxide film was formed to have a film thickness of about 100 nm by a DC sputtering method. After that, a photoresist was applied onto the Mg-In oxide film, and a resist pattern similar to the pattern of the active layer 66 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mg-In oxide film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the active layer 66. As a result, the active layer 66 was formed so that a channel was formed between the source electrode 64 and the drain electrode 65.

Finally, the passivation layer 112 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 112 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 112 was formed by removing the resist pattern as well. By these steps, the volatile semiconductor memory element 60 was manufactured.

The volatile semiconductor memory element 60 produced by these steps exhibited low power consumption characteristics.

From the above, it is possible to manufacture a high-performance volatile semiconductor memory device by a low-cost process in which the first oxide is used as the gate insulating layer and the capacitor dielectric layer and the first oxide is patterned by wet etching. all right.

[Example 24]
In Example 24, the volatile semiconductor memory element 70 shown in FIG. 10 was manufactured. First, a coating liquid for forming a gate insulating layer for forming the gate insulating layer 73 was prepared on a substrate 71 (8 inches) made of p-type Si. Specifically, in 4.0 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, the coating liquid for forming the gate insulating layer was dropped onto the substrate 71 and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (film thickness 10 nm). It was.

Next, after forming a polycrystalline silicon film by the CVD method, the polycrystalline silicon film was patterned by a photolithography step to obtain a gate electrode 72. Then, using the gate electrode 72 as a mask, the gate insulating layer is immersed in 0.1 mol / L hydrochloric acid (wako 083-0111) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the gate electrode 72 is not formed. 73 was formed.

Next, after depositing SION by the CVD method, the entire surface was dry-etched to form the gate side wall insulating film 74. Next, using the gate electrode 72 and the gate sidewall insulating film 74 as a self-aligning mask, phosphorus ions were implanted into the substrate 71 and the ions were diffused to form the source region 75 and the drain region 76.

_{Next, SiO 2} was deposited by the CVD method, and the first interlayer insulating film 77 having through holes opened was formed by the photolithography step. A polycrystalline silicon film was deposited by a CVD method, a through hole was embedded, and a bit wire electrode 78 was formed by a photolithography process.

_{Next, SiO 2} was deposited by the CVD method, and a second interlayer insulating film 79 having a through hole opened on the drain region 76 was formed by a photolithography step. Next, a polycrystalline silicon film was formed by a CVD method, and a second capacitor electrode 80 was formed by a photolithography step.

Next, the capacitor dielectric layer 81 was formed. The coating liquid for forming the gate insulating layer was dropped onto the second interlayer insulating film 79 and the second capacitor electrode 80, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 30 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the capacitor dielectric layer 81 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then it was added to the stripping solution (Tokyo Oka stripping solution 104). The capacitor dielectric layer 81 was formed by immersing for 2 minutes and removing the resist pattern.

Next, a polycrystalline silicon film was formed by a CVD method, and a first capacitor electrode 82 was formed by a photolithography step. Finally, the passivation layer 113 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 113 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 113 was formed by removing the resist pattern as well. By these steps, the volatile semiconductor memory element 70 was manufactured.

The volatile semiconductor memory element 70 produced by these steps exhibited low power consumption characteristics.

From the above, it is possible to manufacture a high-performance volatile semiconductor memory device by a low-cost process in which the first oxide is used as the gate insulating layer and the capacitor dielectric layer and the first oxide is patterned by wet etching. all right.

[Example 25]
In Example 25, the non-volatile semiconductor memory element 90 shown in FIG. 11 was manufactured. First, the gate electrode 92 was formed on the substrate 91 made of non-alkali glass. Specifically, a Mo film was formed on the substrate 91 by a DC sputtering method so as to have a thickness of about 30 nm. After that, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 92 formed by prebaking, exposure with an exposure apparatus, and development was formed. Furthermore, the Mo film in the region where the resist pattern was not formed was removed by RIE. After that, the gate electrode 92 was formed by removing the resist pattern as well.

Next, the first gate insulating layer 93 was formed. First, a coating liquid for forming a gate insulating layer was prepared. Specifically, in 1.2 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, the coating liquid for forming the gate insulating layer was dropped onto the substrate 91 and the gate electrode 92, and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (thickness 135 nm). It was. After that, a photoresist (Tokyo Oka TSMR8800-BE) was applied to form a resist pattern similar to the pattern of the first gate insulating layer 93 formed by prebaking, exposure with an exposure apparatus, and development.

Next, it was immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern was not formed, and then it was added to the stripping solution (Tokyo Oka stripping solution 104). The first gate insulating layer 93 was formed by immersing for 2 minutes to remove the resist pattern.

Next, the floating gate electrode 94 was formed. Specifically, a Mo film was formed on the first gate insulating layer 93 by a DC sputtering method so as to have a thickness of about 15 nm. After that, a photoresist was applied, and a resist pattern similar to the pattern of the floating gate electrode 94 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mo film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the floating gate electrode 94.

Next, the second gate insulating layer 95 was formed. _{Specifically, SiO 2} was formed on the first gate insulating layer 93 and the floating gate electrode 94 by a CVD method so as to have a thickness of 50 nm. After that, a photoresist was applied, and a resist pattern similar to the pattern of the second gate insulating layer 95 formed by prebaking, exposure with an exposure apparatus, and development was formed. _{Further, the SiO 2} film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the second gate insulating layer 95.

Next, the source electrode 96 and the drain electrode 97 were formed. Specifically, an ITO film, which is a transparent conductive film, was formed on the second gate insulating layer 95 by a DC sputtering method so that the film thickness was about 100 nm. After that, a photoresist was applied onto the ITO film, and a resist pattern similar to the patterns of the source electrode 96 and the drain electrode 97 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the ITO film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the source electrode 96 and the drain electrode 97 made of the ITO film.

Next, the active layer 98 was formed. Specifically, an Mg-In oxide film was formed to have a film thickness of about 100 nm by a DC sputtering method. After that, a photoresist was applied onto the Mg-In oxide film, and a resist pattern similar to the pattern of the active layer 98 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mg-In oxide film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed to form the active layer 98.

As a result, the active layer 98 was formed so that a channel was formed between the source electrode 96 and the drain electrode 97.

Finally, the passivation layer 114 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 114 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 114 was formed by removing the resist pattern as well. The non-volatile semiconductor memory element 90 was manufactured by the above steps.

The non-volatile semiconductor memory element 90 produced by these steps exhibited low power consumption characteristics.

From the above, it was found that a high-performance non-volatile semiconductor memory device can be manufactured by a low-cost process in which the first oxide is used as the first gate insulating layer and the first oxide is patterned by wet etching. It was.

[Example 26]
In Example 26, the non-volatile semiconductor memory element 100 shown in FIG. 12 was manufactured. _{First, a SiO 2} film finally to be the second gate insulating layer 104 is formed at 5 nm on the substrate 101 made of p-type Si by thermally oxidizing the surface, and then finally a floating gate electrode is formed by the CVD method. A polycrystalline silicon film of 105 was formed.

Next, a coating liquid for forming a gate insulating layer for forming the first gate insulating layer 102 was prepared. Specifically, in 4.0 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium toluene solution of 2-ethylhexanoate are added. (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 .09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, the coating liquid for forming the gate insulating layer was dropped onto the substrate 101 and spin-coated under predetermined conditions. Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, calcination was performed at 400 ° C. for 3 hours in an O 2} atmosphere to obtain an amorphous strontium lanthanum zirconium oxide (film thickness 10 nm). It was.

Next, after forming a polycrystalline silicon film by the CVD method, the polycrystalline silicon film was patterned by a photolithography step to obtain a gate electrode 103. Then, using the gate electrode 103 as a mask, it is immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the gate electrode 103 is not formed. The gate insulating layer 102 was formed. Further, the floating gate electrode 105 and the second gate insulating layer 104 (tunnel insulating layer) were formed by sequentially etching the _{polycrystalline silicon film and the SiO 2} film under the first gate insulating layer 102 by dry etching. ..

Next, after SION was deposited by the CVD method, the entire surface was dry-etched to form the gate side wall insulating film 106. Next, using the gate electrode 103 and the gate sidewall insulating film 106 as a self-aligning mask, phosphorus ions were implanted into the substrate 101 and the ions were diffused to form the source region 107 and the drain region 108.

Finally, the passivation layer 115 was formed. Specifically, a SiON film was formed by plasma CVD so that the average film thickness was 300 nm. After that, a photoresist was applied onto the SiON film to form a resist pattern similar to the pattern of the passivation layer 115 formed by prebaking, exposure with an exposure apparatus, and development. Further, the SiON film in the region where the resist pattern was not formed was removed by RIE. After that, the passivation layer 115 was formed by removing the resist pattern as well. Through the above steps, the non-volatile semiconductor memory element 100 was manufactured.

The non-volatile semiconductor memory element 100 produced by these steps exhibited low power consumption characteristics.

From the above, it was found that a high-performance non-volatile semiconductor memory device can be manufactured by a low-cost process in which the first oxide is used as the first gate insulating layer and the first oxide is patterned by wet etching. It was.

[Example 27]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) 0.14 mL and calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content) are added to 1 mL of toluene. 3% -8%, Alfa36657, manufactured by Alfa Aesar) was mixed with 0.37 mL to obtain a coating solution for forming a first passivation layer. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-
To 1.2 mL of cyclohexylbenzene, 2.17 mL of 2-ethylhexanoate lanthanum toluene solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and 2-ethylhexanoate strontium toluene solution (Sr content 2%). , Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.63 mL was mixed to obtain a coating solution for forming a second passivation layer. The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 3.

次に、図１６（ｂ）のような、ボトムコンタクト／トップゲート型の電界効果型トランジスタを作製した。

Next, a bottom contact / top gate type field effect transistor as shown in FIG. 16 (b) was manufactured.

-Formation of source and drain electrodes-
First, a source electrode 14 and a drain electrode 15 were formed on a substrate 11 made of glass. Specifically, an Al (aluminum) alloy film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Al alloy film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the Al alloy film in the region where the resist pattern was not formed was removed by etching. After that, the resist pattern was also removed to form the source electrode 14 and the drain electrode 15 made of an Al alloy film.

-Formation of active layer-
Next, the active layer 16 was formed. Specifically, a Mg—In oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Mg-In oxide film, and a resist pattern similar to the pattern of the active layer 16 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mg—In oxide film in the region where the resist pattern was not formed was removed by etching. After that, the active layer 16 was formed by removing the resist pattern as well. As a result, the active layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

-Formation of gate insulating layer-
Next, the gate insulating layer 13 was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16. _{Specifically, an Al 2} O ₃ film was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16 by RF sputtering so that the average film thickness was about 300 nm.

-Formation of gate electrode-
Next, the gate electrode 12 was formed on the gate insulating layer 13. Specifically, a Mo (molybdenum) film was formed on the gate insulating layer 13 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Mo film, and a resist pattern similar to the pattern of the gate electrode 12 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the Mo film in the region where the resist pattern was not formed was removed by etching. After that, the resist pattern was also removed to form the gate electrode 12 made of Mo film.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm in 5 seconds). The rotation was stopped so that Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, it was rotated at 3,000 rpm for 20 seconds, and the rotation was stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), and is formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in 0.36 wt% hydrochloric acid (Wako 083-01115) for 20 seconds, and the first oxide film in the region where the resist pattern was not formed was removed by etching. , A second passivation layer 17b was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in 2.5 wt% hydrofluoric acid for 15 seconds, and the film of the second oxide in the region where the resist pattern was not formed was removed by etching. Passivation layer 17a of 1 was formed.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 28]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) 0.13 mL and magnesium 2-ethylhexanoate toluene solution (Mg content 3%, Strem) in 1 mL of toluene. 12-1260, Strem Chemicals) 0.32 mL and 2-ethylhexanoic acid barium toluene solution (Ba content 8%, Wako 021-09471, Wako Chemicals Co., Ltd.) 0.40 mL are mixed and the first passivation. A coating solution for layer formation was obtained. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-
0.54 g of scandium (III) tris (2,2,6,6-tetramethyl-3,5-hebutandionate) hydrate (SIGMA-ALDRICH 517607, manufactured by SIGMA-ALDRICH) in 1.2 mL of cyclohexylbenzene. , Magnesium 2-ethylhexanoate toluene solution (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) 0.12 mL, and calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content 3% -8%). , Alfa36657, manufactured by Alfa Aesar) 0.08 mL was mixed to obtain a coating solution for forming a second passivation layer. The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 3.

Next, a bottom contact / top gate type field effect transistor was manufactured in the same manner as in Example 27. However, the stacking order of the first passivation layer 17a and the second passivation layer 17b was reversed from that of Example 27.

-Formation of source and drain electrodes-
First, a source electrode 14 and a drain electrode 15 were formed on a substrate 11 made of glass. Specifically, an Al (aluminum) alloy film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Al alloy film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the Al alloy film in the region where the resist pattern was not formed was removed by etching. After that, the resist pattern was also removed to form the source electrode 14 and the drain electrode 15 made of an Al alloy film.

-Formation of active layer-
Next, the active layer 16 was formed. Specifically, a Mg—In oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Mg-In oxide film, and a resist pattern similar to the pattern of the active layer 16 formed by prebaking, exposure with an exposure apparatus, and development was formed. Further, the Mg—In oxide film in the region where the resist pattern was not formed was removed by etching. After that, the active layer 16 was formed by removing the resist pattern as well. As a result, the active layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

-Formation of gate insulating layer-
Next, the gate insulating layer 13 was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16. _{Specifically, an Al 2} O ₃ film was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16 by RF sputtering so that the average film thickness was about 300 nm.

-Formation of gate electrode-
Next, the gate electrode 12 was formed on the gate insulating layer 13. Specifically, a Mo (molybdenum) film was formed on the gate insulating layer 13 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist was applied onto the Mo film, and a resist pattern similar to the pattern of the gate electrode 12 formed by prebaking, exposure by an exposure apparatus, and development was formed. Further, the Mo film in the region where the resist pattern was not formed was removed by etching. After that, the resist pattern was also removed to form the gate electrode 12 made of Mo film.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 500 rpm for 5 seconds and then at 3,000 rpm. It was rotated for 20 seconds and stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the second passivation layer 170b and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds to reach 0 rpm in 5 seconds). Stopped the rotation). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the first passivation layer 170a (the first oxide film) and formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the first passivation layer 17a was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in a mixed solution of 19 wt% ammonium fluoride and 18 wt% ammonium hydrogen fluoride for 15 seconds, and the second part of the region where the resist pattern was not formed by etching was performed. The oxide film was removed to form the first passivation layer 17a.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in 5 wt% oxalic acid heated to 30 ° C. for 4 minutes, and the first oxide film in the region where the resist pattern was not formed was removed by etching to remove the first oxide film. Passivation layer 17b of 2 was formed.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 29]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and aluminum di (s-butoxide) acetoacetic ester chelate (Al content 8) .4%, Alfa89349, manufactured by Alfa Aesar) 0.13 mL and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 2.02 mL are mixed, and the first A coating liquid for forming a passivation layer was obtained. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-
1.2 mL of cyclohexylbenzene, 0.19 g of samarium acetylacetonate trihydrate (Strem 93-6226, manufactured by Strem Chemicals), and a toluene solution of gadrinium 2-ethylhexanoate (Gd content 25%, Strem 64-3500, Strem). 0.27 mL of (manufactured by Chemicals) and 0.49 mL of a toluene solution of barium 2-ethylhexanoate (Ba content 8%, Wako 022-09471, manufactured by Wako Chemicals Co., Ltd.) are mixed to form a coating solution for forming a second passivation layer. Got The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 3.

Next, a bottom contact / top gate type field effect transistor as shown in FIG. 16 (b) was manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm in 5 seconds). The rotation was stopped so that Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, it was rotated at 3,000 rpm for 20 seconds, and the rotation was stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), and is formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in a mixed solution of 57.9 wt% phosphoric acid and 21.1 wt% nitric acid for 30 seconds, and the first oxide in the region where the resist pattern was not formed by etching was performed. The film was removed to form a second passivation layer 17b.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in 4 wt% TMAH (tetramethylammonium hydroxide) for 1 minute, and the film of the second oxide in the region where the resist pattern was not formed was removed by etching. , The first passivation layer 17a was formed.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 30]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
To 1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyl disilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and (4,5,5-tetramethyl-1,4,4,5-tetramethyl-1, 0.08 g of 3,2-dioxaborolan-2-yl) benzene (Wako 325-59912, manufactured by Wako Chemical Co., Ltd.) and a toluene solution of magnesium 2-ethylhexanoate (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals). ) 0.37 mL was mixed to obtain a coating liquid for forming a first passivation layer. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-
To 1.2 mL of cyclohexylbenzene, 0.57 mL of a 2-ethylhexanoate neodymium 2-ethylhexanoic acid solution (Nd content 12%, Strem 60-2400, manufactured by Strem Chemicals) and europium 2-ethylhexanoate (Strem 93-6311). , Strem Chemicals) 0.28 g and 2-ethylhexanoate magnesium toluene solution (Mg content 3%, Strem 12-1260, Strem Chemicals) 0.12 mL are mixed to form a second passivation layer coating solution. Got The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 3.

Next, a bottom contact / top gate type field effect transistor was produced in the same manner as in Example 28 (the stacking order of the first passivation layer 17a and the second passivation layer 17b is opposite to that of Example 27).

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 500 rpm for 5 seconds and then at 3,000 rpm. It was rotated for 20 seconds and stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the second passivation layer 170b and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds to reach 0 rpm in 5 seconds). Stopped the rotation). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the first passivation layer 170a (the first oxide film) and formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the first passivation layer 17a was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in a mixed solution of 14 wt% ammonium fluoride and 12 wt% ammonium hydrogen fluoride for 15 seconds, and the second part of the region where the resist pattern was not formed by etching was performed. The oxide film was removed to form the first passivation layer 17a.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in 6 wt% hydrogen peroxide solution for 2 minutes, and the first oxide film in the region where the resist pattern was not formed was removed by etching, and the second passivation was performed. Layer 17b was formed.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 31]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
To 1 mL of toluene, 0.17 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and a solution of strontium 2-ethylhexanoate in toluene (Sr content 2%, Wako) 195-09561, manufactured by Wako Chemical Co., Ltd., 0.47 mL and 0.21 mL of 2-ethylhexanoate barium-toluene solution (Ba content 8%, Wako 022-09471, manufactured by Wako Chemical Co., Ltd.) were mixed and used as the first solution. A coating solution for forming a passivation layer was obtained. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-
0.16 g of scandium (III) tris (2,2,6,6-tetramethyl-3,5-hebutandionate) hydrate (SIGMA-ALDRICH 517607, manufactured by SIGMA-ALDRICH) in 1.2 mL of cyclohexylbenzene. , 2-Ethylhexanoic acid lanthanum toluene solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.46 mL and 2-ethylhexanoate calcium 2-ethylhexanoic acid solution (Ca content 3%- 8%, Alfa36657, manufactured by Alfa Aesar) 0.03 mL, 2-ethylhexanoate strontium toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.34 mL, 2-ethylhexanoic acid oxidation A zirconium mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) was mixed with 0.07 mL to obtain a coating solution for forming a second passivation layer. The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 4.

次に、図１６（ｂ）のような、ボトムコンタクト／トップゲート型の電界効果型トランジスタを作製した。ソース電極１４、ドレイン電極１５、活性層１６、ゲート絶縁層１３、及びゲート電極１２は、実施例２７と同様の方法で形成した。

Next, a bottom contact / top gate type field effect transistor as shown in FIG. 16 (b) was manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm in 5 seconds). The rotation was stopped so that Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, it was rotated at 3,000 rpm for 20 seconds, and the rotation was stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), and is formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in 0.36 wt% hydrochloric acid for 20 seconds, and the first oxide film in the region where the resist pattern was not formed was removed by etching to remove the first passivation layer. 17b was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in a mixed solution of 14 wt% ammonium fluoride and 3.2 wt% ammonium hydrogen fluoride for 1 minute, and by etching, the first portion of the region where the resist pattern was not formed. The film of the oxide of 2 was removed to form the first passivation layer 17a.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 32]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
1 mL of toluene, 0.15 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and a 2-ethylhexanoic acid solution of calcium 2-ethylhexanoate (Ca content). 3% -8%, Alfa36657, manufactured by Alfa Aesar) was mixed with 0.31 mL to obtain a coating solution for forming a first passivation layer. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-
Cyclohexylbenzene 1.2 mL, disprocium acetylacetonate trihydrate (Strem 66-2002, manufactured by Strem Chemicals) 0.13 g, and itterbium acetylacetonate trihydrate (Strem 70-2202, manufactured by Strem Chemicals) 0. 27 g, 0.12 mL of magnesium toluene 2-ethylhexanoate solution (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) and 2-ethylhexanoic acid solution of hafnium 2-ethylhexanoate (Gelest AKH332, manufactured by Gelest). The mixture was mixed with 0.10 mL to obtain a coating solution for forming a second passivation layer. The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 4.

Next, a bottom contact / top gate type field effect transistor as shown in FIG. 16 (b) was manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm in 5 seconds). The rotation was stopped so that Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, it was rotated at 3,000 rpm for 20 seconds, and the rotation was stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), and is formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in a mixed solution of 55 wt% phosphoric acid, 30 wt% acetic acid, and 5 wt% nitric acid for 30 seconds, and the first oxidation of the region where the resist pattern was not formed by etching. The film was removed to form a second passivation layer 17b.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in 6 wt% TMAH (tetramethylammonium hydroxide) for 1 minute, and the film of the second oxide in the region where the resist pattern was not formed was removed by etching. The first passivation layer 17a was formed.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 33]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
1 mL of toluene, 0.09 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and aluminum di (s-butoxide) acetoacetic ester chelate (Al content 8) .4%, Alfa89349, manufactured by Alfa Aesar) 0.18 mL and barium toluene 2-ethylhexanoate solution (Ba content 8%, Wako 021-09471, manufactured by Wako Chemical Co., Ltd.) 0.69 mL were mixed, and the first A coating liquid for forming a passivation layer was obtained. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-
1.2 mL of cyclohexylbenzene, 0.51 g of yttrium 2-ethylhexanoate (Strem 39-2400, manufactured by Strem Chemicals), and a toluene solution of magnesium 2-ethylhexanoate (Mg content 3%, manufactured by Strem 12-1260, manufactured by Strem Chemicals). ) 0.06 mL and 0.07 mL of a 2-ethylhexanoate hafnium 2-ethylhexanoate solution (Gelest AKH332, manufactured by Gelest) were mixed to obtain a coating liquid for forming a second passivation layer. The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 4.

Next, a bottom contact / top gate type field effect transistor was produced in the same manner as in Example 28 (the stacking order of the first passivation layer 17a and the second passivation layer 17b is opposite to that of Example 27).

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the gate insulating layer 13 and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 500 rpm for 5 seconds and then at 3,000 rpm. It was rotated for 20 seconds and stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the second passivation layer 170b and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds to reach 0 rpm in 5 seconds). Stopped the rotation). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the first passivation layer 170a (the first oxide film) and formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the first passivation layer 17a was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in 5 wt% hydrofluoric acid for 15 seconds, and the second oxide film in the region where the resist pattern was not formed was removed by etching to remove the first passivation layer 170a. A passivation layer 17a was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in a mixed solution of 80 wt% phosphoric acid, 10 wt% acetic acid, and 5 wt% nitric acid for 30 seconds, and the first oxidation of the region where the resist pattern was not formed by etching. The film was removed to form a second passivation layer 17b.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 34]
<Manufacturing of field effect transistor>
-Preparation of coating liquid for forming the first passivation layer-
1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Oka Kogyo Co., Ltd.) and aluminum di (s-butoxide) acetoacetic ester chelate (Al content 8) .4%, Alfa89349, manufactured by Alfa Aesar) 0.10 mL and (4,5,5-tetramethyl-1,3,2-dioxaborolan-2-yl) benzene (Wako 325-59912, Wako Co., Ltd.) 0.07 g of chemical), 0.09 mL of calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content 3% -8%, Alfa36657, manufactured by Alfa Aesar), and strontium 2-ethylhexanoate toluene solution (Sr). A coating solution for forming a first passivation layer was obtained by mixing with 0.19 mL of Wako 195-09561 (manufactured by Wako Chemical Co., Ltd.) having a content of 2%. The second oxide formed by the coating liquid for forming the first passivation layer has the composition shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-
Cyclohexylbenzene 1.2 mL, 2-ethylhexanoate lanthanum toluene solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL, 2-ethylhexanoate strontium toluene solution (Sr content 2%) , Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0.09 mL are mixed. Then, a coating solution for forming a second passivation layer was obtained. The first oxide formed by the coating liquid for forming the second passivation layer has the composition shown in Table 4.

Next, a bottom contact / top gate type field effect transistor as shown in FIG. 16 (b) was manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the coating liquid for forming the first passivation layer was dropped onto the gate insulating layer and the gate electrode 12, and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm in 5 seconds). I stopped the rotation so that Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the coating liquid for forming the second passivation layer was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, it was rotated at 3,000 rpm for 20 seconds, and the rotation was stopped so that it became 0 rpm in 5 seconds). Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air _{, firing was performed at 400 ° C. for 3 hours in an O 2} atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), and is formed by prebaking, exposure by an exposure apparatus, and development. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b was immersed in 0.36 wt% hydrochloric acid (wako083-01115 manufactured by Wako Pure Chemical Industries, Ltd.) for 20 seconds, and the first oxide film in the region where the resist pattern was not formed by etching was performed. Was removed to form a second passivation layer 17b.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a was immersed in a mixed solution of 14 wt% ammonium fluoride and 12 wt% ammonium hydrogen fluoride for 15 seconds, and the second part of the region where the resist pattern was not formed by etching was performed. The oxide film was removed to form the first passivation layer 17a.

-Mask removal-
Then, the resist pattern was also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.
<Transistor characteristic evaluation of field effect transistor>
The transistor characteristics of the field-effect transistor produced in Examples 27 to 34 were evaluated. The transistor characteristics of Examples 27 to 34 are the voltage between the gate electrode 12 and the source electrode 14 (Vgs) and the voltage between the drain electrode 15 and the source electrode 14 when the voltage between the drain electrode 15 and the source electrode 14 (Vds) = + 10V. The relationship with the current (Ids) (Vgs-Ids) was measured.

Further, the field effect mobility in the saturation region was calculated from the evaluation result of the transistor characteristics (Vgs-Ids). Further, the ratio (on / off ratio, on / off ratio) of the Ids of the transistor in the on state (for example, Vgs = + 10V) and the off state (for example, Vgs = −10V) was calculated. In addition, the S value was calculated as an index of the sharpness of the rise of Ids with respect to the application of Vgs. Further, the threshold voltage (Vth) was calculated as the rising voltage value of Ids with respect to the application of Vgs.

Table 5 shows the mobility, on / off ratio, S value, and Vth calculated from the transistor characteristics of the field-effect transistor manufactured in Examples 27 to 34. In the following, as a result of the transistor characteristics, excellent transistor characteristics are expressed in that the mobility is high, the on / off ratio is high, the S value is low, and Vth is around 0V. Specifically, mobility ^{3 cm} 2 / Vs or more, on / off ratio of 1.0 × 10 ⁸ or more, excellent transistor characteristics that S value is 0.7 or less, Vth is in the range of ± 5V It is expressed as.

From Table 5, the field-effect transistor produced in Examples 27 to 34 has high mobility, high on / off ratio, low S value, Vth is around 0V, and exhibits excellent transistor characteristics. Understand.

＜電界効果型トランジスタのトランジスタ信頼性評価＞
実施例２７〜３４で作製した電界効果型トランジスタに対し、大気中（温度５０℃、相対湿度５０％）でＢＴＳ試験を１００時間実施した。

<Transistor reliability evaluation of field effect transistor>
The field effect transistors manufactured in Examples 27 to 34 were subjected to a BTS test in the atmosphere (temperature 50 ° C., relative humidity 50%) for 100 hours.

The stress conditions were the following four conditions.
(1) Vgs = + 10V and Vds = 0V
(2) Vgs = + 10V and Vds = + 10V
(3) Vgs = -10V and Vds = 0V
(4) Vgs = -10V and Vds = + 10V
Further, every time the BTS test elapsed for a certain period of time, the relationship between Vgs and Ids (Vgs-Ids) was measured when Vds = + 10V.

In the field effect transistor produced in Example 34, the results of Vgs-Ids in the BTS test in which the stress conditions were Vgs = + 10V and Vds = 0V are shown in FIG. 32, and the field effect produced in Example 34. The amount of change (ΔVth) of the threshold voltage with respect to the stress time under the stress conditions Vgs = + 10V and Vds = 0V of the type transistor is shown in FIG. 33.

Table 6 shows the values of ΔVth at a stress time of 100 hours in the BTS test of the field effect transistors manufactured in Examples 27 to 34. Here, ΔVth indicates the amount of change in Vth from a stress time of 0 hours to a certain stress time.

From FIGS. 32, 33, and Table 6, it can be seen that the field-effect transistor produced in Example 34 has a small ΔVth shift and exhibits excellent reliability in the BTS test. From Table 6, it can be seen that the field effect transistors produced in Examples 27 to 33 have a small ΔVth shift and show excellent reliability for the BTS test.

以上、好ましい実施の形態等について詳説したが、上述した実施の形態等に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態等に種々の変形及び置換を加えることができる。

Although the preferred embodiments and the like have been described in detail above, the embodiments are not limited to the above-described embodiments and the like, and various embodiments and the like described above are used without departing from the scope of the claims. Modifications and substitutions can be added.

10, 10A, 10B, 10C, 20, 30 Electric field effect transistors 11, 21, 51, 61, 71, 91 Substrate 12 Gate electrode 13 Gate insulation layer 14 Source electrode 15 Drain electrode 16 Active layer 17 Passion layer 17a, 41a, 41b 1st passivation layer 17b, 41b, 42b 2nd passivation layer 22 1st gate electrode 23 Gate insulating layer 24 1st source electrode 25 1st drain electrode 26 1st active layer 27 1st passivation layer 32 Second gate electrode 34 Second source electrode 35 Second drain electrode 36 Second active layer 37 Second passion layer 200 Organic EL display element 210 Drive circuit 220 Interlayer insulating film 230 Organic EL element 240 Partition 250 Seal Stop layer 260 Adhesive layer 270 Opposed insulating substrate

Japanese Unexamined Patent Publication No. 2011-151370 JP-A-2015-111653

Claims (20)

A method for manufacturing a field-effect transistor having a gate insulating layer, an active layer, and a passivation layer.
The first step of forming the gate insulating layer and the second step of forming the passivation layer include at least one of the first step and the second step.
A step of forming a first oxide containing an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanide.
An electric field comprising a step of etching the first oxide with a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide solution. Method of manufacturing effect type transistor. The passivation layer includes a first passivation layer and a second passivation layer.
The second step is
A step of forming a first passivation layer containing a second oxide containing Si and an alkaline earth metal, and
A step of forming a second passivation layer which is arranged in contact with the first passivation layer and contains the first oxide.
A step of etching the first passivation layer by contacting it with a second solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium hydrogen fluoride, and an organic alkali.
The method for manufacturing a field-effect transistor according to claim 1, further comprising a step of etching the second passivation layer by bringing it into contact with the first solution. The second step is
A step of forming the first passivation layer on the second passivation layer and
The step of forming a mask on the first passivation layer and
After forming the mask, the first passivation layer is brought into contact with the second solution for etching.
After etching the first passivation layer, the second passivation layer is brought into contact with the first solution for etching.
The method for manufacturing a field effect transistor according to claim 2, further comprising a step of removing the mask. The second step is
A step of forming the second passivation layer on the first passivation layer and
The step of forming a mask on the second passivation layer and
After forming the mask, the second passivation layer is brought into contact with the first solution for etching.
After etching the second passivation layer, a step of etching by bringing the first passivation layer into contact with the second solution.
The method for manufacturing a field effect transistor according to claim 2, further comprising a step of removing the mask. The gate insulating layer includes a first gate insulating layer and a second gate insulating layer.
The first step is
A step of forming a first gate insulating layer containing a second oxide containing Si and an alkaline earth metal, and a step of forming the first gate insulating layer.
A step of forming a second gate insulating layer which is arranged in contact with the first gate insulating layer and contains the first oxide.
A step of etching the first gate insulating layer by contacting it with a second solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium hydrogen fluoride, and an organic alkali.
The method for manufacturing a field-effect transistor according to claim 1, further comprising a step of etching the second gate insulating layer by bringing it into contact with the first solution. The first step is
A step of forming the first gate insulating layer on the second gate insulating layer and
The step of forming a mask on the first gate insulating layer and
After forming the mask, the first gate insulating layer is brought into contact with the second solution for etching.
After etching the first gate insulating layer, the second gate insulating layer is brought into contact with the first solution for etching.
The method for manufacturing a field effect transistor according to claim 5, further comprising a step of removing the mask. The first step is
A step of forming the second gate insulating layer on the first gate insulating layer and
The step of forming a mask on the second gate insulating layer and
After forming the mask, the second gate insulating layer is brought into contact with the first solution for etching.
After etching the second gate insulating layer, the step of etching by bringing the first gate insulating layer into contact with the second solution, and
The method for manufacturing a field effect transistor according to claim 5, further comprising a step of removing the mask. The method for manufacturing a field-effect transistor according to claim 2 or 5, wherein the second oxide contains at least one of Al and B. The method for manufacturing a field-effect transistor according to claim 1, wherein the first oxide is a normal dielectric amorphous oxide. The method for manufacturing a field effect transistor according to claim 1, wherein the first oxide contains at least one of Al, Ti, Zr, Hf, Nb, and Ta. The method for manufacturing a field effect transistor according to claim 1, wherein the active layer is made of an oxide semiconductor. The method for manufacturing a field-effect transistor according to claim 1, wherein the gate insulating layer, the active layer, and the passivation layer are formed on an insulating substrate. The active layer is a semiconductor substrate and
The method for manufacturing a field-effect transistor according to claim 1, wherein the gate insulating layer and the passivation layer are formed on the semiconductor substrate. Each step in the method for manufacturing a field effect transistor according to claim 1 and
A first capacitor electrode connected to the drain electrode of the electric field effect transistor, a second capacitor electrode, and a capacitor dielectric layer provided between the first capacitor electrode and the second capacitor electrode are formed. A method for manufacturing a volatile semiconductor memory element, which comprises a process. The step of forming the capacitor dielectric layer is
The step of forming the first oxide and
The method for manufacturing a volatile semiconductor memory device according to claim 14, further comprising a step of etching the first oxide by contacting it with the first solution. Each step in the method for manufacturing a field effect transistor according to claim 1 and
A method for manufacturing a non-volatile semiconductor memory device, which comprises a step of forming a second gate insulating layer and a floating gate electrode between the active layer and the gate insulating layer. A method for manufacturing a display element, comprising a step of forming a drive circuit including a field effect transistor and a step of forming an optical control element whose optical output is controlled according to a drive signal from the drive circuit.
A method for manufacturing a display element, wherein the step of forming the drive circuit includes each step in the method for manufacturing a field effect transistor according to claim 1. The method for manufacturing a display element according to claim 17, wherein the optical control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoresis element, or an electrowetting element. A method for manufacturing an image display device including a display in which a plurality of display elements are arranged in a matrix and a display control device for individually controlling each of the display elements, wherein the step of forming the display elements is claimed. Item 17. A method for manufacturing an image display device, which comprises each step in the method for manufacturing a display element according to Item 17 or 18. The step of forming the image display device, which is a method of manufacturing a system having an image display device and an image data creation device for supplying image data to the image display device, is the image display device according to claim 19. A method of manufacturing a system, characterized in that each step in the manufacturing method is included.

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