TW202013469A - Method for manufacturing a field effect transistor, method for manufacturing a volatile semiconductor memory element, method for manufacturing a non-volatile semiconductor memory element, method for manufacturing a display element, method for manufacturing an image display device, and method for manufacturing a system - Google Patents

Abstract

A method for manufacturing a field effect transistor including a gate-insulating layer, an active layer, and a passivation layer. The method includes a first process of forming the gate- insulating layer; and a second process of forming the passivation layer. At least one of the first process and the second process includes: forming a first oxide containing an alkaline earth metal and at least one of gallium, scandium, yttrium, and a lanthanoid; and etching the first oxide by use of a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide water.

Description

Method for manufacturing field effect transistor, method for manufacturing volatile semiconductor memory element, method for manufacturing non-volatile semiconductor memory element, method for manufacturing display element, method for manufacturing image display device and method for manufacturing system

The present invention relates to a method of manufacturing a field effect transistor (FET), a method of manufacturing a volatile semiconductor memory element, a method of manufacturing a non-volatile semiconductor memory element, a method of manufacturing a display element, and a method of manufacturing an image display device And the method of manufacturing the system.

The FET is a type of semiconductor device. The FET applies a voltage to the gate electrode to provide a gate for the flow of electrons or holes according to the electric field of the channel to control the current between the source electrode and the drain electrode.

Because of the characteristics of FETs, FETs are used for switching elements and amplifying elements. Because FETs display small gate currents and have a flat appearance, FETs can be easily manufactured or integrated relative to bipolar transistors. Therefore, in integrated circuits used in electronic devices, FETs are already irreplaceable components.

Traditionally, silicon insulating layers are widely used as gate insulating layers for FETs. However, in recent years, with the increasing demand for more advanced integration of FETs and low energy consumption, a technique for forming a gate insulating layer has been developed which implements a so-called high-k insulating film, which has 'S dielectric constant is much higher than that of silicon insulating layer. For example, a FET and a semiconductor memory have been disclosed having a gate insulation formed by oxides including alkaline earth metals and elements selected from gallium (Ga), scandium (Sc), yttrium (Y), and lanthanides Layer (see, for example, Japanese Unexamined Patent Publication No. 2011-151370).

In addition, oxides including alkaline earth metals and rare earth elements (eg, Sc, Y, lanthanides) have reliable barrier performance. Therefore, there has been disclosed a FET having a passivation layer formed of oxides including alkaline earth metals and rare earth elements (see, for example, Japanese Unexamined Patent Publication No. 2015-111653).

One aspect of the present invention provides a method of manufacturing an FET including a gate insulating layer, an active layer, and a passivation layer. The method includes: a first procedure for forming the gate insulating layer; and a second procedure for forming the passivation layer. At least one of the first procedure and the second procedure includes: forming a first oxide, the first oxide including an alkaline earth metal and at least one of gallium, scandium, yttrium, and lanthanide; and using A first solution etches the first oxide. The first solution includes at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide.

10, 10A, 10B, 10C, 50, 110, 110A, 110B, 110C, 110D, 110E, 110F, 110G, 120, 810, 820, 840

11, 21, 51, 61, 71, 91, 121, 321‧‧‧ substrate

12, 52, 62, 72, 92, 103, 124, G‧‧‧ gate electrode

13, 23, 53, 63, 73, 123, 351 ‧‧‧ gate insulating layer

14, 58, 64, 96, 125, S‧‧‧ source electrode

15, 59, 65, 97, 126, D‧‧‧ Drain electrode

16, 66, 98, 122 ‧‧‧ active layer

17, 27A, 111, 112, 113, 114, 115, 128 ‧‧‧ passivation layer

17a, 27, 41a, 42a, 170a‧‧‧‧The first passivation layer

17b, 37, 41b, 42b, 170b ‧‧‧ second passivation layer

20‧‧‧ First field effect transistor

22, 322‧‧‧ First gate electrode

24、325‧‧‧First source electrode

25、327‧‧‧First drain electrode

26、329‧‧‧First active layer

30‧‧‧second field effect transistor

32、323‧‧‧Second gate electrode

34、326‧‧‧Second source electrode

35、328‧‧‧Second drain electrode

36、330‧‧‧Second active layer

43, 57, 127‧‧‧ interlayer insulating film

45、712‧‧‧Cathode

54‧‧‧Insulating film on the side wall of the gate

55, 75, 107, 122a ‧‧‧ source region

56, 76, 108, 122b ‧‧‧ Drain area

60, 70‧‧‧ Volatile semiconductor memory device

67、82‧‧‧First capacitor electrode

68, 81‧‧‧ capacitor dielectric layer

69、80‧‧‧Second capacitor electrode

74、106‧‧‧Insulating film of gate side wall

77‧‧‧ First interlayer insulating film

78‧‧‧bit line electrode

79‧‧‧The second interlayer insulating film

90、100‧‧‧Nonvolatile semiconductor memory device

13a, 93, 102, 130a ‧‧‧ first gate insulating layer

94, 105‧‧‧ floating gate electrode

13b, 95, 104, 130b ‧‧‧ second gate insulating layer

130、170‧‧‧Insulation

150, 150A, 150B, 150C, 200, 200A ‧‧‧ organic electroluminescence display element

210, 320, 730‧‧‧ drive circuit

220‧‧‧Interlayer insulating film

220x, 220y, 220z

230, 350, 750‧‧‧ organic electroluminescent element

231‧‧‧Lower electrode

232‧‧‧ organic electroluminescent layer

233‧‧‧Upper electrode

240‧‧‧Partition wall

250‧‧‧Sealing layer

260‧‧‧adhesive layer

270‧‧‧Insulated substrate

300, 310‧‧‧ mask

352‧‧‧ organic electroluminescent layer

500‧‧‧TV installation

501‧‧‧Main control device

503‧‧‧Tuner

504‧‧‧Analog to Digital Converter

505‧‧‧ Demodulation circuit

506‧‧‧Transport stream decoder

511‧‧‧Sound decoder

512‧‧‧Digital analog converter

513‧‧‧Sound output circuit

514‧‧‧speaker

521‧‧‧Image decoder

522‧‧‧Image-Option synthesis circuit on the screen

523‧‧‧Image output circuit

524‧‧‧Image display device

525‧‧‧ On-screen option drawing circuit

531‧‧‧Memory

532‧‧‧Operation device

541‧‧‧ Driver interface

542‧‧‧Hard disk device

543‧‧‧CD device

551‧‧‧Infrared light receiver

552‧‧‧Communication control device

610‧‧‧ Antenna

620‧‧‧Remote control transmitter

700‧‧‧ screen

702、703‧‧‧Display element

710‧‧‧Monitor

714‧‧‧Anode

740‧‧‧ organic electroluminescent film layer

742‧‧‧Electronic transmission layer

744‧‧‧luminous layer

746‧‧‧Electric tunnel transmission layer

760、830‧‧‧Capacitor

762、772‧‧‧Paired electrode

770‧‧‧Liquid crystal element

780‧‧‧Display control device

782‧‧‧Image data processing circuit

784‧‧‧scan line drive circuit

786‧‧‧ data line drive circuit

X0, X1, X2, X3, ..., Xn-2, Xn-1 ‧‧‧ scan line

Y0, Y1, Y2, Y3, ..., Ym-1‧‧‧ data line

Y0i, Y1i, Y2i, Y3i, ..., Ym-1i ‧‧‧ current supply line

FIG. 1 is a cross-sectional view showing an example of the FET according to the first embodiment;

FIGS. 2A to 2D are (first) drawings showing an example of the steps of manufacturing the FET according to the first embodiment;

FIGS. 3A to 3C are (second) drawings showing an example of the steps of manufacturing the FET according to the first embodiment;

4A to 4C are cross-sectional views showing examples of modified manufacturing FETs according to the first embodiment;

FIG. 5 is a cross-sectional view showing an example of the FET according to the second embodiment;

FIG. 6 is a cross-sectional view for describing the configuration of an organic electroluminescence display element according to the third embodiment and a method of manufacturing an organic electroluminescence display element according to the third embodiment;

FIG. 7 is a cross-sectional view for describing the configuration of a modified organic electroluminescent display element according to the third embodiment and the method of manufacturing an organic electroluminescent display element according to the modification of the third embodiment;

8 is a cross-sectional view for describing the configuration of the FET according to the fourth embodiment and the method of manufacturing the FET according to the fourth embodiment;

9 is a cross-sectional view for describing the configuration of the volatile semiconductor memory device according to the fifth embodiment and the method of manufacturing the volatile semiconductor memory device according to the fifth embodiment;

10 is a cross-sectional view for describing the configuration of the volatile semiconductor memory device according to the sixth embodiment and the method of manufacturing the volatile semiconductor memory device according to the sixth embodiment;

11 is a cross-sectional view for describing the configuration of the non-volatile semiconductor memory device according to the seventh embodiment and the method of manufacturing the non-volatile semiconductor memory device according to the seventh embodiment;

FIG. 12 is a cross-sectional view for describing the configuration of the non-volatile semiconductor memory device according to the eighth embodiment and the method of manufacturing the non-volatile semiconductor memory device according to the eighth embodiment;

FIG. 13 is a cross-sectional view illustrating an FET according to the ninth embodiment;

14A and 14B are (first) drawings illustrating an example of the steps of manufacturing the FET according to the ninth embodiment;

15A to 15C are (second) drawings illustrating an example of the steps of manufacturing the FET according to the ninth embodiment;

16A to 16C are cross-sectional views illustrating examples of modified FETs according to the ninth embodiment;

FIG. 17 is a cross-sectional view illustrating an example of the FET according to the tenth embodiment;

18A to 18D are (first) drawings illustrating an example of the steps of manufacturing the FET according to the tenth embodiment;

FIGS. 19A to 19C are (second) drawings illustrating an example of the steps of manufacturing the FET according to the tenth embodiment;

20A to 20C are cross-sectional views illustrating examples of modified FETs according to the tenth embodiment;

21A and 21B are (first) cross-sectional views illustrating the configuration of the organic EL display element according to the eleventh embodiment and the method of manufacturing the organic EL display element according to the eleventh embodiment;

22A and 22B are (second) cross-sectional views illustrating the configuration of the organic EL display element according to the eleventh embodiment and the method of manufacturing the organic EL display element according to the eleventh embodiment;

FIG. 23 is a block diagram illustrating the configuration of the television device according to the twelfth embodiment;

FIG. 24 is a (first) drawing describing the television device according to the twelfth embodiment;

FIG. 25 is a (second) drawing describing the television device according to the twelfth embodiment;

FIG. 26 is a (third) diagram for describing the television device according to the twelfth embodiment;

FIG. 27 is a diagram describing a display element according to the twelfth embodiment;

FIG. 28 is a diagram describing an organic EL element according to a twelfth embodiment;

FIG. 29 is a (fourth) diagram describing the television device according to the twelfth embodiment;

FIG. 30 is a (first) drawing describing another display element according to the twelfth embodiment;

FIG. 31 is a (second) drawing describing another display element according to the twelfth embodiment;

Figure 32 is a diagram illustrating the change in Vgs-Ids characteristics before and after the Bias Temperature Stress (BTS) test; and

FIG. 33 is a diagram illustrating the relationship between the threshold voltage shift (ΔVth) and the pressurization time.

For a method for performing patterning on oxides including alkaline earth metals and elements selected from gallium (Ga), scandium (Sc), yttrium (Y), and lanthanides, Japanese Patent Unexamined Publication No. 2011- No. 151370 discloses a dry etching lithography process. However, dry etching is not good in terms of the use of dangerous gases, harm to the environment, and cost of required equipment. Therefore, in terms of patterning execution, a wet etching lithography process is preferred.

In addition, by using an etchant made of hydrofluoric acid, it is possible to perform wet etching on a silicon insulating layer (for example, SiO ₂ and SiON) that is widely used as a gate insulating layer and a passivation layer. However, there are no reports of solutions successfully used to perform wet etching on oxides including alkaline earth metals and rare earth metals. Therefore, in the case where the gate insulating layer or the passivation layer is formed of oxides including alkaline earth metals and elements selected from Ga, Sc, Y, and lanthanides, patterning is performed by wet etching in the photolithography process it's difficult.

Therefore, in the process for manufacturing an FET having a gate insulating layer or a passivation layer formed of oxides including alkaline earth metals and elements selected from Ga, Sc, Y, and lanthanides, it is preferable that the gate The insulating layer or passivation layer is formed by wet etching in a photolithography process.

An object of the present invention is to manufacture a gate having a first oxide formed on a layer formed by a first oxide including alkaline earth metals and at least one of Ga, Sc, Y, and lanthanides The FET method of the polar insulating layer and/or the passivation layer is patterned by the use of wet etching.

According to the technique disclosed by the present invention, on a layer formed of a first oxide including alkaline earth metal and at least one of Ga, Sc, Y, and lanthanide elements, to produce a layer formed of the first oxide The method of the gate insulating layer and/or the FET of the passivation layer is possible to perform patterning through the use of wet etching.

The following description describes embodiments of the present invention by referring to the accompanying drawings. In each drawing, the same element will use the same element symbol to omit repeated description.

The inventors of the present invention found that by contacting the first solution (the first solution includes at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide) with the first oxide (the first oxide includes Element A (that is, alkaline earth metal) and element B (that is, at least one of Ga, Sc, Y, and lanthanides)) may be etched on the first oxide. The following embodiments will establish the above knowledge of the inventor.

(First embodiment)

[Configuration of FET]

FIG. 1 is a cross-sectional view showing an example of the FET according to the first embodiment. According to FIG. 1, the FET 10 is a bottom gate/bottom contact FET. The FET 10 includes: a substrate 11; a gate electrode 12; a gate insulating layer 13; a source electrode 14; a drain electrode 15; an active layer 16; and Passivation layer 17. It should be noted that the FET 10 is a typical example of the semiconductor device according to the present invention.

In addition, the passivation layer according to the present invention is a layer having at least a function of isolating/protecting the active layer (eg, semiconductor layer) from moisture, oxygen, hydrogen, etc. in the environment. In addition, it is not only suitable for the active layer, but the passivation layer may have the function of protecting other components of the FET (eg, gate insulating layer, source electrode, drain electrode, gate electrode, etc.). One of the functions of the passivation layer according to the present invention is to protect the FET (or at least a part of the FET) from the materials forming a plurality of layers on the FET or to protect the FET (or at least a part of the FET) from the process of forming such layers.

In addition, even if the passivation layer is physically separated from other components of the FET by, for example, an electroluminescence element or the like, regardless of where the passivation layer is formed, the passivation layer of the FET is regarded as one of the components of the FET. That is, for example, the passivation layer formed after the formation of the electroluminescence element or the like and the passivation layer formed adjacent to the interlayer insulating layer or the like are regarded as the passivation layer of the FET.

In addition, the passivation layer may be referred to as a protective layer.

The FET 10 includes: a gate electrode 12 formed on a substrate 11 having insulating properties; and a gate insulating layer 13 formed to cover the gate electrode 12. In addition, the source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13 and the active layer 16 is formed to partially cover the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are formed at a predetermined distance by the active layer 16, and the active layer 16 will serve as a channel region. In addition, a passivation layer 17 is formed on the gate insulating layer 13 to cover the source electrode 14, the drain electrode 15 and the active layer 16. The following description further describes the various components of the FET 10.

It should be noted that in the first embodiment, for convenience, the surface of the FET 10 formed by the passivation layer 17 is referred to as being on the top side or on one side, and the surface of the FET 10 formed by the substrate 11 It is called on the bottom side or on the other side. In addition, the surface of each element facing the passivation layer 17 is called a top surface or one surface, and the surface of each element facing the substrate 11 is called a bottom surface or another surface. It should be noted that the FET 10 may be used upside down, or may be set at any predetermined angle. In addition, the planar viewing angle is the viewing angle from the position of the normal direction of the top surface of the substrate 11 to the object. In addition, the planar shape is a shape looking toward the object from a position in the normal direction of the top surface of the substrate 11.

There is no specific limitation on the shape, arrangement and size of the substrate 11, and the shape, arrangement and size of the substrate 11 can be appropriately selected according to requirements. The material of the substrate 11 is not particularly limited, and the material of the substrate 11 can be appropriately selected according to requirements. For example, the material of the substrate 11 may be a glass material, a ceramic material, a plastic material, a film material, or the like.

There is no specific limit to the material made of glass, and the material made of glass can be appropriately selected according to needs. For example, the glass material may be alkali-free glass, silica glass, or the like. In addition, there are no specific restrictions on plastic materials and film materials, and plastic materials and film materials can be appropriately selected according to needs. For example, plastic materials and film materials can be polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), polyethylene terephthalate (PEN) Wait.

The gate electrode 12 is formed on a predetermined area of the substrate 11. The gate electrode 12 is an electrode to which a gate voltage is applied. The material of the gate electrode 12 is not particularly limited, and the material of the gate electrode 12 can be appropriately selected according to requirements. For example, the material of the gate electrode 12 may be aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), copper (Cu), zinc (Zn), nickel (Ni), Metals such as chromium (Cr), tantalum (Ta), molybdenum (Mo), and titanium (Ti) may be alloys of the above metals or mixed materials including the above metals. In addition, the material of the gate electrode 12 may be a conductive oxide, such as indium oxide, zinc oxide, tin oxide, gallium oxide, or niobium oxide, and may be a composite of the above conductive oxides or a mixed material including the above conductive oxides Wait. In addition, the material of the gate electrode 12 may be an organic conductor, for example, polydioxyethylthiophene (PEDOT), polyaniline (PANI), or the like. There is no specific limit to the average thickness of the gate electrode 12, and the average thickness of the gate electrode 12 can be appropriately selected according to requirements. However, the preferred film thickness is in the range of greater than 10 nm to less than 1 μm, and the more preferred film thickness is in the range of greater than 50 nm to less than 300 nm.

The gate insulating layer 13 is a layer disposed between the gate electrode 12 and the active layer 16 to insulate the gate electrode 12 from the active layer 16. There is no specific limit to the average thickness of the gate insulating layer 13, and the average thickness of the gate insulating layer 13 can be appropriately selected according to requirements. However, the preferred film thickness is in the range of greater than 50 nm to less than 3 μm, and the more preferred film thickness is in the range of greater than 100 nm to less than 1 μm.

The source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13. The source electrode 14 and the drain electrode 15 are formed to be separated by a predetermined distance. The source electrode 14 and the drain electrode 15 are electrodes for passing current in response to the application of the gate voltage of the gate electrode 12. It should be noted that the wires connecting the source electrode 14 and the drain electrode 15 may be formed on the same layer as the source electrode 14 and the drain electrode 15.

The materials of the source electrode 14 and the drain electrode 15 are not particularly limited, and the materials of the source electrode 14 and the drain electrode 15 can be appropriately selected according to requirements. For example, the material of the source electrode 14 and the drain electrode 15 may be aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), copper (Cu), zinc (Zn), Metals such as nickel (Ni), chromium (Cr), tantalum (Ta), molybdenum (Mo), and titanium (Ti) may be alloys of the above metals or mixed materials including the above metals.

In addition, the materials of the source electrode 14 and the drain electrode 15 may be conductive oxides, such as indium oxide, zinc oxide, tin oxide, gallium oxide, or niobium oxide, and may be a composite of the above conductive oxides or include the above conductive Oxide mixed materials, etc. In addition, the materials of the source electrode 14 and the drain electrode 15 may be organic conductors, such as polydioxyethylthiophene (PEDOT) and polyaniline (PANI). The average thickness of the source electrode 14 and the drain electrode 15 is not particularly limited, and the average thickness of the source electrode 14 and the drain electrode 15 can be appropriately selected according to requirements. However, the preferred film thickness is in the range of greater than 10 nm to less than 1 μm, and the more preferred film thickness is in the range of greater than 50 nm to less than 300 nm.

The active layer 16 is formed on the gate insulating layer 13 to partially cover the source electrode 14 and the drain electrode 15. The active layer 16 between the source electrode 14 and the drain electrode 15 serves as a channel region. There is no specific limit to the average thickness of the active layer 16, and the average thickness of the active layer 16 can be appropriately selected according to requirements. However, the preferred film thickness is in the range of greater than 5 nm to less than 1 μm, and the more preferred film thickness is in the range of greater than 10 nm to less than 0.5 μm.

There is no specific limitation on the material of the active layer 16, and the material of the active layer 16 can be appropriately selected according to requirements. For example, the material of the active layer 16 may be an oxide semiconductor, for example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), or In-Ga-Zn-O, and may be an organic semiconductor, for example, pentacene (pentacene). Among the above materials, an oxide semiconductor is preferable in terms of the stability of the boundary between the gate insulating layer 13 and the first passivation layer 17.

The passivation layer 17 is formed on the gate insulating layer 13 to cover the source electrode 14, the drain electrode 15 and the active layer 16. There is no specific limit to the average thickness of the passivation layer 17, and the average thickness of the passivation layer 17 can be appropriately selected according to requirements. However, the preferred film thickness is in the range of greater than 50 nm to less than 3 μm, and the more preferred film thickness is in the range of greater than 100 nm to less than 1 μm. It should be noted that although the planar shape of the passivation layer 17 corresponds to the planar shape of the gate insulating layer 13 in FIG. 1, the planar shape of the passivation layer 17 is not limited to this. For example, the planar shape of the passivation layer 17 may be smaller than the planar shape of the gate insulating layer 13. In addition, the planar shape of the passivation layer 17 may be larger than that of the gate insulating layer 13 so that the passivation layer 17 covers the side surface of the gate insulating layer 13.

At least one of the gate insulating layer 13 and the passivation layer 17 is formed of oxide. The oxides used in the following embodiments (hereinafter referred to as "first oxides") include group A elements (ie, alkaline earth metals) and group B elements (ie, Ga, Sc, Y, and lanthanides) At least one of the elements) and, if necessary, other elements. The alkaline earth metal included in the first oxide may be of one type, and may be of two types or more.

The alkaline earth metal may be beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and radium (Ra).

The lanthanides can be lanthanum (La), cerium (Ce), cerium (Pr), neodymium (Nd), ytterbium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), lanthanum (Tb), Dysprosium (Dy), 鈥 (Ho), erbium (Er), yin (Tm), ytterbium (Yb) and lutetium (Lu).

The first oxide is preferably a paraelectric amorphous oxide. The paraelectric amorphous oxide is stable in the atmosphere, and can form an amorphous structure smoothly in a large composition range. However, the first oxide may partially include a crystalline material.

For improving the characteristics of the transistor, the gate insulating layer 13 is preferably formed of a paraelectric material to reduce hysteresis in the transfer characteristics of the transistor. Except in certain situations (eg, transistors are used as memory, etc.), the presence of hysteresis is generally not good for devices with transistors that have switching characteristics.

Paraelectric material is a dielectric material that is not piezoelectric material, pyroelectric material or ferroelectric material. In other words, the paraelectric material is a dielectric material that is not polarized by pressure or is not inherently polarized in the absence of an external power plant. In addition, for appearance characteristics, piezoelectric materials, pyroelectric materials, and ferroelectric materials should be crystalline. That is, the gate insulating layer 13 formed of an amorphous material can only be paraelectric.

Alkaline earth metal oxides can easily react with moisture and carbon dioxide in the environment, and can be easily converted into hydroxides or carbonates. Therefore, the alkaline earth metal oxide itself is not suitable for application to electronic devices. In addition, simple oxides (for example, Ga, Sc, Y, and lanthanides) easily crystallize, which can cause problems in leakage current. However, the first oxide including group A elements (that is, alkaline earth metals) and group B elements (that is, at least one of Ga, Sc, Y, and lanthanides) may be in a large composition range The paraelectric amorphous film is smoothly formed in the atmosphere, so it is suitable for the gate insulating layer 13.

Ce has a valence of four, which is special among lanthanides, and when combined with alkaline earth metals, crystals with a perovskite structure are formed. Therefore, the group B element is preferably not Ce, to obtain an amorphous phase.

Compared to perovskite-structured crystals, although crystal phases such as spinel structures may exist in oxides including alkaline earth metals and Ga, such crystals are only at high temperatures (ie, generally higher than Celsius) 1000 degrees). In addition, because the existence of a stable crystalline phase including alkaline earth metals and oxides of Sc, Y, or lanthanides has not been found, even if the subsequent steps are performed at high temperatures, crystal deposition from the amorphous phase hardly occurs. In addition, for oxides including alkaline earth metals and Ga, Sc, Y, or lanthanoid elements, when the oxide is composed of three or more metal elements, the amorphous phase is more stable.

In terms of producing high dielectric constant materials, the composition ratio of elements such as Ba, Sr, Lu, and La is preferably increased. In addition, because the first oxide has a reliable barrier performance against moisture, oxygen, etc. in the environment, the first oxide can be used as the material of the passivation layer 17.

In addition, the first oxide preferably includes a group C element (ie, a third element), and the group C element is aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium At least one of (Nb) and tantalum (Ta) to further stabilize the amorphous phase and improve thermal stability, thermal resistance, and denseness.

For the composition ratio of group A elements (that is, alkaline earth metals) and group B elements (that is, at least one of Ga, Sc, Y, and lanthanides) included in the first oxide, there is no Specific restrictions, and can be appropriately selected according to their needs. However, the composition ratio preferably satisfies the following range.

From oxides (eg, BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ And Lu ₂ O ₃ ), at least one of Group A elements (that is, alkaline earth metals) and Group B elements (that is, Ga, Sc, Y, and lanthanides) included in the first oxide A) The composition ratio (Group A element: Group B element) is preferably a molar percentage of 10.0 or more to a molar percentage of 67.0 or less: a molar percentage of 33.0 or more to a molar percentage of 90.0 or less.

For group A elements (ie, alkaline earth metals), group B elements (ie, at least one of Ga, Sc, Y, and lanthanides) included in the first oxide, and group C elements ( That is, the composition ratio of at least one of Al, Ti, Zr, Hf, Nb, and Ta) is not particularly limited, and can be appropriately selected according to its needs. However, the composition ratio preferably satisfies the following range.

From oxides (eg, BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅ ) After calculation, the group A elements included in the first oxide (ie, alkaline earth Metal), group B elements (ie, at least one of Ga, Sc, Y, and lanthanides) and group C elements (ie, at least one of Al, Ti, Zr, Hf, Nb, and Ta) A) The composition ratio (A group element: B group element: C group element) is preferably a molar percentage of 5.0 or more to a molar percentage of 22.0 or less: a molar percentage of 33.0 or more to a molar ratio of 90.0 or less Percentage: The molar percentage above 5.0 to the molar percentage below 45.0.

Oxides that constitute the first oxide (for example, BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅ ) can be analyzed by X-ray fluorescence analysis and electron microprobe The instrument and inductively coupled plasma atomic emission spectrometer and other devices are calculated by the analysis of the cationic elements included in the oxide.

In the case where the gate insulating layer 13 is formed of the first oxide, the material of the passivation layer 17 is not particularly limited. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. Similarly, in the case where the passivation layer 17 is formed of the first oxide, there is no specific limit to the material of the gate insulating layer 13. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the gate insulating layer 13 and the passivation layer 17. In this case, the boundary between the gate insulating layer 13 and the first passivation layer 17 will be more stable. Therefore, the gate insulating layer 13 and the first passivation layer 17 may have more reliable characteristics.

[Method of manufacturing FET]

The following description describes the method for manufacturing the FET in FIG. FIGS. 2A to 3C are diagrams showing an example of the steps of manufacturing the FET according to the first embodiment.

First, in the step shown in FIG. 2A, the substrate 11 is prepared. Next, a conductive thin film is formed on the substrate 11 by a method such as vacuum vapor deposition, and then, a pattern is performed on the conductive thin film by a method such as photolithography and etching to form the gate electrode 12 in a predetermined shape. In order to clean the surface and improve the adhesion of the substrate 11, before forming the gate electrode 12, it is preferable to perform a pre-processing procedure (for example, oxygen plasma cleaning, ultraviolet ozone cleaning, or ultraviolet irradiation cleaning). As described above, the materials and thicknesses of the substrate 11 and the gate electrode 12 can be appropriately selected.

The method of forming the gate electrode 12 is not particularly limited, and the method can be appropriately selected according to its needs. For example, thin film formation can be performed by sputtering, vacuum vapor deposition, dip coating, spin coating, die-coating, etc., and then, patterning can be performed by photolithography . As another example, thin film formation can be performed by a printing procedure, for example, inkjet printing, nanoimprinting, or gravure printing.

Next, in the step shown in FIG. 2B, an insulating layer 130 (that is, a layer that will eventually form the gate insulating layer 13) is formed on the substrate 11 to cover the gate electrode 12. There is no specific limitation on the method of forming the insulating layer 130, and the method can be appropriately selected according to its needs. For example, the thin film formation can be performed by the following procedures, such as sputtering, pulsed laser deposition (PLD), chemical vapor deposition (CVD), and atomic layer deposition (ALD), etc. vacuum procedures or dip coating methods , Spin coating, die coating and other solution procedures. As another example, thin film formation can be performed by a printing procedure, for example, inkjet printing, nanoimprinting, or gravure printing. The thickness and material of the insulating layer 130 are as described in the above description about the gate insulating layer 13.

Next, in the step shown in FIG. 2C, patterning is performed on the insulating layer 130 formed on the substrate 11 by photolithography and wet etching to form the gate insulating layer 13 in a predetermined shape. Specifically, first, an etching mask is formed on the insulating layer 130. There is no specific limitation on the etching mask. For example, the etching mask can usually be performed by performing spin coating, pre-baking, exposure, development, and pre-baking on the resist material. As another example, metal patterns or oxide patterns formed by a photolithography process can be used for masking.

After forming the mask, the gate insulating layer 13 is formed by performing etching on the insulating layer 130. The etching can be performed on the first oxide constituting the gate insulating layer 13 by contacting the oxide with a solution (hereinafter referred to as "first solution"), the first solution including hydrochloric acid, oxalic acid, nitric acid, phosphoric acid , At least one of acetic acid, sulfuric acid and hydrogen peroxide. Specifically, the etching method may be immersing the first oxide in a first solution including at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide or will include oxalic acid, nitric acid, phosphoric acid, acetic acid, The first solution of at least one of sulfuric acid and hydrogen peroxide is dropped on the first oxide, and then the substrate 11 and the like are rotated.

The concentration of hydrochloric acid is preferably in the range of 0.001 mol/L or more and 6 mol/L or less, more preferably in the range of 0.01 mol/L or more and 1 mol/L or less. The concentration of oxalic acid is preferably in the range of 0.1% or more and 10% or less, and more preferably in the range of 1% or more and 5% or less. The concentration of nitric acid is preferably in the range of 0.1% or more and 40% or less, and more preferably in the range of 1% or more and 20% or less. The concentration of phosphoric acid is preferably in the range of 1% or more and 90% or less, and more preferably in the range of 10% or more and 80% or less. The concentration of acetic acid is preferably in the range of 0.1% or more and 80% or less, and more preferably in the range of 1% or more and 50% or less. The concentration of sulfuric acid is preferably in the range of 0.1% or more and 50% or less, and more preferably in the range of 1% or more and 20% or less. The concentration of hydrogen peroxide is preferably in the range of 0.1% or more and 20% or less, and more preferably in the range of 1% or more and 10% or less. Among the above solution components, hydrochloric acid and a mixed solution including phosphoric acid and nitric acid are preferred because of the high solubility for the first oxide.

After the insulating layer 130 is formed as the gate insulating layer 13 by the etching method, the mask is removed. There are no specific restrictions on the steps to remove the mask. For example, the mask can be soaked in a solution that dissolves the mask to remove the mask.

Next, in the step shown in FIG. 2D, the source electrode 14 and the drain electrode 15 having a predetermined shape are formed on the gate insulating layer 13. In order to clean the surface and improve the adhesion of the gate insulating layer 13, before forming the source electrode 14 and the drain electrode 15, a pre-processing procedure (for example, oxygen plasma cleaning, ultraviolet ozone cleaning, or ultraviolet irradiation cleaning) is preferably performed.

The method of forming the source electrode 14 and the drain electrode 15 is not particularly limited, and the method can be appropriately selected according to its needs. For example, thin film formation can be performed by sputtering, vacuum vapor deposition, dip coating, spin coating, die coating, etc., and then, patterning can be performed by photolithography. As another example, thin film formation may be performed by a printing procedure to directly form a desired shape, for example, inkjet printing, nanoimprinting, or gravure printing. As described above, the materials and thicknesses of the source electrode 14 and the drain electrode 15 can be appropriately selected.

Next, in the step shown in FIG. 3A, an active layer 16 having a predetermined shape is formed on the gate insulating layer 13. There is no specific limitation on the method of forming the active layer 16, and the method can be appropriately selected according to its needs. For example, thin film formation can be performed by sputtering, vacuum vapor deposition, dip coating, spin coating, die coating, etc., and then, patterning can be performed by photolithography. As another example, thin film formation may be performed by a printing procedure to directly form a desired shape, for example, inkjet printing, nanoimprinting, or gravure printing. As described above, the material and thickness of the active layer 16 can be appropriately selected.

Next, in the step shown in FIG. 3B, an insulating layer 170 (that is, a layer that will eventually form the passivation layer 17) is formed on the substrate 11 and the gate insulating layer 13 to cover the source electrode 14 and the drain electrode 15 and active layer 16. There is no specific limitation on the method of forming the insulating layer 170, and the method can be appropriately selected according to its needs. For example, thin film formation can be performed by the following procedures, for example, vacuum procedures such as sputtering, pulsed laser deposition, chemical vapor deposition, and atomic layer deposition, or dip coating, spin coating, die coating, etc. Solution procedures. As another example, thin film formation can be performed by a printing procedure, for example, inkjet printing, nanoimprinting, or gravure printing. The thickness and material of the insulating layer 170 are as described in the above description about the passivation layer 17.

Next, in the step shown in FIG. 3C, patterning is performed on the insulating layer 170 formed on the substrate 11 and the gate insulating layer 13 by photolithography and wet etching to form a passivation with a predetermined shape Layer 17. The specific method is the same as the method of forming the insulating layer 130 as the gate insulating layer 13 shown in FIG. 2C.

Through the above steps, the bottom gate/bottom contact FET 10 can be manufactured.

As described above, according to the first embodiment, by including the group A element (ie, alkaline earth metal) and the group B element (ie, at least one of Ga, Sc, Y, and lanthanides) At least one of the gate insulating layer 13 and the passivation layer 17 is formed by an oxide. In addition, wet etching is performed using a first solution including at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide to pattern the first oxide into a predetermined shape. Preferably, the gate insulating layer 13 and the passivation layer 17 are formed by a wet etching method using the first solution. Here, there is no need to perform traditional dry etching that can cause various problems, such as the use of dangerous gases, damage to the environment, and cost to the required equipment.

In addition, because the dielectric constant of the first oxide is in the range of 6 to 20, which is higher than the SiO ₂ film, using the first oxide as the gate insulating layer 13 will cause the FET to operate at a low voltage (or low energy consumption )drive. In addition, because the first oxide has a high barrier performance, using the first oxide as the passivation layer 17 will produce a highly reliable FET.

That is, the use of the first oxide as the gate insulating layer 13 and the passivation layer 17 and the wet etching of the first oxide will produce high quality with low cost, high safety, and low environmental damage (that is, low energy Power consumption and high reliability) FET.

<Modification of the first embodiment>

The following description of modifications to the first embodiment will describe an example of FETs with different layer configurations compared to the first embodiment. It should be noted that in the modified description of the first embodiment, the description of the same configuration that has been described in the above description will be omitted.

FIGS. 4A to 4C are cross-sectional views showing examples of modified manufacturing FETs according to the first embodiment. The FETs shown in FIGS. 4A to 4C are typical examples of semiconductor devices according to the present invention.

The FET 10A shown in FIG. 4A is a bottom gate/top contact FET. The FET 10A includes: a gate electrode 12 formed on a substrate 11 having insulating properties; and a gate insulating layer 13 formed to cover the gate electrode 12. In addition, the active layer 16 is formed on the gate insulating layer 13, and the source electrode 14 and the drain electrode 15 are partially formed on the active layer 16 at a predetermined distance by the active layer 16 that will serve as a channel region. In addition, a passivation layer 17 is formed on the gate insulating layer 13 to cover the source electrode 14, the drain electrode 15 and the active layer 16.

The FET 10B shown in FIG. 4B is a top gate/bottom contact FET. The FET 10B includes: a source electrode 14 and a drain electrode 15 formed on a substrate 11 having insulating properties; and an active layer 16 formed to partially cover the source electrode 14 and the drain electrode 15. In addition, the gate insulating layer 13 is formed to cover the source electrode 14, the drain electrode 15 and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. In addition, a passivation layer 17 is formed on the gate insulating layer 13 to cover the gate electrode 12.

The FET 10C shown in FIG. 4C is a top gate/top contact FET. The FET 10C includes: an active layer 16 formed on a substrate 11 having insulating properties; and a source electrode 14 and a drain electrode 15 partially formed on the active layer 16 at a predetermined distance by the active layer 16 which will serve as a channel region on. In addition, the gate insulating layer 13 is formed to cover the source electrode 14, the drain electrode 15 and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. In addition, a passivation layer 17 is formed on the gate insulating layer 13 to cover the gate electrode 12.

As described above, there is no specific limitation on the layer configuration according to the present invention. It can be arbitrarily selected in the configurations shown in FIGS. 1 to 4C according to requirements. In the FETs 10A, 10B, and 10C shown in FIGS. 4A to 4C, at least one of the gate insulating layer 13 and the passivation layer 17 is formed of the first oxide, and the gate insulating layer 13 and the passivation Layer 17 can be manufactured by a method similar to that used by FET 10. Therefore, the present invention has advantages similar to those of the FET 10 in terms of the FETs 10A, 10B, and 10C.

<Second Embodiment>

The following description of the second embodiment will describe the FET manufacturing method shown in FIG. 5. It should be noted that in the description of the second embodiment, the description of the same configuration that has been described in the above description will be omitted.

FIG. 5 is a cross-sectional view showing an example of the FET according to the second embodiment. The FET shown in FIG. 5 is a typical example of the semiconductor device according to the present invention.

The FET 120 shown in FIG. 5 is a top gate/self-aligned FET. The FET 120 includes: an active layer 122 formed on a substrate 121 having insulating properties; a gate insulating layer 123 formed on the active layer 122; and a gate electrode 124 formed on the gate insulating layer 123. In addition, the FET 120 includes an interlayer insulating film 127 formed to cover the substrate 121, the active layer 122, and the gate electrode 124. Region 122a is a source region, and region 122b is a drain region. In addition, the source electrode 125 and the drain electrode 126 are formed on the interlayer insulating film 127. The source electrode 125 and the drain electrode 126 are connected to the active layer 122 through a through hole formed on the interlayer insulating film 127. In addition, a passivation layer 128 is formed to cover the interlayer insulating film 127, the source electrode 125, and the drain electrode 126.

For the top gate/self-aligned FET 120, since the area where the gate electrode 124 overlaps the source electrode 125 and the drain electrode 12 (that is, the overlapping area) is missing, it is better than that in FIGS. 1 and 4A. It is possible to reduce the parasitic capacitance more in Figures 4B and 4C. Therefore, the FET 120 can perform a faster operation.

In the first embodiment, the same oxide used for at least one of the gate insulating layer 13 and the passivation layer 17 may be used for at least one of the gate insulating layer 123 and the passivation layer 128.

In the case where the first oxide is used for the gate insulating layer 123, there is no specific limit to the material of the passivation layer 128. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, in the case where the first oxide is used for the passivation layer 128, there is no specific limit to the material of the gate insulating layer 123. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the gate insulating layer 123 and the passivation layer 128. In such a case, the boundary between the gate insulating layer 123 and the passivation layer 128 will be more stable. Therefore, the gate insulating layer 13 and the first passivation layer 17 may have more reliable characteristics.

The substrate 121, the active layer 122, the gate electrode 124, the source electrode 125, and the drain electrode 126 can be used, for example, for the substrate 11, the active layer 16, the gate electrode 12, the source electrode 14, and the drain electrode 15 respectively. The same material is formed.

In addition, the material of the interlayer insulating film 127 is not particularly limited. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

[Method of manufacturing FET]

Next, the following description will describe the method of manufacturing the FET 120. Although the following description will describe a method of manufacturing the FET having the gate insulating layer 123 and the passivation layer 128 each formed of the first oxide, the FET 120 is not limited thereto.

First, the active layer 122, the gate insulating layer 123, and the gate electrode 124 are formed on the substrate 121. For example, the following are the forming steps: performing thin film formation of the active layer 122 on the substrate 121; then, performing thin film formation of the gate insulating layer 123; then, performing thin film formation of the gate electrode 124; and then, by photolithography The gate electrode 124 and the gate insulating layer 123 are sequentially etched.

The same procedure as the first embodiment can be used for the film formation of the gate insulating layer 123 and the gate electrode 124. The mask used in the etching process of the gate electrode 124 can be used for the mask used in the etching process of the gate insulating layer 123, or the pattern of the gate electrode 124 itself can be used as a mask.

In addition, in the case where the gate electrode 124 is formed of a material suitable for wet etching using a first solution of at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide, this procedure can be borrowed It is simplified by the method of simultaneously performing the etching of the gate insulating layer 123 and the gate electrode 124. For example, the gate electrode 124 is a single layer formed of Al, Al alloy, Mo, Mo alloy, or the gate electrode 124 is a laminate layer formed of Al, Al alloy, Mo, Mo alloy, and In the case of using a mixed solution including nitric acid, phosphoric acid, and acetic acid as an etchant, etching may be performed on the gate insulating layer 123 and the gate electrode 124 at the same time.

In addition, after the gate insulating layer 123 performs thin film formation and patterning on the substrate 121, thin film formation and patterning of the gate electrode 124 may be performed.

Next, an interlayer insulating film 127 is formed. There are no specific restrictions on its materials and procedures. For example, the material for forming the interlayer insulating film 127 may be an insulating material, for example, SiON or SiO ₂ , and the procedure for forming the interlayer insulating film 127 may be a vacuum deposition method, for example, a chemical vapor deposition method or a sputtering method. There are no specific restrictions on the patterning method. For example, the desired pattern can be obtained by photolithography and other methods, and the required perforations can be formed.

As shown in FIG. 5, before forming the interlayer insulating film 127, argon (Ar) plasma treatment or the like may be performed to reduce the resistance of the source region 122a and the drain region 122b.

Next, the source electrode 125 and the drain electrode 126 are formed. The source electrode 125 and the drain electrode 126 are formed on the through hole provided on the interlayer insulating film 127 and connected to the active layer 122 (that is, the source region 122a and the drain region 122b).

The same procedure as the first embodiment can be used for the procedure of forming the source electrode 125 and the drain electrode 126.

Finally, a passivation layer 128 is formed. The materials and procedures are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the FET 120 is manufactured.

As described above, similar to the first embodiment, the first oxide is used as at least one of the gate insulating layer 123 and the passivation layer 128 and a low-cost patterning process that performs wet etching on the first oxide is used to High-quality (ie, low energy consumption and high reliability) FETs are produced.

<Third Embodiment>

The following description of the third embodiment will describe an example of an organic electroluminescence display element. It should be noted that in the description of the third embodiment, the description of the same configuration that has been described in the above description will be omitted.

[Organic electroluminescence display element]

FIG. 6 is a cross-sectional view for describing the configuration of the organic electroluminescence display element 200 according to the third embodiment and the method of manufacturing the organic electroluminescence display element 200 according to the third embodiment. According to FIG. 6, the organic electroluminescent display element 200 includes: a driving circuit 210; an interlayer insulating film 220; an organic electroluminescent element 230; a partition wall 240; a sealing layer 250; an adhesive layer 260; and an opposite insulating substrate 270.

The drive circuit 210 is composed of the first FET 20 and the second FET 30. The first FET 20 includes: a first gate electrode 22 formed on a substrate 21 having insulating properties; a gate insulating layer 23; a first source electrode 24; a first drain electrode 25; a first active layer 26; and First passivation layer 27. In addition, the second FET 30 includes: a second gate electrode 32 formed on the substrate 21 having insulating properties; a gate insulating layer 23; a second source electrode 34; a second drain electrode 35; and a second active layer 36 ;; And the second passivation layer 37. For at least one of the gate insulating layer 23, the first passivation layer 27, and the second passivation layer 37, the same first can be used as at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment Oxide.

The driving circuit 210 has one or two transistors/one capacitor structure in which the first drain electrode 25 provided on the first FET 20 and the second gate electrode 32 provided on the second FET 30 are The through holes formed in the gate insulating layer 23 are connected. It should be noted that, in FIG. 6, although there is no particular limitation on where the capacitor is formed, a capacitor is formed between the second gate electrode 32 and the second source electrode 34. That is, if necessary, a capacitor having an appropriate size and configuration can be formed.

The interlayer insulating film 220 is formed to cover the first FET 20 and the second FET 30 provided on the driving circuit 210. On the interlayer insulating film 220, an organic electroluminescent element 230 and a partition wall 240 are formed.

The organic electroluminescent element 230 is a light control element, which includes a lower electrode 231, an organic electroluminescent layer 232, and an upper electrode 233. The lower electrode 231 of the organic electroluminescent element 230 is connected to the second drain electrode 35 of the second FET 30 through a through hole 220x formed on the interlayer insulating film 220.

It should be noted that, as shown in the organic electroluminescence display element 200A of FIG. 7, the first passivation layer 27 and the second passivation layer 37 may be integrally formed to become the passivation layer 27A. In this case, the lower electrode 231 of the organic electroluminescent element 230 is connected to the second drain electrode 35 of the second FET 30 through the through holes 220y, 220z formed on the interlayer insulating film 220 and the passivation layer 27A, respectively.

Regarding the lower electrode 231 of the organic electroluminescence element 230, a conductive oxide such as ITO, In ₂ O ₃ , SnO ₂ , ZnO, Ag-Nd alloy, or the like can be used. For the upper electrode 233, Al-Mg-Ag alloy, Al-Li alloy, ITO, or the like can be used.

The organic electroluminescent layer 232 includes an electron transport layer, a light emitting layer, and a hole transport layer. In addition, the upper electrode 233 is connected to the electron transport layer, and the lower electrode 231 is connected to the hole transport layer. When a predetermined voltage is applied between the lower electrode 231 and the upper electrode 233, the electrons and holes injected from the lower electrode 231 and the upper electrode 233 are recombined in the organic electroluminescent layer 232, so that the light emitting layer is generated due to Energy. In other words, when the first FET 20 and the second FET 30 are turned on, the organic electroluminescent element 230 emits light.

The organic electroluminescent elements 230 are stacked in the following order: the sealing layer 250; the adhesive layer 260; and the opposite insulating substrate 270.

[Method of manufacturing organic electroluminescence display element]

Next, the following description will describe a method of manufacturing the organic electroluminescence display element 200. The first FET 20 and the second FET 30 can be manufactured by the same materials and procedures as those used for the FETs 10 to 10C according to the first embodiment.

It should be noted that in order to form the through hole 220z of the passivation layer 27A using the first oxide shown in FIG. 7, after forming the passivation layer 27A and before forming the interlayer insulating film 220, a mask may be provided, the mask having An opening corresponding to a part of the passivation layer 27A formed in the through hole 220z. Next, etching may be performed on the passivation layer 27A through the mask by using a first solution including at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide.

Alternatively, the film formation of the passivation layer 27A and the interlayer insulating film 220 may be continuously performed, and then the through hole 220y is formed on the interlayer insulating film 220. Next, the interlayer insulating film 220 having the through hole 220y may be used as a mask to form the through hole 220z on the passivation layer 27A.

For the interlayer insulating film 220 and the partition wall 240, various materials and procedures can be used. For example, the materials of the interlayer insulating film 220 and the partition wall 240 may be inorganic oxides (eg, SiO ₂ , SiON, or SiNx) or insulating materials (eg, acrylic, polyimide, etc.). Regarding the process of forming the interlayer insulating film 220 and the partition wall 240, film formation may be performed by sputtering or spin coating, followed by patterning by photolithography, or film formation may be performed by a printing process, for example , Inkjet printing, nano-imprinting or gravure printing to perform the desired shape.

The method of manufacturing the organic electroluminescent element 230 is not particularly limited, and various conventional techniques can be used. For example, a vacuum deposition method (eg, vacuum vapor deposition method or sputtering method) or a solution procedure (eg, inkjet method or nozzle coating method) may be used.

For the sealing layer 250, various materials and procedures can be used. For example, the material of the sealing layer 250 may be an inorganic oxide (eg, SiO ₂ , SiON, SiNx, etc.). For example, forming the sealing layer 250 may be a vacuum deposition method, for example, a chemical vapor deposition method or a sputtering method.

After the sealing layer 250 is formed, the opposing insulating substrate 270 is attached through the adhesive layer 260 with a material such as epoxy resin or acrylic resin, to complete the formation of the organic electroluminescent display device 200.

As described above, using the first oxide as at least one of the gate insulating layer 13 and the passivation layer 17 and using a low-cost patterning process that performs wet etching on the first oxide to produce high quality (ie, Low energy consumption and high reliability) FET.

It should be noted that the display element according to the second embodiment includes at least the light control element and a driving circuit for driving the light control element, and may further include other elements if necessary. Regarding the light control element, there is no specific limitation, as long as it is an element that can control the output of light according to the driving signal, the light control element can be appropriately selected according to its needs. Although a display element having an organic electroluminescence element is used as an example of the above description, a display element having a liquid crystal element, an electrochromic element, an electrophoresis element, an electrowetting element, etc. can be produced instead of the organic electroluminescence element.

There is no specific limit to the driving circuit, as long as it has the FET according to the first embodiment, the driving circuit can be appropriately selected according to its needs. Regarding other elements, there is no specific limitation, and other elements may be appropriately selected according to their needs.

<Fourth embodiment>

The following description of the fourth embodiment will describe another example of the FET. It should be noted that in the description of the fourth embodiment, the description of the same configuration that has been described in the above description will be omitted.

[Configuration of FET]

8 is a cross-sectional view for describing the configuration of the FET according to the fourth embodiment and the method of manufacturing the FET according to the fourth embodiment. According to FIG. 8, the FET 50 includes: a substrate 51; a gate electrode 52; a gate insulating layer 53; a gate sidewall insulating film 54; a source region 55; a drain region 56; an interlayer insulating film 57; a source electrode 58; Drain electrode 59; and passivation layer 111. It should be noted that the FET 50 is a typical example of the semiconductor device according to the present invention.

In the first embodiment, the same oxide used for at least one of the gate insulating layer 13 and the passivation layer 17 can be used for at least one of the gate insulating layer 53 and the passivation layer 111.

In the case where the first oxide is used for the gate insulating layer 53, there is no specific limit to the material of the passivation layer 111. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, in the case where the first oxide is used for the passivation layer 111, there is no specific limit to the material of the gate insulating layer 53. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the gate insulating layer 53 and the passivation layer 111. In this case, the boundary between the gate insulating layer 53 and the passivation layer 111 will be more stable. Therefore, the gate insulating layer 53 and the passivation layer 111 may have more reliable characteristics.

[Method of manufacturing FET]

Next, the following description describes a method for manufacturing the FET 50. Although the following description describes a method for manufacturing the FET having the gate insulating layer 53 and the passivation layer 111 both formed of the first oxide, the FET 50 is not limited to this.

Regarding the manufacture of the FET 50, first, the substrate 51 which is a semiconductor substrate is prepared. With regard to the material of the substrate 51, there is no particular limitation as long as it is a semiconductor material. The material of the substrate 51 may be appropriately selected from Si, germanium (Ge), etc., and impurities may be added if necessary.

Next, the gate insulating layer 53 is formed on the substrate 51. Regarding the procedure, there is no specific limitation, and thin film formation can be performed by a vacuum deposition method, such as chemical vapor deposition, atomic layer deposition, or sputtering method, and then, a desired pattern is formed by a photolithography method or the like. The gate insulating layer 53 may be formed as an amorphous thin film in any of the thin film forming methods described above.

Next, the gate electrode 52 is formed. There are no specific restrictions on materials and procedures. For example, the material of the gate electrode 52 may be polysilicon, a metal material such as Al, or a stacked layer formed of polysilicon, a metal material, and a barrier metal such as TiN or TaN. For example, the procedure for forming the gate electrode 52 may be a vacuum deposition method, for example, a chemical vapor deposition method or a sputtering method. In addition, with regard to lowering the resistance, a silicide (for example, Ni, Co, or Ti) layer may be formed on the surface of the gate electrode 52.

The patterning method of the gate electrode 52 is not particularly limited. For example, a mask may be formed using a photoresist, and then photolithography is performed to remove a part of the gate insulating layer 53 or the gate electrode 52 that is not covered by the mask in the wet etching method.

The procedure of forming the gate insulating layer 53 may be the same as the procedure of forming the gate insulating layer 13 of the first embodiment. There is no particular limitation on the material of the mask used to perform wet etching on the gate insulating layer 53. For example, the pattern of the gate electrode 52 can be used as a mask.

Next, the gate sidewall insulating film 54 is formed on the side of the gate insulating layer 53 or the gate electrode 52. There are no specific restrictions on materials and procedures. For example, the material of the gate sidewall insulating film 54 may be an insulating material, such as SiON or SiO ₂ , and the procedure for forming the gate sidewall insulating film 54 may be a vacuum deposition method, such as a chemical vapor deposition method or a sputtering method. There are no specific restrictions on the patterning method. For example, thin film formation can be performed on the substrate 51 using the material of the gate side wall insulating film 54 and then, etch-back can be performed on the entire surface by dry etching.

Next, ion implantation is selectively performed on the substrate 51 to form the source region 55 and the drain region 56. Regarding the reduction of electrical resistance, a silicide (for example, Ni, Co, or Ti) layer may be formed on the surfaces of the source region 55 and the drain region 56.

Next, an interlayer insulating film 57 is formed. There are no specific restrictions on materials and procedures. For example, the material of the interlayer insulating film 57 may be an insulating material, for example, SiON or SiO ₂ , and the procedure for forming the interlayer insulating film 57 may be a vacuum deposition method, for example, a chemical vapor deposition method or a sputtering method. In addition, the method of patterning is also not particularly limited, and a desired pattern can be formed by a method such as photolithography, and if necessary, a through hole can be formed.

Next, the source electrode 58 and the drain electrode 59 are formed. The source electrode 58 and the drain electrode 59 are formed to be in contact with the source region 55 and the drain region 56 respectively to fill the through holes formed on the interlayer insulating film 57.

There are no specific restrictions on the materials and procedures for forming the source electrode 58 and the drain electrode 59. For example, the materials of the source electrode 58 and the drain electrode 59 may be metallic materials, such as Al or Cu. Regarding the procedure for forming the source electrode 58 and the drain electrode 59, for example, a vacuum deposition method can be used to fill the perforation, for example, a sputtering method, and then, patterning is performed by a photolithography method. In addition, a chemical vapor deposition method or an electroplating method may be used to fill the perforation, and then planarization may be performed by a chemical mechanical polishing method or the like. In addition, if necessary, a stacked layer may be used, which has a layer barrier metal, such as TiN or TaN. In addition, a tungsten plug (W-Plug) can be used, and tungsten can be used to fill the perforations by chemical vapor deposition.

Finally, the passivation layer 111 is formed. The procedures and materials thereof may be the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the FET is manufactured.

It should be noted that regarding the FET 50, the substrate 51 serves as an active layer to form a channel between the source region 55 and the drain region 56. In addition, between the gate insulating layer 53 and the substrate 51 formed of Si, an active layer formed of SiGe or the like may be formed. In addition, although FIG. 8 shows a top gate structure, the aforementioned gate insulating layer 53 can be used for a so-called double gate structure and FinFET.

As described above, similar to the first embodiment, the first oxide is used as at least one of the gate insulating layer and the passivation layer and a low-cost patterning process using wet etching on the first oxide to produce high quality (That is, low energy consumption and high reliability) FET.

<Fifth Embodiment>

The following description of the fifth embodiment describes an example of a volatile semiconductor memory device. It should be noted that in the description of the fifth embodiment, the description of the same configuration that has been described in the above description will be omitted.

[Configuration of volatile semiconductor memory devices]

9 is a cross-sectional view describing the configuration of the volatile semiconductor memory device according to the fifth embodiment and the method of manufacturing the volatile semiconductor memory device according to the fifth embodiment. According to FIG. 9, the volatile semiconductor memory device 60 includes: a substrate 61 which is an insulating substrate; a gate electrode 62; a gate insulating layer 63; a source electrode 64; a drain electrode 65; an active layer 66; a first capacitor electrode 67; capacitive dielectric layer 68; second capacitive electrode 69; and passivation layer 112. It should be noted that the volatile semiconductor memory device 60 is a typical example of the semiconductor device according to the present invention.

In the first embodiment, the same oxide used for at least one of the gate insulating layer 13 and the passivation layer 17 can be used for at least one of the gate insulating layer 63 and the passivation layer 112.

In the case where the gate insulating layer 63 is formed with the first oxide, there is no specific limitation regarding the material of the passivation layer 112. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, in the case where the passivation layer 112 is formed with the first oxide, there is no specific limitation regarding the material of the gate insulating layer 63. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the gate insulating layer 63 and the passivation layer 112. In this case, the boundary between the gate insulating layer 63 and the passivation layer 112 will be more stable. Therefore, the gate insulating layer 63 and the passivation layer 112 may have more reliable characteristics.

Preferably, the capacitor dielectric layer 68 is also formed by the first oxide.

[Method of manufacturing volatile semiconductor memory device]

Next, the following description describes a method of manufacturing the volatile semiconductor memory device 60. Although the following description describes a method for manufacturing a volatile semiconductor memory device having a gate insulating layer 63 and a passivation layer 112 each formed of a first oxide, the volatile semiconductor memory device 60 is not limited to this.

Regarding the manufacture of the volatile semiconductor memory element 60, first, the substrate 61 is prepared. The material of the substrate 61 may be the same as the material used for the substrate 11 according to the first embodiment. Next, a gate electrode 62 is formed on the substrate 61. The procedure and material for forming the gate electrode 62 may be the same as the procedure and material for forming the gate electrode 12 according to the first embodiment.

Next, the second capacitor electrode 69 is formed. Regarding the formation of the second capacitive electrode 69, various materials and procedures can be used. For example, the material of the second capacitor electrode 69 may be a metal (for example, Mo, Al, Cu, or ruthenium (Ru)), an alloy of the above metals, a transparent conductive oxide (for example, ITO or ATO), an organic conductor (for example, PEDOT , PANI), etc. Regarding the procedure for forming the second capacitor electrode 69, for example, thin film formation can be performed by sputtering, spin coating, die coating, or the like, and then, patterning can be performed by photolithography. In addition, a method of a printing program can be performed to directly form a desired shape, for example, inkjet printing, nanoimprinting, or gravure printing.

It should be noted that, in the case where the materials and procedures for forming the gate electrode 62 and the second capacitor electrode 69 are the same, the gate electrode 62 and the second capacitor electrode 69 can be simultaneously formed.

Next, the gate insulating layer 63 is formed with the first oxide. The procedure for forming the gate insulating layer 63 may be the same as the procedure for the gate insulating layer 13 according to the first embodiment.

Next, a capacitor dielectric layer 68 is formed on the second capacitor electrode 69. Regarding the material of the capacitor dielectric layer 68, there is no specific limitation. For example, the material of the capacitor dielectric layer 68 may be a high dielectric constant oxide material including Hf oxide, Ta oxide, La oxide, etc., or may be a ferroelectric material, such as lead zirconate titanate (PZT), Strontium bismuth tantalate (SBT), etc. Among the above materials, the first oxide is preferably used to form the capacitor dielectric layer 68.

Regarding procedures, there are no specific restrictions. For example, thin film formation can be performed by a vacuum deposition method, such as chemical vapor deposition, atomic layer deposition, or sputtering method, and then, a desired pattern can be formed by a photolithography method or the like. It can be formed into an amorphous thin film by any of the above thin film forming methods.

It should be noted that, in the case where the materials and procedures for forming the gate insulating layer 63 and the capacitor dielectric layer 68 are the same, the gate insulating layer 63 and the capacitor dielectric layer 68 can be simultaneously formed.

Next, the source electrode 64 and the drain electrode 65 are formed. The materials and procedures for forming the source electrode 64 and the drain electrode 65 may be the same as those used for the source electrode 14 and the drain electrode 15 according to the first embodiment.

Next, the first capacitor electrode 67 is formed. For the formation of the first capacitor electrode 67, various materials and procedures can be used. For example, the material of the first capacitor electrode 67 may be a metal (eg, Mo, Al, Cu, or Ru), an alloy of the above metals, a transparent conductive oxide (eg, ITO or ATO), an organic conductor (eg, PEDOT, PANI) Wait. Regarding the procedure for forming the first capacitor electrode 67, for example, thin film formation can be performed by sputtering, spin coating, die coating, or the like, and then, patterning can be performed by photolithography. In addition, a method of a printing program can be performed to directly form a desired shape, for example, inkjet printing, nanoimprinting, or gravure printing.

It should be noted that in the case where the materials and procedures for forming the source electrode 64, the drain electrode 65, and the first capacitor electrode 67 are the same, the source electrode 64, the drain electrode 65, and the first capacitor electrode 67 can be simultaneously formed.

Next, the active layer 66 is formed. Regarding the material of the active layer 66, there is no specific limit. For example, the material of the active layer 66 may be an oxide semiconductor, for example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), or In-Ga-Zn-O, and may be an organic semiconductor, for example, pentacene (pentacene). Among the above materials, in terms of the stability of the boundary of the gate insulating layer 63 to the active layer 66, an oxide semiconductor is preferable. There are no specific restrictions on the procedure for forming the active layer 66. For example, thin film formation can be performed by the following procedures, for example, vacuum procedures such as sputtering, pulsed laser deposition, chemical vapor deposition, and atomic layer deposition, or dip coating, spin coating, die coating, etc. Solution procedures. Alternatively, the desired shape can be directly formed by a printing procedure, for example, inkjet printing, nanoimprinting, or gravure printing.

Finally, the passivation layer 112 is formed. The procedure and material for forming the passivation layer 112 may be the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the volatile semiconductor memory device 60 is manufactured.

Here, considering the relative positions of the gate electrode 62, the gate insulating layer 63, the source electrode 64, the drain electrode 65, and the active layer 66, the volatile semiconductor memory device 60 has a so-called bottom gate/bottom contact configuration . However, the volatile semiconductor memory device according to the fifth embodiment is not limited thereto, and may have a configuration such as bottom gate/top contact, top gate/bottom contact, or top gate/top contact.

In addition, the planar structure of the first capacitor electrode 67, the capacitor dielectric layer 68, and the second capacitor electrode 69 of such a volatile semiconductor memory element 60 may form a three-dimensional structure, etc., to increase the capacitance of the capacitor.

As described above, a low-cost patterning process using the first oxide as the gate insulating layer and passivation layer and using wet etching on the first oxide will produce a high-quality (ie, low energy consumption and high reliability) FET . In addition, in addition to being on the gate insulating layer, using the first oxide in the capacitor dielectric layer will preferably produce FETs with lower power consumption.

<Sixth Embodiment>

The following description of the sixth embodiment describes another example of a volatile semiconductor memory device. It should be noted that in the description about the sixth embodiment, the description of the same configuration that has been described in the above description will be omitted.

[Configuration of volatile semiconductor memory devices]

10 is a cross-sectional view for describing the configuration of the volatile semiconductor memory device according to the sixth embodiment and the method of manufacturing the volatile semiconductor memory device according to the sixth embodiment. According to FIG. 10, the volatile semiconductor memory device 70 includes: a substrate 71, which is an insulating substrate; a gate electrode 72; a gate insulating layer 73; a gate sidewall insulating film 74; a source region 75; a drain region 76; First interlayer insulating film 77; bit line electrode 78; second interlayer insulating film 79; second capacitor electrode 80; capacitor dielectric layer 81; first capacitor electrode 82; and passivation layer 113. It should be noted that the volatile semiconductor memory device 70 is a typical example of the semiconductor device according to the present invention.

In the first embodiment, the same oxide used for at least one of the gate insulating layer 13 and the passivation layer 17 can be used for at least one of the gate insulating layer 73 and the passivation layer 113.

In the case where the gate insulating layer 73 is formed with the first oxide, there is no specific limitation regarding the material of the passivation layer 113. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, in the case where the passivation layer 113 is formed with the first oxide, there is no specific limitation regarding the material of the gate insulating layer 73. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the gate insulating layer 73 and the passivation layer 113. In such a case, the boundary between the gate insulating layer 73 and the passivation layer 113 will be more stable. Therefore, the gate insulating layer 73 and the passivation layer 113 may have more reliable characteristics.

Preferably, the capacitor dielectric layer 81 is also formed by the first oxide.

[Method of manufacturing volatile semiconductor memory device]

Next, the following description describes a method of manufacturing the volatile semiconductor memory element 70. Although the following description describes a method for manufacturing a volatile semiconductor memory device having a gate insulating layer 73 and a passivation layer 113 each formed of a first oxide, the volatile semiconductor memory device 70 is not limited to this.

The materials and materials of the volatile semiconductor memory device 70, the substrate 71, the gate electrode 72, the gate insulating layer 73, the gate sidewall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 The procedure can be the same as the substrate 51, the gate electrode 52, the gate insulating layer 53, the gate sidewall insulating film 54, the source region 55, the drain region 56 and the interlayer insulating film 57 according to the fourth embodiment.

After the gate insulating layer 73, the gate electrode 72, the gate sidewall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 are formed on the substrate 71, a bit line electrode 78 is formed. There are no specific restrictions on materials and procedures. For example, the material of the bit line electrode 78 may be Al, Cu, or the like. Regarding the procedure for forming the bit line electrode 78, for example, the perforation can be filled by a vacuum deposition method, for example, a sputtering method or a chemical vapor deposition method, and then, patterning is performed by a photolithography method. In addition, a chemical vapor deposition method or an electroplating method may be used to fill the perforation, and then planarization may be performed by a chemical mechanical polishing method or the like. In addition, if necessary, a stacked layer may be used, which has a layer barrier metal, such as TiN or TaN. In addition, a tungsten plug (W-Plug) can be used, and tungsten can be used to fill the perforations by chemical vapor deposition.

Next, a second interlayer insulating film 79 is formed. The materials and procedures for forming the second interlayer insulating film 79 may be the same as the interlayer insulating film 57 according to the fourth embodiment.

Next, the second capacitor electrode 80 is formed. There are no specific restrictions on its materials and procedures. For example, the material of the second capacitor electrode 80 may be metal (for example, Al, Cu, or Ru), polysilicon, or the like. Regarding the procedure for forming the second capacitor electrode 80, for example, a vacuum deposition method can be used to fill the perforation, for example, a sputtering method or a chemical vapor deposition method, and then, patterning is performed by a photolithography method. In addition, a chemical vapor deposition method or an electroplating method may be used to fill the perforation, and then planarization may be performed by a chemical mechanical polishing method or the like. In addition, if necessary, a stacked layer may be used, which has a layer barrier metal, such as TiN or TaN. In addition, a tungsten plug (W-Plug) can be used, and tungsten can be used to fill the perforations by chemical vapor deposition.

Next, the capacitor dielectric layer 81 is formed. There is no specific limitation on the material of the capacitor dielectric layer 81. For example, there is no specific limitation on the material of the capacitor dielectric layer 81. For example, the material of the capacitor dielectric layer 81 may be a high dielectric constant oxide material including Hf oxide, Ta oxide, La oxide, etc., or may be a ferroelectric material, such as lead zirconate titanate (PZT), Strontium bismuth tantalate (SBT), etc. Among the above materials, the first oxide is preferably used to form the capacitor dielectric layer 81.

There is no specific limitation on the procedure for forming the capacitor dielectric layer 81. For example, thin film formation can be performed by a vacuum deposition method, such as chemical vapor deposition, atomic layer deposition, or sputtering method, and then, a desired pattern can be formed by a photolithography method or the like. It can be formed into an amorphous thin film by any of the above thin film forming methods. In the case where the capacitor dielectric layer 81 is formed of the first oxide, the same procedure as the gate insulating layer 13 according to the first embodiment can be used.

Next, the first capacitor electrode 82 is formed. For the formation of the first capacitive electrode 82, various materials and procedures can be used. For example, the material of the first capacitor electrode 82 may be metal (for example, Al, Cu, or Ru), polysilicon, or the like. Regarding the procedure for forming the first capacitor electrode 82, for example, thin film formation may be performed by a vacuum deposition method, for example, chemical vapor deposition method or sputtering method, and then, patterning may be performed by a method such as photolithography. In addition, if necessary, a stacked layer may be used, which has a layer barrier metal, such as TiN or TaN.

Finally, the passivation layer 113 is formed. The materials and procedures for forming the passivation layer 113 are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the volatile semiconductor memory device 70 is manufactured.

It should be noted that although the description about the volatile semiconductor memory element 70 describes a volatile semiconductor memory element having a stacked structure with a capacitor disposed on the FET, the volatile semiconductor memory element 70 is not limited to this. For example, the volatile semiconductor memory element 70 may be a volatile semiconductor memory element having a trench structure in which the capacitor is disposed in a trench formed on the semiconductor substrate under the FET.

In addition, the planar structure of the second capacitor electrode 80, the capacitor dielectric layer 81, and the first capacitor electrode 82 of such a volatile semiconductor memory element 70 may form a three-dimensional structure, etc., to increase the capacitance of the capacitor.

As described above, using the first oxide as at least one of the gate insulating layer and the passivation layer and the low-cost patterning process using wet etching on the first oxide to produce high quality (ie, low energy consumption and High reliability) volatile semiconductor memory device. In addition, in addition to being on the gate insulating layer, using the first oxide in the capacitor dielectric layer will preferably produce a volatile semiconductor memory device with lower energy consumption.

<Seventh Embodiment>

The following description of the seventh embodiment describes an example of a non-volatile semiconductor memory device. It should be noted that in the description of the seventh embodiment, the description of the same configuration that has been described in the above description will be omitted.

[Configuration of non-volatile semiconductor memory devices]

11 is a cross-sectional view for describing the configuration of the non-volatile semiconductor memory device according to the seventh embodiment and the method of manufacturing the non-volatile semiconductor memory device according to the seventh embodiment. According to FIG. 11, the non-volatile semiconductor memory device 90 includes: a substrate 91, which is an insulating substrate; a gate electrode 92; a first gate insulating layer 93; a floating gate electrode 94; a second gate insulating layer 95; Source electrode 96; drain electrode 97; active layer 98; and passivation layer 114. It should be noted that the non-volatile semiconductor memory device 90 is a typical example of the semiconductor device according to the present invention.

In the first embodiment, the same oxide used for at least one of the gate insulating layer 13 and the passivation layer 17 can be used for at least one of the gate insulating layer 93 and the passivation layer 114.

In the case where the gate insulating layer 93 is formed with the first oxide, there is no specific limitation regarding the material of the passivation layer 114. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, in the case where the passivation layer 114 is formed with the first oxide, there is no specific limitation regarding the material of the gate insulating layer 93. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the gate insulating layer 93 and the passivation layer 114. In such a case, the boundary between the gate insulating layer 93 and the passivation layer 114 will be more stable. Therefore, the gate insulating layer 93 and the passivation layer 114 may have more reliable characteristics.

The gate insulating layer 93 is a so-called gate electrode insulating layer. The second gate insulating layer 95 is a so-called channel insulating layer. The gate electrode 92 is a so-called control gate electrode. By controlling the state of the voltage applied to the source electrode 96, the drain electrode 97, and the gate electrode 92, electrons are allowed to pass through the second gate insulating layer 95 as a channel insulating layer to enter and exit the floating gate due to the channel effect极 electrode 94. In this way, the function of memory is achieved.

[Method of manufacturing non-volatile semiconductor memory device]

Next, the following description describes a method of manufacturing the non-volatile semiconductor memory device 90. Although the following description describes a method for manufacturing a non-volatile semiconductor memory device having a gate insulating layer 93 and a passivation layer 114 each formed of a first oxide, the non-volatile semiconductor memory device 90 is not limited to this.

Regarding the manufacture of the non-volatile semiconductor memory element 90, first, the substrate 91 is prepared. The material of the substrate 91 may be the same as the material used for the substrate 11 according to the first embodiment.

Next, the gate electrode 92 is formed on the substrate 91. The procedure and material for forming the gate electrode 92 may be the same as the procedure and material for forming the gate electrode 12 according to the first embodiment.

Next, the gate insulating layer 93 is formed with the first oxide to cover the gate electrode 92. The procedure for forming the gate insulating layer 93 may be the same as the procedure for forming the gate insulating layer 13 according to the first embodiment.

Next, a floating gate electrode 94 is formed on the gate insulating layer 93. Regarding the formation of the floating gate electrode 94, various materials and procedures can be used. For example, the material of the floating gate electrode 94 may be a metal (eg, Mo, Al, Cu), an alloy of the above metals, a transparent conductive oxide (eg, ITO or ATO), an organic conductor (eg, PEDOT, PANI), or the like. Regarding the procedure for forming the floating gate electrode 94, for example, thin film formation can be performed by a sputtering method, spin coating method, die coating method, or the like, and then, patterning can be performed by photolithography. In addition, a method of a printing program can be performed to directly form a desired shape, for example, inkjet printing, nanoimprinting, or gravure printing.

Next, a second gate insulating layer 95 is formed to cover the floating gate electrode 94. There is no specific restriction on the material, and it can be appropriately selected according to needs. Among the materials, low dielectric constant insulating materials such as SiO ₂ or fluoropolymers are preferred to improve the coupling ratio. Regarding the procedure for forming the second gate insulating layer 95, there is no specific limitation. For example, a vacuum process (for example, sputtering, chemical vapor deposition, atomic layer deposition, etc.), or a solution process (for example, spin coating, die coating, or nozzle coating) or (by using Including metal alkoxides, metal composites, etc. or, if necessary, polymers) inkjet printing. In addition, a photolithography method or a printing method may be used to directly form a desired shape.

Next, the source electrode 96 and the drain electrode 97 are formed on the second gate insulating layer 95. The materials and procedures for forming the source electrode 96 and the drain electrode 97 may be the same as those used for the source electrode 14 and the drain electrode 15 according to the first embodiment.

Next, the active layer 98 is formed. Regarding the material of the active layer 98, there is no specific limit. For example, the material of the active layer 98 may be an oxide semiconductor, for example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), or In-Ga-Zn-O, and may be an organic semiconductor, for example, pentacene (pentacene). Among the above materials, oxide semiconductors are preferred. There are no specific restrictions on the procedure for forming the active layer 98. For example, thin film formation can be performed by the following procedures, for example, vacuum procedures such as sputtering, pulsed laser deposition, chemical vapor deposition, and atomic layer deposition, or solution procedures such as dip coating and spin coating. Alternatively, the desired shape can be directly formed by a printing procedure, for example, inkjet printing, nanoimprinting, or gravure printing.

Finally, the passivation layer 114 is formed. The procedure and material for forming the passivation layer 114 may be the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the non-volatile semiconductor memory device 90 is manufactured.

Here, in view of the relative positions of the gate electrode 92, the source electrode 96, the drain electrode 97, and the active layer 98, the non-volatile semiconductor memory element 90 has a so-called bottom gate/bottom contact configuration. However, the non-volatile semiconductor memory device 90 according to the seventh embodiment is not limited thereto. For example, the non-volatile semiconductor memory device 90 may have, for example, bottom gate/top contact, top gate/bottom contact, or top gate/ Top contact configuration.

In addition, the planar structure of the gate electrode 92, the gate insulating layer 93, and the floating gate electrode 94 of such a nonvolatile semiconductor memory device 90 may form a three-dimensional structure, etc., to increase the capacitance of the capacitor.

As described above, using the first oxide as at least one of the gate insulating layer and the passivation layer and the low-cost patterning process using wet etching on the first oxide to produce high quality (i.e., low energy consumption and High reliability) Non-volatile semiconductor memory device. That is, the voltage used for writing/erasing can be reduced to reduce the leakage current and improve the durability of the device.

<Eighth Embodiment>

The following description of the eighth embodiment describes another example of a non-volatile semiconductor memory device. It should be noted that in the description of the eighth embodiment, the description of the same configuration that has been described in the above description will be omitted.

[Configuration of non-volatile semiconductor memory devices]

12 is a cross-sectional view for describing the configuration of the non-volatile semiconductor memory device according to the eighth embodiment and the method of manufacturing the non-volatile semiconductor memory device according to the eighth embodiment. According to FIG. 12, the non-volatile semiconductor memory device 100 includes: a substrate 101, which is an insulating substrate; a first gate insulating layer 102; a gate electrode 103; a second gate insulating layer 104; a floating gate electrode 105; a gate The polar sidewall insulating film 106; the source region 107; the drain region 108; and the passivation layer 115. It should be noted that the non-volatile semiconductor memory device 100 is a typical example of the semiconductor device according to the present invention.

The same oxide used for at least one of the gate insulating layer 13 and the passivation layer 17 in the first embodiment can be used for at least one of the first gate insulating layer 102 and the passivation layer 115.

In the case where the first gate insulating layer 102 is formed with the first oxide, there is no specific limitation regarding the material of the passivation layer 115. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, in the case where the passivation layer 115 is formed with the first oxide, there is no specific limitation regarding the material of the first gate insulating layer 102. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. However, the first oxide can be used for both the first gate insulating layer 102 and the passivation layer 115. In such a case, the boundary between the first gate insulating layer 102 and the passivation layer 115 will be more stable. Therefore, the first gate insulating layer 102 and the passivation layer 115 may have more reliable characteristics.

The first gate insulating layer 102 is a so-called gate electrode insulating layer. The second gate insulating layer 104 is a so-called channel insulating layer. The gate electrode 103 is a so-called control gate electrode. By controlling the state of voltage application to the source region 107, the drain region 108, and the gate electrode 103, electrons are allowed to pass through the second gate insulating layer 104 as a channel insulating layer to enter and exit the floating gate due to the channel effect极 electrode105. In this way, the function of memory is achieved.

[Method of manufacturing non-volatile semiconductor memory device]

Next, the following description describes a method of manufacturing the non-volatile semiconductor memory device 100. Although the following description describes a method for manufacturing a non-volatile semiconductor memory device having a first gate insulating layer 102 and a passivation layer 115 each formed of a first oxide, the non-volatile semiconductor memory device 100 is not limited to this .

Regarding the manufacture of the non-volatile semiconductor memory element 100, first, the substrate 101 is prepared. The material of the substrate 101 may be the same as the material used for the substrate 51 according to the fourth embodiment.

Next, the second gate insulating layer 104 is formed. Regarding the material of the second gate insulating layer 104, there is no particular limitation, although, for example, it is preferably a low dielectric constant insulating material, such as SiO ₂ . There is no specific limitation on the procedure for forming the second gate insulating layer 104. For example, a vacuum deposition method, for example, thermal energy oxidation method, sputtering method, chemical vapor deposition method, or atomic layer deposition method may be used.

Next, the floating gate electrode 105 is formed. There are no specific restrictions on the materials and procedures for forming the floating gate electrode 105. For example, the material of the floating gate electrode 105 may be polysilicon, a metal material such as Al, or a stacked layer formed of polysilicon, a metal material, and a barrier metal such as TiN or TaN. For example, the procedure for forming the floating gate electrode 105 may be a vacuum deposition method, for example, a chemical vapor deposition method or a sputtering method.

Next, the first gate insulating layer 102 is formed with the first oxide. The procedure and material for forming the first gate insulating layer 102 may be the same as the procedure and material for forming the gate insulating layer 13 according to the first embodiment.

Next, the gate electrode 103 is formed. The materials and procedures for forming the gate electrode 103 may be the same as those for forming the gate insulating layer 53 according to the fourth embodiment.

There is no specific limitation on the patterning of the first gate insulating layer 102, the gate electrode 103, the second gate insulating layer 104, and the floating gate electrode 105. For example, photolithography can be used to form the desired pattern.

Next, the gate sidewall insulating film 106 is formed. The materials and procedures for forming the gate sidewall insulating film 106 may be the same as those used for forming the gate sidewall insulating film 54 according to the fourth embodiment. Next, ion implantation is selectively performed on the substrate 101 to form the source region 107 and the drain region 108. Regarding the reduction of resistance, a silicide (for example, Ni, Co, or Ti) layer may be formed on the surfaces of the source region 107 and the drain region 108.

Finally, the passivation layer 115 is formed. The procedure and material for forming the passivation layer 115 may be the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the non-volatile semiconductor memory device 100 is manufactured.

The planar structure of the first gate insulating layer 102, the gate electrode 103, and the floating gate electrode 105 of such a nonvolatile semiconductor memory device 100 may form a three-dimensional structure, etc., to increase the capacitance of the capacitor.

As described above, using the first oxide as at least one of the first gate insulating layer and the passivation layer and a low-cost patterning process using wet etching on the first oxide to produce high quality (ie, low energy Consumption and high reliability) non-volatile semiconductor memory devices. In other words, the voltage used for writing/erasing can be reduced to reduce leakage current and improve the durability of the device.

<Ninth Embodiment>

The following description of the ninth embodiment illustrates an example of an FET having multiple passivation layers. Note that in the description of the ninth embodiment, the same configuration as that explained in the above embodiment will be omitted.

[Configuration of FET]

FIG. 13 is a cross-sectional view illustrating the FET according to the ninth embodiment. According to FIG. 13, the FET 110 is a bottom gate/bottom contact FET, which includes a substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, an active layer 16, and a first passivation layer 17a and the second passivation layer 17b. Note that the FET 110 is a typical example of the semiconductor device of the present invention.

The FET 110 includes a gate electrode 12 formed on a substrate 11, and the gate electrode 12 is covered with a gate insulating layer 13 having insulating properties. Next, the source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13, and the active layer 16 partially covering the source electrode 14 and the drain electrode 15 is formed. The source electrode 14 and the drain electrode 15 are formed at a predetermined distance through the active layer 16, and the active layer 16 serves as a channel region. In addition, a first passivation layer 17a is formed on the gate insulating layer 13 to cover the source electrode 14, the drain electrode 15 and the active layer 16, and a second passivation layer 17b is formed on the first passivation layer 17a.

In practice, the passivation layer is formed as the upper layer of the substrate 11. The passivation layer includes a first passivation layer 17a and a second passivation layer 17b in contact with the first passivation layer. In the example of FIG. 13, a first passivation layer 17a is formed on the gate insulating layer 13, and the first passivation layer 17a covers the source electrode 14, the drain electrode 15, and the active layer 16.

Regarding the passivation layer, the configurations of the first passivation layer 17a and the second passivation layer 17b are not particularly limited, and the configuration can be appropriately selected according to the intended purpose. As shown in FIG. 13, the first passivation layer 17a may be configured to be closer to the active layer 16 than the second passivation layer 17b. Conversely, the second passivation layer 17b may be configured to be closer to the active layer 16 than the first passivation layer 17a. In addition, the second passivation layer 17b may be configured to cover the top surface and the side surface of the first passivation layer 17a. Conversely, the first passivation layer 17a may be configured to cover the top and side surfaces of the second passivation layer 17b.

(First passivation layer 17a)

The first passivation layer 17a is preferably a second oxide.

(Second oxide)

The second oxide contains silicon (Si) and alkaline earth metal, and more preferably at least one of aluminum (Al) and boron (B). In addition, other elements may be further contained as needed.

Regarding the second oxide, SiO ₂ composed of Si has an amorphous structure. In addition, the alkaline earth metal has a function of cutting Si—O bonds. Therefore, the dielectric constant and linear expansion coefficient of the second oxide can be controlled according to the composition ratio of Si and alkaline earth metal.

The second oxide preferably contains at least one of Al and B. Both Al ₂ O ₃ composed of Al and B ₂ O ₃ composed of B form an amorphous structure similar to SiO ₂ . Therefore, the second oxide containing Al and/or B has a more stable amorphous structure, and thus can form an insulating layer with higher uniformity. In addition, when the alkaline earth metal changes the coordination structure of Al and B according to the composition ratio, the dielectric constant and linear expansion coefficient of the second oxide can be controlled.

Examples of the alkaline earth metal in the second oxide may be beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), etc. The alkaline earth metal may be composed of one of the above elements or two or more of the above elements.

The composition ratio of Si and alkaline earth metal contained in the second oxide is not particularly limited, and the composition ratio can be appropriately selected according to the intended purpose. However, the preferred composition ratio is within the following range.

The composition ratio of Si and alkaline earth metal (Si: alkaline earth metal) contained in the second oxide, calculated from oxides (SiO ₂ , BeO, MgO, CaO, SrO, BaO), is preferably 50.0 mol% to 90.0 mol%: 10mol% to 50mol%.

The composition ratio of Si, alkaline earth metal, and at least one of Al and B contained in the second oxide is not particularly limited, and the composition ratio can be appropriately selected according to the intended purpose. However, the preferred composition ratio is within the following range.

The composition ratio of Si, alkaline earth metal, and at least one of Al and B (Si: alkaline earth metal: at least one of Al and B) contained in the second oxide is composed of oxides (SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) after calculation, preferably 50.0mol% to 90.0mol%: 5.0mol% to 20.0mol%: 5.0mol% to 30.0mol%.

X-ray fluorescence spectroscopy, electron probe microanalysis (EPMA), inductively coupled plasma atomic emission spectroscopy (ICP-AES), etc. For the cationic element, the ratio of oxides contained in the second oxide (eg, SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) can be calculated.

The dielectric constant of the first passivation layer 17a is not particularly limited, and the dielectric constant can be appropriately selected according to the intended purpose.

In order to measure the dielectric constant of the first passivation layer 17a, a capacitor formed by stacking a lower electrode, a dielectric layer (that is, the first passivation layer 17a), and an upper electrode can be fabricated, and then an impedance tester (LCR meter) is used ) To measure the dielectric constant.

The linear expansion coefficient of the first passivation layer 17a is not particularly limited, and the linear expansion coefficient can be appropriately selected according to the intended purpose.

The linear expansion coefficient of the first passivation layer 17a can be measured using, for example, a thermomechanical analysis device. In the method of measuring the linear expansion coefficient, a sample for measurement having the same composition as the first passivation layer 17a can be produced without making an FET.

(Second passivation layer 17b)

The second passivation layer 17b contains the first oxide. The first oxide may be the same material as that used for the gate insulating layer 13 or the passivation layer 17 listed in the first embodiment. In other words, the first oxide contains at least element A (that is, alkaline earth metal) and element B (that is, at least one of gallium (Ga), scandium (Sc), yttrium (Y), and lanthanide). In addition, other elements may be further contained as needed.

The dielectric constant of the second passivation layer 17b is not particularly limited, and the dielectric constant can be appropriately selected according to the intended purpose. The dielectric constant of the second passivation layer 17b can be measured using, for example, the same method as that used to measure the dielectric constant of the first passivation layer 17a.

The linear expansion coefficient of the second passivation layer 17b is not particularly limited, and the linear expansion coefficient can be appropriately selected according to the intended purpose. The linear expansion coefficient of the second passivation layer 17b can be measured using, for example, the same method as that used to measure the linear expansion coefficient of the first passivation layer 17a.

The inventor found that the passivation layer formed by the stacked structure of the first passivation layer 17a and the second passivation layer 17b exhibits excellent barrier performance against moisture, oxygen, nitrogen, etc. in the environment. The first passivation layer 17a contains a second oxide including silicon (Si) and alkaline earth metals, and the second passivation layer 17b contains an element A (that is, alkaline earth metals) and element B (that is, gallium (Ga), scandium (Sc ), at least one of yttrium (Y) and lanthanides) (such as paraelectric amorphous phase oxide). Such a passivation layer can produce a high-reliability FET, and the threshold voltage variation during the Bias Temperature Stress (BTS) test is small.

[Method of manufacturing FET]

The following description explains the method of manufacturing the FET 110 as shown in FIG. 14A to 15C are diagrams illustrating an example of steps of manufacturing the FET 110 of the ninth embodiment.

First, the same steps as those explained in FIGS. 2A to 3A in the first embodiment are performed. In the step illustrated in FIG. 14A, a first passivation layer 170a (that is, a layer where the first passivation layer 17a is to be formed during the etching process) is formed on the entire substrate 11 and the gate insulating layer 13, and the first passivation layer 170a covers the source electrode 14, the drain electrode 15, and the active layer 16. Then, a second passivation layer 170b (that is, a layer where the second passivation layer 17b is to be formed during the etching process) is formed on the entire first passivation layer 170a.

The method for forming the first passivation layer 170a and the second passivation layer 170b is not particularly limited, and the method can be appropriately selected according to the intended purpose. For example, a vacuum process (such as sputtering, pulsed laser deposition, chemical vapor deposition, and atomic layer deposition) can be used to form the thin film.

In addition, in order to form the first passivation layer 170a, a coating liquid containing the precursor of the second oxide (that is, a coating liquid for forming the first passivation layer) may be prepared, and then the coating liquid may be applied or printed. The target object is then baked under appropriate conditions. Similarly, in order to form the second passivation layer 170b, a coating liquid containing the precursor of the first oxide (that is, a coating liquid for forming the second passivation layer) may be prepared, and then the coating liquid may be applied or printed on Apply to the target, then bake the target under appropriate conditions.

The average film thickness of the first passivation layer 170a is preferably 10 nm to 1000 nm, and more preferably 20 nm to 500 nm. The average film thickness of the second passivation layer 170b is preferably 10 nm to 1000 nm, and more preferably 20 nm to 500 nm.

--Coating liquid for forming the first passivation layer--

The coating solution for forming the first passivation layer contains at least a silicon-containing compound, an alkaline earth metal compound, and a solvent, and preferably further contains at least one of an aluminum-containing compound and a boron-containing compound. In addition, if necessary, the coating solution for forming the first passivation layer may further contain other elements.

--Silicon compounds--

The silicon-containing compound may be, for example, an inorganic silicon compound, an organic silicon compound, or the like.

The inorganic silicon compound may be, for example, tetrachlorosilane, tetrabromosilane, tetraiodosilane, or the like.

There is no particular restriction on the organic silicon compound, as long as it is a compound containing silicon and organic groups. The organosilicon compound can be appropriately selected according to the intended purpose. Silicon and organic groups can be bonded together through, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, a phenyl group that may include a substituent, and the like. The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms.

The organosilicon compound may be, for example, tetramethoxysilane, tetraethoxysilane, tetraisopropoxysilane, tetrabutoxysilane, 1,1,1,3,3,3-hexamethyldisilazane (HMDS, TOKYO Products of OHKA KOGYO Co., Ltd.), bistrimethylsilylacetylene, triphenylsilane, 2-ethylhexanoic acid silicon, tetraethoxysilane, etc.

The content of the silicon-containing compound in the coating solution for forming the first passivation layer is not particularly limited, and the content of the silicon-containing compound can be appropriately selected according to the intended purpose.

--Alkaline earth metal compounds--

The alkaline earth metal-containing compound may be, for example, an inorganic alkaline earth metal compound, an organic alkaline earth metal compound, or the like. The alkaline earth metal in the alkaline earth metal-containing compound may be, for example, beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), or the like.

The inorganic alkaline earth metal compound may be, for example, alkaline earth metal nitrate, alkaline earth metal sulfate, alkaline earth metal chloride, alkaline earth metal fluoride, alkaline earth metal bromide, alkaline earth metal iodide, or the like.

The alkaline earth metal nitrate may be, for example, magnesium nitrate, calcium nitrate, strontium nitrate, barium nitrate, or the like.

The alkaline earth metal sulfate may be, for example, magnesium sulfate, calcium sulfate, strontium sulfate, barium sulfate, or the like.

The alkaline earth metal fluoride may be, for example, magnesium fluoride, calcium fluoride, strontium fluoride, barium fluoride, or the like.

The alkaline earth metal chloride may be, for example, magnesium chloride, calcium chloride, strontium chloride, barium chloride, or the like.

The metal bromide on the base may be, for example, magnesium bromide, calcium bromide, strontium bromide, barium bromide, or the like.

The alkaline earth metal iodide may be, for example, magnesium iodide, calcium iodide, strontium iodide, barium iodide, or the like.

The organic alkaline earth metal compound is not particularly limited as long as it contains an alkaline earth metal and an organic group. The organic alkaline earth metal compound can be appropriately selected according to the intended purpose. Alkaline earth metal and organic groups can be bonded together via, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, a phenyl group that may include a substituent, an acetone group that may include a substituent, The sulfuric acid group of the substituent may be included. The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms; an acyloxy group partially substituted with a benzene ring, such as benzoic acid; an acyloxy group partially substituted with a hydroxyl group, such as lactic acid; and Acyloxy groups of two or more carbonyl groups, such as oxalic acid and citric acid.

The organic alkaline earth metal compound may, for example, contain magnesium methoxide, magnesium ethoxide, diethylmagnesium, magnesium acetate, magnesium formate, magnesium acetone, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, citric acid Magnesium, magnesium salicylate, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium formate, calcium ethoxide, calcium acetate, calcium formate, calcium acetone, calcium bis(trimethylacetate) methane , Calcium 2-ethylhexanoate, calcium lactate, calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, calcium benzoate, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetyl Strontium acetone, strontium 2-ethylhexanoate, strontium lactate, strontium naphthenate, strontium salicylate, strontium oxalate, barium ethoxide, barium isopropoxide, barium acetate, barium formate, barium acetone, 2-ethyl Barium hexanoate, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, barium benzoate, barium trifluoromethanesulfonate, acetone beryllium, etc.

The content of the alkaline earth metal-containing compound in the coating solution for forming the first passivation layer is not particularly limited, and the content of the alkaline earth metal-containing compound can be appropriately selected according to the intended purpose.

--Aluminum compounds-

The aluminum-containing compound may be, for example, an inorganic aluminum compound, an organic aluminum compound, or the like.

The inorganic aluminum compound may be, for example, aluminum chloride, aluminum nitrate, aluminum bromide, aluminum hydroxide, aluminum borate, aluminum trifluoride, aluminum iodide, aluminum sulfate, aluminum phosphate, aluminum ammonium sulfate, or the like.

There is no particular limitation on the organoaluminum compound, as long as it is a compound containing aluminum (Al) and an organic group. The organoaluminum compound can be appropriately selected according to the intended purpose. Aluminum (Al) and organic groups can be bonded together via, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, an acetone group that may include a substituent, a sulfate group that may include a substituent, etc. . The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms; an acyloxy group partially substituted with a benzene ring, such as benzoic acid; an acyloxy group partially substituted with a hydroxyl group, such as lactic acid; and Acyloxy groups of two or more carbonyl groups, such as oxalic acid and citric acid.

The organoaluminum compound may be, for example, isopropyl aluminum oxide, secondary butyl aluminum oxide, triethyl aluminum, ethoxy diethyl aluminum, aluminum acetate, aluminum acetone, aluminum hexafluoroacetate, 2-ethyl Aluminum hexanoate, aluminum lactate, aluminum benzoate, bis-secondary butoxyacetate aluminum chelate, and aluminum trifluoromethanesulfonate.

The content of the aluminum-containing compound in the coating solution for forming the first passivation layer is not particularly limited, and the content of the aluminum-containing compound can be appropriately selected according to the intended purpose.

--Boron-containing compounds-

The boron-containing compound may be, for example, an inorganic boron compound, an organic boron compound, or the like.

The inorganic boron compound may be, for example, orthoboric acid, boron oxide, boron tribromide, tetrafluoroboric acid, aluminum borate, magnesium borate, and the like. The boron oxide may be, for example, diboron dioxide, diboron trioxide, tetraboron trioxide, tetraboron pentoxide, or the like.

The organic boron compound is not particularly limited as long as it contains boron (B) and an organic group. The organoboron compound can be appropriately selected according to the intended purpose. Boron (B) and organic groups can be bonded together via, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, a phenyl group that may include a substituent, a sulfate group that may include a substituent, may include Thienyl and the like of the substituent. The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. Examples of the alkoxy group include an organic group having two or more oxygen atoms, and two of the oxygen atoms are bonded to boron to form a ring structure with the boron. In addition, examples of the alkoxy group include an alkoxy group in which the alkyl group is substituted with organosilane. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms.

The organoboron compound can be, for example, (R)-5,5-diphenyl-2-methyl-3,4-propanol-1,3,2-oxazolylborane, triisopropylboron, 2- Isopropoxy-4,4,5,5-tetramethyl-1,3,2-dioxaborolane, bis(hexenylglycolic acid) diboron, 4-(4,4, 5,5-tetramethyl-1,3,2,-dioxaborol-2-yl)-1H-pyrazole, (4,4,5,5-tetramethyl-1,3,2 -Dioxolane-2-yl)benzene, tertiary butyl-N-(4-(4,4,5,5-tetramethyl-1,2,3,-dioxolane Borane-2-yl)phenyl]carbamate, phenylboronic acid, 3-acetoxyphenylboronic acid, boron trifluoride acetic acid complex, boron tetrafluoride cyclobutane complex, 2-thiophene Boric acid, tris(trimethylsilane) borate, etc.

The content of the boron-containing compound in the coating solution for forming the first passivation layer is not particularly limited, and the content of the boron-containing compound can be appropriately selected according to the intended purpose.

---Solvent---

The solvent is not particularly limited, as long as it can stably dissolve and disperse the compound. The solvent can be appropriately selected according to the intended purpose. The solvent can be, for example, toluene, xylene, mesitylene, cumene, pentylbenzene, dodecylbenzene, bicyclohexane, cyclohexylbenzene, decane, undecane, dodecane, tridecane , Tetradecane, pentadecane, tetrahydronaphthalene, decahydronaphthalene, isopropanol, ethyl benzoate, N,N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, ore Olein, dimethylpropenyl urea, 4-butyrolactone, 2-methoxyethanol, propylene glycol, water, etc.

The content of the solvent in the coating solution for forming the first passivation layer is not particularly limited, and the content of the solvent can be appropriately selected according to the intended purpose.

The composition ratio of the silicon-containing compound and the alkaline earth metal-containing compound in the coating solution for forming the first passivation layer (silicon-containing compound: alkaline earth metal-containing compound) is not particularly limited, and the composition ratio can be appropriately determined according to the intended purpose select. However, the composition ratio is preferably within the following range.

In the coating solution for forming the first passivation layer, the composition ratio of silicon (Si) and alkaline earth metal (silicon: alkaline earth metal) is calculated from oxides (such as SiO ₂ , BeO, MgO, CaO, SrO, BaO) It is preferably in the range of 50.0 mol% to 90.0 mol%: 10.0 mol% to 50.0 mol%.

Composition ratio of at least one of silicon-containing compound, alkaline earth metal-containing compound, aluminum-containing compound, and boron-containing compound in the coating solution for forming the first passivation layer (silicon-containing compound: alkaline-earth metal-containing compound: aluminum-containing At least one of the compound and the boron-containing compound) is not particularly limited, and the composition ratio can be appropriately selected according to the intended purpose. However, the composition ratio is preferably within the following range.

In the coating solution for forming the first passivation layer, the composition ratio of silicon, alkaline earth metal, and at least one of the aluminum-containing compound and the boron-containing compound (silicon: alkaline earth metal: at least one of aluminum and boron), Calculated from oxides (SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ), preferably from 50.0mol% to 90.0mol%: 5.0mol% to 20.0mol%: 5.0 mol% to 30.0mol%.

--Coating liquid for forming the second passivation layer--

The coating solution for forming the second passivation layer contains at least an alkaline earth metal-containing compound (that is, an element A-containing compound), an element B-containing compound, and a solvent. In addition, the coating solution for forming the second passivation layer preferably further contains at least one of the element C-containing compounds. In addition, if necessary, the coating solution for forming the second passivation layer may further contain other elements.

---Alkaline earth metal compounds (compounds containing element A) ---

The alkaline earth metal-containing compound may be, for example, an inorganic alkaline earth metal compound, an organic alkaline earth metal compound, etc. The alkaline earth metal in the alkaline earth metal compound may, for example, include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr) , Barium (Ba), etc.

The inorganic alkaline earth metal compound may be, for example, alkaline earth metal nitrate, alkaline earth metal sulfate, alkaline earth metal chloride, alkaline earth metal fluoride, alkaline earth metal bromide, alkaline earth metal iodide, or the like.

The alkaline earth metal nitrate may be, for example, magnesium nitrate, calcium nitrate, strontium nitrate, barium nitrate, or the like.

The alkaline earth metal sulfate may be, for example, magnesium sulfate, calcium sulfate, strontium sulfate, barium sulfate, or the like.

The alkaline earth metal chloride may be, for example, magnesium chloride, calcium chloride, strontium chloride, barium chloride, or the like.

The alkaline earth metal fluoride may be, for example, magnesium fluoride, calcium fluoride, strontium fluoride, barium fluoride, or the like.

The alkaline earth metal bromide may be, for example, magnesium bromide, calcium bromide, strontium bromide, barium bromide, or the like.

The alkaline earth metal iodide may be, for example, magnesium iodide, calcium iodide, strontium iodide, barium iodide, or the like.

The organic alkaline earth metal compound is not particularly limited as long as it contains an alkaline earth metal and an organic group. The organic alkaline earth metal compound can be appropriately selected according to the intended purpose. Alkaline earth metal and organic groups can be bonded together via, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, a phenyl group that may include a substituent, an acetone group that may include a substituent, The sulfuric acid group of the substituent may be included. The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms; an acyloxy group partially substituted with a benzene ring, such as benzoic acid; an acyloxy group partially substituted with a hydroxyl group, such as lactic acid; and Acyloxy groups of two or more carbonyl groups, such as oxalic acid and citric acid.

The organic alkaline earth metal compound may be, for example, magnesium methoxide, magnesium ethoxide, diethyl magnesium, magnesium acetate, magnesium formate, magnesium acetone, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, magnesium citrate , Magnesium salicylate, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium formate, calcium ethoxide, calcium acetate, calcium formate, calcium acetone acetone, calcium bis(trimethylacetate) methane, Calcium 2-ethylhexanoate, calcium lactate, calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, calcium benzoate, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetone acetone Strontium, Strontium 2-ethylhexanoate, Strontium lactate, Strontium naphthenate, Strontium salicylate, Strontium oxalate, Barium ethoxide, Barium isopropoxide, Barium acetate, Barium formate, Barium acetone, 2-ethylhexyl Barium acid, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, barium benzoate, barium trifluoromethanesulfonate, bis(acetylacetone) beryllium, etc.

The content of the alkaline earth metal-containing compound in the coating solution for forming the second passivation layer is not particularly limited, and the content of the alkaline earth metal-containing compound can be appropriately selected according to the intended purpose.

(Compounds containing element B)

The rare earth element in the element B-containing compound may be, for example, gallium (Ga), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), palladium (Pr), neodymium (Nd), or praseodymium (Pm) , Sm, Eu, Gd, Tb, Dy, Ho, Er, Er, Yb, and Lu Wait.

The element-containing B compound may be, for example, an inorganic element-containing B compound, an organic element-containing B compound, or the like.

The inorganic element-containing B compound may be, for example, element B nitrate, element B sulfate, element B fluoride, element B chloride, element B bromide, element B iodide, or the like.

The element B nitrate may be, for example, gallium nitrate, scandium nitrate, yttrium nitrate, lanthanum nitrate, cerium nitrate, gallium nitrate, neodymium nitrate, samarium nitrate, europium nitrate, gadolinium nitrate, yttrium nitrate, dysprosium nitrate, berthium nitrate, erbium nitrate, nitric acid Qin, ytterbium nitrate, ytterbium nitrate, etc.

The element B sulfate may be, for example, gallium sulfate, scandium sulfate, yttrium sulfate, lanthanum sulfate, cerium sulfate, gallium sulfate, neodymium sulfate, samarium sulfate, europium sulfate, gadolinium sulfate, yttrium sulfate, dysprosium sulfate, purium sulfate, erbium sulfate, sulfuric acid Qin, ytterbium sulfate, ytterbium sulfate, etc.

The element B fluoride may be, for example, gallium fluoride, scandium fluoride, yttrium fluoride, lanthanum fluoride, cerium fluoride, gallium fluoride, neodymium fluoride, samarium fluoride, europium fluoride, gadolinium fluoride, yttrium fluoride , Dysprosium fluoride, fluorinated fluorinated, erbium fluoride, fluorinated fluoride, ytterbium fluoride, lutetium fluoride, etc.

The element B chloride may be, for example, gallium chloride, scandium chloride, yttrium chloride, lanthanum chloride, cerium chloride, gallium chloride, neodymium chloride, samarium chloride, europium chloride, gadolinium chloride, arsenic chloride , Dysprosium chloride, 鈥 chloride, erbium chloride, squalene chloride, ytterbium chloride, lutetium chloride, etc.

The element B bromide may be, for example, gallium bromide, scandium bromide, yttrium bromide, lanthanum bromide, cerium bromide, bromide bromide, neodymium bromide, samarium bromide, europium bromide, gallium bromide, bromobromide , Dysprosium bromide, berthium bromide, erbium bromide, bromide, ytterbium bromide, ytterbium bromide, etc.

The element B iodide may be, for example, gallium iodide, scandium iodide, yttrium iodide, lanthanum iodide, cerium iodide, gallium iodide, neodymium iodide, samarium iodide, europium iodide, gadolinium iodide, iodine iodide , Dysprosium iodide, iodine iodide, erbium iodide, iodine iodide, ytterbium iodide, ytterbium iodide, etc.

The organic element B compound is not particularly limited, as long as it is a compound containing element B and an organic group. The organic element B compound can be appropriately selected according to the intended purpose. The element B and the organic group may be bonded together through, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, an acetone group that may include a substituent, and a cyclopentane that may include a substituent Alkenyl and so on. The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms.

The organic element B compound may be, for example, tris(cyclopentadienyl) gallium, isopropyl scandium oxide, scandium acetate, tris(cyclopentadienyl) scandium, yttrium isopropyl oxide, yttrium 2-ethylhexanoate, tris (Acetylacetone) yttrium, tri(cyclopentadienyl)yttrium, isopropyl lanthanum oxide, 2-ethylhexanoic acid lanthanum, tri(acetylacetone) lanthanum, tri(cyclopentadienyl)lanthanum, 2- Cerium ethylhexanoate, tris(acetoacetone)cerium, tris(cyclopentadienyl)cerium, isopropyl oxide, oxalate, tris(acetoacetone) oxide, tris(cyclopentadienyl) oxide, Neodymium isopropoxide, neodymium 2-ethylhexanoate, neodymium trifluoroacetoacetate, neodymium tris(isopropylcyclopentadienyl), sternium tris(ethylcyclopentadienyl), samarium isopropoxide, Samarium 2-ethylhexanoate, tris(acetylacetone) samarium, tris(cyclopentadienyl) samarium, europium 2-ethylhexanoate, tri(acetylacetone) europium, tri(ethylcyclopentadiene Yl) europium, isopropyl gadolinium oxide, 2-ethylhexanoic acid gadolinium, tris(acetoacetone) gadolinium, tris(cyclopentadienyl) gadolinium, yttrium acetate, tris(acetoacetone) yttrium, tris(cyclo (Pentadienyl) ytterbium, isopropyl dysprosium oxide, dysprosium acetate, dysprosium tris(acetone), dysprosium tris(ethylcyclopentadienyl), dysprosium isopropoxide, urs isopropoxide, urs acetate, tris(cyclopentadienyl acetate) )', erbium isopropoxide, erbium acetate, erbium tris(acetylacetone), erbium tris(cyclopentadienyl), erbium triacetate, squalene acetate, squalene tris(acetone), strium tris(cyclopentadienyl), Ytterbium isopropoxide, ytterbium acetate, ytterbium tris(acetone), ytterbium tris(cyclopentadienyl), ytterbium oxalate, ytterbium oxalate, tris(ethylcyclopentadienyl) lutetium, etc.

The content of the element B-containing compound in the coating solution for forming the second passivation layer is not particularly limited, and the content of the element B-containing compound can be appropriately selected according to the intended purpose.

---Elemental C Compounds ---

The element C-containing compound may be, for example, aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), or the like.

The element-containing C compound may be, for example, an inorganic element-containing C compound, an organic element-containing C compound, or the like.

The inorganic element-containing C compound may be, for example, element C nitrate, element C sulfate, element C fluoride, element C chloride, element C bromide, element C iodide, or the like.

The inorganic element-containing C compound may be, for example, aluminum nitrate, aluminum sulfate, aluminum fluoride, aluminum chloride, aluminum bromide, aluminum iodide, aluminum hydroxide, aluminum phosphate, aluminum ammonium sulfate, titanium disulfide, titanium fluoride, Titanium chloride, titanium bromide, titanium iodide, zirconium sulfate, zirconium carbonate, zirconium fluoride, zirconium chloride, zirconium bromide, zirconium iodide, hafnium sulfate, hafnium fluoride, hafnium chloride, hafnium bromide, iodine Hafnium, niobium fluoride, niobium chloride, niobium bromide, tantalum fluoride, tantalum chloride, tantalum bromide, etc.

The organic element-containing C compound is not particularly limited as long as it contains the element C and an organic group. The organic element-containing C compound can be appropriately selected according to the intended purpose. The element C and the organic group may be bonded together through, for example, ionic bonds, covalent bonds, coordination bonds, and the like.

There is no particular restriction on the organic group, and the organic group can be appropriately selected according to the intended purpose. The organic group may be, for example, an alkyl group that may include a substituent, an alkoxy group that may include a substituent, an oxy group that may include a substituent, an acetone group that may include a substituent, and a cyclopentane that may include a substituent Alkenyl and so on. The alkyl group may be, for example, an alkyl group having 1 to 6 carbon atoms and the like. The alkoxy group may be, for example, an alkoxy group having 1 to 6 carbon atoms and the like. The acyloxy group may be, for example, an acyloxy group having 1 to 10 carbon atoms.

The organic element C compound may be, for example, isopropylaluminum oxide, secondary butylaluminum oxide, triethylaluminum, ethoxydiethylaluminum, aluminum acetate, aluminum acetone, aluminum hexafluoroacetone, 2-ethyl Aluminum hexanoate, aluminum lactate, aluminum benzoate, bi-secondary butoxyacetyl acetate acetate chelate, aluminum trifluoromethanesulfonate, titanium isopropoxide, chlorinated di(cyclopentadienyl) Titanium, zirconium butyrate, isopropyl zirconium oxide, zirconium bis(2-ethylhexanoate), zirconium bis(n-butoxy)diacetone, zirconium tetra(acetone) zirconium, tetrakis(cyclopentadiene) Base) zirconium, hafnium butoxide, hafnium isopropoxide, hafnium tetrakis(2-ethylhexanoate), hafnium di(n-butoxy)diacetone, hafnium diacetone, hafnium tetra(acetone), di(cyclopentane) Alkenyl) dimethyl hafnium, niobium ethoxide, niobium 2-ethylhexanoate, di(cyclopentadienyl) niobium chloride, tantalum ethoxide, tantalum tetraethoxyacetone tantalum, etc.

The content of the element C-containing compound in the coating solution for forming the second passivation layer is not particularly limited, and the content of the element C-containing compound can be appropriately selected according to the intended purpose.

---Solvent---

The solvent is not particularly limited, as long as it can stably dissolve and disperse the compound. The solvent can be appropriately selected according to the intended purpose. The solvent can be, for example, toluene, xylene, mesitylene, cumene, pentylbenzene, dodecylbenzene, bicyclohexane, cyclohexylbenzene, decane, undecane, dodecane, tridecane , Tetradecane, pentadecane, tetrahydronaphthalene, decahydronaphthalene, isopropanol, ethyl benzoate, N,N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, ore Olein, dimethylpropenyl urea, 4-butyrolactone, 2-methoxyethanol, propylene glycol, water, etc.

The content of the solvent in the coating solution for forming the second passivation layer is not particularly limited, and the content of the solvent can be appropriately selected according to the intended purpose.

There is no particular limitation on the composition ratio of the alkaline earth metal-containing compound (that is, the element-containing compound A) and the element B-containing compound in the coating solution for forming the second passivation layer (alkaline earth metal-containing compound: element-containing B compound), the The composition ratio can be appropriately selected according to the intended purpose. However, the composition ratio is preferably within the following range.

In the coating solution for forming the second passivation layer, at least one of element A (that is, alkaline earth metal) and element B (that is, gallium (Ga), scandium (Sc), yttrium (Y), and lanthanide) ) Composition ratio (element A: element B), composed of oxides (such as BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O _3. After calculation, Tm ₂ O ₃ , Yb ₂ O ₃ , and Lu ₂ O ₃ ) are preferably in the range of 10.0 mol% to 67.0 mol%: 33.0 mol% to 90.0 mol%.

The composition ratio of at least one of the alkaline earth metal-containing compound (that is, the element-containing compound A), the element B-containing compound, and the element C-containing compound in the coating solution for forming the second passivation layer (alkaline earth metal-containing compound: Element-containing B compound: element-containing B compound: element-containing C compound) is not particularly limited, and the composition ratio can be appropriately selected according to the intended purpose. However, the composition ratio is preferably within the following range.

In the coating solution for forming the second passivation layer, at least one of element A (that is, alkaline earth metal), element B (that is, gallium (Ga), scandium (Sc), yttrium (Y), and lanthanide) ) And the composition ratio of element C (that is, at least one of aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), and tantalum (Ta)) (element A: element B: Element C), composed of oxides (eg BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ ) after calculation, preferably in 5.0mol% to 22.0mol%: 33.0 mol% to 90.0mol%: in the range of 5.0mol% to 45.0mol%.

---Method of forming first passivation layer and second passivation layer---

The following description explains an example of a method of forming the first passivation layer 170a using the coating liquid for forming the first passivation layer, and a method of forming the second passivation layer 170b using the coating liquid for forming the second passivation layer. The method for forming the first passivation layer 170a and the second passivation layer 170b includes a coating step and a heat treatment step, and may further include other steps as needed.

The details of the coating step are not particularly limited, as long as it is a step of applying the coating liquid for forming the first passivation layer or the coating liquid for forming the second passivation layer on the object to be coated. The details of the coating step can be appropriately selected according to the intended purpose. The coating method is not particularly limited, and the coating method can be appropriately selected according to the intended purpose. For example, a solution process can be performed to form a thin film, which is then patterned using photolithography. In addition, printing processes such as inkjet printing, nanoimprinting, and gravure printing can be used to directly form a thin film having a predetermined shape. As for the solution process, dip coating, spin coating, die coating, nozzle printing, etc. can be used.

The details of the heat treatment step are not particularly limited, as long as it is the coating liquid for forming the first passivation layer or the coating liquid for forming the second passivation layer (the coating liquid will be applied to the target to be coated) The step of heat treatment is sufficient. The details of the heat treatment step can be appropriately selected according to the intended purpose. It should be noted that when the heat treatment step is performed, the coating liquid for forming the first passivation layer and the coating liquid for forming the second passivation layer applied on the object to be coated can be allowed to dry naturally. In the heat treatment step, steps of solvent drying and formation of oxide (ie, first oxide or second oxide) are performed.

In the heat treatment step, the drying of the solvent (hereinafter referred to as "drying procedure") and the formation of the first oxide or the second oxide (hereinafter referred to as "generation procedure") are preferably performed at different temperatures. In other words, it is preferable to raise the temperature after drying the solvent to generate the first oxide or the second oxide. The formation of the second oxide includes decomposition of at least one of the silicon-containing compound, the alkaline earth metal-containing compound, the aluminum-containing compound, the boron-containing compound, and the like. The formation of the first oxide includes decomposition of at least one of the alkaline earth metal-containing compound (that is, the element-containing compound A), the element-containing B compound, the element-containing C compound, and the like.

The temperature of the drying procedure is not particularly limited, and the temperature can be appropriately selected according to the solvent contained. For example, the temperature may be in the range of 80°C to 180°C. As for the drying procedure, using a vacuum drying furnace or the like can effectively perform drying at a lower temperature. There is no particular limitation on the duration of the drying procedure, and the processing time can be appropriately selected according to the intended purpose. For example, the treatment time may be in the range of 1 minute to 1 hour.

Although the temperature of the generation process is preferably in the range of 100°C to 550°C, more preferably in the range of 200°C to 500°C, the temperature of the generation process is not particularly limited, and the treatment temperature can be arbitrary according to the intended purpose Decide. There is no particular limitation on the time for generating the program, and the processing time can be arbitrarily determined according to the intended purpose. For example, the treatment time may be in the range of 1 hour to 5 hours.

It should be noted that in the heat treatment step, the drying procedure and the generating procedure may be performed continuously, or may be performed in multiple steps.

The method of heat treatment is not particularly limited, and the method of heat treatment can be appropriately selected according to the intended purpose. For example, the target to be coated can be heated. Although an oxygen environment is preferred, the environment for heat treatment is not particularly limited, and the environment for heat treatment can be appropriately selected according to the intended purpose. When the heat treatment is performed in an oxygen environment, the decomposition products can be smoothly released and discharged from the system, and the first oxide or the second oxide can be accelerated.

In the heat treatment step, in order to accelerate the reaction in the production process, after the drying process, the target object after drying is irradiated with ultraviolet light having a wavelength of 400 nm or shorter, which has a remarkable effect. By irradiating with ultraviolet light with a wavelength of 400 nm or shorter, the chemical bond of the organic material contained in the dried target can be cut, and the organic material can be decomposed, so that the first oxide or the second oxide can be made effective To form. There is no particular limitation on the ultraviolet light having a wavelength of 400 nm or shorter, and the ultraviolet light may be appropriately selected according to the intended purpose. For example, ultraviolet light with a wavelength of 222 nm emitted by an excimer lamp can be used. In addition, it is preferable to apply ozone instead of ultraviolet irradiation, or to use it together with ultraviolet irradiation. Applying ozone to the dried target can accelerate the formation of oxides.

In the step illustrated in FIG. 14B, a mask 300 is formed on a predetermined area of the second passivation layer. The material of the mask 300 is not particularly limited as long as it is a material used as a protective film during the etching step of the first passivation layer 170a and the second passivation layer 170b, and the material can be appropriately selected according to the intended purpose. There is no particular limitation on the type of the material of the mask 300, and the type of the material can be appropriately selected according to the intended purpose. For example, positive photoresist and negative photoresist can be used.

Next, in the step illustrated in FIG. 15A, the second passivation layer 170b is etched to form the second passivation layer 17b having a predetermined shape. The second passivation layer 170b may be etched using a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide aqueous solution. The etching method is, for example, a dipping method of immersing the second passivation layer 170b in the first solution; a spraying method of spraying the second passivation layer 170b with the first solution; and when the substrate 11 including the second passivation layer 170b is rotated The spin coating method in which the first solution drops over the second passivation layer 170b.

The concentration of hydrochloric acid in the first solution is preferably in the range of 0.04 wt% to 40 wt%. The concentration of oxalic acid in the first solution is preferably in the range of 0.1 wt% to 10 wt%. The concentration of nitric acid in the first solution is preferably in the range of 0.1 wt% to 40 wt%. The concentration of phosphoric acid in the first solution is preferably in the range of 0.1 wt% to 85 wt%. The concentration of acetic acid in the first solution is preferably in the range of 1 wt% to 50 wt%. The concentration of sulfuric acid in the first solution is preferably in the range of 1 wt% to 20 wt%. The concentration of the hydrogen peroxide aqueous solution in the first solution is preferably in the range of 1wt% to 10wt%. It is preferable to use a mixed solution containing hydrochloric acid, phosphoric acid and nitric acid, or a mixed solution containing phosphoric acid, nitric acid and acetic acid as the first solution.

Next, in the step illustrated in FIG. 15B, the first passivation layer 170a is etched to form the first passivation layer 17a having a predetermined shape. The first passivation layer 170a may be etched using a second solution (hereinafter referred to as "second solution") containing at least one of hydrofluoric acid, ammonium fluoride, ammonium bifluoride, and an organic base. The etching method is, for example, a dipping method of immersing the first passivation layer 170a in the second solution; a spraying method of spraying the first passivation layer 170a with the second solution; and when the substrate 11 including the first passivation layer 170a rotates The spin coating method in which the second solution drops over the first passivation layer 170a.

In the ninth embodiment, as illustrated in FIG. 15A, the second passivation layer 170b is etched, and then as described in FIG. 15B, the first passivation layer 170a is continuously etched. As such, for the second passivation layer 170b and the first passivation layer 170a, it is not necessary to form the mask 300, which means that in terms of the number of steps, the patterning process of the passivation layer can be simplified. Therefore, a passivation layer having a predetermined shape can be formed with high productivity.

The concentration of hydrofluoric acid in the second solution is preferably in the range of 0.1 wt% to 10 wt%. The concentration of ammonium fluoride in the second solution is preferably in the range of 5wt% to 25wt%. The concentration of ammonium bifluoride in the second solution is preferably in the range of 1wt% to 25wt%. The concentration of the organic base in the second solution is preferably in the range of 1wt% to 15wt%. It is preferable to use a mixed solution containing hydrofluoric acid, ammonium fluoride, and ammonium bifluoride as the second solution.

Next, in the step illustrated in FIG. 15C, the mask 300 is removed. The method of removing the mask 300 is not particularly limited, and the method can be appropriately selected according to the intended purpose. For example, in the case of using a photoresist as the mask 300, the mask 300 may be dissolved and removed by using a solution such as a photoresist stripping agent. In addition, the method of removing the mask 300 is preferably a method that does not damage the passivation layer. Through the above steps, the bottom gate/bottom contact FET 110 can be manufactured.

As described above, the FET 110 according to the ninth embodiment includes the first passivation layer and the second passivation layer configured to contact each other as the passivation layer. The first passivation layer is composed of a second oxide containing silicon (Si) and alkaline earth metal, and the second passivation layer is composed of containing element A (alkaline earth metal) and element B (gallium (Ga), scandium (Sc), At least one of yttrium (Y) and lanthanide elements) is composed of the first oxide.

In addition, the method of manufacturing the FET 110 according to the ninth embodiment includes contacting the first passivation layer 170a with a second solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium bifluoride, and an organic base to perform a wet method Etching, and includes contacting the second passivation layer 170b with a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide aqueous solution to perform wet etching.

Preferably, the first passivation layer 170a and the second passivation layer 170b are wet-etched using the solution for the first passivation layer 170a and the solution for the second passivation layer 170b, respectively, as described above. Here, there is no need to perform conventional dry etching including the use of hazardous gases, damage to the environment, and the cost of equipment required.

In addition, the passivation layer formed by the stacked structure of the second oxide and the first oxide exhibits excellent barrier performance, so that a highly reliable FET can be manufactured (for example, the critical voltage variation is small in the BTS test ).

That is, by performing wet etching using the solution for the first passivation layer 170a and the solution for the second passivation layer 170b as described above, it can be manufactured under the conditions of low cost, high safety, and minimal damage to the environment High-quality FET (with low energy consumption and high reliability).

<Modification of the ninth embodiment>

The description about the modification of the ninth embodiment illustrates an example of FETs having different layer configurations compared to the ninth embodiment. It should be noted that, in the modified description of the ninth embodiment, the same configuration that has been explained in the above description will be omitted.

16A to 16C are cross-sectional views illustrating examples of modified FETs according to the ninth embodiment. The FET described with reference to FIGS. 16A to 16C is a typical example of the semiconductor device of the present invention.

According to FIG. 16A, the FET 110A is a bottom gate/top contact FET. The FET 110A includes a gate electrode 12 formed on a substrate 11 having insulating properties, and includes a gate insulating layer 13 covered on the gate electrode 12. In addition, an active layer 16 is formed on the gate insulating layer 13, and a source electrode 14 and a drain electrode 15 are formed on part of the active layer 16, and the source electrode 14 and the drain electrode 15 are separated by a predetermined distance via the active layer 16 The active layer 16 serves as a channel area. In addition, a first passivation layer 17a is formed on the gate insulating layer 13 to cover the source electrode 14, the drain electrode 15 and the active layer 16, and a second passivation layer 17b is formed on the first passivation layer 17a.

According to FIG. 16B, the FET 110B is a top gate/bottom contact FET. The FET 110B includes a source electrode 14 and a drain electrode 15 formed on a substrate 11 with insulating properties, and includes a portion that covers the source electrode 14 and the drain electrode. The active layer 16 of the polar electrode 15. In addition, a gate insulating layer 13 is formed to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. In addition, a first passivation layer 17a is formed on the gate insulating layer 13 to cover the gate electrode 12, and a second passivation layer 17b is formed on the first passivation layer 17a.

According to FIG. 16C, the FET 110C is a top gate/top contact FET. The FET 110C includes an active layer 16 formed on a substrate 11 having insulating properties, and includes a source electrode 14 and a drain formed on a portion of the active layer 16 The electrode 15 and the source electrode 14 and the drain electrode 15 are separated by a predetermined distance via an active layer 16, which serves as a channel region. In addition, a gate insulating layer 13 is formed to cover the source electrode 14, the drain electrode 15 and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. In addition, a first passivation layer 17a is formed on the gate insulating layer 13 to cover the gate electrode 12, and a second passivation layer 17b is formed on the first passivation layer 17a.

As described above, the present invention does not particularly limit the thin film configuration of the FET, and the configurations shown in FIGS. 13 to 16C can be appropriately selected according to the intended purpose. The first passivation layer 17a and the second passivation layer 17b formed on the FET 110A, FET 110B, and FET 110C shown in FIGS. 16A to 16C can be manufactured by the same method as the FET 110. Therefore, the FET 110A, FET 110B, and FET 110C of the present invention can produce the same advantageous effects as the FET 110.

It should be noted that, contrary to that shown in FIGS. 16A to 16C, the second passivation layer 17b may be configured to be closer to the active layer 16 than the first passivation layer 17a. In addition, the second passivation layer 17b may be configured to cover the top surface and the side surface of the first passivation layer 17a. In addition, the first passivation layer 17a may be configured to cover the top surface and the side surface of the second passivation layer 17b.

<Tenth Embodiment>

The following description of the tenth embodiment illustrates an example of a FET having a gate insulating layer with a two-layer structure. It should be noted that, in the description of the tenth embodiment, the same configuration that has been explained in the above embodiment will be omitted.

[Configuration of FET]

FIG. 17 is a cross-sectional view illustrating the FET according to the tenth embodiment. According to FIG. 17, the FET 110D is a bottom gate/bottom contact FET, which includes a substrate 11, a gate electrode 12, a first gate insulating layer 13a, a second gate insulating layer 13b, a source electrode 14, and a drain electrode 15. The active layer 16 and the first passivation layer 17a. It should be noted that the FET 110D is a typical example of the semiconductor device of the present invention.

For the gate insulating layer having a two-layer structure (that is, the first gate insulating layer 13a and the second gate insulating layer 13b), and for the passivation layer composed only of the first passivation layer 17a, the FET 110D Unlike FET 110 (see Figure 13). It should be noted that the passivation layer may be composed of only the second passivation layer 17b, and may be composed of the first passivation layer 17a and the second passivation layer 17b having a two-layer structure similar to the FET 110.

The configuration of the first gate insulating layer 13a and the second gate insulating layer 13b is not particularly limited, and the configuration can be appropriately selected according to the intended purpose. As shown in FIG. 17, the first gate insulating layer 13 a may be arranged closer to the gate electrode 12 than the second gate insulating layer 13 b. Conversely, the second gate insulating layer 13b may be configured to be closer to the gate electrode 12 than the first gate insulating layer 13a. In addition, the second gate insulating layer 13b may be configured to cover the top surface and the side surface of the first gate insulating layer 13a. Conversely, the first gate insulating layer 13a may be configured to cover the top and side surfaces of the second gate insulating layer 13b.

The first gate insulating layer 13a may be formed using the same material as the first passivation layer 17a. The second gate insulating layer 13b may be formed using the same material as the second passivation layer 17b.

[Method of manufacturing FET]

The following description explains the method of manufacturing the FET 110D as shown in FIG. 18A to 19C are diagrams illustrating an example of the steps of manufacturing the FET 110D according to the tenth embodiment.

First, in the step illustrated in FIG. 18A, a gate electrode 12 having a predetermined shape is formed on the substrate 11, which is similar to the step illustrated in FIG. 2A.

Next, in the step illustrated in FIG. 18B, a first gate insulating layer 130a (that is, a layer to be formed as the first gate insulating layer 13a in the etching process) is formed on the entire substrate 11 to cover Gate electrode 12. Then, a second gate insulating layer 130b is formed on the entire first gate insulating layer 130a (that is, one layer of the second gate insulating layer 13b is to be formed during the etching process).

The first gate insulating layer 130a may be formed using the same material as the first passivation layer 170a. The second gate insulating layer 130b may be formed using the same material as the second passivation layer 170b. In addition, the method for forming the first gate insulating layer 130a is not particularly limited, and the method can be appropriately selected from the methods for forming the first passivation layer 170a as described above according to the intended purpose. Similarly, the method for forming the second gate insulating layer 130b is not particularly limited, and the method can be appropriately selected from the methods for forming the second passivation layer 170b as described above according to the intended purpose.

Next, in the step illustrated in FIG. 18C, a mask 310 is formed on a predetermined area of the second gate insulating layer 130b, which is similar to the step illustrated in FIG. 14B. Then, in the step illustrated in FIG. 18D, the second gate insulating layer 130b is etched to form a second gate insulating layer 13b having a predetermined shape, which is similar to the step illustrated in FIG. 15A.

Next, in the step illustrated in FIG. 19A, the first gate insulating layer 130a is etched to form a first gate insulating layer 13a having a predetermined shape, which is similar to the step illustrated in FIG. 15B. Then, in the step illustrated in FIG. 19B, the mask 310 is removed, which is similar to the step illustrated in FIG. 15C.

Next, in the steps as illustrated in FIG. 19C, the same steps as described in FIGS. 2D to 3C of the first embodiment are performed to manufacture the bottom gate/bottom contact FET 110D. It should be noted that, if necessary, the passivation layer may be composed of only the first passivation layer 17a, and may be composed of only the second passivation layer 17b. In addition, the passivation layer may be composed of a first passivation layer 17a and a second passivation layer 17b having a two-layer structure similar to the FET 110.

As described above, the FET 110D according to the tenth embodiment includes the first gate insulating layer 13a and the second gate insulating layer 13b configured to contact each other as a passivation layer. The first gate insulating layer 13a is composed of a second oxide containing silicon (Si) and alkaline earth metal, and the second gate insulating layer 13b is composed of containing element A (alkaline earth metal) and element B (gallium (Ga) , Scandium (Sc), yttrium (Y) and at least one of the lanthanides) composed of the first oxide.

In addition, the method of manufacturing the FET 110D according to the tenth embodiment includes contacting the first gate insulating layer 130a with a second solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium bifluoride, and an organic base to perform The step of wet etching, which includes contacting the second gate insulating layer 130b with a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide aqueous solution to perform wet Etched steps.

It is preferable to wet-etch the first gate insulating layer 130a and the second gate insulating layer 130b using the solution for the first gate insulating layer 130a and the solution for the second gate insulating layer 130b as described above. The present invention does not require conventional dry etching that involves the use of hazardous gases, damage to the environment, and the cost of equipment.

In addition, when the dielectric constant of the first oxide is in the range of 6 to 20 (higher than the dielectric constant of the SiO ₂ film), using the first oxide as the gate insulating layer can drive the FET at a low voltage ( Or low energy consumption).

That is, wet etching using the solution for the first gate insulating layer 130a and the solution for the second gate insulating layer 130b as described above can be performed at low cost, high safety, and minimal environmental damage Manufacture of high-quality FETs (with low energy consumption and high reliability).

<Modification of Tenth Embodiment>

The description about the modification of the tenth embodiment illustrates an example of FETs with different layer configurations compared to the tenth embodiment. It should be noted that, in the modified description of the tenth embodiment, the same configuration that has been explained in the above description will be omitted.

20A to 20C are cross-sectional views illustrating examples of modified FETs according to the tenth embodiment. The FET described with reference to FIGS. 20A to 20C is a typical example of the semiconductor device of the present invention.

According to FIG. 20A, the FET 110E is a bottom gate/top contact FET. The FET 110E includes a gate electrode 12 formed on a substrate 11 having insulating properties. In addition, a first gate insulating layer 13a is formed to cover the gate electrode 12, and a second gate insulating layer 13b is formed on the first gate insulating layer 13a.

In addition, an active layer 16 is formed on the second gate insulating layer 13b, and a source electrode 14 and a drain electrode 15 are formed on a portion of the active layer 16, and the source electrode 14 and the drain electrode 15 are predetermined via the active layer 16 The distance is separated, and the active layer 16 serves as a channel area. In addition, a first passivation layer 17 a is formed on the second gate insulating layer 13 b to cover the source electrode 14, the drain electrode 15 and the active layer 16.

According to FIG. 20B, the FET 110F is a top gate/bottom contact FET. The FET 110F includes a source electrode 14 and a drain electrode 15 formed on a substrate 11 having insulating properties, and includes a portion that covers the source electrode 14 and the drain electrode. The active layer 16 of the polar electrode 15. In addition, a first gate insulating layer 13a is formed to cover the source electrode 14, the drain electrode 15, and the active layer 16. In addition, a second gate insulating layer 13b is formed on the first gate insulating layer 13a, and a gate electrode 12 is formed on the second gate insulating layer 13b. In addition, a first passivation layer 17a is formed on the second gate insulating layer 13b to cover the gate electrode 12.

According to FIG. 20C, the FET 110G is a top gate/top contact FET. The FET 110G includes an active layer 16 formed on a substrate 11 having insulating properties, and includes a source electrode 14 and a drain formed on a portion of the active layer 16 The electrode 15 and the source electrode 14 and the drain electrode 15 are separated by a predetermined distance via an active layer 16 which serves as a channel region. In addition, a first gate insulating layer 13a is formed to cover the source electrode 14, the drain electrode 15, and the active layer 16. In addition, a second gate insulating layer 13b is formed on the first gate insulating layer 13a, and a gate electrode 12 is formed on the second gate insulating layer 13b. In addition, a first passivation layer 17a is formed on the second gate insulating layer 13b to cover the gate electrode 12.

As described above, the present invention does not particularly limit the thin film configuration of the FET, and the configurations shown in FIGS. 17 to 20C can be appropriately selected according to the intended purpose. The first gate insulating layer 13 and the second gate insulating layer 13b formed on the FET 110E, FET 110F, and FET 110G shown in FIGS. 20A to 20C can be manufactured by the same method as the FET 110D. Therefore, the FET 110E, FET 110F, and FET 110G of the present invention can produce the same advantageous effects as the FET 110D.

Here, contrary to what is shown in FIGS. 20A to 20C, the second gate insulating layer 13b may be disposed closer to the active layer 16 than the first gate insulating layer 13a. In addition, the second gate insulating layer 13b may be configured to cover the top surface and the side surface of the first gate insulating layer 13a. In addition, the first gate insulating layer 13a may be configured to cover the top surface and the side surface of the second gate insulating layer 13b. It should be noted that the passivation layer may be composed of only the second passivation layer 17b, and may be composed of the first passivation layer 17a and the second passivation layer 17b having a two-layer structure similar to the FET 110.

<Eleventh embodiment>

The following description of the eleventh embodiment illustrates an example of an organic EL display element. It should be noted that, in the description of the eleventh embodiment, the same configuration that has been explained in the above embodiment will be omitted.

21A to 22B are cross-sectional views illustrating the configuration of the organic EL display element according to the eleventh embodiment and the method of manufacturing the organic EL display element according to the eleventh embodiment.

The organic EL display element 150 shown in FIG. 21A is a display element including an organic EL element 350 and a drive circuit 320 which are combined together. In addition, the organic EL display element 150 has a bottom contact/top gate FET.

The organic EL display element 150A shown in FIG. 21B is a display element including the organic EL element 350 and the drive circuit 320 bonded together. In addition, the organic EL display element 150A has a top contact/top gate FET.

The organic EL display elements 150 and 150A include a substrate 321, a first gate electrode 322, a second gate electrode 323, a gate insulating layer 351, a first source electrode 325, a second source electrode 326, and a first drain electrode 327, second drain electrode 328, first active layer 329, second active layer 330, first passivation layer 41a, second passivation layer 41b, interlayer insulating film 43, organic EL layer 352, and cathode 45.

The first drain electrode 327 and the second gate electrode 323 are connected through a through hole formed on the gate insulating layer 351. The second drain electrode 328 serves as an anode of the organic EL element 350.

It should be noted that in FIGS. 21A and 21B, a capacitor is formed between the second gate electrode 323 and the second drain electrode 328. There is no particular restriction on where to form the capacitor. That is, if necessary, a capacitor having an appropriate size and configuration is formed.

The substrate 321, the first gate electrode 322, the second gate electrode 323, the gate insulating layer 351, the first source electrode 325 may be formed using materials, processes, etc. in the description about the FET according to the ninth embodiment. The second source electrode 326, the first drain electrode 327, the second drain electrode 328, the first active layer 329, the second active layer 330, the first passivation layer 41a, and the second passivation layer 41b.

It should be noted that the first passivation layer 41a and the second passivation layer 41b correspond to the first passivation layer 17a and the second passivation layer 17b in the FET 110 or the like, respectively. In addition, similar to the ninth embodiment, the configuration of the passivation layers of the first passivation layer 41a and the second passivation layer 41b is not particularly limited, and the configuration can be appropriately selected according to the intended purpose. In addition, the second passivation layer 41b may be configured to cover the top surface and the side surface of the first passivation layer 41a, and the first passivation layer 41a may be configured to cover the top surface and the side surface of the second passivation layer 41b.

The material type of the interlayer insulating film 43 (or planarization film) is not particularly limited, and the material type can be appropriately selected according to the intended purpose. The material type may be, for example, organic materials, inorganic materials, organic-inorganic composite materials, and the like.

The organic material may be, for example, a resin, and the resin may be, for example, polyimide, acrylic resin, fluororesin, non-fluororesin, olefin resin, or silicone resin, and a photosensitive resin composed of the above resin.

The inorganic material may be, for example, a spin-on glass (SOG) material, such as AQUAMICA produced by AZ Electronic Materials.

The organic-inorganic composite material may be, for example, an organic-inorganic composite compound composed of a silane compound disclosed in Japanese Unexamined Patent Publication No. 2007-158146.

The interlayer insulating film 43 preferably has barrier performance against moisture, oxygen, hydrogen, etc. in the environment.

The formation method of the interlayer insulating film 43 is not particularly limited, and the formation method can be appropriately selected according to the intended purpose. For example, a method of directly forming a thin film having a predetermined shape via a spin coating method, an inkjet printing method, a slit coating method, a nozzle printing method, a gravure printing method, a dip coating method, and the like can be directly formed. In addition, in the case of using a photosensitive material, patterning can be performed by photolithography.

In addition, after forming the interlayer insulating film 43, by performing heat treatment as a post-treatment, the characteristics of the FET constituting the display element can be effectively stabilized.

The method for manufacturing the organic EL layer 352 and the cathode 45 is not particularly limited, and the method can be appropriately selected according to the intended purpose. The manufacturing method of the organic EL layer 352 and the cathode 45 may be, for example, a vacuum deposition method (for example, vacuum vapor deposition method and sputtering method), and may be, for example, a solution process (for example, inkjet printing method, nozzle coating method, etc.).

As described above, it is possible to manufacture so-called bottom-emission organic EL display elements 150 and 150A that emit light emitted through the substrate 321. Here, the substrate 321, the gate insulating layer 351, and the second drain electrode (ie, anode) 328 need to be transparent.

The organic EL display element 150B shown in FIG. 22A is a display element including an organic EL element 350 and a drive circuit 320 which are combined together. In addition, the organic EL display element 150B has a bottom contact/bottom gate FET.

The organic EL display element 150C shown in FIG. 22B is a display element including the organic EL element 350 and the drive circuit 320 bonded together. In addition, the organic EL display element 150C has a top contact/bottom gate FET.

Unlike the organic EL display elements 150 and 150A, the organic EL display elements 150B and 150C include a first passivation layer 42a and a second passivation layer 42b in addition to the first passivation layer 41a and the second passivation layer 41b. The first passivation layer 42a and the second passivation layer 42b may be formed using materials, processes, etc. in the description about the FET according to the ninth embodiment.

It should be noted that the first passivation layer 42a and the second passivation layer 42b correspond to the first passivation layer 17a and the second passivation layer 17b in the FET 110 or the like, respectively. In addition, similar to the ninth embodiment, the configuration of the passivation layers of the first passivation layer 42a and the second passivation layer 42b is not particularly limited, and the configuration can be appropriately selected according to the intended purpose. In addition, the second passivation layer 42b may be configured to cover the top surface and the side surface of the first passivation layer 42a, and the first passivation layer 42a may be configured to cover the top surface and the side surface of the second passivation layer 42b.

It should be noted that FIGS. 21A to 22B illustrate that the organic EL element 350 is arranged beside the drive circuit 320, but the organic EL element 350 may be arranged above the drive circuit 320. Here, the display element is still a bottom-emission type, that is, to emit the light emitted through the substrate 321, so the driving circuit 320 needs to be transparent. As for the source electrode, the drain electrode, and the anode, conductive transparent oxides such as ITO, indium oxide (In ₂ O ₃ ), tin dioxide (SnO ₂ ), zinc oxide (ZnO), or gallium (Ga ) Added zinc oxide (ZnO), aluminum (Al) added zinc oxide (ZnO), and antimony (Sb) added tin dioxide (SnO ₂ ).

<Twelfth Embodiment>

The description of the twelfth embodiment illustrates an example of an image display device and system using the FET according to the first embodiment. It should be noted that, in the description of the twelfth embodiment, the same configuration that has been explained in the above embodiment will be omitted.

In FIG. 23, the schematic configuration diagram of the television device 500 according to the twelfth embodiment is taken as a system. Here, the connecting lines shown in Figure 23 are used to indicate the paths representing signals and information flows, and do not describe all the connection relationships between the blocks.

The television device 500 according to the twelfth embodiment includes a main control device 501, a tuner 503, an analog-digital converter (ADC) 504, a demodulation circuit 505, and a transport stream (TS) decoder 506 , Audio decoder 511, digital-analog converter (DAC) 512, audio output circuit 513, speaker 514, video decoder 521, video-on-screen display (OSD) synthesis circuit 522, The image output circuit 523, the image display device 524, the OSD drawing circuit 525, the memory 531, the operating device 532, the driver interface (IF) 541, the infrared light receiver 551, the communication control device 552, and the like.

The main control device 501 is composed of a central processing unit (CPU), flash read-only memory (ROM), dynamic random access memory (RAM), etc. The main control device 501 performs control of the entire television device 500. The flash ROM stores computer programs readable by the CPU written in code and various data for processing by the CPU. In addition, RAM is used as the memory of the working area.

The tuner 503 selects a broadcast based on a predetermined channel from broadcast wavelengths received via the antenna 610. The ADC 504 converts the output signal (ie, analog information) from the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information output from the ADC 504.

The TS decoder 506 performs TS decoding on the output signal from the demodulation circuit 505, and then separates audio information and video information. The sound decoder 511 decodes the sound information from the TS decoder 506. An analog-to-digital converter (DAC) 512 converts the output signal from the sound decoder 511 into an analog signal.

The sound output circuit 513 outputs the output signal from the digital-to-analog converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video-OSD synthesis circuit 522 synthesizes the output signal from the video decoder 521 and the output signal from the OSD rendering circuit 525.

The video output circuit 523 outputs the output signal from the video-OSD synthesis circuit 522 to the video display device 524. The OSD rendering circuit 525 includes a character generator for displaying characters and graphics on the image display device 524. The OSD rendering circuit 525 generates a signal including display information based on an instruction from the operating device 532 or the IR light receiver 551.

The memory 531 temporarily accumulates audio-visual (AV) data and the like. The operation device 532 provided with an input medium (not shown in FIG. 23) such as a control panel transmits various information items input by the user to the main control device 501. The driver interface 541 is an interactive communication interface and conforms to ATAPI (AT Attachment Packet Interface) or other specifications.

The hard disk device 542 is composed of a hard disk, a drive device for driving the hard disk, and the like. The drive device stores data in the hard disk and retrieves the stored data from the hard disk. The optical disc device 543 stores the data in an optical disc (such as a DVD) and extracts the data stored in the optical disc.

The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and transmits the optical signal to the main control device 501. The communication control device 552 controls communication with the Internet, and the communication control device 552 can obtain various information through the Internet.

The image display device 524 includes a screen 700 as shown in FIG. 24 and a display control device 780. As shown in FIG. 25, the screen 700 includes a display 710 composed of a plurality of (n x m) display elements 702 arranged in a matrix.

In addition, as in the example shown in FIG. 26, the display 710 includes n scanning lines arranged at equal intervals along the X-axis direction (that is, X0, X1, X2, X3, ..., Xn-2, Xn- 1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction and m current supply lines arranged at equal intervals along the Y-axis direction (Y0i, Y1i, Y2i, Y3i, ..., Ym-1i). In addition, each display element 702 can be identified based on the scan line and the data line.

As in the example shown in FIG. 27, each display element 702 includes an organic EL element 750 and a driving circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. In addition, the display 710 is a 32-inch color display, however, the size of the display 710 is not particularly limited.

As in the example shown in FIG. 28, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714.

The organic EL element 750 may be arranged beside the FET, for example. In this case, the organic EL element 750 and the FET can be formed on the same substrate. However, the configuration of the organic EL element 750 is not particularly limited. For example, the organic EL element 750 may be arranged above the FET. In this case, the gate electrode needs to be transparent. Therefore, it is preferable to use, for example, ITO, indium oxide (In ₂ O ₃ ), tin dioxide (SnO ₂ ), zinc oxide (ZnO) or gallium (Ga) added zinc oxide (ZnO), aluminum (Al) added oxide A conductive transparent oxide such as tin dioxide (SnO ₂ ) added with zinc (ZnO) and antimony (Sb) is used as the gate electrode.

Aluminum (Al) is used as the cathode 712 provided on the organic EL element 750. It should be noted that magnesium (Mg)-silver (Ag) alloy, aluminum (Al)-lithium (Li) alloy, and indium tin oxide (ITO) may also be used as the cathode 712. As the anode 714, ITO was used. It should be noted that conductive oxides such as indium oxide (In ₂ O ₃ ), tin dioxide (SnO ₂ ) or zinc oxide (ZnO), and silver (Ag)-neodymium (Nd) alloys, etc. can also be used as anodes 714.

The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. In addition, the cathode 712 is connected to the electron transport layer 742, and the anode 714 is connected to the hole transport layer 746. The light-emitting layer 744 emits light by applying a predetermined voltage between the anode 714 and the cathode 712.

In addition, as shown in FIG. 27, the driving circuit 720 includes two FETs 810 and 820 and a condenser 830. The FET 810 is used as a switching element. The gate electrode G is connected to a predetermined scan line, and the source electrode S is connected to a predetermined data line. In addition, the drain electrode D is connected to one end of the capacitor 830.

The capacitor 830 is provided to store the state of the FET 810, in other words, to store data. The other end of the capacitor 830 is connected to a predetermined current supply line.

The FET 820 is provided to supply a large amount of current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the FET 810. In addition, the drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

Here, when the FET 810 turns to the "ON" state, the FET 820 drives the organic EL element 750

As in the example shown in FIG. 29, the display control device 780 includes an image data processing circuit 782, a scanning line drive circuit 784, and a data line drive circuit 786.

The video data processing circuit 782 determines the brightness of the plurality of display elements 702 of the display 710 based on the output signal from the video output circuit 523. The scanning line driving circuit 784 applies voltage to specific n scanning lines according to instructions from the image data processing circuit 782. The data line drive circuit 786 applies a voltage to specific m data lines according to instructions from the image data processing circuit 782.

As explained above, the television device 500 according to the twelfth embodiment has an image data generation unit composed of an image decoder 521, an image-OSD synthesis circuit 522, an image output circuit 523, and an OSD rendering circuit 525 .

In addition, in the above example, it is explained that the optical control element is an organic EL element, however, the optical control element is not particularly limited. The optical control element may be, for example, a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element.

For example, in the case where the optical control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 30, the display element 703 does not require a current supply line.

In addition, as in the example shown in FIG. 20, the driving circuit 730 may be composed of only one FET 840, and the FET 840 is similar to the FET 810 and FET 820 shown in FIG. 27. The FET 840 has a gate electrode G and a source electrode S, where the gate electrode G is connected to a predetermined scan line, and the source electrode S is connected to a predetermined data line. In addition, the drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. The element symbols 762 and 772 in FIG. 31 indicate the paired electrodes (that is, common electrodes) of the capacitor 760 and the liquid crystal element 770, respectively.

In addition, in the above example, it is explained that the system is a television device, however, the system is not particularly limited. That is, the system only needs to include the above-mentioned image display device 524 as a device for displaying images and information. For example, the system may be a computer system in which a computer (such as a personal computer) and the image display device 524 are connected to each other.

In addition, the image display device 524 can be used as a display unit in mobile information devices (eg, mobile phones, mobile music players, mobile video players, e-books, and personal digital assistants (PDAs)); it can also be used in image capture devices ( (Such as digital cameras or camcorders). In addition, the image display device 524 can be used for a display unit installed in a transportation system (such as vehicles, airplanes, trains, and ships) for displaying various information. In addition, the image display device 524 can be used for a display unit for displaying various information installed in a measuring device, an analyzing device, a medical device, an advertising medium, or the like.

[Example 1]

In Example 1, the bottom gate/bottom contact FET 10 as shown in FIG. 1 is manufactured.

(Formation of gate electrode)

First, the gate electrode 12 is formed on the substrate 11. Specifically, a conductive Mo film is formed on the substrate 11 made of glass by direct-current (DC) sputtering method, so that the average film thickness is about 100 nm. Subsequently, the gate electrode 12 is coated with a photoresist material, and then pre-baked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the gate electrode 12. Then, the part of the Mo film not covered by the photoresist pattern is removed by reactive ion eating (RIE). Then, the photoresist pattern is also removed to form the gate electrode 12.

(Formation of gate insulating layer)

Next, the gate insulating layer 13 is formed. First, a coating liquid for forming a gate insulating layer is prepared. Specifically, by mixing 1.2 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (7% La; Wako 122-03371; product of WAKO CHEMICAL, LTD.), 0.57 mL of 2-ethyl Strontium hexanoate toluene solution (2% Sr; Wako 195-09561; product of WAKO CHEMICAL, LTD.) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (12% Zr; Wako 269-01116; WAKO CHEMICAL, LTD. product), to prepare a coating solution for forming the gate insulating layer.

Next, a coating droplet for forming the gate insulating layer is deposited on the substrate 11 and the gate electrode 12, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm). Subsequently, the Mo/Al/Mo laminated film was coated with a photoresist (TSMR-8800BE; a product of TOKYO OHKA KOGYO Co., Ltd.), and then prebaked, exposed through an exposure device, and developed to form a material having The photoresist pattern of the formed gate insulating layer 13.

Next, the portion of the Sr-La-Zr oxide not covered by the photoresist pattern is etched by soaking in 0.1 mol/L hydrochloric acid (Wako 083-01115; product of Wako Pure Chemical Industries, Ltd.) for 30 seconds, and then The photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104; a product of TOKYO OHKA KOGYO Co., Ltd.) for 2 minutes to form the gate insulating layer 13. Here, part of the Sr-La-Zr oxide is removed to expose part of the gate electrode 12 so that a voltage can be applied to the gate electrode 12.

(Formation of source electrode and drain electrode)

Next, the source electrode 14 and the drain electrode 15 are formed. Specifically, a conductive Mo film is formed on the gate insulating layer 13 by the DC sputtering method, so that the average film thickness is about 100 nm. Subsequently, the Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the source electrode 14 and the drain electrode 15. Then, the part of the Mo film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the source electrode 14 and the drain electrode 15.

(Form active layer)

Next, the active layer 16 is formed. Specifically, the Mg-In-based oxide (In ₂ MgO ₄ ) thin film is formed by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, an Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the active layer 16. Then, the part of the Mg-In-based oxide film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the active layer 16. Through the above steps, the active layer 16 is obtained to form a channel between the source electrode 14 and the drain electrode 15.

(Formation of passivation layer)

Next, a passivation layer 17 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a passivation layer 17. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the passivation layer 17.

Through the above steps, the bottom gate/bottom contact FET 10 is manufactured.

[Example 2]

The FET 10 was manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Formation of Gate Insulation Layer)", the etchant used for Sr-La-Zr was 5% oxalic acid.

[Example 3]

The FET 10 was manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Formation of Gate Insulation Layer)", the etchant used for Sr-La-Zr was 20% nitric acid.

[Example 4]

The FET 10 was manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Gate Insulation Formation)", the etchant for Sr-La-Zr was 50% phosphoric acid.

[Example 5]

The FET 10 was manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Formation of Gate Insulation Layer)", the etchant for Sr-La-Zr was 5% acetic acid and soaked in The time of the etchant is other than 6 minutes.

[Example 6]

The FET 10 was manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Gate Insulation Formation)", the etchant used for Sr-La-Zr was 10% sulfuric acid.

[Example 7]

The FET 10 is manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Formation of Gate Insulation Layer)", the etchant for Sr-La-Zr is 20% nitric acid, Other than the mixed solution of 60% phosphoric acid and 2.0% water.

[Example 8]

The FET 10 is manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Formation of Gate Insulation Layer)", the etchant for Sr-La-Zr contains 5% nitric acid, Other than the mixed solution of 80% phosphoric acid, 10% acetic acid and 5.0% water.

[Example 9]

The FET 10 was manufactured in exactly the same manner as used in Example 1, except that in the step corresponding to Example 1 "(Formation of Gate Insulation Layer)", the etchant used for Sr-La-Zr was 5% hydrogen peroxide.

[Example 10]

In Example 10, the top gate/self-aligned FET 120 as shown in FIG. 5 was manufactured.

(Form active layer)

First, the active layer 122 is formed on the substrate 121. Specifically, an Mg-In-based oxide (In ₂ MgO ₄ ) thin film is formed on the substrate 121 made of glass by the DC sputtering method, so that the average thin film thickness is about 100 nm. Subsequently, the Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the active layer 122. Then, the part of the Mg-In-based oxide film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the active layer 122.

(Formation of gate insulating layer and gate electrode)

Next, the gate insulating layer 123 is formed. On the substrate 121 and the active layer 122, the same coating droplets used for forming the gate insulating layer as used in Example 1 were applied on the substrate 121 and the active layer 122, and then a spin coating process was performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm). Then, a conductive Mo/Al/Mo laminated film is formed by the DC sputtering method so that the average film thickness is about 300 nm (that is, 50 nm/200 nm/50 nm). Subsequently, the Mo/Al/Mo laminated film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the gate electrode 124. Then, the Mo/Al/Mo laminated film and Sr-La-Zr oxide were immersed in a mixed solution containing 5% nitric acid, 80% phosphoric acid, 10% acetic acid, and 5% water for 30 seconds to move Except for the parts of the Mo/Al/Mo laminated film and Sr-La-Zr oxide that are not covered by the photoresist pattern. Then, the photoresist pattern is also removed to form the gate insulating layer 123 and the gate electrode 124.

(Forming an interlayer insulating layer)

Next, an interlayer insulating layer 127 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having an interlayer insulating layer 127. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the interlayer insulating layer 127.

(Formation of source electrode and drain electrode)

Next, the source electrode 125 and the drain electrode 126 are formed. Specifically, a conductive Mo/Al/Mo laminated film is formed on the interlayer insulating layer 127 by the DC sputtering method so that the average film thickness is about 300 nm (that is, 50 nm/200 nm/50 nm). Subsequently, the Mo/Al/Mo laminated film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the source electrode 125 and the drain electrode 126. Then, the part of the Mo/Al/Mo laminated film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to obtain a source electrode 125 and a drain electrode 126 formed of a Mo/Al/Mo laminated film.

(Formation of passivation layer)

Next, a passivation layer 128 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the passivation layer 128. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Next, the photoresist pattern is also removed to form the passivation layer 128. Through the above steps, the top gate/self-aligned FET 120 is manufactured.

(Evaluate transistor characteristics)

The transistor characteristics of each of the FETs manufactured in Examples 1 to 10 were evaluated. The evaluation of transistor characteristics is based on the voltage (Vgs) between the gate electrode 12 and the source electrode 14 and the source electrode 14 when the voltage (Vds) between the source electrode 14 and the drain electrode 15 is +10V Measurement of the relationship (Vgs-Ids) with the current (Ids) of the drain electrode 15.

Furthermore, based on the evaluation result of the transistor characteristics (Vgs-Ids), the field-effect mobility in the saturation region is calculated. Further, the S value is calculated as an indicator of the rise-sharpness of Ids that responds to the application of Vgs. Further, the ratio (ie, on/off ratio) of the transistor from Ids in the "on" state (for example, Vgs=+10V) to the "off" state (for example, Vgs=-10V) is calculated. Further, a threshold voltage (Vth) is calculated, which is a voltage value corresponding to an increase in Ids in response to the application of Vgs.

Regarding the results of the transistor characteristics, the preferred transistor characteristics are: high mobility; high on/off ratio; low S value; and Vth around 0V. In particular, preferred transistor characteristics: mobility 3cm ² / Vs or more; on / off ratio of more than 1.0 x 10 ^8; S values below 0.7; and Vth is a range of ± 5V.

Furthermore, the capacitance of the gate insulating layer is also measured to calculate the dielectric constant. When the gate insulating layer has a dielectric constant of 6 or more, the energy consumption is considered to be low.

The evaluation results of the transistor characteristics of the FETs manufactured in Examples 1 to 10 are shown in Table 1. Note that all the FETs manufactured in Examples 1 to 10 have better transistor characteristics. Furthermore, the dielectric constants of the gate insulating layers according to Examples 1 to 10 are all about 13, so the power consumption of the FET is considered to be low.

As described above, it is confirmed that high-quality FETs can be produced using the first oxide for the gate insulating layer and the low-cost patterning process using wet etching on the first oxide.

[Table 1]

[Example 11]

In Example 11, the bottom gate/bottom contact FET 10 as shown in FIG. 1 was manufactured.

(Formation of gate electrode)

First, the gate electrode 12 was formed on the substrate 11 in the same manner as in Example 1.

(Formation of gate insulating layer)

Next, the gate insulating layer 13 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a gate insulating layer 13. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the gate insulating layer 13.

(Formation of source electrode and drain electrode)

Next, the source electrode 14 and the drain electrode 15 are formed on the substrate 11 in the same manner as in Example 1.

(Form active layer)

Next, the active layer 16 is formed in the same manner as in Example 1.

(Formation of passivation layer)

Next, a passivation layer 17 is formed. First, a coating liquid for forming a passivation layer is prepared. Specifically, by mixing 1.2 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a passivation layer.

Next, the coating droplets used to form the passivation layer are on the substrate 11, the gate electrode 12, the gate insulating layer 13, the source electrode 14, the drain electrode 15 and the active layer 16, and then proceed under predetermined conditions Spin coating procedure. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm). Subsequently, the Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a passivation layer 17 corresponding to the formation.

Next, etch the part of Sr-La-Zr oxide not covered by the photoresist pattern by immersing in 0.1 mol/L hydrochloric acid (ie, Wako 083-01115) for 30 seconds, and then immerse in the photoresist stripper (Ie, STRIPPER 104; product of TOKYO OHKA KOGYO Co., Ltd.) for 2 minutes to remove the photoresist pattern to form the passivation layer 17. Here, part of the Sr-La-Zr oxide is removed to expose part of the gate electrode 12, source electrode 14 and drain electrode 15, so that voltage can be applied to the gate electrode 12, source electrode 14 and drain electrode Electrode 15.

[Example 12]

The FET 10 was manufactured in exactly the same method as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 5% oxalic acid.

[Example 13]

The FET 10 was manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 20% nitric acid.

[Example 14]

The FET 10 was manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 50% phosphoric acid.

[Example 15]

The FET 10 was manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 5% acetic acid and soaked in the etchant The time is 6 minutes away.

[Example 16]

The FET 10 was manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 10% sulfuric acid.

[Example 17]

The FET 10 was manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 20% nitric acid, 60% Other than a mixed solution of phosphoric acid and 20% water.

[Example 18]

The FET 10 is manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr contains 5% nitric acid, 80% Other than a mixed solution of phosphoric acid, 10% acetic acid and 5.0% water.

[Example 19]

The FET 10 was manufactured in exactly the same manner as used in Example 11, except that in the step corresponding to Example 11 "(Formation of Passivation Layer)", the etchant used for Sr-La-Zr was 5% hydrogen peroxide.

(Evaluate transistor characteristics)

In the same manner as that employed in Example 1 to Example 10, the mobility, on/off ratio, S value, and critical voltage (Vth) were calculated for each FET manufactured in Example 11 to Example 19. Furthermore, for each FET manufactured in Examples 11 to 19, a BTS test of 100 hours in this environment (temperature: 50°C; relative humidity: 50%) was performed.

Provide the following 4 conditions as pressure conditions:

(1) Vgs=+10V, and Vds=0V

(2) Vgs=+10V, and Vds=+10V

(3) Vgs=-10V, and Vds=0V

(4) Vgs=-10V, and Vds=+10V

In the BTS test, whenever a predetermined length of time passes, measure the relationship between Vgs and Ids under Vds=+10V (Vgs-Ids) to evaluate the deviation of the critical voltage (△Vth ). When the shift of the critical voltage (ΔVth) at a pressurization time of 100 hours is 3V or less, the FET is considered to be reliable.

The evaluation results of the transistor characteristics of the FETs manufactured in Examples 11 to 19 are shown in Table 2. Note that all the FETs manufactured in Examples 11 to 19 have better transistor characteristics. Also, note that for each result, the threshold voltage shift (ΔVth) is less than 1V, so the FET is considered to have high reliability.

As described above, it is confirmed that high-quality FETs can be produced using the first oxide used for the passivation layer and the low-cost patterning process using wet etching on the first oxide.

[Table 2]

[Example 20]

In Example 20, the organic EL display element 200 shown in FIG. 6 was manufactured. First, the first gate electrode 22 and the second gate electrode 32 are formed on the substrate 21. Specifically, a Mo thin film is formed on the substrate 21 made of alkali-free glass by a DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, the Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern to be formed. Then, the part of the Mo film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the first gate electrode 22 and the second gate electrode 32.

Next, a gate insulating layer 23 is formed on the substrate 21, the first gate electrode 22, and the second gate electrode 32. First, a coating liquid 1L for forming a gate insulating layer having the same composition as Example 1 was prepared.

Next, the coating solution for forming the gate insulating layer is applied to the substrate 21, the first gate electrode 22, and the second gate electrode 32 by a slit coating method. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm).

Then, Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then pre-baked, exposed through an exposure device, and developed to form a photoresist having a gate insulating layer 23 corresponding to the formation pattern.

Next, etch the part of Sr-La-Zr oxide that is not covered by the photoresist pattern by immersing in 0.1mol/L hydrochloric acid (Wako 083-01115) for 30 seconds, and then immerse in the photoresist stripper (ie , STRIPPER 104; product of TOKYO OHKA KOGYO Co., Ltd.) for 2 minutes to remove the photoresist pattern to form a gate insulating layer 23 having a through hole on the second gate electrode 32.

Then, the first source electrode 24, the second source electrode 34, the first drain electrode 25, and the second drain electrode 35 are formed. Specifically, a transparent and conductive ITO thin film is formed on the gate insulating layer 23 by the DC sputtering method, so that the average film thickness is about 100 nm. Subsequently, the ITO film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern to be formed.

Furthermore, the part of the ITO film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the first source electrode 24, the second source electrode 34, the first drain electrode 25, and the second drain electrode 35. In this way, the first drain electrode 25 and the second gate electrode 32 are connected by the through hole formed in the gate insulating layer 23.

Next, the first active layer 26 and the second active layer 36 are formed. Specifically, the Mg-In-based oxide thin film is formed by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, the Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern to be formed. Then, the part of the Mg-In-based oxide film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the first active layer 26 and the second active layer 36.

In this way, the first active layer 26 is formed so that the channel is formed between the first source electrode 24 and the first drain electrode 25. Furthermore, the second active layer 36 is formed so that the channel is formed between the second source electrode 34 and the second drain electrode 35.

Next, the first passivation layer 27 and the second passivation layer 37 are formed. First, a coating liquid for forming a passivation layer is prepared. Specifically, by mixing 1.2 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a passivation layer.

Next, apply the coating droplets used to form the gate insulating layer on the substrate 21, the first gate electrode 22, the second gate electrode 32, the gate insulating layer 23, the first source electrode 24, the first drain On the electrode 25, the second source electrode 34, the second drain electrode 35, the first active layer 26, and the second active layer 36, a spin coating process is then performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm). Then, the Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then pre-baked, exposed through an exposure device, and developed to form the first passivation layer 27 and the second corresponding to the desired formation The photoresist pattern of the passivation layer 37.

Next, etch the part of Sr-La-Zr oxide that is not covered by the photoresist pattern by immersing in 0.1mol/L hydrochloric acid (Wako 083-01115) for 30 seconds, and then immerse in the photoresist stripper (ie , STRIPPER 104) for 2 minutes to remove the photoresist pattern to form the first passivation layer 27 and the second passivation layer 37. Through the above steps, the drive circuit substrate 321 of the double transistor/single capacitor is manufactured.

Next, an interlayer insulating film 220 (ie, a polarizing film) is formed on the driving circuit 210. Specifically, a positive photosensitive organic material (SUMIRESIN EXCEL® CRC series; a product of Sumitomo Bakelite Co., Ltd.) is applied by spin coating, and then pre-baked, exposed through an exposure device, and developed to form a desired pattern. Then, a post-baking process was performed at a temperature of 320°C for 30 minutes to form an interlayer insulating film 220 provided with perforations 220x on the second drain electrode 35. The average thin film thickness of the interlayer insulating film 220 formed in this way is about 3 μm.

Next, a lower electrode 231 formed as a pixel electrode. Specifically, the Ag-Pd-Cu thin film and the ITO thin film are continuously formed by the DC sputtering method, so that the average film thickness of each layer is about 100 nm. Subsequently, the Ag-Pd-Cu film and the ITO film are coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to obtain a desired photoresist pattern. Then, the ITO film and the Ag-Pd-Cu film are sequentially removed by RIE. Then, the photoresist pattern is also removed to form the lower electrode 231.

Next, the partition 240 is formed. Specifically, a positive photosensitive polyimide resin (DL-1000; a product of Toray Industries, Inc.) is applied by spin coating, then pre-baked, exposed through an exposure device, and developed to form a desired pattern . Then, the post-baking process is performed at a temperature of 230° C. for 30 minutes to form the partition wall 240.

Then, by means of inkjet equipment, an organic EL layer 232 is formed on the lower electrode 231 using a high molecular weight organic light emitting material.

Next, the upper electrode 233 is formed. Specifically, the upper electrode 233 is formed on the organic EL layer 232 and the partition wall 240 by vacuum deposition of MgAg.

Next, the sealing layer 250 is formed. Specifically, the SiN thin film is formed by the plasma CVD method so that the average thin film thickness is about 2 μm to form the sealing layer 250 on the upper electrode 233.

Then, attachment to the insulating substrate 270 is performed. Specifically, an adhesive layer 260 is formed on the sealing layer 250 and then attached to the opposite insulating substrate 270 as an alkali-free glass substrate.

The organic EL display element 200 manufactured through the above steps shows a quality with low power consumption and high reliability.

As described above, high-quality organic EL display elements can be produced using the first oxide for the first insulating layer and the passivation layer and the low-cost patterning process using wet etching on the first oxide.

[Example 21]

In Example 21, the organic EL display element 200A shown in FIG. 7 was manufactured. Specifically, the organic EL display element 200A was manufactured in exactly the same manner as in Example 20, except that the first passivation layer 27 and the second passivation layer 37 (see FIG. 6) in Example 20 were changed to the integrated passivation layer 27A.

The manufactured organic EL display element 200A shows a quality with low energy consumption and high reliability.

As described above, using the first oxide for the gate insulating layer and the passivation layer and the low-cost patterning process using wet etching on the first oxide can produce a high-quality organic EL display element.

[Example 22]

In Example 22, the FET 50 (ie, MOS-FET) as shown in FIG. 8 is manufactured. First, a coating liquid for forming a gate insulating layer is prepared to form a gate insulating layer 53 on a substrate 51 (8 inches) containing p-type Si. Specifically, by mixing 4.0 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating solution for forming a passivation layer.

Next, a coating droplet for forming a gate insulating layer is deposited on the substrate 51, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 10 nm).

Next, a polysilicon film is formed by CVD, and then patterned on the polysilicon film by photolithography to form the gate electrode 52. Then, using the gate electrode 52 as a mask, the portion of the Sr-La-Zr oxide not covered by the gate electrode 52 is etched by soaking in 0.1 mol/L hydrochloric acid (Wako 083-01115) for 5 seconds to form Gate insulation layer 53.

Next, SiON is deposited by CVD, and then dry etching is performed on the entire substrate to form the gate sidewall insulating film 54. Then, using the gate electrode 52 and the gate sidewall insulation layer 54 as a self-alignment mask, phosphorus ion distribution is performed on the substrate 51 to achieve the purpose of ion diffusion, so as to form the source region 55 and the drain region 56.

Next, SiO ₂ is deposited by CVD, and then photolithography is performed to form an interlayer insulating film 57 having an opening such as a through hole. Finally, an Al layer is deposited by sputtering to fill the through holes, and then patterned by photolithography to form the source electrode 58 and the drain electrode 59.

Finally, the passivation layer 111 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, a SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a passivation layer 111 to be formed. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the passivation layer 111. Through the above steps, the FET 50 is manufactured,

The FET 50 manufactured in Example 22 showed low energy consumption quality. Furthermore, the dielectric constant of the gate insulating layer 53 is 13.3, so the energy consumption of the FET is considered to be low.

As described above, high-quality FETs can be produced using the first oxide for the gate insulating layer and the low-cost patterning process using wet etching on the first oxide.

[Example 23]

In Example 23, a volatile semiconductor memory element 60 as shown in FIG. 9 was manufactured. First, a gate electrode 62 and a second capacitor electrode 69 are formed on a substrate 61 made of alkali-free glass. Specifically, the Mo thin film is formed on the substrate 61 by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, a Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the gate electrode 62 and the second capacitor electrode 69 to be formed. Then, the part of the Mo film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the gate electrode 62 and the second capacitor electrode 69.

Next, the gate insulating layer 63 is formed. First, a coating liquid for forming a gate insulating layer is prepared. Specifically, by mixing 1.2 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a gate insulating layer.

Next, the coating droplet for forming the gate insulating layer is deposited on the substrate 61, the gate electrode 62, and the second capacitor electrode 69, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm). Then, Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then pre-baked, exposed through an exposure device, and developed to form a photoresist having a gate insulating layer 63 corresponding to the formation pattern.

Next, etch the part of Sr-La-Zr oxide that is not covered by the photoresist pattern by immersing in 0.1mol/L hydrochloric acid (Wako 083-01115) for 30 seconds, and then immerse in the photoresist stripper (ie , STRIPPER 104) for 2 minutes to remove the photoresist pattern to form the gate insulating layer 63.

Next, a capacitor dielectric layer 68 is formed. The coating droplets for forming the gate insulating layer described above are deposited on the substrate 61, the gate electrode 62, the second capacitor electrode 69, and the gate insulating layer 63, and then the spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 30nm). Then, Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then pre-baked, exposed through an exposure device, and developed to form a photoresist having a capacitance dielectric layer 68 corresponding to the to-be-formed pattern.

Next, etch the part of Sr-La-Zr oxide that is not covered by the photoresist pattern by immersing in 0.1mol/L hydrochloric acid (Wako 083-01115) for 5 seconds, and then immerse in the photoresist stripper (ie , STRIPPER 104) for 2 minutes to remove the photoresist pattern to form the capacitor dielectric layer 68.

Next, the source electrode 64 and the drain electrode 65 are formed. In Example 23, the source electrode 65 forms a capacitor together with the capacitor dielectric layer 68 and the second capacitor electrode 69.

Specifically, a transparent and conductive ITO film is formed on the gate insulating layer 63 and the capacitor dielectric layer 68 by the DC sputtering method, so that the average film thickness is about 100 nm. Subsequently, the ITO film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the source electrode 64 and the drain electrode 65 to be formed. Then, the part of the ITO film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the source electrode 64 and the drain electrode 65.

Next, the active layer 66 is formed. Specifically, the Mg-In-based oxide thin film is formed by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, the Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the active layer 66 to be formed. Then, the part of the Mg-In-based oxide film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the active layer 66. In this way, the active layer 66 is formed so that the channel is formed between the source electrode 64 and the drain electrode 65.

Finally, the passivation layer 112 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the passivation layer 112 to be formed. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the passivation layer 112. Through the above steps, the volatile semiconductor memory device 60 is manufactured.

The volatile semiconductor memory device 60 manufactured in the above steps shows the quality of low energy consumption.

As described above, high-quality volatile semiconductor memory devices can be produced using the first oxide for the gate insulating layer and the capacitor dielectric layer and using a low-cost patterning process that performs wet etching on the first oxide .

[Example 24]

In Example 24, the volatile semiconductor memory element 70 shown in FIG. 10 was manufactured. First, a coating liquid for forming a gate insulating layer is prepared to form a gate insulating layer 73 on a substrate 71 (8 inches) containing p-type Si. Specifically, by mixing 4.0 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a gate insulating layer.

Next, a coating droplet for forming a gate insulating layer is deposited on the substrate 71, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 10 nm).

Next, a polysilicon film is formed by CVD, and then patterned on the polysilicon film by photolithography to form a gate electrode 72. Then, using the gate electrode 72 as a mask, the portion of the Sr-La-Zr oxide not covered by the gate electrode 72 is etched by soaking in 0.1 mol/L hydrochloric acid (Wako 083-01115) for 5 seconds to form Gate insulation layer 73.

Next, SiON is deposited by CVD, and then dry etching is performed on the entire substrate to form the gate sidewall insulating film 74. Then, using the gate electrode 72 and the gate sidewall insulating layer 74 as a self-alignment mask, the phosphor ion distribution is performed on the substrate 71 to achieve the purpose of ion diffusion, so as to form the source region 75 and the drain region 76.

Next, SiO ₂ is deposited by CVD, and then photolithography is performed to form an interlayer insulating film 77 having openings such as through holes. Then, a polysilicon film is deposited by CVD to fill the through holes, and a bit line electrode 78 is formed by photolithography.

Next, SiO ₂ is deposited by a CVD method, and then photolithography is performed to form a second interlayer insulating film 79 having an opening such as a hole in the drain region. Then, a polysilicon film is formed by CVD, and a second capacitor electrode 80 is formed by photolithography.

Next, a capacitor dielectric layer 81 is formed. The coating droplets for forming the gate insulating layer are deposited on the second interlayer insulating film 79 and the second capacitor electrode 80, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 30nm). Then, Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then pre-baked, exposed through an exposure device, and developed to form light having a dielectric layer 81 corresponding to the gate capacitor to be formed Resistance pattern.

Next, etch the part of Sr-La-Zr oxide that is not covered by the photoresist pattern by immersing in 0.1mol/L hydrochloric acid (Wako 083-01115) for 5 seconds, and then immerse in the photoresist stripper (ie , STRIPPER 104) for 2 minutes to remove the photoresist pattern to form the capacitor dielectric layer 81.

Then, a polysilicon film is formed by CVD, and a first capacitor electrode 82 is formed by photolithography. Finally, the passivation layer 113 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a passivation layer 113 to be formed. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the passivation layer 113. Through the above steps, the volatile semiconductor memory element 70 is manufactured.

The volatile semiconductor memory device 70 manufactured in the above steps shows a low energy consumption quality.

As described above, the use of the first oxide for the gate insulating layer and the capacitor dielectric layer and the low-cost patterning process using wet etching on the first oxide can produce high-quality volatile semiconductor memory devices .

[Example 25]

In Example 25, a non-volatile semiconductor memory element 90 as shown in FIG. 11 was manufactured. First, a gate electrode 92 is formed on a substrate 91 made of alkali-free glass. Specifically, the Mo thin film is formed on the substrate 91 by the DC sputtering method so that the average thin film thickness is about 30 nm. Subsequently, a Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the gate electrode 92 to be formed. Then, the part of the Mo film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the gate electrode 92.

Next, the first gate insulating layer 93 is formed. First, a coating liquid for forming a gate insulating layer is prepared. Specifically, by mixing 1.2 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a gate insulating layer.

Next, the coating droplet for forming the gate insulating layer is deposited on the substrate 91 and the gate electrode 92, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 135nm). Then, Sr-La-Zr oxide is coated with a photoresist (ie, TSMR8800-BE), and then prebaked, exposed through an exposure device, and developed to form a photoresist having a gate insulating layer 93 corresponding to the formation pattern.

Next, etch the part of Sr-La-Zr oxide that is not covered by the photoresist pattern by immersing in 0.1mol/L hydrochloric acid (Wako 083-01115) for 30 seconds, and then immerse in the photoresist stripper (ie , STRIPPER 104) for 2 minutes to remove the photoresist pattern to form the first gate insulating layer 93.

Next, a floating gate electrode 94 is formed. Specifically, a Mo film is formed on the first gate insulating layer 93 by the DC sputtering method so that the average film thickness is about 15 nm. Subsequently, a Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a floating gate electrode 94 to be formed. Then, the part of the Mo film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the floating gate electrode 94.

Next, a second gate insulating layer 95 is formed. Specifically, an SiO ₂ film is formed on the first gate insulating layer 93 and the floating gate electrode 94 by CVD, so that the average film thickness is about 50 nm. Subsequently, the SiO ₂ film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the second gate insulating layer 95 to be formed. Then, the part of the SiO ₂ film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the second gate insulating layer 95.

Next, the source electrode 96 and the drain electrode 97 are formed. Specifically, a transparent and conductive ITO film is formed on the second gate insulating layer 95 by the DC sputtering method, so that the average film thickness is about 100 nm. Subsequently, an ITO thin film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the source electrode 96 and the drain electrode 97. Then, the part of the ITO film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the source electrode 96 and the drain electrode 97 from the ITO film.

Then, the active layer 98 is formed. Specifically, the Mg-In-based oxide thin film is formed by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, an Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern corresponding to the active layer 98 to be formed. Then, the part of the Mg-In-based oxide film not covered by the photoresist pattern is removed by RIE. Next, the photoresist pattern is also removed to form the active layer 98.

In this way, the active layer 98 is formed so that the channel is formed between the source electrode 96 and the drain electrode 97.

Finally, the passivation layer 114 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a passivation layer 114 to be formed. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the passivation layer 114. Through the above steps, the non-volatile semiconductor memory device 90 is manufactured.

The non-volatile semiconductor memory device 90 manufactured in the above steps shows the quality of low energy consumption.

As described above, high-quality non-volatile semiconductor memory devices can be produced by using the first oxide for the first gate insulating layer and the low-cost patterning process using wet etching on the first oxide.

[Example 26]

In Example 26, the nonvolatile semiconductor memory device 100 shown in FIG. 12 was manufactured. First, thermal energy oxidation is performed on the surface of the substrate 101 containing p-type Si to form a SiO ₂ thin film with a thin film thickness of 5 nm, which eventually becomes the second gate insulating layer 104. Then, a polysilicon thin film which eventually becomes the floating gate electrode 105 is formed by the CVD method.

Next, a coating liquid for forming the gate insulating layer is prepared to form the first gate insulating layer 102. Specifically, by mixing 4.0 mL of cyclohexylbenzene, 1.95 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), and 0.57 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195 -09561) and 0.09 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a gate insulating layer.

Next, a coating droplet for forming a passivation layer is deposited on the substrate 101, and then a spin coating process is performed under predetermined conditions. Then, after performing a drying program for 1 hour in an environment of 120°C, a burning program was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a paraelectric and amorphous Sr-La-Zr oxide ( With a film thickness of 10 nm).

Next, a polysilicon film is formed by CVD, and then patterned on the polysilicon film by photolithography to form the gate electrode 103. Then, using the gate electrode 103 as a mask, the portion of the Sr-La-Zr oxide not covered by the gate electrode 103 is etched by soaking in 0.1 mol/L hydrochloric acid (Wako 083-01115) for 5 seconds to form First gate insulating layer 102. Furthermore, the polysilicon film and the SiO ₂ film under the first gate insulating layer 102 are sequentially etched by dry etching to form a floating gate electrode 105 and a second gate insulating layer 104 (ie, channel insulating layer).

Next, SiON is deposited by CVD, and then dry etching is performed on the entire substrate to form the gate sidewall insulating film 106. Then, using the gate electrode 103 and the gate sidewall insulating layer 106 as a self-alignment mask, phosphorus ion distribution is performed on the substrate 101 to achieve the purpose of ion diffusion, so as to form the source region 107 and the drain region 108.

Finally, the passivation layer 115 is formed. Specifically, the SiON film is formed by the plasma CVD method so that the average film thickness is about 300 nm. Subsequently, the SiON film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to form a photoresist pattern having a passivation layer 115 to be formed. Then, the part of the SiON film not covered by the photoresist pattern is removed by RIE. Then, the photoresist pattern is also removed to form the passivation layer 115. Through the above steps, the non-volatile semiconductor memory device 100 is manufactured.

The non-volatile semiconductor memory device 100 manufactured in the above steps shows the quality of low energy consumption.

As described above, using the first oxide for the gate insulating layer and the low-cost patterning process using wet etching on the first oxide, a high-quality non-volatile semiconductor memory device can be produced.

[Example 27]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.14 mL of HMDS, and 0.37 mL of 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (3 to 8% Ca; Alfa 36657; product of Alfa Aesar), prepared for the formation of the first passivation Layer of coating liquid. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 2.17 mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371) and 0.63 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195-09561) To prepare a coating solution for forming a passivation layer. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 3.

[table 3]

Then, an example of the bottom contact/top gate FET shown in FIG. 16B is manufactured.

-Formation of source electrode and drain electrode-

First, the gate electrode 14 and the drain electrode 15 are formed on the substrate 11 made of glass. Specifically, an Al alloy thin film is formed on the substrate 11 by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, the Al alloy film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to produce a photoresist pattern having the same source electrode 14 and drain electrode 15 to be formed. Then, the portion of the Al film not covered by the photoresist pattern is removed in an etching procedure. Then, the photoresist pattern is also removed to obtain the source electrode 14 and the drain electrode 15 formed of the Al alloy thin film.

-Form active layer-

Next, the active layer 16 is formed. Specifically, the Mg-In-based oxide (In ₂ MgO ₄ ) thin film is formed by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, an Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to produce a photoresist pattern having the same active layer 16 to be formed. Then, the part of the Mg-In-based oxide film not covered by the photoresist pattern is removed through an etching process. Then, the photoresist pattern is also removed to obtain an active layer to form a channel between the source electrode 14 and the drain electrode 15.

-Formation of gate insulating layer-

Next, a gate insulating layer 13 is formed on the substrate 11, the source electrode 14, the drain electrode 15 and the active layer 16. Specifically, an Al ₂ O ₃ film is formed on the substrate 11, the source electrode 14, the drain electrode 15 and the active layer 16 by radio-frequency (RF) sputtering method, so that the average film thickness is about 300 nm .

-Formation of gate electrode-

Next, the gate electrode 12 is formed on the gate insulating layer 13. Specifically, a Mo film is formed on the gate insulating layer 13 by the DC sputtering method so that the average film thickness is about 100 nm. Subsequently, a Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to produce a photoresist pattern having the same gate electrode 12 to be formed. Then, the part of the Mo film not covered by the photoresist pattern is removed in an etching procedure. Then, the photoresist pattern is also removed to obtain the gate electrode 12 formed of the Mo film.

-Forming a first passivation layer 170a-

Next, apply 0.4 mL of the coating droplets used to form the first passivation layer on the gate insulating layer 13 and the gate electrode 12, and then perform the spin coating procedure under predetermined conditions: spin at a speed of 3000 rmp 20 Seconds, then reduce the speed to 0 rpm in 5 seconds and stop spinning. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Forming a second passivation layer 170b-

Next, place 0.6 mL of the coating droplets used to form the second passivation layer on the first passivation layer 170a, and then perform the spin coating procedure under predetermined conditions: spin at 500 rpm for 5 seconds, and then at 3000 rpm For 20 seconds, then reduce the speed to 0 rpm in 5 seconds and stop spinning. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Form a mask-

Next, the second passivation layer 170b (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then prebaked, exposed through an exposure device, and developed to produce a The photoresist pattern of the two passivation layers 17b is the same.

-Etching procedure for the second passivation layer 170b-

Next, the second passivation layer 170b is immersed in 0.36wt% hydrochloric acid (ie, Wako 083-01115) for 20 seconds as an etching procedure to remove the portion of the first oxide film that is not covered by the photoresist pattern to obtain the first二passivation layer 17b.

-Etching procedure for the first passivation layer 170a-

Next, the first passivation layer 170a is immersed in 2.5wt% hydrochloric acid for 15 seconds as an etching procedure to remove the portion of the second oxide film not covered by the photoresist pattern to obtain the first passivation layer 17a.

-Remove mask-

Next, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104; product of TOKYO OHKA KOGYO Co., Ltd.) for 2 minutes.

[Example 28]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.13 mL of HMDS, 0.32 mL of 2-ethylhexanoic acid magnesium toluene solution (3% Mg; Strem 12-1260; product of Strem Chemicals Inc.) and 0.40 mL of 2-ethylhexanoic acid A barium toluene solution (8% Ba; Wako 021-09471; product of WAKO CHEMICAL, LTD.) prepares a coating solution for forming the first passivation layer. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 0.54 g of tris(2,2,6,6-tetramethyl-3,5-heptanedione acid) scandium(III) hydrate (SIGMA-ALDRICH 517607; Sigma-Aldrich Co. LLC product), 0.12 mL of 2-ethylhexanoic acid magnesium toluene solution (ie, Strem 12-1260) and 0.08 mL of 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (ie, Alfa36657) To prepare a coating solution for forming the second passivation layer. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 3.

Next, the bottom contact/top gate FET as described in Example 27 was fabricated. However, compared to Example 27, the stacking order of the first passivation layer 17a and the second passivation layer 17b is reversed.

-Formation of source electrode and drain electrode-

First, the gate electrode 14 and the drain electrode 15 are formed on the substrate 11 made of glass. Specifically, an Al alloy thin film is formed on the substrate 11 by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, the Al alloy film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to produce a photoresist pattern having the same source electrode 14 and drain electrode 15 to be formed. Then, the part of the Al film not covered by the photoresist pattern is removed in an etching procedure. Then, the photoresist pattern is also removed to obtain the source electrode 14 and the drain electrode 15 formed of the Al alloy thin film.

-Form active layer-

Next, the active layer 16 is formed. Specifically, the Mg-In-based oxide (In ₂ MgO ₄ ) thin film is formed by the DC sputtering method so that the average thin film thickness is about 100 nm. Subsequently, an Mg-In-based oxide film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to produce a photoresist pattern having the same active layer 16 to be formed. Then, the portion of the Mg-In-based oxide film not covered by the photoresist pattern is removed in an etching procedure. Then, the photoresist pattern is also removed to obtain an active layer, so that a channel is formed between the source electrode 14 and the drain electrode 15.

-Formation of gate insulating layer-

Next, a gate insulating layer 13 is formed on the substrate 11, the source electrode 14, the drain electrode 15 and the active layer 16. Specifically, an Al ₂ O ₃ thin film is formed on the substrate 11, the source electrode 14, the drain electrode 15 and the active layer 16 by RF sputtering, so that the average film thickness is about 300 nm.

-Formation of gate electrode-

Next, the gate electrode 12 is formed on the gate insulating layer 13. Specifically, a Mo film is formed on the gate insulating layer 13 by the DC sputtering method so that the average film thickness is about 100 nm.

Subsequently, a Mo film is coated with a photoresist, and then prebaked, exposed through an exposure device, and developed to produce a photoresist pattern having the same gate electrode 12 to be formed. Then, the part of the Mo film not covered by the photoresist pattern is removed in an etching procedure. Then, the photoresist pattern is also removed to obtain the gate electrode 12 formed of the Mo film.

-Forming a second passivation layer 170b-

Next, place 0.6 mL of the coating droplets used to form the second passivation layer on the gate insulating layer 13 and the gate electrode 12, and then perform the spin coating procedure under predetermined conditions: spin at a speed of 500 rpm 5 Seconds, then at 3000 rpm for 20 seconds, then use 5 seconds to reduce the speed to 0 rpm and stop spinning. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Forming a first passivation layer 170a-

Next, place 0.4 mL of the coating droplet used to form the first passivation layer on the second passivation layer 170b, and then perform the spin-coating procedure under predetermined conditions: spin at 3000 rpm for 20 seconds, and then use 5 Seconds to reduce the speed to 0 rpm and stop spinning. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

Next, the first passivation layer 170a (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce a A passivation layer 17a has the same photoresist pattern.

-Etching procedure for the first passivation layer 170a-

Next, the first passivation layer 170a is immersed in a mixed solution containing 19wt% ammonium fluoride and 18wt% ammonium bifluoride for 15 seconds as an etching process to remove the portion of the second oxide film not covered by the photoresist pattern To obtain the first passivation layer 17a.

-Etching procedure for the second passivation layer 170b-

Next, the second passivation layer 170b is immersed in 5wt% oxalic acid heated to 30°C for 4 minutes as an etching procedure to remove the portion of the first oxide film not covered by the photoresist pattern to obtain the second passivation layer 17b.

-Remove mask-

Next, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

[Example 29]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.11 mL of HMDS, 0.13 mL of aluminum bis (isobutoxy) acetoacetate chelate (8.4% Al; Alfa 89349; product of Alfa Aesar) and 2.02 mL of 2-ethyl A strontium hexanoate toluene solution (ie, Wako 195-09561) prepares a coating solution for forming the first passivation layer. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 0.19 g of acetoacetone-samarium trihydrate (Strem 93-6226; a product of Strem Chemicals, Inc.), 0.27 mL of a 2-ethylhexanoic acid toluene solution (25% Gd ; Strem 64-3500; a product of Strem Chemicals Inc.) and 0.49 mL of 2-ethylhexanoic acid barium toluene solution (ie, Wako 021-09471) to prepare a coating liquid for forming the second passivation layer. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 3.

Then, a bottom contact/top gate FET as shown in FIG. 16B is manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Forming a first passivation layer 170a-

Then, 0.4 mL of the coating droplet used to form the first passivation layer was deposited on the gate insulating layer 13 and the gate electrode 12, and then a spin-coating procedure was performed under predetermined conditions: spin at 3000 rpm for 20 seconds , Then reduce the speed to 0 rpm in 5 seconds and stop the rotation. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Forming a second passivation layer 170b-

Then, 0.6 mL of the coating droplet for forming the second passivation layer was placed on the first passivation layer 170a, and then a spin coating procedure was performed under predetermined conditions: rotation at 500 rpm for 5 seconds, and then at 3000 rmp Speed for 20 seconds, then reduce the speed to 0 rpm in 5 seconds and stop spinning. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Form a mask-

Then, the second passivation layer 170b (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce a second film with the desired The passivation layer 17b has the same photoresist pattern.

-Etching procedure for the second passivation layer 170b-

Then, the second passivation layer 170b is immersed in a mixed solution containing 57.9wt% phosphoric acid and 21.1wt% nitric acid for 30 seconds as an etching procedure to remove the portion of the first oxide film not covered by the photoresist pattern, The second passivation layer 17b is obtained.

-Etching procedure for the first passivation layer 170a-

Then, the first passivation layer 170a is immersed in 4wt% tetramethylammonium hydroxide (TMAH) for 1 minute as an etching process to remove the portion of the second oxide not covered by the photoresist pattern to obtain the first Passivation layer 17a.

-Remove mask-

Then, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

[Example 30]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.11 mL of HMDS, 0.08 g of (4,4,5,5-tetramethyl-1,3,2-dioxaborol-2-yl)benzene (Wako 325-59912 ; A product of WAKO CHMICAL, LTD.) and 0.37 mL of a 2-ethylhexanoic acid magnesium toluene solution (ie, Strem 12-1260) to prepare a coating liquid for forming the first passivation layer. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 3.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 0.57 mL of 2-ethylhexanoic acid neodymium 2-ethylhexanoic acid solution (12% Nd; Strem 60-2400; product of Strem Chemicals Inc.), 0.28 g of 2-ethyl Europium hexanoate (Strem 93-6311; product of Strem Chemicals Inc.) and 0.12 mL of 2-ethylhexanoic acid magnesium toluene solution (ie, Strem 12-1260) to prepare a coating for forming the second passivation layer liquid. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 3.

Then, a bottom contact/top gate FET as described in Example 28 was fabricated. However, compared to Example 27, the stacking order of the first passivation layer 17a and the second passivation layer 17b is reversed.

-Forming a second passivation layer 170b-

Then, 0.6 mL of the coating droplet for forming the second passivation layer was applied on the gate insulating layer 13 and the gate electrode 12, and then a spin coating procedure was performed under predetermined conditions: spin at 500 rpm for 5 seconds , Then at a speed of 3000rmp for 20 seconds, then use 5 seconds to reduce the speed to 0rpm and stop rotating. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Forming a first passivation layer 170a-

Then, 0.4 mL of the coating droplet for forming the first passivation layer was placed on the second passivation layer 170b, and then the spin-coating procedure was performed under predetermined conditions: spin at 3000 rpm for 20 seconds, and then use 5 seconds Reduce the speed to 0 rpm and stop spinning. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Form a mask-

Then, the first passivation layer 170a (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce the first The passivation layer 17a has the same photoresist pattern.

-Etching procedure for the first passivation layer-

Then, the first passivation layer 170a is immersed in a mixed solution containing 14wt% ammonium fluoride and 12wt% ammonium bifluoride for 15 seconds as an etching process to remove the portion of the second oxide film not covered by the photoresist pattern, To obtain the first passivation layer 17a.

-Etching procedure for the second passivation layer-

Then, the second passivation layer 170b is immersed in 6wt% hydrogen peroxide water for 2 minutes as an etching procedure to remove the portion of the first oxide film not covered by the photoresist pattern to obtain the second passivation layer 17b.

-Remove mask-

Then, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

[Example 31]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.17 mL of HMDS, 0.47 mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195-09561) and 0.21 mL of 2-ethylhexanoic acid barium toluene solution (ie, Wako 021- 09471), preparing a coating solution for forming the first passivation layer. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 0.16 g of tris(2,2,6,6-tetramethyl-3,5-heptanedione acid) scandium(III) hydrate (ie, SIGMA-ALDRICH 517607), 1.46mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), 0.03mL of 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (ie, Alfa36657), 0.34mL of 2-ethyl Strontium hexanoate toluene solution (ie, Wako 195-09561) and 0.07 mL of 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare the coating for forming the second passivation layer Cloth liquid. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 4.

[Table 4]

Then, a bottom contact/top gate FET as shown in FIG. 16B is manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Forming a first passivation layer 1708-

Then, 0.4 mL of the coating droplet used to form the first passivation layer was deposited on the gate insulating layer 13 and the gate electrode 12, and then a spin-coating procedure was performed under predetermined conditions: spin at 3000 rpm for 20 seconds , Then reduce the speed to 0 rpm in 5 seconds and stop the rotation. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Forming a second passivation layer 170b-

Then, 0.6 mL of the coating droplet for forming the second passivation layer was placed on the first passivation layer 170a, and then a spin coating procedure was performed under predetermined conditions: rotation at 500 rpm for 5 seconds, and then at 3000 rmp Speed for 20 seconds, then reduce the speed to 0 rpm in 5 seconds and stop spinning. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Form a mask-

Then, the second passivation layer 170b (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce a second film with the desired The passivation layer 17b has the same photoresist pattern.

-Etching procedure for the second passivation layer 170b-

Then, the second passivation layer 170b is immersed in 0.36wt% hydrochloric acid for 20 seconds as an etching procedure to remove the portion of the first oxide film not covered by the photoresist pattern to obtain the second passivation layer 17b.

-Etching procedure for the first passivation layer 170a-

Then, the first passivation layer 170a is immersed in a mixed solution containing 14wt% ammonium fluoride and 3.2wt% ammonium bifluoride for 1 minute as an etching procedure to remove the portion of the second oxide film not covered by the photoresist pattern To obtain the first passivation layer 17a.

-Remove mask-

Then, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

[Example 32]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.15 mL of HMDS, and 0.31 mL of 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (that is, Alfa 36657), a coating liquid for forming the first passivation layer was prepared. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 0.13 g of acetone dysprosium triacetate trihydrate (Strem 66-2002; a product of Strem Chemicals Inc.), 0.27 g of ytterbium acetone acetone trihydrate (Strem 70-2202; Strem Chemicals Inc. product), 0.12 mL of 2-ethylhexanoic acid magnesium toluene solution (ie, Strem 12-1260) and 0.10 mL of 2-ethylhexanoic hafnium 2-ethylhexanoic acid solution (Gelest AKH332; Gelest , Inc. product), preparing a coating solution for the second passivation layer. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 4.

Then, a bottom contact/top gate FET as shown in FIG. 16B is manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Forming a first passivation layer 170a-

Then, 0.4 mL of the coating droplet used to form the first passivation layer was deposited on the gate insulating layer 13 and the gate electrode 12, and then a spin-coating procedure was performed under predetermined conditions: spin at 3000 rpm for 20 seconds , Then reduce the speed to 0 rpm in 5 seconds and stop the rotation. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Forming a second passivation layer 170b-

Then, 0.6 mL of the coating droplet for forming the second passivation layer was placed on the first passivation layer 170a, and then a spin coating procedure was performed under predetermined conditions: rotation at 500 rpm for 5 seconds, and then at 3000 rmp Speed for 20 seconds, then reduce the speed to 0 rpm in 5 seconds and stop spinning. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Form a mask-

Then, the second passivation layer 170b (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce a second layer with the desired The passivation layer 17b has the same photoresist pattern.

-Etching procedure for the second passivation layer 170b-

Then, the second passivation layer 170b is immersed in a mixed solution containing 55wt% phosphoric acid, 30wt% acetic acid, and 5wt% nitric acid for 30 seconds as an etching process to remove the first oxide film not covered by the photoresist pattern In part, the second passivation layer 17b is obtained.

-Etching procedure for the first passivation layer 170a-

Then, the first passivation layer 170a is immersed in 6wt% TMAH for 1 minute as an etching procedure to remove the portion of the second oxide film not covered by the photoresist pattern to obtain the first passivation layer 17a.

-Remove mask-

Then, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

[Example 33]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.09 mL of HMDS, 0.18 mL of bis(isobutoxy) acetoacetate aluminum chelate (ie, Alfa89349) and 0.69 mL of 2-ethylhexanoic acid barium toluene solution (ie , Wako 021-09471), preparing a coating solution for forming the first passivation layer. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-

By mixing 1.2 mL of cyclohexylbenzene, 0.51 g of yttrium 2-ethylhexanoate (Strem 39-2400; a product of Strem Chemicals Inc.), 0.06 mL of magnesium 2-ethylhexanoate in toluene solution (ie, Strem 12 -1260) and 0.07 mL of 2-ethylhexanoic hafnium 2-ethylhexanoic acid solution (ie, Gelest AKH332; a product of Gelest, Inc.) to prepare a coating liquid for forming the second passivation layer. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 4.

Then, a bottom contact/top gate FET as described in Example 28 was fabricated. However, compared to Example 27, the stacking order of the first passivation layer 17a and the second passivation layer 17b is reversed.

-Forming a second passivation layer 170b-

Then, 0.6 mL of the coating droplet for forming the second passivation layer was applied on the gate insulating layer 13 and the gate electrode 12, and then a spin coating procedure was performed under predetermined conditions: spin at 500 rpm for 5 seconds , Then at a speed of 3000rmp for 20 seconds, then use 5 seconds to reduce the speed to 0rpm and stop rotating. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Forming a first passivation layer 170a-

Then, 0.4 mL of the coating droplet for forming the first passivation layer was placed on the second passivation layer 170b, and then the spin-coating procedure was performed under predetermined conditions: spin at 3000 rpm for 20 seconds, and then use 5 seconds Reduce the speed to 0 rpm and stop spinning. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Form a mask-

Then, the first passivation layer 170a (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce the first The passivation layer 17a has the same photoresist pattern.

-Etching procedure for the first passivation layer 170a-

Then, the first passivation layer 170a is immersed in 5wt% hydrofluoric acid for 15 seconds as an etching procedure to remove the portion of the second oxide film not covered by the photoresist pattern to obtain the first passivation layer 17a.

-Etching procedure for the second passivation layer 170b-

Then, the second passivation layer 170b is immersed in a mixed solution containing 80wt% phosphoric acid, 10wt% acetic acid, and 5wt% nitric acid for 30 seconds as an etching procedure to remove the first oxide film not covered by the photoresist pattern In part, the second passivation layer 17b is obtained.

-Remove mask-

Then, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

[Example 34]

<manufacturing FET>

-Preparation of coating liquid for forming the first passivation layer-

By mixing 1 mL of toluene, 0.11 mL of HMDS, 0.10 mL of bis(isobutoxy) acetoacetate aluminum chelate (ie, Alfa89349), 0.07 g of (4,4,5,5-tetramethyl -1,3,2-dioxaborolan-2-yl)benzene (ie Wako 325-59912), 0.09 mL of calcium 2-ethylhexanoate solution in 2-ethylhexanoic acid (ie Alfa36657) And 0.19 mL of a 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195-9561) to prepare a coating liquid for forming the first passivation layer. The composition of the second oxide formed using the coating liquid for forming the first passivation layer is shown in Table 4.

-Preparation of coating liquid for forming the second passivation layer-

Through mixing 1.2mL of cyclohexylbenzene, 1.95mL of 2-ethylhexanoic acid lanthanum toluene solution (ie, Wako 122-03371), 0.57mL of 2-ethylhexanoic acid strontium toluene solution (ie, Wako 195-09561) And 0.09 mL of a 2-ethylhexanoic acid zirconium oxide mineral spirit solution (ie, Wako 269-01116) to prepare a coating liquid for forming a second passivation layer. The composition of the first oxide formed using the coating liquid for forming the second passivation layer is shown in Table 4.

Then, a bottom contact/top gate FET as shown in FIG. 16B is manufactured. The source electrode 14, the drain electrode 15, the active layer 16, the gate insulating layer 13, and the gate electrode 12 were formed in the same manner as in Example 27.

-Forming a first passivation layer 170a-

Then, 0.4 mL of the coating droplet used to form the first passivation layer was deposited on the gate insulating layer 13 and the gate electrode 12, and then a spin-coating procedure was performed under predetermined conditions: spin at 3000 rpm for 20 seconds , Then reduce the speed to 0 rpm in 5 seconds and stop the rotation. Then, after the drying procedure was performed for 1 hour in an environment of 120°C, the burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a second oxide thin film used as the first passivation layer 170a. Here, the average film thickness of the first passivation layer 170a is about 25 nm.

-Forming a second passivation layer 170b-

Then, 0.6 mL of the coating droplet for forming the second passivation layer was placed on the first passivation layer 170a, and then a spin coating procedure was performed under predetermined conditions: rotation at 500 rpm for 5 seconds, and then at 3000 rmp Speed for 20 seconds, then reduce the speed to 0 rpm in 5 seconds and stop spinning. Then, after a drying procedure was performed for 1 hour in an environment of 120°C, a burning procedure was performed for 3 hours at a temperature of 400°C in an environment filled with O ₂ to obtain a first oxide thin film used as the second passivation layer 170b. Here, the average film thickness of the second passivation layer 170b is about 135 nm.

-Form a mask-

Then, the second passivation layer 170b (ie, the first oxide film) is coated with a photoresist (ie, TSMR-8800BE), and then pre-baked, exposed through an exposure device, and developed to produce a second film with the desired The passivation layer 17b has the same photoresist pattern.

-Etching procedure for the second passivation layer 170b-

Then, the second passivation layer 170b is immersed in 0.36wt% hydrochloric acid (ie, Wako 083-01115) for 20 seconds as an etching procedure to remove the portion of the first oxide film not covered by the photoresist pattern to obtain the second Passivation layer 17b.

-Etching procedure for the first passivation layer 170a-

Then, the first passivation layer 170a is immersed in a mixed solution containing 14wt% ammonium fluoride and 12wt% ammonium bifluoride for 15 seconds as an etching process to remove the portion of the second oxide film not covered by the photoresist pattern, To obtain the first passivation layer 17a.

-Remove mask-

Then, the photoresist pattern was also removed by soaking in a photoresist stripper (ie, STRIPPER 104) for 2 minutes.

(Evaluate transistor characteristics)

The transistor characteristics of each of the FETs manufactured in Examples 27 to 34 were evaluated. The evaluation of the characteristics of each transistor according to Examples 27 to 34 is based on the difference between the gate electrode 12 and the source electrode 14 when the voltage (Vds) between the source electrode 14 and the drain electrode 15 is +10V Measurement of voltage (Vgs) and current (Ids) relationship between source electrode 14 and drain electrode 15 (Vgs-Ids).

Furthermore, based on the evaluation result of the transistor characteristics (Vgs-Ids), the field-effect mobility in the saturation region is calculated. Further, the ratio (ie, on/off ratio) of the transistor from Ids in the "on" state (for example, Vgs=+10V) to Ids in the "off" state (for example, Vgs=-10V) is calculated. Furthermore, the value of S is calculated as an indicator of the sharpness of the rise in Ids reflected by the application of Vgs. Further, a threshold voltage (Vth) is calculated, which is a voltage value corresponding to an increase in Ids reflected by the application of Vgs.

The mobility, on/off ratio, S value, and Vth calculated from the transistor characteristics of the FETs manufactured from Examples 27 to 34 are shown in Table 5. In the following description, regarding the results of transistor characteristics, the preferred transistor characteristics are: high mobility; high on/off ratio; low S value; and Vth around 0V. In particular, preferred transistor characteristics: mobility 3cm ² / Vs or more; on / off ratio of more than 1.0 x 10 ^8; S values below 0.7; and Vth is a range of ± 5V.

As shown in FIG. 5, it is confirmed that the FETs manufactured in Examples 27 to 34 have better transistor characteristics, that is, have high mobility, high on/off ratio, low S value, and Vth around 0V.

[table 5]

(Evaluate transistor characteristics)

The FETs manufactured in Examples 27 to 34 were subjected to a 100-hour BTS test under this environment (temperature: 50°C; relative humidity: 50%).

Provide the following 4 conditions as pressure conditions:

(1) Vgs=+10V, and Vds=0V

(2) Vgs=+10V, and Vds=+10V

(3) Vgs=-10V, and Vds=0V

(4) Vgs=-10V, and Vds=+10V

Moreover, in the BTS test, whenever a predetermined length of time passes, the relationship between Vgs and Ids under the condition of Vds=+10V (Vgs-Ids) is measured.

For the FET fabricated in Example 34, the results of Vgs-Ids under the pressure conditions of Vgs=+10V and Vds=0V in the BTS test are shown in FIG. 32. Furthermore, for the FET manufactured in Example 34, under the pressure conditions of Vgs=+10V and Vds=0V, the shift of the critical voltage with respect to the pressurization time (ΔVth) is shown in FIG. 33.

In addition, for the FETs manufactured in Examples 27 to 34, the value of ΔVth at 100 hours of pressurization time in the BTS test is shown in Table 6. Here, ΔVth is the deviation of Vth from the pressurization time 0 to any time.

According to Figure 32, Figure 33, and Table 6, the FET manufactured in Example 34 is more reliable for BTS testing, that is, has a low ΔVth offset. According to Table 6, the FETs manufactured in Examples 27 to 33 are more reliable for BTS testing, that is, have a low ΔVth offset.

[Table 6]

Further, the present invention is not limited to these embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

10‧‧‧Field effect transistor

11‧‧‧ substrate

12‧‧‧Gate electrode

13‧‧‧Gate insulation

14‧‧‧Source electrode

15‧‧‧ Drain electrode

16‧‧‧Active layer

17‧‧‧passivation layer

Claims (20)

A method of manufacturing a field effect transistor, the field effect transistor includes a gate insulating layer, an active layer and a passivation layer, the method includes: A first procedure for forming the gate insulating layer; and A second procedure for forming the passivation layer, Wherein, at least one of the first program and the second program includes: Forming a first oxide including an alkaline earth metal and at least one of gallium, scandium, yttrium, and lanthanide; and The first oxide is etched using a first solution. The first solution includes at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide. The method for manufacturing a field effect transistor according to item 1 of the patent application scope, wherein the passivation layer includes a first passivation layer and a second passivation layer, and wherein the second procedure includes: Forming the first passivation layer including a second oxide, the second oxide including silicon and an alkaline earth metal; Forming the second passivation layer including the first oxide, the second passivation layer being configured to contact the first passivation layer; Contacting the first passivation layer with a second solution to etch the first passivation layer, the second solution including at least one of hydrofluoric acid, ammonium fluoride, ammonium bifluoride, and an organic base; and The second passivation layer is brought into contact with the first solution to etch the second passivation layer. According to the method of manufacturing field effect transistors described in item 2 of the patent application scope, the second procedure includes: Forming the first passivation layer on the second passivation layer; Forming a mask on the first passivation layer; After forming the mask, contacting the first passivation layer with the second solution to etch the first passivation layer; After etching the first passivation layer, contacting the second passivation layer with the first solution to etch the second passivation layer; and Remove the mask. According to the method of manufacturing field effect transistors described in item 2 of the patent application scope, the second procedure includes: Forming the second passivation layer on the first passivation layer; Forming a mask on the second passivation layer; After forming the mask, contacting the second passivation layer with the first solution to etch the second passivation layer; After etching the second passivation layer, contacting the first passivation layer with the second solution to etch the first passivation layer; and Remove the mask. The method of manufacturing a field effect transistor according to item 1 of the patent application scope, wherein the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and Among them, the first procedure includes: Forming the first gate insulating layer including a second oxide, the second oxide including silicon and an alkaline earth metal; Forming the second gate insulating layer including the first oxide, the second gate insulating layer being configured to contact the first gate insulating layer; Contacting the first gate insulating layer with a second solution to etch the first gate insulating layer, the second solution including at least one of hydrofluoric acid, ammonium fluoride, ammonium bifluoride, and an organic base; and The second gate insulating layer is brought into contact with the first solution to etch the second gate insulating layer. The method for manufacturing field effect transistors according to item 5 of the patent application scope, wherein the first procedure includes: Forming the first gate insulating layer on the second gate insulating layer; Forming a mask on the first gate insulating layer; After the mask is formed, the first gate insulating layer is brought into contact with the second solution to etch the first gate insulating layer; After etching the first gate insulating layer, contacting the second gate insulating layer with the first solution to etch the second gate insulating layer; and Remove the mask. According to the method for manufacturing the field effect transistor described in item 5 of the patent application scope, the first procedure includes: Forming the second gate insulating layer on the first gate insulating layer; Forming a mask on the second gate insulating layer; After the mask is formed, the second gate insulating layer is brought into contact with the first solution to etch the second gate insulating layer; After etching the second gate insulating layer, contacting the first gate insulating layer with the second solution to etch the first gate insulating layer; and Remove the mask. According to the method of manufacturing a field effect transistor described in item 2 or 5 of the patent application scope, wherein the second oxide includes at least one of aluminum and boron. According to the method of manufacturing the field effect transistor described in item 1 of the patent application scope, wherein the first oxide is a paraelectric amorphous oxide. According to the method of manufacturing a field effect transistor described in item 1 of the patent scope, wherein the first oxide includes at least one of aluminum, titanium, zirconium, hafnium, niobium, and tantalum. According to the method for manufacturing a field effect transistor described in item 1 of the patent scope, the active layer is made of an oxide semiconductor. The method for manufacturing a field effect transistor according to item 1 of the scope of the patent application, wherein the gate insulating layer, the active layer and the passivation layer are formed on an insulating substrate. According to the method of manufacturing a field effect transistor described in item 1 of the patent scope, wherein the active layer is a semiconductor substrate, and wherein the gate insulating layer and the passivation layer are formed on the semiconductor substrate. A method for manufacturing a volatile semiconductor memory element, the method includes: a) Form a field effect transistor according to the method described in item 1 of the patent application scope; b) forming a first capacitor electrode connected to a drain electrode of the field effect transistor; c) forming a second capacitor electrode; and d) A capacitive dielectric layer is formed between the first capacitive electrode and the second capacitive electrode. The method for manufacturing a volatile semiconductor memory device according to item 14 of the patent application scope, wherein the step d) of forming the capacitor dielectric layer includes: Forming the first oxide; and The first oxide is brought into contact with the first solution to etch the first oxide. A method for manufacturing a non-volatile semiconductor memory element, the method includes: Form a field effect transistor according to the method described in item 1 of the patent application scope; and A second gate insulating layer and a floating gate electrode are formed between the active layer and the gate insulating layer. A method of manufacturing a display element, the method comprising: a) forming a driver circuit including a field effect transistor; and b) forming a light control element to control the light output according to a drive signal obtained from the drive circuit, Wherein, the step a) of forming the driving circuit includes forming the field effect transistor according to the method described in item 1 of the patent application scope. The method of manufacturing a display element according to item 17 of the patent application scope, wherein the light control element is any of an electroluminescent element, an electrochromic element, a liquid crystal element, an electrophoretic element or an electrowetting element one. A method of manufacturing an image display device including a screen and a display control device, the screen including a plurality of display elements arranged in a matrix, the display control device being configured to specifically control among the display elements For each, the method includes: The procedure for forming such display elements, Wherein, the procedure for forming the display elements includes forming a display element according to the method described in Item 17 or Item 18 of the patent application. A method of manufacturing a system. The system includes an image display device and an image data generation unit configured to provide image data to the image display device. The method includes: The program that forms the image display device, Wherein, the procedure for forming the image display device includes forming the image display device according to the method described in item 19 of the patent application scope.

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