JP2019179861A - Field-effect transistor, display device, image display unit, and system - Google Patents

Abstract

To provide a field-effect transistor that can keep a leakage current down while using a high-k gate insulator film.SOLUTION: In a field-effect transistor having a gate insulator film, the gate insulator film has a first gate insulator film that is any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and a second gate insulator film that is in contact with the first gate insulator film and has an oxide containing an alkaline earth metal element and at least any one element of lanthanoid excluding Ga, Sc, Y, and Ce.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a field effect transistor, a display element, an image display device, and a system.

  A field effect transistor (FET) has a low gate current and has a planar structure, and thus can be easily manufactured and integrated as compared with a bipolar transistor. Therefore, the FET is an indispensable element in the integrated circuit used in the current electronic equipment.

  Conventionally, a silicon-based insulating film has been widely used for a gate insulating layer of a field effect transistor. However, in recent years, demands for further higher integration and lower power consumption of field-effect transistors have increased, and so-called high-k insulating films having a dielectric constant much higher than that of silicon-based insulating films are used for gate insulating layers. For example, field effect transistors and semiconductor memories using, as a gate insulating layer, a composite metal oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid Has been proposed.

  On the other hand, in recent years, due to problems such as an increase in manufacturing cost due to an increase in manufacturing equipment accompanying an increase in substrate size, technological development for manufacturing semiconductor devices by a coating process has been actively conducted. As for a composite metal oxide insulating film containing a metal and an element selected from Ga, Sc, Y, and a lanthanoid, an ink, a method for manufacturing the insulating film, and a method for manufacturing a semiconductor device have been proposed (for example, , See Patent Document 1).

  However, the film thickness distribution of the composite metal oxide insulating film is easily affected by the material and shape of the substrate to be coated. For example, when the composite metal oxide insulating film is used as a gate insulating film of a field effect transistor, The film thickness is likely to be non-uniform due to the influence of the underlying electrode (gate electrode or source / drain electrode) pattern, and as a result, the leakage current may increase.

  An object of the present invention is to provide a field-effect transistor that can suppress a leakage current while using a high-k gate insulating film.

Means for solving the problems are as follows. That is,
The field effect transistor of the present invention is
A field effect transistor having a gate insulating film,
The gate insulating film is in contact with the first gate insulating film, which is one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, the alkaline earth metal element, and Ga And a second gate insulating film having an oxide containing at least one element of a lanthanoid excluding Sc, Y, and Ce.

  According to the present invention, it is possible to provide a field-effect transistor that can suppress a leakage current while using a high-k gate insulating film.

FIG. 1 is a schematic diagram of an example of a bottom gate / top contact field effect transistor. FIG. 2 is a schematic diagram of an example of a bottom-gate / bottom-contact field effect transistor. FIG. 3 is a schematic view of another example of a bottom-gate / top-contact field effect transistor. FIG. 4 is a schematic diagram of another example of a bottom-gate / bottom-contact field effect transistor. FIG. 5 is a schematic configuration diagram showing an example of a television device as a system of the present invention. FIG. 6 is a diagram (part 1) for explaining the image display device in FIG. FIG. 7 is a diagram (part 2) for explaining the image display device in FIG. FIG. 8 is a diagram (part 3) for explaining the image display device in FIG. FIG. 9 is a diagram for explaining an example of the display element of the present invention. FIG. 10 is a schematic configuration diagram illustrating an example of a positional relationship between an organic EL element and a field effect transistor in a display element. FIG. 11 is a schematic configuration diagram illustrating another example of the positional relationship between the organic EL element and the field effect transistor in the display element. FIG. 12 is a schematic configuration diagram illustrating an example of an organic EL element. FIG. 13 is a diagram for explaining the display control apparatus. FIG. 14 is a diagram for explaining a liquid crystal display. FIG. 15 is a diagram for explaining the display element in FIG. FIG. 16A is a schematic diagram for explaining an example of a method for producing a field-effect transistor (part 1). FIG. 16B is a schematic diagram for explaining an example of a method of manufacturing a field effect transistor (part 2). FIG. 16C is a schematic diagram for explaining an example of a method of manufacturing a field effect transistor (part 3). FIG. 16D is a schematic diagram for explaining an example of a method of manufacturing a field effect transistor (part 4). FIG. 16E is a schematic view for explaining an example of a method for producing a field effect transistor (part 5). FIG. 16F is a schematic view for explaining an example of a method for producing a field effect transistor (No. 6). FIG. 16G is a schematic view for explaining one example of a method for producing a field effect transistor (part 7). FIG. 16H is a schematic diagram for explaining an example of a method of manufacturing a field effect transistor (No. 8). FIG. 16I is a schematic diagram for explaining an example of a method of manufacturing a field effect transistor (No. 9). FIG. 16J is a schematic view for explaining an example of a method of manufacturing a field effect transistor (No. 10). FIG. 17A is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 1). FIG. 17B is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 2). FIG. 17C is a schematic diagram for explaining another example of the method for producing the field-effect transistor (part 3). FIG. 17D is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 4). FIG. 17E is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 5). FIG. 17F is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 6). FIG. 17G is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 7). FIG. 17H is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 8). FIG. 17I is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 9). FIG. 18A is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 1). FIG. 18B is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 2). FIG. 18C is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 3). FIG. 18D is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 4). FIG. 18E is a schematic view for explaining another example of the method for producing the field-effect transistor (part 5). FIG. 18F is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 6). FIG. 18G is a schematic diagram for explaining another example of the method for producing the field-effect transistor (part 7). FIG. 18H is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 8). FIG. 18I is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 9). FIG. 19A is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 1). FIG. 19B is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 2). FIG. 19C is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 3). FIG. 19D is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 4). FIG. 19E is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 5). FIG. 19F is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 6). FIG. 19G is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 7). FIG. 19H is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 8). FIG. 19I is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 9). FIG. 19J is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 10). FIG. 20A is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 1). FIG. 20B is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 2). FIG. 20C is a schematic diagram for explaining another example of the method for producing the field-effect transistor (part 3). FIG. 20D is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 4). FIG. 20E is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 5). FIG. 20F is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 6). FIG. 20G is a schematic diagram for explaining another example of the method for producing the field-effect transistor (part 7). FIG. 20H is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 8). FIG. 20I is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 9). FIG. 20J is a schematic view for explaining another example of the method for producing the field-effect transistor (No. 10). FIG. 21A is a schematic diagram for explaining another example of the method for producing the field-effect transistor of the comparative example (part 1). FIG. 21B is a schematic diagram for explaining another example of the method for producing the field-effect transistor of the comparative example (part 2). FIG. 21C is a schematic diagram for explaining another example of the method for producing the field-effect transistor of the comparative example (part 3). FIG. 21D is a schematic diagram for explaining another example of the method for manufacturing the field-effect transistor of the comparative example (part 4). FIG. 21E is a schematic diagram for explaining another example of the method for producing the field-effect transistor of the comparative example (part 5). FIG. 21F is a schematic diagram for explaining another example of the method for manufacturing the field-effect transistor of the comparative example (part 6). FIG. 21G is a schematic diagram for explaining another example of the method for producing the field-effect transistor of the comparative example (part 7). FIG. 21H is a schematic diagram for explaining another example of the method for producing the field-effect transistor of the comparative example (part 8). FIG. 22A is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 1). FIG. 22B is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 2). FIG. 22C is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 3). FIG. 22D is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 4). FIG. 22E is a schematic view for explaining another example of the method of manufacturing the field effect transistor (part 5). FIG. 22F is a schematic view for explaining another example of the method of manufacturing the field effect transistor (No. 6). FIG. 22G is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (part 7). FIG. 22H is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 8). FIG. 22I is a schematic diagram for explaining another example of the method of manufacturing the field effect transistor (No. 9).

(Field effect transistor)
The field effect transistor of the present invention includes at least a gate insulating film, and further includes other members such as a gate electrode, a source electrode, a drain electrode, and a semiconductor layer as necessary.

In the field effect transistor of the present invention, as described in detail below, the gate insulating film includes a first gate insulating film and a second gate insulating film.
The first gate insulation is any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
The second gate insulating film is an oxide containing an alkaline earth metal element and at least one of lanthanoid elements excluding Ga, Sc, Y, and Ce (hereinafter referred to as “composite oxide”). Have).
The second gate insulating film is in contact with the first gate insulating film.

  The field effect transistor of the present invention is suitably used for a bottom gate structure field effect transistor. In particular, after the second gate insulating film and the semiconductor layer are continuously formed, the semiconductor layer and the second gate insulating film are formed. It is suitably used for a field effect transistor having a bottom gate bottom contact structure manufactured by a process of etching in this order.

<Gate insulation film>
The gate insulating film includes at least a first gate insulating film and a second gate insulating film in contact with the first gate insulating film.
The gate insulating film is not limited to a two-layer structure of a first gate insulating film and a second gate insulating film, and may further have a three-layer structure having a third gate insulating film.

  The arrangement of the first gate insulating film and the second gate insulating film in the gate insulating film is not particularly limited and can be appropriately selected according to the purpose. The first gate insulating film May be disposed closer to the semiconductor layer than the second gate insulating film, or the second gate insulating film may be disposed closer to the semiconductor layer than the first gate insulating film. Good. For example, the first gate insulating film may be disposed closer to the semiconductor layer than the second gate insulating film, and the first gate insulating film may be in contact with the semiconductor layer. On the other hand, the second gate insulating film may be disposed closer to the semiconductor layer than the first gate insulating film, and the second gate insulating film may be in contact with the semiconductor layer. The second gate insulating film may be disposed so as to cover the upper surface and the side surface of the first gate insulating film, and the second gate insulating film may be disposed so as to cover the upper surface and the side surface of the second gate insulating film. One gate insulating film may be disposed.

  A silicon oxide film, a silicon nitride film, and a silicon oxynitride film formed by a vacuum film formation method such as a sputtering method and a CVD method have a merit that a dense, volume resistance value and high withstand voltage can be obtained. Since it is isotropically deposited, it is uniformly deposited with substantially the same film thickness along the unevenness of the base, resulting in an insulating film surface step that is not different from the base step. However, the coating solution for forming the second gate insulating film made of an oxide containing an alkaline earth metal element and at least one of lanthanoid elements excluding Ga, Sc, Y, and Ce is used immediately after coating. In the case of being a liquid, the effect of flattening the unevenness of the base is obtained by the balance between the surface tension and the viscosity. Therefore, even when the first gate insulating film and the second gate insulating film are formed relatively thin, the source electrode formed on the gate insulating film, the drain electrode, and the gate electrode formed below the gate insulating film When a voltage is applied between them, the probability of occurrence of electric field concentration is lowered, so that the defect rate is lowered.

-First gate insulating film-
As the first gate insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are preferably used.

  The silicon oxide film, silicon nitride film, and silicon oxynitride film are formed by sputtering, PLD (pulsed laser deposition pulsed laser deposition) ALD (Atomic Layer Deposition atomic layer deposition), CVD (Chemical Vapor Deposition) chemical vapor deposition. ) And the like. Among them, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film manufactured by CVD are known to be stable materials having high productivity, few defects, and excellent insulating properties, and TFT (Thin Film Transistor). Widely used as a gate insulating film of a thin film transistor.

A stoichiometric silicon oxide film is expressed as SiO _2, and a stoichiometric silicon nitride film is expressed as Si ₃ N ₄ , but a silicon oxynitride film SiON is an arbitrary mixture of SiO ₂ and Si ₃ N _4. It is possible to produce a composition and have intermediate physical properties, for example, the relative dielectric constant of SiO ₂ is 3.9, the relative dielectric constant of Si ₃ N ₄ is 7.5, and SiO _x N _y is A film having a relative dielectric constant between 3.9 and 7.5 can be produced depending on the values of x and y.
The relative dielectric constant can be measured using, for example, an LCR meter or the like by fabricating a capacitor in which a lower electrode, a dielectric layer (the first gate insulating film), and an upper electrode are stacked.

When the silicon oxide film, silicon nitride film, silicon oxynitride film is formed by sputtering, Si, SiO ₂ , Si ₃ N ₄ , SiO _x N _y target having a desired composition, Ar, etc. The silicon oxide film, silicon nitride film, and silicon oxynitride film can be formed by generating plasma in a vacuum in which an inert gas is mixed with oxygen gas, nitrogen gas, or the like as necessary. When the PLD method is used, the silicon oxide film, the silicon nitride film, and the silicon oxynitride film can be formed by irradiating the target with a pulsed laser in a vacuum using a target similar to the sputtering method.
However, in order to form a film on a large-area substrate having a side of 1 meter or more by the sputtering method or the PLD method, it is necessary to use a huge target, so that it is difficult to increase productivity.
Therefore, in general, in order to form a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, a plasma CVD method is often used in which plasma is generated in a vacuum and raw materials are decomposed and deposited on a substrate.

In order to deposit a silicon oxide film by plasma CVD, it can be formed using a mixed gas such as SiH ₃ (silane), O ₂ , N ₂ O, and Ar at a substrate temperature of 300 ° C. to 400 ° C. Also, when tetraethoxysilane (TEOS), which is a liquid organic silane material, is used as a raw material, when a mixed gas of vaporized TEOS and O ₂ gas is used, the substrate temperature is 200 ° C. to 300 ° C. at a relatively low temperature and high speed. A silicon oxide film can be deposited.

The silicon nitride film can be formed by plasma CVD using SiH ₄ (silane), NH ₃ (ammonia), N ₂ (nitrogen), and N ₂ O as raw materials at a substrate temperature of 300 ° C. to 400 ° C.
Silicon nitride film is amorphous, since is possible to combine completely nitrogen unpaired electrons of all Si is difficult, a-SiN was added trace hydrogen x: _H hydrogenated amorphous silicon nitride is generally used It has been. Similarly, SiO _x N _y : H hydrogenated silicon oxynitride to which a small amount of hydrogen is added is also used. It is known that electrical insulation is improved by partial hydrogenation.

  When the first gate insulating film is in contact with the semiconductor layer, the first gate insulating film is provided by a vacuum film forming method such as the sputtering method, the PLD method, the ALD method, or the CVD method. By forming the semiconductor layer, the interface between the first gate insulating film and the semiconductor layer can be formed without being exposed to the atmosphere, so that a bond can be made at a clean interface, and the first gate insulating film and the semiconductor layer can be joined. It is possible to avoid defects such as contamination of the interface (that is, the channel portion where current flows) by photolithography and adhesion of foreign matter.

  There is no restriction | limiting in particular as average thickness of the said 1st gate insulating film, Although it can select suitably according to the objective, 20 nm-2 micrometers are preferable, and 50 nm-500 nm are more preferable.

-Second gate insulating film-
The second gate insulating film contains a complex oxide.
The second gate insulating film is preferably formed of the complex oxide itself.

-Composite oxide-
The composite oxide contains at least an element A which is an alkaline earth metal and a element B which is at least one of lanthanoids excluding Ga, Sc, Y and Ce, and preferably Al (aluminum) , Ti (titanium), Zr (zirconium), Hf (hafnium), Nb (niobium), and Ta (tantalum) element C is contained, and if necessary, other components are contained To do.

The composite oxide is preferably a paraelectric amorphous oxide.
In the case where the second gate insulating film is in contact with the semiconductor layer, it is preferable that the second gate insulating film be formed of an amorphous material in terms of further improving the characteristics of the transistor. This is because if the second gate insulating film is formed using a crystalline material, leakage current due to crystal grain boundaries cannot be suppressed to a low level, leading to deterioration of transistor characteristics.
Further, it is necessary that the second gate insulating film is a paraelectric material in order to reduce hysteresis in the transfer characteristics of the transistor. The exception is the special case where the transistor is used for a memory or the like, but it is not preferable that hysteresis exists in a device that normally uses the switching characteristics of the transistor.
A paraelectric material is a dielectric material other than a piezoelectric material, pyroelectric material, or ferroelectric material, that is, a dielectric material that does not generate polarization due to pressure or has spontaneous polarization in the absence of an external electric field. Point to. In addition, the piezoelectric body, pyroelectric body, and ferroelectric need to be crystals in order to exhibit their characteristics. That is, when the second gate insulating film is formed of an amorphous material, the second gate insulating film necessarily becomes a paraelectric material.

  The paraelectric amorphous oxide is stable in the atmosphere and can stably form an amorphous structure in a wide composition range. This is because the oxide system containing the element A, which is an alkaline earth metal, and the element B, which is at least one of lanthanoids excluding Ga, Sc, Y, and Ce, is in the atmosphere. In other words, an amorphous structure can be stably formed in a wide composition range.

  In general, simple oxides of alkaline earth metals easily react with moisture and carbon dioxide in the atmosphere, easily form hydroxides and carbonates, and are not suitable for electronic devices alone. . Further, simple oxides of rare earth elements are easily crystallized, and leakage current becomes a problem when considering application to electronic devices. However, the present inventors have described the paraelectric amorphous oxide containing the element A which is an alkaline earth metal and the element B which is at least one of lanthanoids excluding Ga, Sc, Y and Ce. However, it has been found that an amorphous film can be stably formed in a wide composition range. Since the paraelectric amorphous oxide exists stably in a wide composition range, the relative dielectric constant and the linear expansion coefficient of the formed paraelectric amorphous oxide can be controlled widely by the composition ratio. Can do.

  The composite oxide preferably contains a C element that is at least one of Al, Ti, Zr, Hf, Nb, and Ta. When the composite oxide contains at least one of Al, Ti, Zr, Hf, Nb, and Ta, thermal stability, heat resistance, and denseness can be further improved. .

  In the composite oxide, the element A which is the alkaline earth metal includes Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium). These may be used individually by 1 type and may use 2 or more types together.

  In the composite oxide, as the B element which is at least one of lanthanoids excluding Ga, Sc, Y, and Ce, Ga (gallium), Sc (scandium), Y (yttrium), La (lanthanum), Pr (Praseodymium), Nd (neodymium), Pm (promethium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (Thulium), Yb (ytterbium), and Lu (lutetium).

The composition ratio of the element A which is the alkaline earth metal and the element B which is at least one of lanthanoids excluding Ga, Sc, Y and Ce in the composite oxide is not particularly limited, Although it can be appropriately selected depending on the above, it is preferably in the following range.
In the composite oxide, the composition ratio of the element A which is an alkaline earth metal and the element B which is at least one of lanthanoids excluding Ga, Sc, Y and Ce (the element A: the element the element B), an oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Pr 2 O 3, Nd 2 O 3, Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu _In terms of ₂ O ₃ ), 10.0 mol% to 67.0 mol%: 33.0 mol% to 90.0 mol% is preferable.

  In the composite oxide, the A element that is the alkaline earth metal, the B element that is at least one of lanthanoids excluding Ga, Sc, Y, and Ce, the Al, the Ti, the Zr, and the Hf The composition ratio with the C element which is at least one of Nb and Ta is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably within the following range.

In the composite oxide, the element A being the alkaline earth metal, the element B being at least one of lanthanoids excluding Ga, Sc, Y, and Ce, the Al, the Ti, the Zr, and the As the composition ratio (the A element: the B element: the C element) with respect to the C element which is at least one of Hf, Nb, and Ta, oxides (BeO, MgO, CaO, SrO, BaO, _{Ga 2 O 3, Sc 2 O} 3, Y 2 O 3, La 2 O 3, Pr 2 O 3, Nd 2 O 3, Pm 2 O 3, Sm 2 O 3, Eu 2 O 3, Gd 2 O 3, _{Tb 2 O 3, Dy 2 O} 3, Ho 2 O 3, Er 2 O 3, Tm 2 O 3, Yb 2 O 3, Lu 2 O 3, Al 2 O 3, TiO 2, ZrO 2, HfO 2, Nb ₂ O _{5, Ta} 2 _{O 5} ) In terms of conversion, 5.0 mol% to 22.0 mol%: 33.0 mol% to 90.0 mol: 5.0 mol% to 45.0 mol% is preferable.

The oxide in the composite oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Pr 2 O 3, Nd 2 O 3, Pm 2 O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ The ratio of O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ ) is, for example, fluorescent X-ray analysis, electron beam microanalysis (EPMA), dielectric coupled plasma emission It can be calculated by analyzing the cation element of the oxide by spectroscopic analysis (ICP-AES) or the like.

The relative dielectric constant of the second gate insulating film is not particularly limited and can be appropriately selected depending on the purpose.
The relative dielectric constant of the second gate insulating film can be measured, for example, by the same method as the relative dielectric constant of the first gate insulating film.

There is no restriction | limiting in particular as a linear expansion coefficient of a said 2nd gate insulating film, According to the objective, it can select suitably.
The linear expansion coefficient can be measured using, for example, a thermomechanical analyzer. In this measurement, the linear expansion coefficient can be measured by separately preparing and measuring a measurement sample having the same composition as the second gate insulating film without producing the field effect transistor. .

  There is no restriction | limiting in particular as average thickness of a said 2nd gate insulating film, Although it can select suitably according to the objective, 20 nm-2 micrometers are preferable, and 50 nm-500 nm are more preferable.

--Insulating film forming ink--
The second gate insulating film can be formed, for example, by applying a gate insulating film forming ink.

  The ink for forming a gate insulating film includes, for example, at least one of a metal organic acid salt and an organometallic complex. In the present invention, the “organometallic complex” includes both an organometallic compound having a metal-carbon bond and a metal complex having a coordination bond.

  The metal organic acid salt is, for example, a substituted or unsubstituted carboxylate. As an example, magnesium acetate, calcium propionate, zirconium naphthenate, barium octylate, lanthanum 2-ethylhexanoate, and the like can be used, but are not limited thereto.

  The organometallic complex includes, for example, an acetylacetonate derivative, a substituted or unsubstituted phenyl group, or a substituted or unsubstituted alkoxy group. Examples include strontium acetylacetonate hydrate, tris (2,2,6,6-tetramethyl-3,5-heptanedionate) neodymium, tetraethoxyacetylacetonatotantalum, titanium butoxide, aluminum di (s- Butoxide) acetoacetic acid ester chelate can be used, but is not limited thereto.

  Furthermore, the organometallic complex may be an organometallic complex containing a carbonyl group, a substituted or unsubstituted alkyl group, or a substituted or unsubstituted cyclodienyl group. As an example, niobium pentacarbonyl, tris (cyclopentadienyl) yttrium, tetrabenzylhafnium, diethylaluminum, and the like can be used, but are not limited thereto.

  Further, the second gate insulating film forming ink contains, for example, the inorganic salt of the metal. As an example, strontium carbonate, scandium nitrate hydrate, gallium sulfate, or the like can be used, but is not limited thereto.

  As the solvent used in the gate insulating film forming ink, a solvent capable of stably dissolving or dispersing the metal raw material compound can be appropriately selected and used. As an example, toluene, isopropanol, ethyl benzoate, N, N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, mineral spirits, dimethylpropylene urea, 4-butyrolactone, 2-methoxyethanol, water, etc. may be used. Yes, but not limited to this.

  Moreover, you may add the thickener for adjusting viscosity, surfactant, etc. according to the application method and the foundation | substrate.

  The inventors of the present invention have a step after the step of forming the gate insulating film by forming the gate insulating film in a stacked structure of the first gate insulating film and the second gate insulating film having different etching selection ratios. It has been found that the choice of materials for the gate electrode, semiconductor layer, source electrode, and drain electrode formed in (1) is greatly expanded.

In the bottom gate type field effect transistor of FIGS. 1 and 2 to be described later, when the source electrode, the drain electrode, and the semiconductor layer on the gate insulating film are etched, the first gate insulating film is The second gate insulating film can be prevented from being etched. Therefore, an etchant that etches the first gate insulating film when the source electrode, the drain electrode, and the semiconductor layer are etched can be used as the etchant for the source electrode, the drain electrode, and the semiconductor layer. it can. By expanding the choice of etchant materials, the choice of gate electrode, semiconductor layer, source electrode, and drain electrode materials is also greatly expanded.
In the bottom gate type field effect transistor of FIGS. 3 and 4, the second gate insulating film is etched when the source electrode, the drain electrode, and the semiconductor layer on the gate insulating film are etched. This can be prevented by the first gate insulating film. Therefore, an etchant that etches the gate insulating film when the source electrode, the drain electrode, and the semiconductor layer are etched can also be used as the etchant for the source electrode, the drain electrode, and the semiconductor layer. By expanding the choice of etchant materials, the choice of gate electrode, semiconductor layer, source electrode, and drain electrode materials is also greatly expanded.

  The inventors of the present invention have a stacked structure of the first gate insulating film and the second gate insulating film in contact with the first gate insulating film as the gate insulating film, so that moisture, oxygen in the atmosphere, The present inventors have found that it exhibits excellent barrier properties against hydrogen. Therefore, in the top gate type field effect transistor using the gate insulating film, the gate insulating film isolates moisture, oxygen, and hydrogen in the atmosphere from the semiconductor layer, and the BTS test is performed even in the absence of the protective layer. Thus, it is possible to provide a field-effect transistor that exhibits a small change in threshold voltage and exhibits high reliability.

  In addition, the inventors of the present invention have a gate insulating film having a stacked structure of the first gate insulating film and the second gate insulating film in contact with the first gate insulating film, and the second gate insulating film However, it has been found that a structure with few defects at the interface between the gate insulating film and the semiconductor layer can be created by placing the semiconductor layer in contact with the semiconductor layer. Therefore, the field effect transistor in which the gate insulating film and the semiconductor layer are combined has fewer defects at the interface between the gate insulating film and the semiconductor layer, and the amount of variation in threshold voltage with respect to the BTS test is reduced. A field-effect transistor that exhibits reliability can be provided. In addition, by using an oxide semiconductor for the semiconductor layer, there are fewer defects at the interface between the gate insulating film and the semiconductor layer, the amount of variation in threshold voltage with respect to the BTS test is smaller, and a field effect that exhibits high reliability. Type transistors can be provided.

<Gate electrode>
The gate electrode is not particularly limited as long as it is an electrode for applying a gate voltage to the field effect transistor, and can be appropriately selected according to the purpose.

  For example, the gate electrode is in contact with the gate insulating film and faces the semiconductor layer with the gate insulating film interposed therebetween.

  The material of the gate electrode is not particularly limited and can be appropriately selected according to the purpose. For example, metals such as Mo, Al, Au, Ag, Cu and alloys thereof, indium tin oxide (ITO), Examples thereof include transparent conductive oxides such as antimony-doped tin oxide (ATO), and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI).

-Formation method of gate electrode-
The method for forming the gate electrode is not particularly limited and may be appropriately selected depending on the purpose. For example, (i) a method of patterning by photolithography after film formation by sputtering, dip coating, or the like, ii) A method of directly forming a desired shape by a printing process such as inkjet, nanoimprint, or gravure.

  There is no restriction | limiting in particular as an average film thickness of the said gate electrode, Although it can select suitably according to the objective, 20 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

<Source electrode and drain electrode>
The source electrode and the drain electrode are not particularly limited as long as they are electrodes for taking out current from the field effect transistor, and can be appropriately selected according to the purpose.

  The source electrode and the drain electrode are formed, for example, in contact with the gate insulating film.

  The material of the source electrode and the drain electrode is not particularly limited and can be appropriately selected according to the purpose. For example, metals such as Mo, Al, Au, Ag, Cu, and alloys thereof, indium oxide Examples thereof include transparent conductive oxides such as tin (ITO) and antimony-doped tin oxide (ATO), and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI).

-Method for forming source electrode and drain electrode-
There is no restriction | limiting in particular as a formation method of the said source electrode and the said drain electrode, According to the objective, it can select suitably, For example, (i) After film-forming by a sputtering method, a dip-coating method, etc., by photolithography Examples thereof include a patterning method, and (ii) a method of directly forming a desired shape by a printing process such as inkjet, nanoimprint, and gravure.

  There is no restriction | limiting in particular as an average film thickness of the said source electrode and the said drain electrode, Although it can select suitably according to the objective, 20 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

<Semiconductor layer>
The semiconductor layer is formed at least between the source electrode and the drain electrode.
Here, “between” is a position where the semiconductor layer functions together with the source electrode and the drain electrode so that the field effect transistor functions. It can be selected as appropriate according to the conditions.

  For example, the semiconductor layer is in contact with the gate insulating film, the source electrode, and the drain electrode.

There is no restriction | limiting in particular as a material of the said semiconductor layer, According to the objective, it can select suitably, For example, a silicon semiconductor, an oxide semiconductor, etc. are mentioned.
Examples of the silicon semiconductor include amorphous silicon and polycrystalline silicon.
Examples of the oxide semiconductor include In—Ga—Zn—O, In—Zn—O, In—Mg—O, and the like.
Among these, an oxide semiconductor is preferable.

-Semiconductor layer formation method-
There is no restriction | limiting in particular as a formation method of the said semiconductor layer, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, an atomic layer After forming a film by a vacuum process such as an evaporation (ALD) method or a solution process such as dip coating, spin coating, or die coating, a desired pattern is directly formed by a method such as patterning by photolithography, or a printing method such as inkjet, nanoimprint, or gravure. Examples include a method of forming a film.

  There is no restriction | limiting in particular as an average film thickness of the said semiconductor layer, Although it can select suitably according to the objective, 5 nm-1 micrometer are preferable and 10 nm-0.5 micrometer are more preferable.

<Field effect transistor>
An example of the field effect transistor of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the field effect transistor 10 includes a base material 11, a gate electrode 12, a first gate insulating film 13, a second gate insulating film 14, a semiconductor layer 15, and a source electrode 16. , A bottom gate / top contact field effect transistor having a drain electrode 17. In FIG. 1, the second gate insulating film is formed on the first gate insulating film, but a bottom gate / bottom contact type may be used as shown in FIG.
Also, as shown in FIGS. 3 and 4, in the field effect transistor of FIGS. 1 and 2, the first gate insulating film and the second gate insulating film may be arranged in reverse.
Furthermore, the field effect transistor of the present invention may be a top gate / top contact field effect transistor or a top gate / bottom contact field effect transistor.

(Display element)
The display element of the present invention includes at least a light control element and a drive circuit that drives the light control element, and further includes other members as necessary.

<Light control element>
The light control element is not particularly limited as long as it is an element that controls light output in accordance with a drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element, electrochromic ( EC) element, liquid crystal element, electrophoretic element, electrowetting element and the like.

<Drive circuit>
The drive circuit is not particularly limited as long as it has the field effect transistor of the present invention, and can be appropriately selected according to the purpose.

<Other members>
There is no restriction | limiting in particular as said other member, According to the objective, it can select suitably.

  Since the display element includes the field effect transistor of the present invention, high-speed driving is possible, long life is possible, and variation between elements can be reduced. In addition, the driving transistor can be operated with a constant gate voltage even if the display element changes with time.

(Image display device)
The image display device of the present invention includes at least a plurality of display elements, a plurality of wirings, and a display control device, and further includes other members as necessary.

<Multiple display elements>
The plurality of display elements are not particularly limited as long as they are a plurality of the display elements of the present invention arranged in a matrix, and can be appropriately selected according to the purpose.

<Multiple wiring>
The plurality of wirings are not particularly limited as long as the gate voltage and the signal voltage can be individually applied to each field effect transistor in the plurality of display elements, and can be appropriately selected according to the purpose.

<Display control device>
The display control device is not particularly limited as long as the gate voltage and the signal voltage of each field effect transistor can be individually controlled via the plurality of wirings according to image data. It can be selected appropriately.

<Other members>
There is no restriction | limiting in particular as said other member, According to the objective, it can select suitably.
Since the image display device includes the display element of the present invention, it is possible to reduce variation between elements, and to display a high-quality image on a large screen.

(system)
The system of the present invention includes at least the image display device of the present invention and an image data creation device.
The image data creation device creates image data based on image information to be displayed, and outputs the image data to the image display device.
Since the system includes the image display device of the present invention, it is possible to display image information with high definition.

Hereinafter, a display element, an image display device, and a system of the present invention will be described with reference to the drawings.
First, a television device as a system of the present invention will be described with reference to FIG. Note that the configuration of FIG. 5 is an example, and the television apparatus as the system of the present invention is not limited to this.

In FIG. 5, a television apparatus 100 includes a main control device 101, a tuner 103, an AD converter (ADC) 104, a demodulation circuit 105, a TS (Transport Stream) decoder 106, an audio decoder 111, a DA converter (DAC) 112, an audio output. Circuit 113, speaker 114, video decoder 121, video / OSD synthesis circuit 122, video output circuit 123, image display device 124, OSD drawing circuit 125, memory 131, operation device 132, drive interface (drive IF) 141, hard disk device 142 An optical disk device 143, an IR light receiver 151, and a communication control device 152.
The video decoder 121, the video / OSD synthesis circuit 122, the video output circuit 123, and the OSD drawing circuit 125 constitute an image data creation device.

The main control device 101 includes a CPU, a flash ROM, a RAM, and the like, and controls the entire television device 100.
The flash ROM stores a program described by codes readable by the CPU, various data used for processing by the CPU, and the like.
The RAM is a working memory.

  The tuner 103 selects a preset channel broadcast from the broadcast waves received by the antenna 210.

  The ADC 104 converts the output signal (analog information) of the tuner 103 into digital information.

  The demodulation circuit 105 demodulates the digital information from the ADC 104.

  The TS decoder 106 performs TS decoding on the output signal of the demodulation circuit 105 and separates audio information and video information.

  The audio decoder 111 decodes the audio information from the TS decoder 106.

  The DA converter (DAC) 112 converts the output signal of the audio decoder 111 into an analog signal.

  The audio output circuit 113 outputs the output signal of the DA converter (DAC) 112 to the speaker 114.

  The video decoder 121 decodes the video information from the TS decoder 106.

  The video / OSD synthesis circuit 122 synthesizes the output signal of the video decoder 121 and the output signal of the OSD drawing circuit 125.

  The video output circuit 123 outputs the output signal of the video / OSD synthesis circuit 122 to the image display device 124.

  The OSD drawing circuit 125 includes a character generator for displaying characters and figures on the screen of the image display device 124. The OSD drawing circuit 125 receives a signal including display information in response to an instruction from the operation device 132 and the IR light receiver 151. Generate.

  AV (Audio-Visual) data and the like are temporarily stored in the memory 131.

  The operation device 132 includes, for example, an input medium (not shown) such as a control panel, and notifies the main control device 101 of various information input by the user.

  The drive IF 141 is a bidirectional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 142 includes a hard disk and a drive device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk.

  The optical disk device 143 records data on an optical disk (for example, a DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 151 receives the optical signal from the remote control transmitter 220 and notifies the main control device 101 of it.

  The communication control device 152 controls communication with the Internet. Various information can be acquired via the Internet.

FIG. 6 is a schematic configuration diagram showing an example of the image display apparatus of the present invention.
In FIG. 6, the image display device 124 includes a display device 300 and a display control device 400.
As shown in FIG. 7, the display device 300 includes a display 310 in which a plurality of (here, n × m) display elements 302 are arranged in a matrix.
Further, as shown in FIG. 8, the display 310 has n scanning lines (X0, X1, X2, X3,..., Xn-2, Xn) arranged at equal intervals along the X-axis direction. -1) and m data lines (Y0, Y1, Y2, Y3,..., Ym-1) arranged at equal intervals along the Y-axis direction, at equal intervals along the Y-axis direction. And m current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged.
Therefore, the display element can be specified by the scanning line and the data line.

Hereinafter, the display element of the present invention will be described with reference to FIG.
FIG. 9 is a schematic configuration diagram showing an example of the display element of the present invention.
As shown in FIG. 9 as an example, the display element includes an organic EL (electroluminescence) element 350 and a drive circuit 320 for causing the organic EL element 350 to emit light. The drive circuit 320 is a current-driven 2Tr-1C basic circuit, but is not limited thereto. That is, the display 310 is a so-called active matrix organic EL display.

  FIG. 10 shows an example of the positional relationship between the organic EL element 350 in the display element 302 and the field effect transistor 20 as a drive circuit. Here, the organic EL element 350 is disposed beside the field effect transistor 20. The field effect transistor 10 and the capacitor (not shown) are also formed on the same substrate.

Although not shown in FIG. 10, it is also preferable to provide a protective film on the active layer 22. As a material for the protective film, SiO ₂ , SiON, SiNx, Al ₂ O ₃ , a fluorine-based polymer, or the like can be used as appropriate. Reference numeral 21 denotes a substrate, reference numeral 23 denotes a source electrode, reference numeral 24 denotes a drain electrode, reference numeral 25 denotes a gate insulating film, and reference numeral 26 denotes a gate electrode.

For example, as shown in FIG. 11, the organic EL element 350 may be disposed on the field effect transistor 20. In this case, since the transparent gate electrode 26 is required, the gate electrode _{26, ITO, In 2 O 3,} ZnO of SnO 2, ZnO, ZnO doped with Ga, Al is added, Sb A transparent oxide having conductivity such as SnO ₂ to which is added is used. Reference numeral 360 denotes an interlayer insulating film (flattening film). For this interlayer insulating film, polyimide, acrylic resin, or the like can be used.

FIG. 12 is a schematic configuration diagram illustrating an example of an organic EL element.
In FIG. 12, the organic EL element 350 includes a cathode 312, an anode 314, and an organic EL thin film layer 340.

  The material of the cathode 312 is not particularly limited and may be appropriately selected depending on the purpose. For example, aluminum (Al), magnesium (Mg) -silver (Ag) alloy, aluminum (Al) -lithium (Li) An alloy, ITO (Indium Tin Oxide), etc. are mentioned. A magnesium (Mg) -silver (Ag) alloy becomes a high reflectance electrode if it is sufficiently thick, and a semitransparent electrode if it is an extremely thin film (less than about 20 nm). Although light is extracted from the anode side in FIG. 12, light can be extracted from the cathode side by using a transparent or semi-transparent electrode for the cathode.

  There is no restriction | limiting in particular as a material of the anode 314, According to the objective, it can select suitably, For example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), a silver (Ag) -neodymium (Nd) alloy, etc. Is mentioned. In addition, when a silver alloy is used, it becomes a high reflectance electrode and is suitable when taking out light from the cathode side.

  The organic EL thin film layer 340 includes an electron transport layer 342, a light emitting layer 344, and a hole transport layer 346. The electron transport layer 342 is connected to the cathode 312, and the hole transport layer 346 is connected to the anode 314. When a predetermined voltage is applied between the anode 314 and the cathode 312, the light emitting layer 344 emits light.

  Here, the electron transport layer 342 and the light emitting layer 344 may form one layer, an electron injection layer may be provided between the electron transport layer 342 and the cathode 312, and hole transport is further performed. A hole injection layer may be provided between the layer 346 and the anode 314.

  Further, the case of so-called “bottom emission” in which light is extracted from the substrate side has been described, but “top emission” in which light is extracted from the side opposite to the substrate may be used.

The drive circuit 320 in FIG. 9 will be described.
The drive circuit 320 includes two field effect transistors 10 and 20 and a capacitor 30.

  The field effect transistor 10 operates as a switch element. The gate electrode G of the field effect transistor 10 is connected to a predetermined scanning line, and the source electrode S of the field effect transistor 10 is connected to a predetermined data line. The drain electrode D of the field effect transistor 10 is connected to one terminal of the capacitor 30.

  The field effect transistor 20 supplies current to the organic EL element 350. The gate electrode G of the field effect transistor 20 is connected to the drain electrode D of the field effect transistor 10. The drain electrode D of the field effect transistor 20 is connected to the anode 314 of the organic EL element 350, and the source electrode S of the field effect transistor 20 is connected to a predetermined current supply line.

  The capacitor 30 stores the state of the field effect transistor 10, that is, data. The other terminal of the capacitor 30 is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 10 is turned on, image data is stored in the capacitor 30 via the signal line Y2, and even after the field effect transistor 10 is turned off, the field effect transistor 10 is turned on. The organic EL element 350 is driven by holding 20 in the “on” state corresponding to the image data.

FIG. 13 is a schematic configuration diagram showing another example of the image display device of the present invention.
In FIG. 13, the image display device includes a display element 302, wiring (scanning line, data line, current supply line), and a display control device 400.
The display control device 400 includes an image data processing circuit 402, a scanning line driving circuit 404, and a data line driving circuit 406.
The image data processing circuit 402 determines the luminance of the plurality of display elements 302 in the display based on the output signal of the video output circuit 123.
The scanning line driving circuit 404 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 402.
The data line driving circuit 406 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 402.

  Moreover, although the said embodiment demonstrated the case where a light control element was an organic EL element, it is not limited to this, For example, a light control element may be an electrochromic element. In this case, the display is an electrochromic display.

  The light control element may be a liquid crystal element. In this case, the display is a liquid crystal display, and a current supply line to the display element 302 ′ is not required as shown in FIG. 14. Further, as shown in FIG. 15, the drive circuit 320 ′ can be configured by one field effect transistor 40 similar to the field effect transistors 10 and 20. In the field effect transistor 40, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to the capacitor 361 and the pixel electrode of the liquid crystal element 370.

  The light control element may be an electrophoretic element, an inorganic EL element, or an electrowetting element.

  As described above, the case where the system of the present invention is a television device has been described. However, the present invention is not limited to this, and the image display device 124 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 124 are connected may be used.

  In addition, the image display device 124 is used as a display unit in a portable information device such as a mobile phone, a portable music player, a portable video player, an electronic BOOK, or a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 124 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 124 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

  Examples of the present invention will be described below, but the present invention is not limited to the following examples.

Example 1
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 1, the bottom gate / top contact type field effect transistor shown in FIG. 1 was fabricated. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A Mo / Al / Mo laminated film (gate electrode precursor 12A) having a film thickness of 30 nm / 200 nm / 20 nm was formed on the substrate 11 by DC sputtering (FIG. 16A). A resist pattern was formed on the formed Mo / Al / Mo laminated film (gate electrode precursor 12A) by photolithography, and etching was performed to form a gate electrode 12 having a predetermined shape (FIG. 16B).

<< Formation of First Gate Insulating Film >>
A 200 nm-thick SiO ₂ film (first gate insulating film precursor 13A) was formed on the base material 11 and the gate electrode 12 by RF magnetron sputtering (FIG. 16C). A resist pattern was formed on the SiO ₂ film by photolithography, and etching was performed to form a first gate insulating film 13 having a predetermined shape (FIG. 16D).

<< Formation of Second Gate Insulating Film >>
Next, a second gate insulating film 14 was formed. First, a second gate insulating film forming coating solution was prepared. Specifically, lanthanum toluene solution of ethyl 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL of cyclohexylbenzene and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a second gate insulating film forming coating solution.

Next, a second gate insulating film forming coating solution was dropped onto the first gate insulating film 13 and spin-coated under predetermined conditions. Subsequently, after drying in air at 120 ° C. for 1 hour, firing is performed in an O ₂ atmosphere at 400 ° C. for 3 hours, and strontium lanthanum zirconium oxide that is a paraelectric material and is amorphous (second gate insulating film) Precursor 14A) was obtained (FIG. 16E). The film thickness was about 100 nm.

  A resist pattern was formed on the amorphous strontium lanthanum zirconium oxide film by photolithography, and etching was performed to form a second gate insulating film 14 having a predetermined shape (FIG. 16F).

<< Semiconductor Layer Formation >>
Next, the semiconductor layer 15 was formed. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film (semiconductor layer precursor 15A) was formed by DC sputtering so as to have an average film thickness of about 20 nm (FIG. 16G). Thereafter, a resist pattern was formed on the Mg—In-based oxide film by photolithography, and etching was performed to form a semiconductor layer 15 having a predetermined shape (FIG. 16H).

<< Formation of Source and Drain Electrodes >>
Next, the source electrode 16 and the drain electrode 17 were formed.
Specifically, a Mo / Al / Mo laminated film (electrode precursor 16A) was formed on the second gate insulating film 14 and the semiconductor layer 15 by DC sputtering so as to have a thickness of 30 nm / 200 nm / 20 nm (FIG. 16). 16I). A resist pattern was formed by photolithography on the formed Mo / Al / Mo laminated film, and etching was performed to form a source electrode 16 and a drain electrode 17 having a predetermined shape (FIG. 16J).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing photolithography and etching five times using five photomasks.

(Example 2)
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 2, the bottom gate / top contact type field effect transistor shown in FIG. 1 was fabricated. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 17A and 17B).

<< Formation of First Gate Insulating Film and Second Gate Insulating Film >>
A 200 nm-thickness SiO ₂ film (first gate insulating film precursor 13A) was formed on the base material 11 and the gate electrode 12 by RF magnetron sputtering (FIG. 17C).

In the same manner as in Example 1, a 100 nm-thick strontium lanthanum zirconium oxide (second gate insulating film precursor 14A) was obtained on the SiO ₂ film (FIG. 17D).

  A resist pattern is formed on the amorphous strontium lanthanum zirconium oxide film by photolithography. First, the second gate insulating film precursor 14A is etched, and then the first gate insulating film precursor 13A is etched. A second gate insulating film 14 and a first gate insulating film 13 having the shape shown in FIG. 17 were formed (FIG. 17E).

<< Semiconductor Layer Formation >>
Next, the semiconductor layer 15 was formed in the same manner as in Example 1. Specifically, the DC sputtering was formed as Mg-In-based oxide _(In 2 MgO ₄₎ film (semiconductor layer precursor 15A) the average film thickness of about 20 nm (FIG. 17F). Thereafter, a resist pattern was formed on the Mg—In-based oxide film by photolithography, and etching was performed to form a semiconductor layer 15 having a predetermined shape (FIG. 17G).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 17H and 17I).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing four photolithographys and five etchings using four photomasks.

(Example 3)
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 3, the bottom gate / top contact type field effect transistor shown in FIG. 1 was produced. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 18A and 18B).

<< Formation of First Gate Insulating Film, Second Gate Insulating Film, Semiconductor Layer >>
Similarly to Example 1, a first gate insulating film precursor 13A, a second gate insulating film precursor 14A, and a semiconductor layer precursor 15A were successively formed to form a laminated film (FIGS. 18C to 18E).
A resist pattern was formed by photolithography using a semiconductor photomask, and the semiconductor layer precursor 15A was etched to form a pattern of the semiconductor layer 15 (FIG. 18F). Subsequently, a resist pattern was formed by photolithography using a photomask for the second gate insulating film, and the pattern of the second gate insulating film 14 was formed by etching the second gate insulating film precursor 14A. . The first gate insulating film precursor 13A was etched as it was to form a pattern of the first gate insulating film 13 (FIG. 18G).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 18H and 18I).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing four photolithographys and five etchings using four photomasks.

Example 4
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 3, the bottom gate / top contact type field effect transistor shown in FIG. 1 was produced. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 19A and 19B).

<< Formation of First Gate Insulating Film, Second Gate Insulating Film, Semiconductor Layer >>
Similarly to Example 1, a first gate insulating film precursor 13A, a second gate insulating film precursor 14A, and a semiconductor layer precursor 15A were successively formed to form a laminated film (FIGS. 19C to 19E).
A resist pattern was formed by photolithography using a semiconductor photomask, and the semiconductor layer precursor 15A was etched to form a pattern of the semiconductor layer 15 (FIG. 19F). Subsequently, a resist pattern was formed by photolithography using a photomask for the second gate insulating film, and the pattern of the second gate insulating film 14 was formed by etching the second gate insulating film precursor 14A. (FIG. 19G). Subsequently, the pattern of the first gate insulating film 13 was formed by etching the first gate insulating film precursor 13A using a photomask of the first gate insulating film. (FIG. 19H).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 19I and 19J).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing five photolithographys and five etchings using five photomasks.

(Example 5)
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 5, the bottom gate / top contact type field effect transistor shown in FIG. 1 was produced. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 20A and 20B).

<< Formation of First Gate Insulating Film >>
A first gate insulating film 13 was formed in the same manner as in Example 1 (FIGS. 20C and 20D).

<< Formation of Second Gate Insulating Film and Semiconductor Layer >>
Similarly to Example 1, a second gate insulating film precursor 14A and a semiconductor layer precursor 15A were successively formed to form a laminated film (FIGS. 20E and 20F).
A resist pattern was formed by photolithography using a semiconductor photomask, and the semiconductor layer precursor 15A was etched to form a pattern of the semiconductor layer 15 (FIG. 20G). Subsequently, a resist pattern was formed by photolithography using a photomask for the second gate insulating film, and the pattern of the second gate insulating film 14 was formed by etching the second gate insulating film precursor 14A. (FIG. 20H).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 20I and 20J).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing five photolithographys and five etchings using five photomasks.

(Comparative Example 1)
<Manufacture of bottom gate / top contact type field effect transistor>
In Comparative Example 1, a bottom gate / top contact type field effect transistor shown in FIG. 21H was manufactured. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 21A and 21B).

<< Formation of gate insulating film and semiconductor layer >>
A gate insulating film precursor 130A was formed in the same manner as <<<< Formation of Second Gate Insulating Film >>>> in Example 1, and further a gate insulating film 130 was formed by photolithography (FIGS. 21C and 21D). Further, the semiconductor layer 15 was formed in the same manner as in <<< Semiconductor Layer Formation >> in Example 1 (FIGS. 21E and 21F).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 21G and 21H).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be fabricated.

(Example 6)
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 6, the bottom gate / top contact type field effect transistor shown in FIG. 1 was fabricated. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 17A and 17B).

<< Formation of First Gate Insulating Film >>
A SiO _1.8 N _0.13 film (first gate) having a thickness of 200 nm is formed on the substrate 11 and the gate electrode 12 by RF magnetron sputtering using a Si target and an Ar, O ₂ , and N ₂ mixed gas. An insulating film precursor 13A) was formed (FIG. 17C).

<< Formation of Second Gate Insulating Film >>
In the same manner as in Example 1, a 100 nm-thick strontium lanthanum zirconium oxide (second gate insulating film precursor 14A) was obtained on the SiO ₂ film (FIG. 17D).

  A resist pattern is formed on the amorphous strontium lanthanum zirconium oxide film by photolithography. First, the second gate insulating film precursor 14A is etched, and then the first gate insulating film precursor 13A is etched. A second gate insulating film 14 and a first gate insulating film 13 having the shape shown in FIG. 17 were formed (FIG. 17E).

<< Semiconductor Layer Formation >>
Next, the semiconductor layer 15 was formed in the same manner as in Example 1. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film (semiconductor layer precursor 15A) was formed by DC sputtering so as to have an average film thickness of about 20 nm (FIG. 17F). Thereafter, a resist pattern was formed on the Mg—In-based oxide film by photolithography, and etching was performed to form a semiconductor layer 15 having a predetermined shape (FIG. 17G).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 17H and 17I).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing four photolithographys and five etchings using four photomasks.

(Example 7)
<Manufacture of bottom gate / top contact type field effect transistor>
In Example 7, the bottom gate / top contact type field effect transistor shown in FIG. 1 was produced. A manufacturing process will be described with reference to FIGS.
<< Formation of gate electrode >>
A gate electrode 12 was formed in the same manner as in Example 1 (FIGS. 17A and 17B).

<< Formation of First Gate Insulating Film >>
A Si ₃ N ₄ film having a thickness of 200 nm was formed on the substrate 11 and the gate electrode 12 by RF magnetron sputtering using a Si target and an Ar, N ₂ mixed gas.

<< Formation of Second Gate Insulating Film >>
In the same manner as in Example 1, on the SiO ₂ film to obtain strontium lanthanum-zirconium oxide with a thickness of 100nm (second gate insulating film precursor 14A) (FIG. 17D).

  A resist pattern is formed on the amorphous strontium lanthanum zirconium oxide film by photolithography. First, the second gate insulating film precursor 14A is etched, and then the first gate insulating film precursor 13A is etched. A second gate insulating film 14 and a first gate insulating film 13 having the shape shown in FIG. 17 were formed (FIG. 17E).

<< Semiconductor Layer Formation >>
Next, the semiconductor layer 15 was formed in the same manner as in Example 1. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film (semiconductor layer precursor 15A) was formed by DC sputtering so as to have an average film thickness of about 20 nm (FIG. 17F). Thereafter, a resist pattern was formed on the Mg—In-based oxide film by photolithography, and etching was performed to form a semiconductor layer 15 having a predetermined shape (FIG. 17G).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 17H and 17I).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing four photolithographys and five etchings using four photomasks.

(Example 8)
<Manufacture of bottom gate / top contact type field effect transistor>
A field effect transistor was fabricated in the same manner as in Example 1.
However, as the second gate insulating film forming coating solution, 2.4 mL of 2-ethylhexanoate calcium mineral spirit solution (Ca content 5 wt%, Wako Chemical 351-01162) and 2-ethylhexanoate yttrium toluene solution (Y content 8 wt. %, Wako Pure Chemical Industries, Ltd. 258-00301) 7.8 mL was mixed, and 10 mL of toluene was further added to dilute the coating solution to form a second gate insulating film 14 (amorphous calcium yttrium oxide).

Example 9
<Manufacture of bottom gate / top contact type field effect transistor>
A field effect transistor was fabricated in the same manner as in Example 1.
However, as a second gate insulating film forming coating solution, 2-methoxyethanol 15 mL, magnesium nitrate hexahydrate (Wako Pure Chemical Industries 130-09532) 0.77 g and lanthanum nitrate hexahydrate (Wako Pure Chemical Industries 128) -01732) A second gate insulating film 14 (amorphous lanthanum magnesium hafnium oxide) is formed using a coating solution in which 4.3 g and 0.82 g of hafnium (IV) dichloride oxide octahydrate (STREM93-7207) are dissolved. Formed.

(Example 10)
<Manufacture of bottom gate / top contact type field effect transistor>
A field effect transistor was fabricated in the same manner as in Example 1.
However, as the second gate insulating film forming coating solution, 2 mL of 2-ethylhexanoate magnesium toluene solution (Mg content 3 wt%, STREM12-1260) and 2-ethylhexanoate yttrium toluene solution (Y content 8 wt%, Wako Pure Chemical Industries, Ltd.) Industrial 258-00301) 11 mL and titanium n-butoxide (Aldrich 244112) 0.35 mL are mixed, and 15 mL of toluene is further added to form a second gate insulating film 14 (amorphous yttrium magnesium titanium oxide) using a diluted coating solution. did.

(Example 11)
In Example 11, the bottom gate / top contact field effect transistor shown in FIG. 3 was produced. A manufacturing process will be described with reference to FIGS.

<< Formation of gate electrode >>
A gate electrode 12 was formed on the substrate 11 in the same manner as in Example 1 (FIGS. 22A and 22B).

<< Formation of First Gate Insulating Film, Second Gate Insulating Film, Semiconductor Layer >>
Next, the second coating liquid for forming a gate insulating film prepared in Example 1 was dropped onto the substrate 11 and the gate electrode 12 and spin-coated under predetermined conditions. Subsequently, after drying in air at 120 ° C. for 1 hour, firing is performed in an O ₂ atmosphere at 400 ° C. for 3 hours, and strontium lanthanum zirconium oxide that is a paraelectric material and is amorphous (second gate insulating film) Precursor 14A) was obtained. The film thickness was about 100 nm (FIG. 22C).

A 200 nm thick SiO ₂ film (first gate insulating film precursor 13A) was formed on the second gate insulating film precursor 14A by RF magnetron sputtering (FIG. 22D).

Next, a semiconductor layer precursor 15A was formed on the first gate insulating film precursor 14A in the same manner as in Example 1 (FIG. 22E). A semiconductor layer 15 was formed by etching the semiconductor layer into a predetermined shape using a predetermined photomask (FIG. 22F).
Next, a resist pattern is formed by photolithography using a photomask for the gate insulating film. First, the first gate insulating film precursor 13A is etched, and then the second gate insulating film precursor 14A is etched. A second gate insulating film 14 and a first gate insulating film 13 having a predetermined shape were formed (FIG. 22G).

<< Formation of Source and Drain Electrodes >>
Finally, as in Example 1, the source electrode 16 and the drain electrode 17 were formed (FIGS. 22H and 22I).

  Through the above steps, the field effect transistor 10 was manufactured. The size of the channel region formed by the semiconductor layer 15, the source electrode 16 and the drain electrode 17 was W (width) 30 μm and L (length) 10 μm.

  As described above, a field effect transistor could be manufactured by performing four photolithographys and five etchings using four photomasks.

(Evaluation of field effect transistor)
The field effect transistors produced in Examples 1 to 11 and Comparative Example 1 were evaluated as shown in Table 1.
The film thickness a of the first and second gate insulating films in the region where only the insulating film is formed on the substrate and the film thickness b of the first and second gate insulating films in the channel region
-Leakage current that flows between the two electrodes when a voltage of +20 V is applied between the gate electrode and the source electrode In any field effect transistor, the second gate insulating film has a film thickness in the region above the lower electrode pattern. You can see that it is getting thinner. As a result, it was found that the leakage current between the gate electrode and the source electrode was as large as 1.2 × 10 ⁻¹⁰ (A) in the field effect transistor manufactured in Comparative Example 1. On the other hand, it was found that the leakage current of the field effect transistors manufactured in Examples 1 to 11 was as low as 1 × 10 ⁻¹³ (A) or less.

As described above, by using a silicon oxide film, a silicon nitride film, or a silicon oxynitride film as the first gate insulating film, a field effect transistor having high insulating properties can be manufactured, and as the second gate insulating film, A composite oxide comprising one or more elements selected from alkaline earth metals and one or more elements selected from lanthanoids excluding Ga, Sc, Y, and Ce It has been found that a structure having few defects at the interface between the second gate insulating film and the semiconductor layer can be created by using the second gate insulating film. Therefore, the field effect transistor in which the gate insulating film and the semiconductor layer are combined has fewer defects at the interface between the gate insulating film and the semiconductor layer, and the amount of variation in threshold voltage with respect to the BTS test is reduced. A field-effect transistor that exhibits reliability can be provided.
In addition, by using the insulating film forming ink in the present invention, the unevenness of the lower layer is flattened, and the electric field is not concentrated on the edge in the electrode cross section, so that the breakdown voltage is increased. Therefore, the transistor can be driven at a high voltage. it can. Furthermore, since the vacuum film formation and the liquid phase film formation that are completely different from each other are combined, the probability that a defect is generated at the same location is remarkably reduced, so that the defect rate can be made almost zero. In addition, by using an oxide semiconductor for the semiconductor layer, defects at the interface between the gate insulating film and the semiconductor layer are further reduced, and a variation amount of the threshold voltage with respect to the BTS test is further reduced. In particular, the second gate insulating film Highly reliable because the second gate insulating film / semiconductor interface, which is a channel, is kept clean when the gate insulating film is photolithography and etched after the semiconductor is stacked and etched before etching. A field effect transistor can be provided.

Aspects of the present invention are as follows, for example.
<1> A field effect transistor having a gate insulating film,
The gate insulating film is in contact with the first gate insulating film, which is any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film; an alkaline earth metal element; and Ga And a second gate insulating film having an oxide containing at least one element of a lanthanoid excluding Sc, Y, and Ce.
<2> The field effect transistor according to <1>, wherein the oxide further includes at least one element of Al, Ti, Zr, Hf, Nb, and Ta.
<3> The field effect transistor further includes a semiconductor layer,
The field effect transistor according to any one of <1> to <2>, wherein the second gate insulating film is in contact with the semiconductor layer.
<4> The field effect transistor further includes a semiconductor layer,
The field effect transistor according to any one of <1> to <2>, wherein the first gate insulating film is in contact with the semiconductor layer.
<5> a light control element whose light output is controlled according to the drive signal;
A drive circuit that includes the field-effect transistor according to any one of <1> to <4>, and that drives the light control element;
It is a display element characterized by comprising.
<6> The display element according to <5>, wherein the light control element includes any one of an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, and an electrowetting element.
<7> An image display device that displays an image according to image data,
A plurality of the display elements according to any one of <5> to <6> arranged in a matrix;
A plurality of wirings for individually applying a gate voltage and a signal voltage to each field effect transistor in the plurality of display elements;
A display control device that individually controls the gate voltage and the signal voltage of each field-effect transistor through the plurality of wirings according to the image data;
An image display apparatus comprising:
<8> The image display device according to <7>,
Creating image data based on image information to be displayed, and outputting the image data to the image display device;
It is a system characterized by comprising.

DESCRIPTION OF SYMBOLS 10 Field effect transistor 11 Base material 12A Gate electrode precursor 12 Gate electrode 13A 1st gate insulating film precursor 13 1st gate insulating film 14A 2nd gate insulating film precursor 14 2nd gate insulating film 15A Semiconductor Layer precursor 15 Semiconductor layer 16A Electrode precursor 16 Source electrode 17 Drain electrode 302, 302 'Display element 310 Display 320, 320' Drive circuit 370 Liquid crystal element 400 Display control device

JP2011-216845A

Claims (8)

A field effect transistor having a gate insulating film,
The gate insulating film is in contact with the first gate insulating film, which is one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, the alkaline earth metal element, and Ga And a second gate insulating film having an oxide containing at least one element of a lanthanoid excluding Sc, Y, and Ce.   The field effect transistor according to claim 1, wherein the oxide further contains at least one element of Al, Ti, Zr, Hf, Nb, and Ta. The field effect transistor further includes a semiconductor layer,
The field effect transistor according to claim 1, wherein the second gate insulating film is in contact with the semiconductor layer. The field effect transistor further includes a semiconductor layer,
The field effect transistor according to claim 1, wherein the first gate insulating film is in contact with the semiconductor layer. A light control element whose light output is controlled according to a drive signal;
A drive circuit that includes the field-effect transistor according to claim 1 and that drives the light control element;
A display element comprising:   The display element according to claim 5, wherein the light control element includes any one of an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, and an electrowetting element. An image display device that displays an image according to image data,
A plurality of display elements according to any one of claims 5 to 6 arranged in a matrix;
A plurality of wirings for individually applying a gate voltage and a signal voltage to each field effect transistor in the plurality of display elements;
A display control device that individually controls the gate voltage and the signal voltage of each field-effect transistor through the plurality of wirings according to the image data;
An image display device comprising: An image display device according to claim 7,
Creating image data based on image information to be displayed, and outputting the image data to the image display device;
A system comprising: