JP2017175125A - Manufacturing method of field-effect transistor, manufacturing method of volatile semiconductor memory device, manufacturing method of nonvolatile semiconductor memory device, manufacturing method of display device, manufacturing method of image display, and manufacturing method of system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To pattern, by wet etching, a layer formed from a first oxide in a method for manufacturing a field-effect transistor in which at least any one of a gate insulator layer and a passivation layer is formed from the first oxide including an alkali-earth metal and at least any one of Ga, Sc, Y and lanthanoids.SOLUTION: A method for manufacturing a field-effect transistor having a gate insulator layer, an active layer, and a passivation layer, comprises: a first step for forming the gate insulator layer; and a second step for forming the passivation layer. At least any one of the first and second steps includes the steps of: forming a first oxide including an alkali-earth metal and at least any one of Ga, Sc, Y and lanthanoids; and etching the first oxide by a first liquid solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and oxygenated water.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a field effect transistor, a method for manufacturing a volatile semiconductor memory element, a method for manufacturing a nonvolatile semiconductor memory element, a method for manufacturing a display element, a method for manufacturing an image display device, and a method for manufacturing a system.

  A field effect transistor (FET), which is a kind of semiconductor element, is based on the principle of applying a voltage to a gate electrode and providing a gate (gate) for the flow of electrons or holes by the electric field of the channel. It is a transistor that controls the current between the electrodes.

  FETs are used as switching elements and amplifying elements because of their characteristics. In addition to a low gate current, the structure is planar, so that it is easier to fabricate and integrate than a bipolar transistor. Therefore, the FET is an indispensable element in the integrated circuit used in the current electronic equipment.

  Conventionally, a silicon-based insulating film has been widely used for a gate insulating layer of a field effect transistor. However, in recent years, demands for further higher integration and lower power consumption of field-effect transistors have increased, and so-called high-k insulating films having a dielectric constant much higher than that of silicon-based insulating films are used for gate insulating layers. Technology is being considered. For example, field effect transistors and semiconductor memories have been proposed in which an oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid is used as a gate insulating layer (for example, a patent) Reference 1).

  In addition, since an oxide containing an alkaline earth metal and a rare earth element (Sc, Y, lanthanoid) has a high barrier property, an oxide containing an alkaline earth metal and a rare earth element is used as a passivation layer. A field effect transistor provided has been proposed (see, for example, Patent Document 2).

  As a patterning method for an oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid, Patent Document 1 discloses a photolithography process using dry etching. The dry etching has disadvantages such as high risk of gas used, high environmental load, and expensive equipment, and patterning by a photolithography process using wet etching is preferable.

By the way, a silicon-based insulating film (SiO ₂ or SiON) that has been widely used for a gate insulating layer or a passivation layer can be wet-etched with a hydrofluoric acid-based etching solution. However, there is no report on a solution that can wet-etch an oxide containing an alkaline earth metal and a rare earth element, and the gate insulating layer or the passivation layer includes an alkaline earth metal, Ga, Sc, Y, and a lanthanoid. When an oxide containing the selected element is used, patterning by a photolithography process using wet etching is difficult.

  Therefore, in a manufacturing process of a field effect transistor using an oxide containing an alkaline earth metal and an element selected from Ga, Sc, Y, and a lanthanoid as a gate insulating layer or a passivation layer, Alternatively, it is desired to form the passivation layer by a photolithography process using wet etching.

  The present invention relates to a field effect transistor in which at least one of a gate insulating layer and a passivation layer is formed of a first oxide containing an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanoid. In the manufacturing method, an object is to pattern a layer formed from the first oxide by wet etching.

  The field effect transistor manufacturing method is a method of manufacturing a field effect transistor having a gate insulating layer, an active layer, and a passivation layer, the first step of forming the gate insulating layer and the passivation. A second step of forming a layer, wherein at least one of the first step and the second step includes an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanoid. Forming a first oxide containing, and etching the first oxide with a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide. And a step of including.

  According to the disclosed technique, a field effect formed from a first oxide in which at least one of the gate insulating layer and the passivation layer includes an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanoid. In the method for manufacturing a type transistor, a layer formed of the first oxide can be patterned by wet etching.

1 is a cross-sectional view illustrating a field effect transistor according to a first embodiment. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the field effect transistor according to the first embodiment; FIG. 6 is a diagram (No. 2) for exemplifying the manufacturing process of the field effect transistor according to the first embodiment; It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 1st Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on 2nd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the organic electroluminescent display element which concern on 3rd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the organic electroluminescent display element which concern on the modification of 3rd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the field effect transistor which concern on 4th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the volatile semiconductor memory element which concerns on 5th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the volatile semiconductor memory element which concerns on 6th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the non-volatile semiconductor memory element which concerns on 7th Embodiment. It is sectional drawing explaining the structure and manufacturing method of the non-volatile semiconductor memory element which concerns on 8th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on 9th Embodiment. It is FIG. (The 1) which illustrates the manufacturing process of the field effect transistor which concerns on 9th Embodiment. It is FIG. (The 2) which illustrates the manufacturing process of the field effect transistor which concerns on 9th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 9th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on 10th Embodiment. It is FIG. (The 1) which illustrates the manufacturing process of the field effect transistor which concerns on 10th Embodiment. It is FIG. (The 2) which illustrates the manufacturing process of the field effect transistor which concerns on 10th Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 10th Embodiment. It is sectional drawing (the 1) explaining the structure and manufacturing method of the organic electroluminescent display element which concern on 11th Embodiment. It is sectional drawing (the 2) explaining the structure and manufacturing method of the organic electroluminescent display element which concern on 11th Embodiment. It is a block diagram which shows the structure of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 1) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 2) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 3) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing of the display element which concerns on 12th Embodiment. It is explanatory drawing of organic EL which concerns on 12th Embodiment. It is explanatory drawing (the 4) of the television apparatus which concerns on 12th Embodiment. It is explanatory drawing (the 1) of the other display element which concerns on 12th Embodiment. It is explanatory drawing (the 2) of the other display element which concerns on 12th Embodiment. It is a figure which shows the Vgs-Ids characteristic change before and behind a BTS test. It is a figure which shows the variation | change_quantity ((DELTA) Vth) of the threshold voltage with respect to stress time.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

  The inventors have prepared a first oxide containing an element A that is an alkaline earth metal and a element B that is at least one of Ga, Sc, Y, and a lanthanoid, hydrochloric acid, oxalic acid, nitric acid, It has been found that etching is possible by contacting with a first solution containing at least one of phosphoric acid, acetic acid, sulfuric acid, and aqueous hydrogen peroxide. The following embodiments are based on the above findings of the inventors.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating a field effect transistor according to the first embodiment. Referring to FIG. 1, a field effect transistor 10 includes a substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, an active layer 16, and a passivation layer 17. This is a bottom-gate / bottom-contact field effect transistor. The field effect transistor 10 is a typical example of a semiconductor device according to the present invention.

  One of the functions of the passivation layer in the present invention is a layer having a function of isolating and protecting at least the active layer (semiconductor layer) from moisture, oxygen, hydrogen, etc. in the atmosphere. In addition, the passivation layer in the present invention may protect not only the active layer but also other components of the field effect transistor (for example, the gate insulating layer, the source electrode, the drain electrode, and the gate electrode). Good. One of the functions of the passivation layer in the present invention is to protect (at least a part of) the field effect transistor from the material of the layer formed on the field effect transistor and the formation process thereof.

  In addition, the passivation layer of the field effect transistor is physically separated from other components of the field effect transistor via, for example, an EL (Electro Luminescence) element or the like, regardless of the place where the field effect transistor is formed. However, it is one of the components of a field effect transistor. That is, for example, a passivation layer formed after forming an EL element or the like or a passivation layer provided in the vicinity of the interlayer insulating film is also a passivation layer of a field effect transistor.

  Further, the passivation layer is sometimes called a protective layer.

  In the field effect transistor 10, a gate electrode 12 is formed on an insulating substrate 11, and a gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 13, and an active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are formed at a predetermined interval that becomes a channel region of the active layer 16. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16. Hereinafter, each component of the field effect transistor 10 will be described in detail.

  In the present embodiment, for the sake of convenience, the passivation layer 17 side is defined as the upper side or one side, and the substrate 11 side is defined as the lower side or the other side. In addition, the surface on the passivation layer 17 side of each part is the upper surface or one surface, and the surface on the substrate 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at an arbitrary angle. Further, the planar view refers to viewing the object from the normal direction of the upper surface of the substrate 11, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the substrate 11.

  There is no restriction | limiting in particular as a shape of the board | substrate 11, a structure, and a magnitude | size, According to the objective, it can select suitably. There is no restriction | limiting in particular as a material of the board | substrate 11, Although it can select suitably according to the objective, For example, a glass base material, a ceramic base material, a plastic base material, a film base material etc. can be used.

  There is no restriction | limiting in particular as a glass base material, Although it can select suitably according to the objective, For example, an alkali free glass, a silica glass, etc. are mentioned. Moreover, there is no restriction | limiting in particular as a plastic base material or a film base material, Although it can select suitably according to the objective, For example, a polycarbonate (PC), a polyimide (PI), a polyethylene terephthalate (PET), a polyethylene naphthalate (PEN) and the like.

  The gate electrode 12 is formed in a predetermined region on the substrate 11. The gate electrode 12 is an electrode for applying a gate voltage. The material of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag) ), Copper (Cu), zinc (Zn), nickel (Ni), chromium (Cr), tantalum (Ta), molybdenum (Mo), titanium (Ti) and other metals, alloys thereof, mixtures of these metals, etc. Can be used. In addition, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, mixtures thereof, and the like may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. There is no restriction | limiting in particular as an average film thickness of the gate electrode 12, Although it can select suitably according to the objective, 10 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

  The gate insulating layer 13 is provided between the gate electrode 12 and the active layer 16 and is a layer for insulating the gate electrode 12 and the active layer 16. There is no restriction | limiting in particular as an average film thickness of the gate insulating layer 13, Although it can select suitably according to the objective, 50 nm-3 micrometers are preferable, and 100 nm-1 micrometer are more preferable.

  The source electrode 14 and the drain electrode 15 are formed on the gate insulating layer 13. The source electrode 14 and the drain electrode 15 are formed at a predetermined interval. The source electrode 14 and the drain electrode 15 are electrodes for taking out a current in response to application of a gate voltage to the gate electrode 12. Note that the source electrode 14 and the drain electrode 15 and the wiring connected to the source electrode 14 and the drain electrode 15 may be formed in the same layer.

  The material of the source electrode 14 and the drain electrode 15 is not particularly limited and may be appropriately selected depending on the purpose. For example, aluminum (Al), platinum (Pt), palladium (Pd), gold (Au) , Silver (Ag), Copper (Cu), Zinc (Zn), Nickel (Ni), Chromium (Cr), Tantalum (Ta), Molybdenum (Mo), Titanium (Ti), etc., alloys thereof, these metals A mixture of the above can be used.

  In addition, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, mixtures thereof, and the like may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. There is no restriction | limiting in particular as an average film thickness of the source electrode 14 and the drain electrode 15, Although it can select suitably according to the objective, 10 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

  The active layer 16 is formed on the gate insulating layer 13 so as to cover a part of the source electrode 14 and the drain electrode 15. The active layer 16 located between the source electrode 14 and the drain electrode 15 becomes a channel region. There is no restriction | limiting in particular as average film thickness of the active layer 16, Although it can select suitably according to the objective, 5 nm-1 micrometer are preferable and 10 nm-0.5 micrometer are more preferable.

  There is no restriction | limiting in particular as a material of the active layer 16, Although it can select suitably according to the objective, For example, a polycrystalline silicon (p-Si), an amorphous silicon (a-Si), In-Ga-Zn-. Examples thereof include oxide semiconductors such as O and organic semiconductors such as pentacene. Among these, it is preferable to use an oxide semiconductor from the viewpoint of stability of the interface with the gate insulating layer 13 and the passivation layer 17.

  The passivation layer 17 is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16. There is no restriction | limiting in particular as an average film thickness of the passivation layer 17, Although it can select suitably according to the objective, 50 nm-3 micrometers are preferable, and 100 nm-1 micrometer are more preferable. In FIG. 1, the planar shape of the passivation layer 17 is matched with the planar shape of the gate insulating layer 13, but the present invention is not limited to this. For example, the planar shape of the passivation layer 17 may be smaller than the planar shape of the gate insulating layer 13. Alternatively, the planar shape of the passivation layer 17 may be made larger than the planar shape of the gate insulating layer 13 to cover the side surface of the gate insulating layer 13.

  At least one of the gate insulating layer 13 and the passivation layer 17 is an oxide. The oxide used in this embodiment (hereinafter referred to as the first oxide) includes an A element that is an alkaline earth metal, gallium (Ga), scandium (Sc), yttrium (Y), and a lanthanoid. And at least one of the B elements, and other components as necessary. The alkaline earth metal contained in the first oxide may be one type or two or more types.

  Examples of the alkaline earth metal include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and radium (Ra).

  Lanthanoids include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium. (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

  The first oxide is preferably a paraelectric amorphous oxide. The paraelectric amorphous oxide is stable in the atmosphere and can stably form an amorphous structure in a wide composition range. However, crystals may be included in part of the first oxide.

  The gate insulating layer 13 made of an amorphous material is a preferable form in terms of improving the characteristics of the transistor. This is because if the gate insulating layer 13 is formed of a crystalline material, the leakage current due to the crystal grain boundary cannot be kept low, leading to deterioration of transistor characteristics.

  Further, it is necessary that the gate insulating layer 13 is a paraelectric material in order to reduce hysteresis in the transfer characteristics of the transistor. The exception is the special case where the transistor is used for a memory or the like, but it is not preferable that hysteresis exists in a device that normally uses the switching characteristics of the transistor.

  A paraelectric material is a dielectric material other than a piezoelectric material, pyroelectric material, or ferroelectric material, that is, a dielectric material that does not generate polarization due to pressure or has spontaneous polarization in the absence of an external electric field. Point to. In addition, the piezoelectric body, pyroelectric body and ferroelectric body need to be crystals in order to exhibit their characteristics. That is, when the gate insulating layer 13 is formed of an amorphous material, the gate insulating layer 13 inevitably becomes a paraelectric material.

  Alkaline earth metal oxides easily react with moisture and carbon dioxide in the atmosphere and easily change to hydroxides and carbonates, and are not suitable for application to electronic devices alone. In addition, simple oxides such as Ga, Sc, Y, and lanthanoids are easily crystallized, and leakage current becomes a problem. However, the first oxide is suitable for the gate insulating layer 13 because it is stable in the atmosphere and can form a paraelectric amorphous film in a wide composition region.

  Ce is specifically tetravalent among lanthanoids and forms crystals with a perovskite structure with an alkaline earth metal. Therefore, in order to obtain an amorphous phase, the element B is preferably not Ce.

  A crystal phase such as a spinel structure exists between the alkaline earth metal oxide and the Ga oxide, but these crystals do not precipitate unless the temperature is very high compared to the perovskite structure crystal (generally 1000 ° C. or more). ). In addition, the existence of a stable crystal phase has not been reported between the alkaline earth metal oxide and the oxide composed of Sc, Y, and lanthanoid, and crystal precipitation from the amorphous phase even after a high temperature post-process. Is rare. Furthermore, when an oxide containing an alkaline earth metal and Ga, Sc, Y, and a lanthanoid is composed of three or more kinds of metal elements, the amorphous phase is further stabilized.

  From the viewpoint of producing a high dielectric constant film, it is preferable to increase the composition ratio of elements such as Ba, Sr, Lu, and La. The first oxide can also be used as a material for the passivation layer 17 because it has an excellent barrier property against moisture and oxygen in the atmosphere.

  The first oxide preferably further includes a C element that is at least one of Al, Ti, Zr, Hf, Nb, and Ta. As a result, the amorphous phase is further stabilized, and thermal stability, heat resistance, and denseness can be further improved.

  The composition ratio of the element A, which is an alkaline earth metal in the first oxide, to the element B, which is at least one of Ga, Sc, Y, and a lanthanoid, is not particularly limited and depends on the purpose. However, the following range is preferable.

In the first oxide, as a composition ratio (element A: element B) of an element A that is an alkaline earth metal and element B that is at least one of Ga, Sc, Y, and a lanthanoid the oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Ce 2 O 3, Pr 2 O 3, Nd 2 O 3, Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , in lu ₂ O ₃₎ in terms of, 10.0mol% ~67.0mol%: 33.0mol% ~90.0mol% is preferred.

  An element A which is an alkaline earth metal in the first oxide, an element B which is at least one of Ga, Sc, Y, and a lanthanoid, and Al, Ti, Zr, Hf, Nb, and Ta. There is no restriction | limiting in particular as a composition ratio with the C element which is at least any one, Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the first oxide, an A element that is an alkaline earth metal, a B element that is at least one of Ga, Sc, Y, and a lanthanoid, Al, Ti, Zr, Hf, Nb, and Ta As the composition ratio (A element: B element: C element) with at least one of the above elements, oxides (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ in O ₅₎ conversion, 5.0mol% ~22.0m l%: 33.0mol% ~90.0mol: 5.0mol% ~45.0mol% is preferred.

Oxide in the first oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Ce 2 O 3, Pr 2 O 3, _{Nd 2 O 3, Pm 2 O} 3, Sm 2 O 3, Eu 2 O 3, Gd 2 O 3, Tb 2 O 3, Dy 2 O 3, Ho 2 O 3, Er 2 O 3, Tm 2 O 3, The ratio of Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ ) is, for example, fluorescent X-ray analysis, electron beam microanalysis ( EPMA), dielectric-coupled plasma emission spectroscopy (ICP-AES), and the like can be calculated by analyzing the cation element of the oxide.

When the first oxide is used for the gate insulating layer 13, the material of the passivation layer 17 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used. Similarly, when the first oxide is used for the passivation layer 17, the material of the gate insulating layer 13 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN is used. it can. However, the first oxide may be used for both the gate insulating layer 13 and the passivation layer 17. In this case, the interface between the gate insulating layer 13 and the passivation layer 17 is stable, and it is easy to obtain more reliable characteristics.

  When the first oxide is used for both the gate insulating layer 13 and the passivation layer 17, the gate insulating layer 13 and the passivation layer 17 do not have to be made of the same material. For example, when the gate insulating layer 13 is made of an oxide containing Mg, Ba, and B as La as an A element, the passivation layer 17 is made of gate insulation such as an oxide containing Ca, Sr as an A element, and Gd as a B element. A first oxide different from layer 13 can be used.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. 2 and 3 are diagrams illustrating the manufacturing process of the field effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, the substrate 11 is prepared. Then, a conductive film is formed on the substrate 11 by a vacuum deposition method or the like, and the formed conductive film is patterned by photolithography and etching to form a gate electrode 12 having a predetermined shape. From the viewpoint of cleaning the surface of the substrate 11 and improving adhesion, it is preferable to perform pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning before forming the gate electrode 12. The material and thickness of the substrate 11 and the gate electrode 12 can be appropriately selected as described above.

  The method for forming the gate electrode 12 is not particularly limited and may be appropriately selected depending on the purpose. For example, after film formation by sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like, There is a method of patterning by photolithography. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure.

  Next, in the step shown in FIG. 2B, an insulating layer 130 (which finally becomes the gate insulating layer 13) covering the gate electrode 12 is formed on the entire surface of the substrate 11. There is no restriction | limiting in particular as a formation method of the insulating layer 130, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, an atomic layer The film forming process may be performed by a vacuum process such as vapor deposition (ALD) or a solution process such as dip coating, spin coating, or die coating. Other examples include printing processes such as inkjet, nanoimprint, and gravure. The material and thickness of the insulating layer 130 are as described for the gate insulating layer 13.

  Next, in the step shown in FIG. 2C, the insulating layer 130 formed on the entire surface of the substrate 11 is patterned by photolithography and wet etching to have a predetermined shape, and the gate insulating layer 13 is formed. Specifically, first, an etching mask is formed over the insulating layer 130. The etching mask is not particularly limited. For example, the mask can be formed by spin-coating, pre-baking, exposing, developing, and post-baking a general-purpose resist material. Alternatively, a metal pattern or an oxide pattern formed by a photolithography process can be used as a mask.

  After forming the mask, the insulating layer 130 is etched to form the gate insulating layer 13. The first oxide constituting the gate insulating layer 13 is a solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide (hereinafter referred to as the first solution and the first solution). Can be etched. Specifically, by immersing the first oxide in the first solution and etching, or dropping the first solution on the first oxide and rotating the substrate 11 The method of etching is mentioned.

  The concentration of hydrochloric acid is preferably 0.001 mol / L to 6 mol / L, and more preferably 0.01 mol / L to 1 mol / L. The concentration of oxalic acid is preferably 0.1 to 10%, and more preferably 1 to 5%. The concentration of nitric acid is preferably 0.1 to 40%, more preferably 1 to 20%. The concentration of phosphoric acid is preferably 1 to 90%, more preferably 10 to 80%. The concentration of acetic acid is preferably 0.1 to 80%, and more preferably 1 to 50%. The concentration of sulfuric acid is preferably 0.1 to 50%, and more preferably 1 to 20%. The concentration of the hydrogen peroxide solution is preferably 0.1 to 20%, and more preferably 1 to 10%. Among these solutions, hydrochloric acid and a mixed solution of phosphoric acid and nitric acid are preferable because the solubility of the first oxide is high.

  After the insulating layer 130 is etched to form the gate insulating layer 13, the mask is removed. The mask removal process is not particularly limited, and can be removed by immersing the mask material in a dissolvable solution, for example.

  Next, in a step shown in FIG. 2D, a source electrode 14 and a drain electrode 15 having a predetermined shape are formed on the gate insulating layer 13. From the viewpoint of cleaning the surface of the gate insulating layer 13 and improving adhesion, pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning is preferably performed before the source electrode 14 and the drain electrode 15 are formed.

  The method for forming the source electrode 14 and the drain electrode 15 is not particularly limited and may be appropriately selected depending on the purpose. For example, sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like may be used. There is a method of patterning by photolithography after film formation. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the source electrode 14 and the drain electrode 15 can be appropriately selected as described above.

  Next, in a step shown in FIG. 3A, an active layer 16 having a predetermined shape is formed on the gate insulating layer 13. The method for forming the active layer 16 is not particularly limited and may be appropriately selected depending on the purpose. For example, after film formation by sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like, There is a method of patterning by photolithography. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the active layer 16 can be appropriately selected as described above.

  Next, in the step shown in FIG. 3B, an insulating layer 170 (finally a passivation layer) that covers the source electrode 14, the drain electrode 15, and the active layer 16 over the entire surface of the substrate 11 and the gate insulating layer 13. 17). There is no restriction | limiting in particular as a formation method of the insulating layer 170, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, an atomic layer The film forming process may be performed by a vacuum process such as vapor deposition (ALD) or a solution process such as dip coating, spin coating, or die coating. Other examples include printing processes such as inkjet, nanoimprint, and gravure. The material and thickness of the insulating layer 170 are as described for the passivation layer 17.

  Next, in the step shown in FIG. 3C, the passivation layer 17 is formed by patterning the insulating layer 170 formed on the entire surface of the substrate 11 and the gate insulating layer 13 by photolithography and wet etching into a predetermined shape. To do. A specific method is the same as the method in which the gate insulating layer 13 is formed from the insulating layer 130 in FIG.

  Through the above steps, a bottom-gate / bottom-contact field effect transistor 10 can be manufactured.

  Thus, in the present embodiment, at least one of the gate insulating layer 13 and the passivation layer 17 is the first element that is an alkaline earth metal, and is at least one of Ga, Sc, Y, and a lanthanoid. It is an oxide containing B element. Then, the first oxide is wet-etched with a solution (first solution) containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide solution, and has a predetermined shape. To pattern.

  By using the first solution, the gate insulating layer 13 and the passivation layer 17 can be suitably wet etched. Since it is not necessary to use a conventional dry etching process, no highly dangerous gas is used, and there are no problems such as environmental impact and the price of the equipment used.

In addition, since the relative permittivity of the first oxide is about 6 to 20, which is higher than that of the SiO ₂ film, the use of the first oxide for the gate insulating layer can reduce the field effect transistor. Voltage drive (low power consumption) is possible. Further, since the first oxide has a high barrier property, the use of the first oxide for the passivation layer 17 makes it possible to increase the reliability of the field effect transistor.

  That is, by using the first oxide for at least one of the gate insulating layer 13 and the passivation layer 17 and wet etching the first oxide, a high-performance (low power consumption, high reliability) electric field is obtained. The effect transistor can be manufactured at low cost, high safety, and low environmental load.

<Modification of First Embodiment>
The modification of the first embodiment shows an example of a field effect transistor having a layer structure different from that of the first embodiment. In the modification of the first embodiment, the description of the same components as those of the already described embodiments may be omitted.

  FIG. 4 is a cross-sectional view illustrating a field effect transistor according to a modification of the first embodiment. Each field effect transistor shown in FIG. 4 is a typical example of the semiconductor device according to the present invention.

  A field effect transistor 10A shown in FIG. 4A is a bottom gate / top contact field effect transistor. In the field effect transistor 10 </ b> A, a gate electrode 12 is formed on an insulating substrate 11, and a gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, an active layer 16 is formed on the gate insulating layer 13, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 at a predetermined interval to be a channel region of the active layer 16. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16.

  A field effect transistor 10B shown in FIG. 4B is a top gate / bottom contact field effect transistor. In the field effect transistor 10 </ b> B, a source electrode 14 and a drain electrode 15 are formed on an insulating substrate 11, and an active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the gate electrode 12.

  A field effect transistor 10C shown in FIG. 4C is a top gate / top contact field effect transistor. In the field effect transistor 10 </ b> C, an active layer 16 is formed on an insulative substrate 11, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 with a predetermined interval serving as a channel region of the active layer 16. Is formed. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the gate electrode 12.

  As described above, the layer structure of the field effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 1 and 4 can be appropriately selected according to the purpose. Also in the field effect transistors 10A, 10B, and 10C shown in FIG. 4, at least one of the gate insulating layer 13 and the passivation layer 17 is the first oxide, and the gate insulating layer 13 and the passivation layer 17 have an electric field. It can be manufactured by the same manufacturing method as the effect transistor 10. Therefore, the field effect transistors 10A, 10B, and 10C have the same effect as the field effect transistor 10.

<Second Embodiment>
In the second embodiment, a method for manufacturing the field effect transistor shown in FIG. 5 will be described. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

  FIG. 5 is a cross-sectional view illustrating a field effect transistor according to the second embodiment. Each field effect transistor shown in FIG. 5 is a typical example of a semiconductor device according to the present invention.

  A field effect transistor 120 illustrated in FIG. 5 is a top-gate self-aligned field effect transistor. An active layer 122 is formed on an insulating substrate 121, a gate insulating layer 123 is formed on the active layer 122, and a gate electrode 124 is further formed thereon. An interlayer insulating film 127 is formed so as to cover the substrate 121, the active layer 122, and the gate electrode 124. Note that 122a indicates a source region, and 122b indicates a drain region.

  Further, a source electrode 125 and a drain electrode 126 are formed on the interlayer insulating film 127. The source electrode 125 and the drain electrode 126 are connected to the active layer 122 through through holes formed in the interlayer insulating film 127. A passivation layer 128 is formed so as to cover the interlayer insulating film 127, the source electrode 125, and the drain electrode 126.

  In the top-gate self-aligned field effect transistor 120, since there is no region (overlap region) where the gate electrode 124 overlaps with the source electrode 125 and the drain electrode 126, FIG. 1, FIG. 4A, FIG. The parasitic capacitance can be reduced as compared with the structures shown in FIGS. 4B and 4C, and a field effect transistor that operates at higher speed can be obtained.

  At least one of the gate insulating layer 123 and the passivation layer 128 is the same oxide as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 in the first embodiment. Can be used.

When the first oxide is used for the gate insulating layer 123, the material of the passivation layer 128 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 128, the material of the gate insulating layer 123 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, SiN or the like is used. it can. However, the first oxide may be used for both the gate insulating layer 123 and the passivation layer 128. In this case, the interface between the gate insulating layer 123 and the passivation layer 128 is stabilized, and more reliable characteristics are easily obtained.

  For example, the substrate 121, the active layer 122, the gate electrode 124, the source electrode 125, and the drain electrode 126 are the same as the substrate 11, the active layer 16, the gate electrode 12, the source electrode 14, and the drain electrode 15 of the first embodiment. Material can be applied.

Further, the material of the interlayer insulating film 127 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, SiN or the like can be used.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor 120 will be described. As an example, a method for manufacturing a field effect transistor having the structure using the first oxide for both the gate insulating layer 123 and the passivation layer 128 will be described, but the present invention is not limited thereto.

  First, the active layer 122, the gate insulating layer 123, and the gate electrode 124 are formed over the substrate 121. Specifically, for example, after the active layer 122 is formed over the substrate 121 and the gate insulating layer 123 is formed, the gate electrode 124 is formed, and the gate electrode 124 and the gate insulating layer 123 are formed by photolithography. It can be formed by sequentially etching.

  A process similar to that of the first embodiment can be used for forming the gate insulating layer 123 and the gate electrode 124. As a mask used in the etching process of the gate insulating layer 123, a mask used in the etching process of the gate electrode 124 may be used, or the pattern of the gate electrode itself may be used as a mask.

  In the case where the gate electrode 124 is made of a material that can be wet etched by the first solution, the gate insulating layer 123 and the gate electrode 124 can be etched at a time, and the process can be further simplified. For example, the gate electrode 124 is a single layer or a stack of Al, Al alloy, Mo, and Mo alloy, and a mixed aqueous solution of nitric acid, phosphoric acid, and acetic acid is used as an etchant, whereby the gate electrode 124 and the gate insulating layer 123 are collectively It becomes possible to perform etching.

  Alternatively, the gate electrode 124 may be formed and patterned after the gate insulating layer 123 is formed and patterned on the substrate 121.

Next, an interlayer insulating film 127 is formed. There are no particular limitations on the material and process, and as the material, for example, an insulator such as SiON or SiO ₂ can be used. The patterning method is not particularly limited, and a desired pattern can be obtained by a photolithography method or the like, and through holes can be formed as appropriate.

  Before forming the interlayer insulating film 127, the resistance of the source region 122a and the drain region 122b in FIG. 5 may be reduced by, for example, Ar plasma treatment.

  Next, the source electrode 125 and the drain electrode 126 are formed. The source electrode 125 and the drain electrode 126 are formed on the through holes formed in the interlayer insulating film 127 and are connected to the active layer 122 (the source region 122a and the drain region 122b). As a process, the same process as that of the first embodiment can be applied.

  Finally, a passivation layer 128 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the field effect transistor 120 is formed.

  As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the first oxide is patterned by wet etching, which is a low-cost process similar to that of the first embodiment. In addition, a field effect transistor with high performance (low power consumption and high reliability) can be realized.

<Third Embodiment>
In the third embodiment, an example of an organic electroluminescence (organic EL) display element will be described. Note that in the third embodiment, description of the same components as those of the already described embodiments may be omitted.

[Structure of organic EL display element]
FIG. 6 is a cross-sectional view for explaining the structure and the manufacturing method of the organic EL display element according to the third embodiment. Referring to FIG. 6, an organic EL display element 200 includes a drive circuit 210, an interlayer insulating film 220, an organic EL element 230, a partition wall 240, a sealing layer 250, an adhesive layer 260, and a counter insulating substrate. 270.

  The drive circuit 210 includes the first field effect transistor 20 and the second field effect transistor 30. The first field effect transistor 20 includes a first gate electrode 22, a gate insulating layer 23, a first source electrode 24, a first drain electrode 25, a first drain electrode 25, and a first drain electrode 25, which are formed on a substrate 21 that is an insulating substrate. 1 active layer 26, and first passivation layer 27. The second field effect transistor 30 includes a second gate electrode 32, a gate insulating layer 23, a second source electrode 34, a second drain electrode 35, and a second active electrode formed on the substrate 21. A layer 36 and a second passivation layer 37 are provided. At least one of the gate insulating layer 23, the first passivation layer 27, and the second passivation layer 37 is used in at least one of the gate insulating layer 13 and the passivation layer 17 in the first embodiment. The same oxide as the first oxide can be used.

  The drive circuit 210 includes a through hole in which the first drain electrode 25 of the first field effect transistor 20 and the second gate electrode 32 of the second field effect transistor 30 are formed in the gate insulating layer 23. The structure is a two-transistor one-capacitor connected via the two. In the case of FIG. 6, a capacitor is formed between the second gate electrode 32 and the second source electrode 34. However, the location where the capacitor is formed is not limited, and a capacitor having a necessary capacity is necessary. It can be designed and formed in various places.

  The interlayer insulating film 220 is formed so as to cover the first field effect transistor 20 and the second field effect transistor 30 of the drive circuit 210, and the organic EL element 230 and the partition wall 240 are formed on the interlayer insulating film 220. Is formed.

  The organic EL element 230 is a light control element having a lower electrode 231, an organic EL layer 232, and an upper electrode 233. The lower electrode 231 of the organic EL element 230 is connected to the second drain electrode 35 of the second field effect transistor 30 through a through hole 220 x formed in the interlayer insulating film 220.

  Note that, as in the organic EL display element 200A shown in FIG. 7, the first passivation layer 27 and the second passivation layer 37 may be integrally formed to form the passivation layer 27A. In this case, the lower electrode 231 of the organic EL element 230 is connected to the second field effect transistor 30 via the through hole 220y formed in the interlayer insulating film 220 and the through hole 220z formed in the passivation layer 27A. Connected to the second drain electrode 35.

In the organic EL element 230, the lower electrode 231 includes, for example, a conductive oxide such as ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, or a silver (Ag) -neodymium (Nd) alloy. Etc. can be used. For the upper electrode 233, for example, aluminum (Al), magnesium (Mg) -silver (Ag) alloy, aluminum (Al) -lithium (Li) alloy, ITO, or the like can be used.

  The organic EL layer 232 has an electron transport layer, a light emitting layer, and a hole transport layer. The upper electrode 233 is connected to the electron transport layer, and the lower electrode 231 is connected to the hole transport layer. When a predetermined voltage is applied between the lower electrode 231 and the upper electrode 233, holes and electrons injected from the lower electrode 231 and the upper electrode 233 are recombined in the organic EL layer 232, and light is emitted by the excited energy. The layer emits light. That is, when the first field effect transistor 20 and the second field effect transistor 30 are turned on, the organic EL element 230 emits light.

  On the organic EL element 230, a sealing layer 250, an adhesive layer 260, and a counter insulating substrate 270 are sequentially stacked.

[Method of manufacturing organic EL display element]
Next, a method for manufacturing the organic EL display element 200 will be described. The first field effect transistor 20 and the second field effect transistor 30 can be manufactured by the same materials and processes as those of the field effect transistor according to the first embodiment.

  In the case where the first oxide is used as the passivation layer 27A in FIG. 7, in order to form the through hole 220z, for example, after forming the passivation layer 27A and before forming the interlayer insulating film 220, the passivation layer A mask for opening a portion for forming the through hole 220z is provided on 27A. Then, the passivation layer 27A may be etched with the first solution through a mask.

  Alternatively, after continuously forming the passivation layer 27A and the interlayer insulating film 220, a through hole 220y is formed in the interlayer insulating film 220, and the interlayer insulating film 220 in which the through hole 220y is formed is used as a mask with the first solution. Etching may be performed to form a through hole 220z in the passivation layer 27A.

Various materials and processes can be used to form the interlayer insulating film 220 and the partition wall 240. As the material, for example, an inorganic oxide such as SiO ₂ , SiON, or SiN _x , or an insulating material such as acrylic or polyimide can be used. Regarding the process, for example, after film formation by a sputtering method, spin coating method, or the like, patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as inkjet, nanoimprint, or gravure.

  A method for manufacturing the organic EL element 230 is not particularly limited, and an existing technique can be used. For example, a vacuum film forming method such as a vacuum deposition method or a sputtering method, or a solution process such as an ink jet or nozzle coating is appropriately used. Can be used.

Various materials and processes can be used to form the sealing layer 250. As the material, for example, inorganic oxides such as SiO ₂ , SiON, SiN _{x and the} like can be used. For the process, for example, a vacuum film forming method such as a CVD method or a sputtering method can be used.

  After forming the sealing layer 250, the organic EL display element 200 is completed by bonding the opposing insulating substrate 270 through an adhesive layer 260 made of a material such as an epoxy resin or an acrylic resin, for example.

  As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the high-performance (low power consumption, high performance) is achieved by a low-cost process in which the first oxide is patterned by wet etching. A reliable organic EL display element can be realized.

  Note that the display element according to this embodiment includes at least a light control element and a drive circuit that drives the light control element, and further includes other members as necessary. The light control element is not particularly limited as long as it is an element that controls light output according to a drive signal, and can be appropriately selected according to the purpose. In the above example, an example of a display element using an organic EL element as the light control element has been described. However, as the light control element, a liquid crystal element, an electrochromic element, an electrophoretic element, and an electrowetting element instead of the organic EL element. It is also possible to realize a display element using the above.

  The drive circuit is not particularly limited as long as it has the field effect transistor according to the first embodiment, and can be appropriately selected according to the purpose. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

<Fourth embodiment>
In the fourth embodiment, another example of a field effect transistor is shown. Note that in the fourth embodiment, descriptions of the same components as those of the above-described embodiments may be omitted.

[Structure of field effect transistor]
FIG. 8 is a cross-sectional view illustrating the structure and manufacturing method of the field effect transistor according to the fourth embodiment. Referring to FIG. 8, the field effect transistor 50 includes a substrate 51, a gate electrode 52, a gate insulating layer 53, a gate sidewall insulating film 54, a source region 55, a drain region 56, and an interlayer insulating film 57. A source electrode 58, a drain electrode 59, and a passivation layer 111. The field effect transistor 50 is a typical example of the field effect transistor according to the present invention.

  At least one of the gate insulating layer 53 and the passivation layer 111 is the same oxide as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 in the first embodiment. Can be used.

When the first oxide is used for the gate insulating layer 53, the material of the passivation layer 111 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 111, the material of the gate insulating layer 53 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN is used. it can. However, the first oxide may be used for both the gate insulating layer 53 and the passivation layer 111. In this case, the interface between the gate insulating layer 53 and the passivation layer 111 is stabilized, and more reliable characteristics are easily obtained.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor 50 will be described. As an example, a method for manufacturing a field-effect transistor having the structure using the first oxide for both the gate insulating layer 53 and the passivation layer 111 will be described, but the present invention is not limited to this.

  In order to manufacture the field effect transistor 50, first, a substrate 51 which is a semiconductor substrate is prepared. The material is not particularly limited as long as it is a semiconductor material, and materials such as Si (silicon) and Ge (germanium) to which a desired impurity is added can be appropriately used.

  Next, a gate insulating layer 53 is formed on the substrate 51. The process is not particularly limited. For example, a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  Next, the gate electrode 52 is formed. There are no particular limitations on the material and process, and as the material, for example, a metal material such as polysilicon or Al, or a laminate of these and a barrier metal such as TiN or TaN can be used. For the process, for example, a vacuum film forming method such as a CVD method or a sputtering method can be used. In order to reduce the resistance, a silicide layer such as Ni, Co, or Ti may be formed on the surface of the gate electrode 52, for example.

  The patterning method of the gate electrode 52 is not particularly limited. For example, a mask is formed using a photoresist, and the gate insulating layer 53 or the gate electrode 52 in a region not covered with the mask is removed by a dry etching method. The law is available.

  The process of the gate insulating layer 53 is the same as that of the gate insulating layer 13 according to the first embodiment. The mask material for wet etching of the gate insulating layer 53 is not particularly limited. For example, the pattern of the gate electrode 52 can be used as a mask.

Next, a gate sidewall insulating film 54 is formed on the side surfaces of the gate insulating layer 53 and the gate electrode 52. There are no particular limitations on the material and process, and as the material, for example, an insulator such as SiON or SiO ₂ can be used. The patterning method is not particularly limited, and for example, a method of forming the gate sidewall insulating film 54 on the entire surface of the substrate and then etching the entire surface by a dry etching method can be used.

  Next, the source region 55 and the drain region 56 are formed by selectively implanting ions into the substrate 51. In order to reduce the resistance, for example, silicide layers such as Ni, Co, and Ti may be formed on the surfaces of the source region 55 and the drain region 56.

Next, an interlayer insulating film 57 is formed. There are no particular limitations on the material and process, and as the material, for example, an insulator such as SiON or SiO ₂ can be used. The patterning method is not particularly limited, and a desired pattern can be obtained by a photolithography method or the like, and through holes can be formed as appropriate.

  Next, the source electrode 58 and the drain electrode 59 are formed. The source electrode 58 and the drain electrode 59 are formed so as to fill the through holes formed in the interlayer insulating film 57 and connect to the source region 55 and the drain region 56.

  There are no particular limitations on the materials and processes, and for example, metal materials such as Al and Cu can be used. As for the process, for example, a through hole is filled by a vacuum film formation method such as a sputtering method and then patterned by a photolithography method, or a through hole is filled by a CVD method or a plating method and then a CMP (Chemical Mechanical Polishing) method is used. A flattening method or the like can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably. Alternatively, a W plug in which the through hole is filled with W may be used by using the CVD method.

  Finally, a passivation layer 111 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, a field effect transistor is formed.

  In the field effect transistor 50, an active layer that forms a channel between the source region 55 and the drain region 56 corresponds to the substrate 51. Further, an active layer such as SiGe may be formed between the substrate 51 made of Si and the gate insulating layer 53. Although FIG. 8 shows a top gate structure, the gate insulating layer 53 described above can also be used in a so-called double gate structure or fin type FET.

  As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the first oxide is patterned by wet etching, which is a low-cost process similar to that of the first embodiment. In addition, a field effect transistor with high performance (low power consumption and high reliability) can be realized.

<Fifth embodiment>
In the fifth embodiment, an example of a volatile semiconductor memory element is shown. Note that in the fifth embodiment, description of the same components as those of the above-described embodiments may be omitted.

[Structure of volatile semiconductor memory device]
FIG. 9 is a cross-sectional view for explaining the structure and the manufacturing method of the volatile semiconductor memory element according to the fifth embodiment. Referring to FIG. 9, a volatile semiconductor memory device 60 includes a substrate 61 that is an insulating substrate, a gate electrode 62, a gate insulating layer 63, a source electrode 64, a drain electrode 65, an active layer 66, A first capacitor electrode 67, a capacitor dielectric layer 68, a second capacitor electrode 69, and a passivation layer 112 are included. The volatile semiconductor memory element 60 is a typical example of the semiconductor device according to the present invention.

  At least one of the gate insulating layer 63 and the passivation layer 112 is the same oxide as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 in the first embodiment. Things can be used.

When the first oxide is used for the gate insulating layer 63, the material of the passivation layer 112 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 112, the material of the gate insulating layer 63 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN is used. it can. However, the first oxide may be used for both the gate insulating layer 63 and the passivation layer 112. In this case, the interface between the gate insulating layer 63 and the passivation layer 112 is stable, and it is easy to obtain more reliable characteristics.

  The capacitor dielectric layer 68 is also preferably the first oxide.

[Method for Manufacturing Volatile Semiconductor Memory Device]
Next, a method for manufacturing the volatile semiconductor memory element 60 will be described. As an example, a method for manufacturing a volatile semiconductor memory device having the structure using the first oxide for both the gate insulating layer 63 and the passivation layer 112 will be described, but the present invention is not limited thereto.

  In order to manufacture the volatile semiconductor memory element 60, first, the substrate 61 is prepared. The material is the same as that of the substrate 11 according to the first embodiment. Next, the gate electrode 62 is formed on the substrate 61. The materials and processes are the same as those of the gate electrode 12 according to the first embodiment.

  Next, a second capacitor electrode 69 is formed. Various materials and processes can be used for the second capacitor electrode 69. As materials, for example, metals and alloys such as Mo, Al, Cu and Ru, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI) are used. it can. As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. It is.

  Note that the gate electrode 62 and the second capacitor electrode 69 may be formed at the same time as long as the materials and processes are the same.

  Next, a gate insulating layer 63 made of the first oxide is formed. The process is the same as that of the gate insulating layer 13 according to the first embodiment.

  Next, a capacitor dielectric layer 68 is formed on the second capacitor electrode 69. The material of the capacitor dielectric layer 68 is not particularly limited. For example, a high dielectric constant oxide material containing Hf oxide, Ta oxide, La oxide, etc., lead zirconate titanate (PZT), strontium tantalate A ferroelectric material typified by bismuth (SBT) can be used. In particular, the capacitor dielectric layer 68 is preferably formed of the first oxide.

  The process is not particularly limited. For example, a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film.

  If the materials and processes of the gate insulating layer 63 and the capacitor dielectric layer 68 are the same, they may be formed simultaneously.

  Next, the source electrode 64 and the drain electrode 65 are formed. The materials and processes are the same as those of the source electrode 14 and the drain electrode 15 according to the first embodiment.

  Next, the first capacitor electrode 67 is formed. Various materials and processes can be used for the first capacitor electrode 67. As materials, for example, metals and alloys such as Mo, Al, Cu and Ru, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI) are used. it can. As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. It is.

  Alternatively, the source electrode 64 and the drain electrode 65 may be formed at the same time as long as the materials and processes of the first capacitor electrode 67 are the same.

  Next, the active layer 66 is formed. The material is not particularly limited, and for example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), an oxide semiconductor such as In-Ga-Zn-O, and an organic semiconductor such as pentacene are appropriately used. it can. Among these, an oxide semiconductor is preferable from the viewpoint of stability at the interface between the gate insulating layer 63 and the active layer 66. The process is not particularly limited. For example, the film is formed by a vacuum process such as a sputtering method, a pulse laser deposition (PLD) method, a CVD method, or an ALD method, or a solution process such as spin coating or dip coating, and then by a photolithography method. It is also possible to directly form a desired shape by patterning or a printing process such as inkjet, nanoimprint, or gravure.

  Finally, a passivation layer 112 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above process, the volatile semiconductor memory element 60 is manufactured.

  In the volatile semiconductor memory element 60, the positional relationship among the gate electrode 62, the gate insulating layer 63, the source electrode 64, the drain electrode 65, and the active layer 66 is a so-called bottom gate / bottom contact type. The volatile semiconductor memory device is not limited to this, and may be, for example, a bottom gate / top contact type, a top gate / bottom contact type, or a top gate / top contact type.

  The first capacitor electrode 67, the capacitor dielectric layer 68, and the second capacitor electrode 69 in the volatile semiconductor memory element 60 have a planar structure. For example, the capacitor may be formed by a method such as a three-dimensional structure. The capacity may be increased.

  As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the high-performance (low power consumption, high power) is achieved by a low-cost process in which the first oxide is patterned by wet etching. A reliable volatile semiconductor memory device can be realized. Further, when the first oxide is used for the capacitor dielectric layer in addition to the gate insulating layer, it is preferable that the power consumption can be further reduced.

<Sixth embodiment>
In the sixth embodiment, another example of a volatile semiconductor memory element is shown. Note that in the sixth embodiment, descriptions of the same components as in the already described embodiments may be omitted.

[Structure of volatile semiconductor memory device]
FIG. 10 is a cross-sectional view for explaining the structure and the manufacturing method of the volatile semiconductor memory element according to the sixth embodiment. Referring to FIG. 10, a volatile semiconductor memory device 70 includes a substrate 71 which is a semiconductor substrate, a gate electrode 72, a gate insulating layer 73, a gate sidewall insulating film 74, a source region 75, and a drain region 76. The first interlayer insulating film 77, the bit line electrode 78, the second interlayer insulating film 79, the second capacitor electrode 80, the capacitor dielectric layer 81, the first capacitor electrode 82, and the passivation layer 113. And have. The volatile semiconductor memory element 70 is a typical example of the semiconductor device according to the present invention.

  At least one of the gate insulating layer 73 and the passivation layer 113 is the same oxide as the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 in the first embodiment. Things can be used.

When the first oxide is used for the gate insulating layer 73, the material for the passivation layer 113 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN can be used.

Similarly, when the first oxide is used for the passivation layer 113, the material of the gate insulating layer 73 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, SiN or the like is used. it can. However, the first oxide may be used for both the gate insulating layer 73 and the passivation layer 113. In this case, the interface between the gate insulating layer 73 and the passivation layer 113 is stable, and it is easy to obtain more reliable characteristics.

  The capacitor dielectric layer 81 is also preferably the first oxide.

[Method for Manufacturing Volatile Semiconductor Memory Device]
Next, a method for manufacturing the volatile semiconductor memory element 70 will be described. As an example, a method for manufacturing a volatile semiconductor memory element having the structure using the first oxide for both the gate insulating layer 73 and the passivation layer 113 will be described, but the present invention is not limited thereto.

  In the volatile semiconductor memory device 70, the substrate 71, the gate electrode 72, the gate insulating layer 73, the gate sidewall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 are described in the fourth embodiment. The substrate 51, the gate electrode 52, the gate insulating layer 53, the gate sidewall insulating film 54, the source region 55, the drain region 56, and the interlayer insulating film 57 can be formed by the same materials and processes.

  After forming the gate insulating layer 73, the gate electrode 72, the gate sidewall insulating film 74, the source region 75, the drain region 76, and the first interlayer insulating film 77 on the substrate 71, the bit line electrode 78 is formed. The material and process are not particularly limited, and for example, Al, Cu, or the like can be used. As for the process, for example, a method of patterning by a photolithography method after embedding a through hole by a vacuum film forming method such as a sputtering method or a CVD method, or a method of planarizing by a CMP method after embedding the through hole by a CVD method or a plating method Can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably. Alternatively, a W plug in which the through hole is filled with W may be used by using the CVD method.

  Next, a second interlayer insulating film 79 is formed. The material and process are the same as those of the interlayer insulating film 57 according to the fourth embodiment.

  Next, the second capacitor electrode 80 is formed. There are no particular limitations on the materials and processes, and examples of materials that can be used include metal materials such as Al, Cu, and Ru, and polysilicon. As for the process, for example, a method of patterning by a photolithography method after embedding a through hole by a vacuum film forming method such as a sputtering method or a CVD method, or a method of planarizing by a CMP method after embedding the through hole by a CVD method or a plating method Can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably. Alternatively, a W plug in which the through hole is filled with W may be used by using the CVD method.

  Next, a capacitor dielectric layer 81 is formed. The material of the capacitor dielectric layer 81 is not particularly limited. For example, a high dielectric constant oxide material containing Hf oxide, Ta oxide, La oxide, etc., lead zirconate titanate (PZT), strontium tantalate A ferroelectric material typified by bismuth (SBT) can be used. Among these, it is preferable to form the capacitor dielectric layer 81 with the first oxide.

  The process is not particularly limited. For example, a desired pattern can be formed by a method such as a photolithography method after film formation by a vacuum film formation method such as a CVD method, an ALD method, or a sputtering method. Any film formation method can be used to form an amorphous film. When the first oxide is used for the capacitor dielectric layer 81, the same process as that for the gate insulating layer 13 according to the first embodiment can be used.

  Next, the first capacitor electrode 82 is formed. The material and process are not particularly limited, and for example, a metal material such as Al, Cu, or Ru, or polysilicon can be used. As the process, for example, a method of patterning by a photolithography method after film formation by a vacuum film formation method such as a CVD method or a sputtering method can be used. Moreover, it is good also as a laminated body with barrier metal layers, such as TiN and TaN, suitably.

  Finally, a passivation layer 113 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above process, the volatile semiconductor memory element 70 is manufactured.

  In the volatile semiconductor memory element 70, the stack type volatile semiconductor memory element in which the capacitor is disposed above the field effect transistor has been described. However, the present invention is not limited to this. For example, a volatile semiconductor memory element having a trench structure in which a trench is formed in a semiconductor substrate and a capacitor is disposed below the field effect transistor may be used.

  In addition, the second capacitor electrode 80, the capacitor dielectric layer 81, and the first capacitor electrode 82 in the volatile semiconductor memory element 70 have a planar structure. For example, the capacitor is formed by a method such as a three-dimensional structure. The capacity may be increased.

  As described above, the first oxide is used as at least one of the gate insulating layer and the passivation layer, and the high-performance (low power consumption, high power) is achieved by a low-cost process in which the first oxide is patterned by wet etching. A reliable volatile semiconductor memory device can be realized. Further, when the first oxide is used for the capacitor dielectric layer in addition to the gate insulating layer, it is preferable that the power consumption can be further reduced.

<Seventh embodiment>
In the seventh embodiment, an example of a nonvolatile semiconductor memory element is shown. Note that in the seventh embodiment, description of the same components as those of the above-described embodiment may be omitted.

[Structure of nonvolatile semiconductor memory device]
FIG. 11 is a cross-sectional view illustrating the structure and manufacturing method of the nonvolatile semiconductor memory element according to the seventh embodiment. Referring to FIG. 11, a nonvolatile semiconductor memory element 90 includes a substrate 91 that is an insulating substrate, a gate electrode 92, a first gate insulating layer 93, a floating gate electrode 94, and a second gate insulating layer. 95, a source electrode 96, a drain electrode 97, an active layer 98, and a passivation layer 114. The nonvolatile semiconductor memory element 90 is a typical example of the semiconductor device according to the present invention.

  At least one of the first gate insulating layer 93 and the passivation layer 114 is the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. The same oxide can be used.

When the first oxide is used for the first gate insulating layer 93, the material of the passivation layer 114 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, SiN or the like is used. it can.

Similarly, when the first oxide is used for the passivation layer 114, the material of the first gate insulating layer 93 is not particularly limited. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN is used. Can be used. However, the first oxide may be used for both the first gate insulating layer 93 and the passivation layer 114. In this case, the interface between the first gate insulating layer 93 and the passivation layer 114 is stable, and more highly reliable characteristics are easily obtained.

  The first gate insulating layer 93 is a so-called gate electrode insulating layer, the second gate insulating layer 95 is a so-called tunnel insulating layer, and the gate electrode 92 is a so-called control gate electrode. Depending on the voltage application conditions to the source electrode 96, the drain electrode 97, and the gate electrode 92, electrons can be transferred into and out of the floating gate electrode 94 through the second gate insulating layer, which is a tunnel insulating layer, by the tunnel effect. Function as.

[Method of Manufacturing Nonvolatile Semiconductor Memory Device]
Next, a method for manufacturing the nonvolatile semiconductor memory element 90 will be described. As an example, a method for manufacturing a nonvolatile semiconductor memory element having the first oxide in both the first gate insulating layer 93 and the passivation layer 114 will be described, but the present invention is not limited to this.

  In order to manufacture the nonvolatile semiconductor memory element 90, first, the substrate 91 is prepared. The material is the same as that of the substrate 11 according to the first embodiment.

  Next, a gate electrode 92 is formed on the substrate 91. The materials and processes are the same as those of the gate electrode 12 according to the first embodiment.

  Next, a first gate insulating layer 93 made of the first oxide is formed so as to cover the gate electrode 92. The process is the same as that of the gate insulating layer 13 according to the first embodiment.

  Next, a floating gate electrode 94 is formed on the first gate insulating layer 93. Various materials and processes are available. Examples of the material include metals and alloys such as Mo, Al, and Cu, transparent conductive oxides such as ITO and ATO, and organic conductors such as polyethylenedioxythiophene (PEDOT) and polyaniline (PANI). As a process, for example, after film formation by sputtering, spin coating, dip coating, etc., patterning can be performed by photolithography, or a desired shape can be directly formed by a printing process such as ink jet, nanoimprint, or gravure. It is.

Next, a second gate insulating layer 95 is formed so as to cover the floating gate electrode 94. There is no restriction | limiting in particular about material, An optimal material can be selected suitably. Among them, in order to improve the coupling ratio, for example, a low dielectric constant insulating material such as SiO ₂ or a fluorine-based polymer is preferable. The process is not particularly limited, for example, vacuum coating methods such as sputtering, CVD, ALD, and spin coating using a coating solution containing a metal alkoxide / metal complex or a coating solution containing a polymer Solution processes such as die coating, nozzle coating, and inkjet can also be used as appropriate, and a desired pattern can be formed by using a photolithography method or directly drawing by a printing method.

  Next, the source electrode 96 and the drain electrode 97 are formed over the second gate insulating layer 95. The materials and processes are the same as those of the source electrode 14 and the drain electrode 15 according to the first embodiment.

  Next, the active layer 98 is formed. The material is not particularly limited, and for example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), an oxide semiconductor such as In-Ga-Zn-O, and an organic semiconductor such as pentacene are appropriately used. it can. Among these, an oxide semiconductor is preferable. The process is not particularly limited. For example, the film is formed by a vacuum process such as a sputtering method, a pulse laser deposition (PLD) method, a CVD method, or an ALD method, or a solution process such as spin coating or dip coating, and then by a photolithography method. It is also possible to directly form a desired shape by patterning or a printing process such as inkjet, nanoimprint, or gravure.

  Finally, a passivation layer 114 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the nonvolatile semiconductor memory element 90 is manufactured.

  In the nonvolatile semiconductor memory element 90, the positional relationship among the gate electrode 92, the source electrode 96, the drain electrode 97, and the active layer 98 is a so-called bottom gate / bottom contact type, but the nonvolatile semiconductor memory according to the present embodiment. The element is not limited to this, and may be, for example, a bottom gate / top contact type, a top gate / bottom contact type, or a top gate / top contact type.

  In the non-volatile semiconductor memory element 90, the gate electrode 92, the first gate insulating layer 93, and the floating gate electrode 94 have a planar structure. For example, the capacitor is formed by a method such as a three-dimensional structure. The capacity may be increased.

  As described above, the first oxide is used as at least one of the first gate insulating layer and the passivation layer, and the first oxide is patterned by wet etching. A non-volatile semiconductor memory element with high power and high reliability can be realized. That is, it is possible to suppress the leakage current, reduce the write / erase voltage, and obtain a longer life element.

<Eighth embodiment>
In the eighth embodiment, another example of a nonvolatile semiconductor memory element is shown. Note that in the eighth embodiment, description of the same components as those of the above-described embodiments may be omitted.

[Structure of nonvolatile semiconductor memory device]
FIG. 12 is a cross-sectional view illustrating the structure and the manufacturing method of the nonvolatile semiconductor memory element according to the eighth embodiment. Referring to FIG. 12, a nonvolatile semiconductor memory device 100 includes a substrate 101, which is a semiconductor substrate, a first gate insulating layer 102, a gate electrode 103, a second gate insulating layer 104, a floating gate electrode 105, and gate sidewall insulation. A film 106, a source region 107, a drain region 108, and a passivation layer 115 are included. The nonvolatile semiconductor memory element 100 is a typical example of the semiconductor device according to the present invention.

  At least one of the first gate insulating layer 102 and the passivation layer 115 is the first oxide used in at least one of the gate insulating layer 13 and the passivation layer 17 of the first embodiment. The same oxide can be used.

When the first oxide is used for the first gate insulating layer 102, the material of the passivation layer 115 is not particularly limited, and for example, an inorganic oxide film such as SiO ₂ , SiON, or SiN is used. it can.

Similarly, when the first oxide is used for the passivation layer 115, the material of the first gate insulating layer 102 is not particularly limited. For example, an inorganic oxide film such as SiO ₂ , SiON, or SiN is used. Can be used. However, the first oxide may be used for both the first gate insulating layer 102 and the passivation layer 115. In this case, the interface between the first gate insulating layer 102 and the passivation layer 115 is stable, and more highly reliable characteristics are easily obtained.

  The first gate insulating layer 102 is a so-called gate electrode insulating layer, the second gate insulating layer 104 is a so-called tunnel insulating layer, and the gate electrode 103 is a so-called control gate electrode. Depending on the voltage application conditions to the source region 107, the drain region 108, and the gate electrode 103, electrons can be taken into and out of the floating gate electrode 105 through the second gate insulating layer 104 that is a tunnel insulating layer by a tunnel effect. Functions as a memory.

[Method of Manufacturing Nonvolatile Semiconductor Memory Device]
Next, a method for manufacturing the nonvolatile semiconductor memory element 100 will be described. As an example, a method for manufacturing a nonvolatile semiconductor memory element using the first oxide for both the first gate insulating layer 102 and the passivation layer 115 will be described, but the present invention is not limited thereto.

  In order to manufacture the nonvolatile semiconductor memory element 100, first, the substrate 101 is prepared. The material is the same as that of the substrate 51 in the fourth embodiment.

Next, the second gate insulating layer 104 is formed. The material is not particularly limited, but for example, a low dielectric constant insulating material such as SiO ₂ is preferable. The process is not particularly limited, and for example, a vacuum oxidation method such as a thermal oxidation method, a sputtering method, a chemical CVD method, or an ALD method can be used.

  Next, the floating gate electrode 105 is formed. There are no particular limitations on the material and process, and as the material, for example, a polysilicon, a metal material such as AL, or a laminate of these and a barrier metal such as TiN or TaN can be used. A vacuum film formation method such as a sputtering method can be used.

  Next, a first gate insulating layer 102 made of the first oxide is formed. The process is the same as that of the gate insulating layer 13 according to the first embodiment.

  Next, the gate electrode 103 is formed. The material and process are the same as those of the gate insulating layer 53 according to the fourth embodiment.

  The patterning of the first gate insulating layer 102, the gate electrode 103, the second gate insulating layer 104, and the floating gate electrode 105 is not particularly limited. For example, a desired pattern can be obtained by a photolithography method.

  Next, the gate sidewall insulating film 106 is formed. The material and process are the same as those of the gate sidewall insulating film 54 in the fourth embodiment. Next, the source region 107 and the drain region 108 are formed by selectively implanting ions into the substrate 101. In order to reduce the resistance, for example, silicide layers such as Ni, Co, and Ti may be formed on the surfaces of the source region 107 and the drain region 108.

  Finally, a passivation layer 115 is formed. The material and process are the same as those of the gate insulating layer 13 according to the first embodiment. Through the above steps, the nonvolatile semiconductor memory element 100 is formed.

  In the nonvolatile semiconductor memory element 100, the first gate insulating layer 102, the gate electrode 103, and the floating gate electrode 105 have a planar structure. For example, the capacitor may be formed by a method such as a three-dimensional structure. The capacity may be increased.

  As described above, the first oxide is used as at least one of the first gate insulating layer and the passivation layer, and the first oxide is patterned by wet etching. A non-volatile semiconductor memory element with high power and high reliability can be realized. That is, it is possible to suppress the leakage current, reduce the write / erase voltage, and obtain a longer life element.

<Ninth embodiment>
In the ninth embodiment, an example of a field effect transistor including a plurality of passivation layers is shown. Note that in the ninth embodiment, a description of the same components as those of the above-described embodiments may be omitted.

[Structure of field effect transistor]
FIG. 13 is a cross-sectional view illustrating a field effect transistor according to the ninth embodiment. Referring to FIG. 13, a field effect transistor 110 includes a substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, an active layer 16, and a first passivation layer 17a. And a bottom gate / bottom contact field effect transistor having the second passivation layer 17b. Note that the field-effect transistor 110 is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 110, the gate electrode 12 is formed on the insulating substrate 11, and the gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 13, and an active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are formed at a predetermined interval that becomes a channel region of the active layer 16. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second passivation layer 17b is further formed on the first passivation layer 17a. Is formed.

  The passivation layer is usually formed above the substrate 11. The passivation layer includes a first passivation layer 17a and a second passivation layer 17b disposed in contact with the first passivation layer 17a. In FIG. 13, as an example, the first passivation layer 17 a is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16.

  The arrangement of the first passivation layer 17a and the second passivation layer 17b in the passivation layer is not particularly limited and may be appropriately selected depending on the purpose. As shown in FIG. 13, the first passivation layer 17a May be disposed on the active layer 16 side with respect to the second passivation layer 17b, or conversely, the second passivation layer 17b may be disposed on the active layer 16 with respect to the first passivation layer 17a. Good. Further, the second passivation layer 17b may be disposed so as to cover the upper surface and the side surface of the first passivation layer 17a, or the first passivation layer so as to cover the upper surface and the side surface of the second passivation layer 17b. 17a may be arranged.

-First passivation layer 17a-
The first passivation layer 17a is preferably a second oxide.

-Second oxide-
The second oxide contains Si (silicon) and an alkaline earth metal, preferably contains at least one of Al (aluminum) and B (boron), and, if necessary, other Contains ingredients.

In the second oxide, SiO ₂ formed of Si forms an amorphous structure. The alkaline earth metal has a function of cutting the Si—O bond. Therefore, it is possible to control the relative dielectric constant and the linear expansion coefficient of the second oxide to be formed by the composition ratio of Si and alkaline earth metal.

The second oxide preferably contains at least one of Al and B. _Al 2 _{O 3} formed by Al, and _B 2 _{O 3} formed by B, in order to form a similarly amorphous structure and SiO _2, wherein in the second oxide, and more stable amorphous structure As a result, a more uniform insulating film can be formed. In addition, since the alkaline earth metal changes the coordination structure of Al and B depending on its composition ratio, it is possible to control the relative dielectric constant and the linear expansion coefficient of the second oxide to be formed. .

  In the second oxide, examples of the alkaline earth metal include Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium). These may be used individually by 1 type and may use 2 or more types together.

  There is no restriction | limiting in particular as composition ratio of Si in the said 2nd oxide, and an alkaline-earth metal, Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the second oxide, the composition ratio of Si and alkaline earth metal (Si: alkaline earth metal) is 50 in terms of oxide (SiO ₂ , BeO, MgO, CaO, SrO, BaO). 0.0 mol% to 90.0 mol%: 10.0 mol% to 50.0 mol% is preferable.

  The composition ratio of Si, the alkaline earth metal, and at least one of Al and B in the second oxide is not particularly limited and may be appropriately selected depending on the intended purpose. Preferably there is.

In the second oxide, the composition ratio (Si: alkaline earth metal: at least one of Al and B) of Si, alkaline earth metal, and at least one of Al and B is an oxide (SiO 2). ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) 50.0 mol% to 90.0 mol%: 5.0 mol% to 20.0 mol%: 5.0 mol% to 30.0 mol% is preferable.

The ratio of the oxide (SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) in the _second oxide is, for example, fluorescent X-ray analysis, electron microanalysis (EPMA) ), Dielectric cation plasma emission spectroscopy (ICP-AES) or the like, and by analyzing the cation element of the oxide.

  There is no restriction | limiting in particular as a dielectric constant of the 1st passivation layer 17a, According to the objective, it can select suitably.

  The relative dielectric constant of the first passivation layer 17a can be measured using, for example, an LCR meter or the like by fabricating a capacitor in which a lower electrode, a dielectric layer (first passivation layer), and an upper electrode are stacked. .

  There is no restriction | limiting in particular as a linear expansion coefficient of the 1st passivation layer 17a, According to the objective, it can select suitably.

  The linear expansion coefficient of the first passivation layer 17a can be measured using, for example, a thermomechanical analyzer. In this measurement, the linear expansion coefficient can be measured by separately preparing and measuring a measurement sample having the same composition as that of the first passivation layer 17a without producing a field effect transistor.

-Second passivation layer 17b-
The second passivation layer 17b contains a first oxide. As the first oxide, the oxide exemplified as the material of the gate insulating layer 13 or the passivation layer 17 in the first embodiment can be used. That is, the first oxide includes at least an element A that is an alkaline earth metal and a element B that is at least one of gallium (Ga), scandium (Sc), yttrium (Y), and a lanthanoid. And, if necessary, it contains other components.

  There is no restriction | limiting in particular as a dielectric constant of the 2nd passivation layer 17b, According to the objective, it can select suitably. The relative dielectric constant of the second passivation layer 17b can be measured, for example, by the same method as the relative dielectric constant of the first passivation layer 17a.

  There is no restriction | limiting in particular as a linear expansion coefficient of the 2nd passivation layer 17b, According to the objective, it can select suitably. The linear expansion coefficient of the second passivation layer 17b can be measured, for example, by the same method as the linear expansion coefficient of the first passivation layer 17a.

  The inventors have made the passivation layer a first passivation layer 17a containing the second oxide and a second passivation layer containing the first oxide (for example, paraelectric amorphous oxide). It has been found that the layered structure of 17b exhibits excellent barrier properties against moisture, oxygen and nitrogen in the atmosphere. Therefore, a field effect transistor including a passivation layer can provide a field effect transistor exhibiting high reliability because a variation amount of a threshold voltage with respect to a BTS (Bias Temperature Stress) test is reduced.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 13 will be described. 14 and 15 are diagrams illustrating the manufacturing process of the field effect transistor according to the ninth embodiment.

  First, after performing the same steps as in FIGS. 2A to 3A of the first embodiment, in the step shown in FIG. 14A, the entire surface of the substrate 11 and the gate insulating layer 13 is formed. Then, a first passivation layer 170a (a layer that is etched to become the first passivation layer 17a) that covers the source electrode 14, the drain electrode 15, and the active layer 16 is formed. Then, a second passivation layer 170b (a layer that is etched to become the second passivation layer 17b) is formed on the entire surface of the first passivation layer 170a.

  There is no restriction | limiting in particular as a formation method of the 1st passivation layer 170a and the 2nd passivation layer 170b, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, chemical Examples include film formation by a vacuum process such as vapor deposition (CVD) and atomic layer deposition (ALD).

  The first passivation layer 170a is prepared by preparing a coating solution (first passivation layer forming coating solution) containing the second oxide precursor, and applying or printing the coating solution on an object to be coated. A film can also be formed by firing this under appropriate conditions. Similarly, the second passivation layer 170b is prepared by applying a coating liquid (second passivation layer forming coating liquid) containing the first oxide precursor, and applying or printing the coating liquid on the object to be coated. However, the film can also be formed by baking it under appropriate conditions.

  The average film thickness of the first passivation layer 170a is preferably 10 to 1,000 nm, and more preferably 20 to 500 nm. The average film thickness of the second passivation layer 170b is preferably 10 to 1,000 nm, and more preferably 20 to 500 nm.

--- First passivation layer forming coating solution-
The first passivation layer forming coating solution contains at least a silicon-containing compound, an alkaline earth metal compound, and a solvent, preferably contains at least one of an aluminum-containing compound and a boron-containing compound, and If necessary, other components are contained.

--- Silicon-containing compound ---
Examples of the silicon-containing compound include inorganic silicon compounds and organic silicon compounds.

  Examples of the inorganic silicon compound include tetrachlorosilane, tetrabromosilane, tetraiodosilane, and the like.

  The organosilicon compound is not particularly limited as long as it is a compound having silicon and an organic group, and can be appropriately selected according to the purpose. The silicon and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have a phenyl group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. As an acyloxy group, a C1-C10 acyloxy group etc. are mentioned, for example.

  Examples of the organosilicon compound include tetramethoxysilane, tetraethoxysilane, tetraisopropoxysilane, tetrabutoxysilane, 1,1,1,3,3,3-hexamethyldisilazane (HMDS), and bis (trimethylsilyl) acetylene. , Triphenylsilane, silicon 2-ethylhexanoate, tetraacetoxysilane and the like.

  There is no restriction | limiting in particular as content of the silicon-containing compound in the coating liquid for 1st passivation layer formation, According to the objective, it can select suitably.

--- Alkaline earth metal-containing compound ---
Examples of the alkaline earth metal-containing compound include inorganic alkaline earth metal compounds and organic alkaline earth metal compounds. Examples of the alkaline earth metal in the alkaline earth metal-containing compound include Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  Examples of inorganic alkaline earth metal compounds include alkaline earth metal nitrates, alkaline earth metal sulfates, alkaline earth metal chlorides, alkaline earth metal fluorides, alkaline earth metal bromides, and alkaline earth metal iodides. Etc.

  Examples of the alkaline earth metal nitrate include magnesium nitrate, calcium nitrate, strontium nitrate, and barium nitrate.

  Examples of the alkaline earth metal sulfate include magnesium sulfate, calcium sulfate, strontium sulfate, and barium sulfate.

  Examples of the alkaline earth metal chloride include magnesium chloride, calcium chloride, strontium chloride, barium chloride and the like.

  Examples of the alkaline earth metal fluoride include magnesium fluoride, calcium fluoride, strontium fluoride, and barium fluoride.

  Examples of the alkaline earth metal bromide include magnesium bromide, calcium bromide, strontium bromide, barium bromide and the like.

  Examples of the alkaline earth metal iodide include magnesium iodide, calcium iodide, strontium iodide, barium iodide and the like.

  The organic alkaline earth metal compound is not particularly limited as long as it is a compound having an alkaline earth metal and an organic group, and can be appropriately selected according to the purpose. The alkaline earth metal and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. An acyloxy group which may have, a phenyl group which may have a substituent, an acetylacetonate group which may have a substituent, a sulfonic acid group which may have a substituent, and the like. It is done. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, Examples include acids and acyloxy groups having two or more carbonyl groups such as citric acid.

  Examples of the organic alkaline earth metal compound include magnesium methoxide, magnesium ethoxide, diethyl magnesium, magnesium acetate, magnesium formate, acetylacetone magnesium, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, magnesium citrate, and salicylic acid. Magnesium, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium methoxide, calcium ethoxide, calcium acetate, calcium formate, acetylacetone calcium, calcium dipivaloylmethanate, calcium 2-ethylhexanoate, calcium lactate , Calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, repose Calcium oxide, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetylacetone strontium, strontium 2-ethylhexanoate, strontium lactate, strontium naphthenate, strontium salicylate, strontium oxalate, barium ethoxide, barium isopoxide , Barium acetate, barium formate, barium acetylacetone, barium 2-ethylhexanoate, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, barium benzoate, barium trifluoromethanesulfonate, bis (acetylacetonate) beryllium, etc. Is mentioned.

  There is no restriction | limiting in particular as content of the alkaline earth metal containing compound in the coating liquid for 1st passivation layer formation, According to the objective, it can select suitably.

--- Aluminum-containing compound ---
Examples of the aluminum-containing compound include inorganic aluminum compounds and organic aluminum compounds.

  Examples of the inorganic aluminum compound include aluminum chloride, aluminum nitrate, aluminum bromide, aluminum hydroxide, aluminum borate, aluminum trifluoride, aluminum iodide, aluminum sulfate, aluminum phosphate, and ammonium ammonium sulfate.

  There is no restriction | limiting in particular as long as it is a compound which has aluminum and an organic group as an organoaluminum compound, According to the objective, it can select suitably. Aluminum and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have, an acetylacetonate group which may have a substituent, and a sulfonic acid group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, Examples include acids and acyloxy groups having two or more carbonyl groups such as citric acid.

  Examples of the organoaluminum compound include aluminum isopropoxide, aluminum-sec-butoxide, triethylaluminum, diethylaluminum ethoxide, aluminum acetate, acetylacetone aluminum, hexafluoroacetylacetonate aluminum, 2-ethylhexanoate aluminum, aluminum lactate, benzoic acid Examples thereof include aluminum acid, aluminum di (s-butoxide) acetoacetate chelate, and aluminum trifluoromethanesulfonate.

  There is no restriction | limiting in particular as content of the aluminum containing compound in the coating liquid for 1st passivation layer formation, According to the objective, it can select suitably.

--- Boron-containing compound ---
Examples of the boron-containing compound include inorganic boron compounds and organic boron compounds.

  Examples of the inorganic boron compound include orthoboric acid, boron oxide, boron tribromide, tetrafluoroboric acid, ammonium borate, magnesium borate and the like. Examples of boron oxide include diboron dioxide, diboron trioxide, tetraboron trioxide, and tetraboron pentoxide.

  The organic boron compound is not particularly limited as long as it is a compound having boron and an organic group, and can be appropriately selected according to the purpose. Boron and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have, a phenyl group which may have a substituent, a sulfonic acid group which may have a substituent, and a thiophene group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. An alkoxy group includes two or more oxygen atoms, and two of the two or more oxygen atoms are bonded to boron and form an organic ring structure together with boron. included. Moreover, the alkoxy group by which the alkyl group contained in the alkoxy group was substituted by the organic silyl group is also included. As an acyloxy group, a C1-C10 acyloxy group etc. are mentioned, for example.

  Examples of the organic boron compound include (R) -5,5-diphenyl-2-methyl-3,4-propano-1,3,2-oxazaborolidine, triisopropyl borate, and 2-isopropoxy-4. , 4,5,5-tetramethyl-1,3,2-dioxaborolane, bis (hexylene glycolato) diboron, 4- (4,4,5,5-tetramethyl-1,3,2-dioxaborolane-2 -Yl) -1H-pyrazole, (4,4,5,5-tetramethyl-1,3,2-dioxaborolan-2-yl) benzene, tert-butyl-N- [4- (4,4,5,5) 5-tetramethyl-1,2,3-dioxaborolan-2-yl) phenyl] carbamate, phenylboronic acid, 3-acetylphenylboronic acid, boron trifluoride acetic acid complex, boron trifluoride sulfolane complex , 2-thiophene boronic acid, tris (trimethylsilyl) borate and the like.

  There is no restriction | limiting in particular as content of the boron containing compound in the coating liquid for 1st passivation layer formation, According to the objective, it can select suitably.

--- Solvent ---
The solvent is not particularly limited as long as it is a solvent that stably dissolves or disperses various compounds, and can be appropriately selected according to the purpose. For example, toluene, xylene, mesitylene, cymene, pentylbenzene, dodecylbenzene, Bicyclohexyl, cyclohexylbenzene, decane, undecane, dodecane, tridecane, tetradecane, pentadecane, tetralin, decalin, isopropanol, ethyl benzoate, N, N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, mineral spirits, dimethylpropylene urea 4-butyrolactone, 2-methoxyethanol, propylene glycol, water and the like.

  There is no restriction | limiting in particular as content of the solvent in the coating liquid for 1st passivation layer formation, According to the objective, it can select suitably.

  The composition ratio of the silicon-containing compound and the alkaline earth metal-containing compound in the first passivation layer-forming coating solution (silicon-containing compound: alkaline earth metal-containing compound) is not particularly limited and is appropriately determined depending on the purpose. Although it can select, it is preferable that it is the following ranges.

In the first passivation layer forming coating solution, the composition ratio between Si and alkaline earth metal (Si: alkaline earth metal) is converted to oxide (SiO ₂ , BeO, MgO, CaO, SrO, BaO). And 50.0 mol% to 90.0 mol%: 10.0 mol% to 50.0 mol% is preferable.

  Composition ratio of silicon-containing compound, alkaline earth metal-containing compound, and aluminum-containing compound and boron-containing compound in the first passivation layer forming coating solution (silicon-containing compound: alkaline earth metal-containing compound: aluminum There is no restriction | limiting in particular as at least any one of a containing compound and a boron containing compound), Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the first passivation layer forming coating solution, the composition ratio of Si, alkaline earth metal, and at least one of Al and B (Si: alkaline earth metal: at least one of Al and B) is oxidized. objects _{(SiO 2, BeO, MgO,} CaO, SrO, BaO, Al 2 O 3, B 2 O 3) in terms of, 50.0mol% ~90.0mol%: 5.0mol% ~20.0mol%: 5. 0 mol% to 30.0 mol% is preferable.

--- Second passivation layer forming coating solution-
The second passivation layer-forming coating solution contains at least an alkaline earth metal-containing compound (A-element-containing compound), a B-element-containing compound, and a solvent, preferably at least of the C-element-containing compound. It contains either and, if necessary, contains other components.

--- Alkaline earth metal-containing compound (element A-containing compound) ---
Examples of the alkaline earth metal-containing compound include inorganic alkaline earth metal compounds and organic alkaline earth metal compounds. Examples of the alkaline earth metal in the alkaline earth metal-containing compound include Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  Examples of inorganic alkaline earth metal compounds include alkaline earth metal nitrates, alkaline earth metal sulfates, alkaline earth metal chlorides, alkaline earth metal fluorides, alkaline earth metal bromides, and alkaline earth metal iodides. Etc.

  Examples of the alkaline earth metal nitrate include magnesium nitrate, calcium nitrate, strontium nitrate, and barium nitrate.

  Examples of the alkaline earth metal sulfate include magnesium sulfate, calcium sulfate, strontium sulfate, and barium sulfate.

  Examples of the alkaline earth metal chloride include magnesium chloride, calcium chloride, strontium chloride, barium chloride and the like.

  Examples of the alkaline earth metal fluoride include magnesium fluoride, calcium fluoride, strontium fluoride, and barium fluoride.

  Examples of the alkaline earth metal bromide include magnesium bromide, calcium bromide, strontium bromide, barium bromide and the like.

  Examples of the alkaline earth metal iodide include magnesium iodide, calcium iodide, strontium iodide, barium iodide and the like.

  The organic alkaline earth metal compound is not particularly limited as long as it is a compound having an alkaline earth metal and an organic group, and can be appropriately selected according to the purpose. The alkaline earth metal and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. An acyloxy group which may have, a phenyl group which may have a substituent, an acetylacetonate group which may have a substituent, a sulfonic acid group which may have a substituent, and the like. It is done. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, Examples include acids and acyloxy groups having two or more carbonyl groups such as citric acid.

  Examples of the organic alkaline earth metal compound include magnesium methoxide, magnesium ethoxide, diethyl magnesium, magnesium acetate, magnesium formate, acetylacetone magnesium, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, magnesium citrate, and salicylic acid. Magnesium, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium methoxide, calcium ethoxide, calcium acetate, calcium formate, acetylacetone calcium, calcium dipivaloylmethanate, calcium 2-ethylhexanoate, calcium lactate , Calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, repose Calcium oxide, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetylacetone strontium, strontium 2-ethylhexanoate, strontium lactate, strontium naphthenate, strontium salicylate, strontium oxalate, barium ethoxide, barium isopropoxide , Barium acetate, barium formate, barium acetylacetone, barium 2-ethylhexanoate, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, barium benzoate, barium trifluoromethanesulfonate, bis (acetylacetonate) beryllium, etc. Is mentioned.

  There is no restriction | limiting in particular as content of the alkaline-earth metal containing compound in the coating liquid for 2nd passivation layer formation, According to the objective, it can select suitably.

--- B element-containing compound ---
As rare earth elements in the B-element-containing compound, Ga (gallium), Sc (scandium), Y (yttrium), La (lanthanum), Ce (cerium), Pr (praseodymium), Nd (neodymium), Pm (promethium) , Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), Lu (lutetium) Is mentioned.

  Examples of the B element-containing compound include inorganic B element compounds and organic B element compounds.

  Examples of the inorganic B element compound include nitrate of B element, sulfate of B element, fluoride of B element, chloride of B element, bromide of B element, iodide of B element, etc. Is mentioned.

  Examples of the nitrate of the element B include gallium nitrate, scandium nitrate, yttrium nitrate, lanthanum nitrate, cerium nitrate, praseodymium nitrate, neodymium nitrate, samarium nitrate, europium nitrate, gadolinium nitrate, terbium nitrate, dysprosium nitrate, holmium nitrate, nitric acid Examples include erbium, thulium nitrate, ytterbium nitrate, and lutetium nitrate.

  Examples of the element B sulfate include gallium sulfate, scandium sulfate, yttrium sulfate, lanthanum sulfate, cerium sulfate, praseodymium sulfate, neodymium sulfate, samarium sulfate, europium sulfate, gadolinium sulfate, terbium sulfate, dysprosium sulfate, holmium sulfate, Examples thereof include erbium sulfate, thulium sulfate, ytterbium sulfate, and lutetium sulfate.

  Examples of the fluoride of the B element include gallium fluoride, scandium fluoride, yttrium fluoride, lanthanum fluoride, cerium fluoride, praseodymium fluoride, neodymium fluoride, samarium fluoride, europium fluoride, and gadolinium fluoride. Terbium fluoride, dysprosium fluoride, holmium fluoride, erbium fluoride, thulium fluoride, ytterbium fluoride, lutetium fluoride, and the like.

  Examples of the chloride of the element B include gallium chloride, scandium chloride, yttrium chloride, lanthanum chloride, cerium chloride, praseodymium chloride, neodymium chloride, samarium chloride, europium chloride, gadolinium chloride, terbium chloride, dysprosium chloride, holmium chloride, Examples thereof include erbium chloride, thulium chloride, ytterbium chloride, and lutetium chloride.

  Examples of the bromide of the element B include gallium bromide, scandium bromide, yttrium bromide, lanthanum bromide, cerium bromide, praseodymium bromide, neodymium bromide, samarium bromide, europium bromide, gadolinium bromide, Examples thereof include terbium bromide, dysprosium bromide, holmium bromide, erbium bromide, thulium bromide, ytterbium bromide, and lutetium bromide.

  Examples of the element B iodide include gallium iodide, scandium iodide, yttrium iodide, lanthanum iodide, cerium iodide, praseodymium iodide, neodymium iodide, samarium iodide, europium iodide, gadolinium iodide, Examples thereof include terbium iodide, dysprosium iodide, holmium iodide, erbium iodide, thulium iodide, ytterbium iodide, and lutetium iodide.

  The organic B element compound is not particularly limited as long as it is a compound having the B element and an organic group, and can be appropriately selected according to the purpose. The element B and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have, an acetylacetonate group which may have a substituent, and a cyclopentadienyl group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. As an acyloxy group, a C1-C10 acyloxy group etc. are mentioned, for example.

  Examples of the organic element B compound include tris (cyclopentadienyl) gallium, scandium isopropoxide, scandium acetate, tris (cyclopentadienyl) scandium, yttrium isopropoxide, yttrium 2-ethylhexanoate, tris ( Acetylacetonato) yttrium, tris (cyclopentadienyl) yttrium, lanthanum isopropoxide, lanthanum 2-ethylhexanoate, lanthanum tris (acetylacetonato) lanthanum, tris (cyclopentadienyl) lanthanum, cerium 2-ethylhexanoate , Tris (acetylacetonato) cerium, tris (cyclopentadienyl) cerium, praseodymium isopropoxide, praseodymium oxalate, tris (acetylacetonato) praseodymium, tri (Cyclopentadienyl) praseodymium, neodymium isopropoxide, neodymium 2-ethylhexanoate, trifluoroacetylacetonate neodymium, tris (isopropylcyclopentadienyl) neodymium, tris (ethylcyclopentadienyl) promethium, samarium isopropoxy Samarium 2-ethylhexanoate, tris (acetylacetonato) samarium, tris (cyclopentadienyl) samarium, europium 2-ethylhexanoate, tris (acetylacetonato) europium, tris (ethylcyclopentadienyl) europium , Gadolinium isopropoxide, gadolinium 2-ethylhexanoate, tris (acetylacetonato) gadolinium, tris (cyclopentadienyl) gadolinium, vinegar Terbium, tris (acetylacetonato) terbium, tris (cyclopentadienyl) terbium, dysprosium isopropoxide, dysprosium acetate, tris (acetylacetonato) dysprosium, tris (ethylcyclopentadienyl) dysprosium, holmium isopropoxide, Holmium acetate, tris (cyclopentadienyl) holmium, erbium isopropoxide, erbium acetate, tris (acetylacetonato) erbium, tris (cyclopentadienyl) erbium, thulium acetate, tris (acetylacetonato) thulium, tris ( Cyclopentadienyl) thulium, ytterbium isopropoxide, ytterbium acetate, tris (acetylacetonato) ytterbium, tris (cyclo Pentadienyl) ytterbium, lutetium oxalate, tris (ethylcyclopentadienyl) lutetium and the like.

  There is no restriction | limiting in particular as content of the B element containing compound in the coating liquid for 2nd passivation layer formation, According to the objective, it can select suitably.

--- Element C-containing compound ---
Examples of the C element include Al (aluminum), Ti (titanium), Zr (zirconium), Hf (hafnium), Nb (niobium), and Ta (tantalum).

  Examples of the C-element-containing compound include an inorganic compound of the C element and an organic compound of the C element.

  Examples of inorganic compounds of the C element include nitrate of the C element, sulfate of the C element, fluoride of the C element, chloride of the C element, bromide of the C element, iodide of the C element Etc.

  Examples of inorganic compounds of the C element include aluminum nitrate, aluminum sulfate, aluminum fluoride, aluminum chloride, aluminum bromide, aluminum iodide, aluminum hydroxide, aluminum phosphate, aluminum ammonium sulfate, titanium sulfide, and titanium fluoride. , Titanium chloride, titanium bromide, titanium iodide, zirconium sulfate, zirconium carbonate, zirconium fluoride, zirconium chloride, zirconium bromide, zirconium iodide, hafnium sulfate, hafnium fluoride, hafnium chloride, hafnium bromide, hafnium iodide , Niobium fluoride, niobium chloride, niobium bromide, tantalum fluoride, tantalum chloride, tantalum bromide and the like.

  The organic compound of the C element is not particularly limited as long as it is a compound having the C element and an organic group, and can be appropriately selected according to the purpose. The C element and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have, an acetylacetonate group which may have a substituent, and a cyclopentadienyl group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. As an acyloxy group, a C1-C10 acyloxy group etc. are mentioned, for example.

  Examples of the organic compound of element C include aluminum isopropoxide, aluminum-sec-butoxide, triethylaluminum, diethylaluminum ethoxide, aluminum acetate, acetylacetone aluminum, hexafluoroacetylacetonate aluminum, 2-ethylhexanoate aluminum, lactic acid Aluminum, aluminum benzoate, aluminum di (s-butoxide) acetoacetate chelate, aluminum trifluoromethanesulfonate, titanium isopropoxide, bis (cyclopentadienyl) titanium chloride, zirconium butoxide, zirconium isopropoxide, bis (2 -Ethylhexanoic acid) zirconium oxide, zirconium di (n-butoxide) bisacetyl sweat toner tote, tetrakis (acetyl) Acetone acid) zirconium, tetrakis (cyclopentadienyl) zirconium, hafnium butoxide, hafnium isopropoxide, tetrakis (2-ethylhexanoate) hafnium, hafnium di (n-butoxide) bisacetylacetonate, tetrakis (acetylacetonate) hafnium, Examples thereof include bis (cyclopentadienyl) dimethylhafnium, niobium ethoxide, niobium 2-ethylhexanoate, bis (cyclopentadienyl) niobium chloride, tantalum ethoxide, and tetraethoxyacetylacetonate tantalum.

  There is no restriction | limiting in particular as content of the C element containing compound in the coating liquid for 2nd passivation layer formation, According to the objective, it can select suitably.

--- Solvent ---
The solvent is not particularly limited as long as it is a solvent that stably dissolves or disperses various compounds, and can be appropriately selected according to the purpose. For example, toluene, xylene, mesitylene, cymene, pentylbenzene, dodecylbenzene, Bicyclohexyl, cyclohexylbenzene, decane, undecane, dodecane, tridecane, tetradecane, pentadecane, tetralin, decalin, isopropanol, ethyl benzoate, N, N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, mineral spirits, dimethylpropylene urea 4-butyrolactone, 2-methoxyethanol, propylene glycol, water and the like.

  There is no restriction | limiting in particular as content of the solvent in the coating liquid for 2nd passivation layer formation, According to the objective, it can select suitably.

  As the composition ratio (alkaline earth metal-containing compound: B-element-containing compound) of the alkaline-earth metal-containing compound (A-element-containing compound) and the B-element-containing compound in the second passivation layer forming coating solution There is no particular limitation, and it can be appropriately selected according to the purpose, but the following range is preferable.

In the second passivation layer forming coating solution, the composition ratio (element A: element B) of element A, which is an alkaline earth metal, and element B, which is at least one of Ga, Sc, Y, and a lanthanoid. as the element), an oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Ce 2 O 3, Pr 2 O 3, Nd 2 O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ in _{O 3, Lu} 2 O ₃₎ in terms of, 10.0mol% ~67.0mol%: 33.0mol% ~90.0mol% is preferred.

  Composition ratio of at least one of alkaline earth metal-containing compound (A-element-containing compound), B-element-containing compound, and C-element-containing compound in the second passivation layer forming coating solution (alkaline earth metal-containing) There is no restriction | limiting in particular as a compound: B element containing compound: C element containing compound), Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the second passivation layer forming coating solution, the element A which is an alkaline earth metal, the element B which is at least one of Ga, Sc, Y, and a lanthanoid, and Al, Ti, Zr, Hf, and Nb , And Ta as the composition ratio (element A: element B: element C) of oxide (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , _{sc 2 O 3, Y 2 O} 3, La 2 O 3, Ce 2 O 3, Pr 2 O 3, Nd 2 O 3, Pm 2 O 3, Sm 2 O 3, Eu 2 O 3, Gd 2 O 3, _{Tb 2 O 3, Dy 2 O} 3, Ho 2 O 3, Er 2 O 3, Tm 2 O 3, Yb 2 O 3, Lu 2 O 3, Al 2 O 3, TiO 2, ZrO 2, HfO 2, Nb in _{2 O 5, Ta 2 O 5} ) in terms of, .0mol% ~22.0mol%: 33.0mol% ~90.0mol: 5.0mol% ~45.0mol% is preferred.

--- Method for forming first and second passivation layers ---
An example of a first passivation layer forming method using the first passivation layer forming coating solution and an example of a second passivation layer forming method using the second passivation layer forming coating solution will be described. The method for forming the first passivation layer 170a and the second passivation layer 170b includes a coating process and a heat treatment process, and further includes other processes as necessary.

  The application step is not particularly limited as long as it is a step of applying the first passivation layer forming coating solution or the second passivation layer forming coating solution to the object to be coated, and is appropriately selected according to the purpose. Can do. The application method is not particularly limited and can be appropriately selected depending on the purpose. For example, a desired method can be selected by a method of patterning by photolithography after film formation by a solution process, a printing method such as inkjet, nanoimprint, or gravure. And a method of directly forming the film shape. Examples of the solution process include dip coating, spin coating, die coating, and nozzle printing.

  The heat treatment step is not particularly limited as long as it is a step of heat-treating the first passivation layer forming coating solution or the second passivation layer forming coating solution applied to the article to be coated. You can choose. Note that when the heat treatment is performed, the first passivation layer forming coating solution or the second passivation layer forming coating solution applied to the article to be coated may be dried by natural drying or the like. By the heat treatment, drying of the solvent, generation of an oxide (the first oxide or the second oxide), and the like are performed.

  In the heat treatment step, solvent drying (hereinafter referred to as “drying process”) and generation of the first oxide or the second oxide (hereinafter referred to as “generation process”) are different. It is preferable to carry out at temperature. That is, it is preferable that after the solvent is dried, the first oxide or the second oxide is generated by raising the temperature. In the production of the second oxide, for example, decomposition of at least one of a silicon-containing compound, an alkaline earth metal-containing compound, an aluminum-containing compound, and a boron-containing compound occurs. In the production of the first oxide, for example, decomposition of at least one of an alkaline earth metal-containing compound (A-element-containing compound), a B-element-containing compound, and a C-element-containing compound occurs.

  There is no restriction | limiting in particular as temperature of a drying process, According to the solvent to contain, it can select suitably, For example, 80 to 180 degreeC is mentioned. In drying, it is effective to use a vacuum oven or the like for lowering the temperature. There is no restriction | limiting in particular as time of a drying process, According to the objective, it can select suitably, For example, 1 minute-1 hour are mentioned.

  There is no restriction | limiting in particular as temperature of a production | generation process, Although it can select suitably according to the objective, 100 degreeC or more and less than 550 degreeC are preferable, and 200 to 500 degreeC is more preferable. There is no restriction | limiting in particular as time of a production | generation process, According to the objective, it can select suitably, For example, 1 hour-5 hours are mentioned.

  In the heat treatment step, the drying process and the generation process may be performed continuously, or may be divided into a plurality of processes.

  There is no restriction | limiting in particular as the method of heat processing, According to the objective, it can select suitably, For example, the method etc. which heat a to-be-coated article are mentioned. There is no restriction | limiting in particular as atmosphere in heat processing, Although it can select suitably according to the objective, Oxygen atmosphere is preferable. By performing the heat treatment in an oxygen atmosphere, the decomposition product can be quickly discharged out of the system, and the generation of the first oxide or the second oxide can be promoted.

  In the heat treatment, it is effective to irradiate the material after the drying treatment with ultraviolet light having a wavelength of 400 nm or less in order to accelerate the reaction of the generation treatment. By irradiating ultraviolet light with a wavelength of 400 nm or less, chemical bonds such as organic substances contained in the substance after the drying treatment can be broken and the organic substances can be decomposed, so that the first oxide or the second oxide can be efficiently decomposed. The oxide can be formed. The ultraviolet light having a wavelength of 400 nm or less is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include ultraviolet light having a wavelength of 222 nm using an excimer lamp. It is also preferable to apply ozone in place of or in combination with ultraviolet light irradiation. By applying ozone to the substance after the drying treatment, generation of oxide is promoted.

  Next, in the step shown in FIG. 14B, a mask 300 is formed in a predetermined region on the second passivation layer 170b. The mask 300 is not particularly limited as long as it is a material that functions as a protective film in the etching process of the first passivation layer 170a and the second passivation layer 170b, and can be appropriately selected depending on the purpose. There is no restriction | limiting in particular as a material of the mask 300, According to the objective, it can select suitably, For example, a positive type photoresist and a negative photoresist are mentioned.

  Next, in the step shown in FIG. 15A, the second passivation layer 170b is etched to form a second passivation layer 17b having a predetermined shape. The second passivation layer 170b can be etched with the first solution. Etching methods include a dipping method in which the second passivation layer 170b is immersed in the first solution, a spray method in which the first solution is sprayed on the second passivation layer 170b, and a second passivation layer 170b. There is a spin method in which the first solution is dropped and the substrate including the second passivation layer 170b is rotated.

  The concentration of hydrochloric acid in the first solution is preferably 0.04 wt% to 40 wt%. The concentration of oxalic acid in the first solution is preferably 0.1 wt% to 10 wt%. The concentration of nitric acid in the first solution is preferably 0.1 wt% to 40 wt%. The concentration of phosphoric acid in the first solution is preferably 0.1 wt% to 85 wt%. The concentration of acetic acid in the first solution is preferably 1 wt% to 50 wt%. The concentration of sulfuric acid in the first solution is preferably 1 wt% to 20 wt%. The concentration of the hydrogen peroxide solution in the first solution is preferably 1 wt% to 10 wt%. The first solution is preferably hydrochloric acid, a mixed solution of phosphoric acid and nitric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.

  Next, in the step shown in FIG. 15B, the first passivation layer 170a is etched to form a first passivation layer 17a having a predetermined shape. The first passivation layer 170a may be etched with a solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium hydrogen fluoride, and organic alkali (hereinafter, may be referred to as the second solution). it can. As an etching method, a dipping method in which the first passivation layer 170a is immersed in the second solution, a spray method in which the second solution is sprayed on the first passivation layer 170a, or a method on the first passivation layer 170a. There is a spin method in which the second solution is dropped and the substrate including the first passivation layer 170a is rotated.

  In the ninth embodiment, after the second passivation layer is etched in the step shown in FIG. 15A, the first passivation layer is continuously etched in the step shown in FIG. 15B. . For this reason, it is not necessary to form a mask in each of the second passivation layer and the first passivation layer, the number of steps for patterning the passivation layer is simplified, the productivity is improved, and a passivation layer having a desired shape is formed. Can be formed.

  The concentration of hydrofluoric acid in the second solution is preferably 0.1 to 10 wt%. The concentration of ammonium fluoride in the second solution is preferably 5 to 25 wt%. The concentration of ammonium hydrogen fluoride in the second solution is preferably 1 to 25 wt%. The concentration of the organic alkali in the second solution is preferably 1 to 15 wt%. As the second solution, a solution of hydrofluoric acid, ammonium fluoride and ammonium hydrogen fluoride is preferable.

  Next, in the step shown in FIG. 15C, the mask 300 is removed. There is no restriction | limiting in particular as a removal method of the mask 300, According to the objective, it can select suitably. For example, when a photoresist is used for the mask 300, the mask 300 can be removed by dissolving the mask 300 with a solution such as a resist stripping solution. Further, as a method for removing the mask 300, it is preferable to select a method that does not damage the passivation layer. Through the above steps, a bottom-gate / bottom-contact field effect transistor 110 can be manufactured.

  As described above, the field effect transistor according to the ninth exemplary embodiment includes the first passivation layer containing the second oxide as the passivation layer and the second passivation containing the first oxide. It is arranged in contact with the passivation layer.

  In the field effect transistor manufacturing method according to the ninth embodiment, the first passivation layer is brought into contact with the second solution to perform wet etching, and the second passivation layer is formed into the first passivation layer. And wet etching by contacting with the solution.

  By using the above solution for each passivation layer, each passivation layer can be suitably wet etched. Since it is not necessary to use a conventional dry etching process, no highly dangerous gas is used, and there are no problems such as environmental impact and the price of the equipment used.

  In addition, since the passivation layer in which the second oxide and the first oxide are stacked has a high barrier property, the field effect transistor has high reliability (for example, the amount of variation in threshold voltage with respect to the BTS test is small). Small).

  That is, high-performance (low power consumption, high reliability) field-effect transistors are manufactured at low cost, high safety, and low environmental load by wet etching each passivation layer using the above solution. It becomes possible to do.

<Modification of Ninth Embodiment>
The modification of the ninth embodiment shows an example of a field effect transistor having a layer structure different from that of the ninth embodiment. Note that in the modification of the ninth embodiment, a description of the same components as those of the above-described embodiment may be omitted.

  FIG. 16 is a cross-sectional view illustrating a field effect transistor according to a modification of the ninth embodiment. Each field effect transistor shown in FIG. 16 is a typical example of the semiconductor device according to the present invention.

  A field effect transistor 110A shown in FIG. 16A is a bottom gate / top contact field effect transistor. In the field effect transistor 110 </ b> A, the gate electrode 12 is formed on the insulating substrate 11, and the gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, an active layer 16 is formed on the gate insulating layer 13, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 at a predetermined interval to be a channel region of the active layer 16. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second passivation layer 17b is further formed on the first passivation layer 17a. Is formed.

  A field effect transistor 110B shown in FIG. 16B is a top-gate / bottom-contact field effect transistor. In the field effect transistor 110 </ b> B, a source electrode 14 and a drain electrode 15 are formed on an insulating substrate 11, and an active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the gate electrode 12, and a second passivation layer 17b is further formed on the first passivation layer 17a.

  A field effect transistor 110C shown in FIG. 16C is a top gate / top contact field effect transistor. In the field effect transistor 110 </ b> C, an active layer 16 is formed on an insulating substrate 11, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 at a predetermined interval to become a channel region of the active layer 16. Is formed. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. Then, a first passivation layer 17a is formed on the gate insulating layer 13 so as to cover the gate electrode 12, and a second passivation layer 17b is further formed on the first passivation layer 17a.

  As described above, the layer structure of the field effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 13 and 16 can be appropriately selected depending on the purpose. Also in the field effect transistors 110A, 110B, and 110C shown in FIG. 16, the first passivation layer 17a and the second passivation layer 17b can be manufactured by the same manufacturing method as the field effect transistor 110. Therefore, the field effect transistors 110A, 110B, and 110C have the same effect as the field effect transistor 110.

  In contrast to FIG. 16A to FIG. 16C, the second passivation layer 17b may be arranged in the active layer 16 rather than the first passivation layer 17a. Further, the second passivation layer 17b may be disposed so as to cover the upper surface and the side surface of the first passivation layer 17a, or the first passivation layer so as to cover the upper surface and the side surface of the second passivation layer 17b. 17a may be arranged.

<Tenth embodiment>
In the tenth embodiment, an example of a field effect transistor including a gate insulating layer having a two-layer structure is shown. Note that in the tenth embodiment, a description of the same components as those of the above-described embodiments may be omitted.

[Structure of field effect transistor]
FIG. 17 is a cross-sectional view illustrating a field effect transistor according to the tenth embodiment. Referring to FIG. 17, a field effect transistor 110D includes a substrate 11, a gate electrode 12, a first gate insulating layer 13a, a second gate insulating layer 13b, a source electrode 14, and a drain electrode 15. A bottom-gate / bottom-contact field effect transistor having an active layer 16 and a first passivation layer 17a. Note that the field-effect transistor 110D is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 110D, the gate insulating layer has a two-layer structure of the first gate insulating layer 13a and the second gate insulating layer 13b, and the passivation layer is only the first passivation layer 17a. This is different from the field effect transistor 110 (see FIG. 13). However, the passivation layer may be only the second passivation layer 17 b or may have a two-layer structure of the first passivation layer 17 a and the second passivation layer 17 b as in the field effect transistor 110.

  The arrangement of the first gate insulating layer 13a and the second gate insulating layer 13b in the gate insulating layer is not particularly limited and can be appropriately selected according to the purpose. As shown in FIG. The gate insulating layer 13a may be disposed closer to the gate electrode 12 than the second gate insulating layer 13b, and conversely, the second gate insulating layer 13b is more gate electrode than the first gate insulating layer 13a. 12 may be arranged. Further, the second gate insulating layer 13b may be disposed so as to cover the upper surface and the side surface of the first gate insulating layer 13a, or the first gate insulating layer 13b may be covered with the first gate insulating layer 13b. The gate insulating layer 13a may be disposed.

  The first gate insulating layer 13a can be formed from the same material as the first passivation layer 17a, and the second gate insulating layer 13b can be formed from the same material as the second passivation layer 17b.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 17 will be described. 18 and 19 are diagrams illustrating the manufacturing process of the field effect transistor according to the tenth embodiment.

  First, in the step shown in FIG. 18A, the gate electrode 12 having a predetermined shape is formed on the substrate 11 in the same manner as the step shown in FIG.

  Next, in the step shown in FIG. 18B, a first gate insulating layer 130a (a layer that is etched to become the first gate insulating layer 13a) covering the gate electrode 12 is formed on the entire surface of the substrate 11. To do. Then, a second gate insulating layer 130b (a layer that is etched to become the second gate insulating layer 13b) is formed over the entire surface of the first gate insulating layer 130a.

  The first gate insulating layer 130a can be formed of a material similar to that of the first passivation layer 170a, and the second gate insulating layer 130b can be formed of a material similar to that of the second passivation layer 170b. Further, the method for forming the first gate insulating layer 130a is not particularly limited, and various methods exemplified as the method for forming the first passivation layer 170a can be appropriately selected depending on the purpose. Similarly, the formation method of the second gate insulating layer 130b is not particularly limited, and various methods exemplified as the formation method of the second passivation layer 170b can be appropriately selected depending on the purpose.

  Next, in the step shown in FIG. 18C, a mask 310 is formed in a predetermined region on the second gate insulating layer 130b in the same manner as the step shown in FIG. 14B. Next, in the step shown in FIG. 18D, as in the step shown in FIG. 15A, the second gate insulating layer 130b is etched to form the second gate insulating layer 13b having a predetermined shape. .

  Next, in the step shown in FIG. 19A, the first gate insulating layer 130a is etched to form the first gate insulating layer 13a having a predetermined shape in the same manner as the step shown in FIG. 15B. . Next, in the step shown in FIG. 19B, the mask 310 is removed in the same manner as the step shown in FIG.

  Next, in the step shown in FIG. 19C, the same steps as those in FIGS. 2D to 3C of the first embodiment are performed, so that a bottom gate / bottom contact type field effect is obtained. A type transistor 110D can be manufactured. However, the passivation layer may be only the first passivation layer 17 a, and may be only the second passivation layer 17 b if necessary. Similarly to the field effect transistor 110, the first passivation layer 17 a and the second passivation layer may be used. A two-layer structure of the layer 17b may be used.

  As described above, the field effect transistor according to the tenth embodiment includes a first gate insulating layer containing the second oxide containing Si and an alkaline earth metal as a gate insulating layer. A second gate insulating layer containing the first oxide containing an element A that is an alkaline earth metal and a B element that is at least one of Ga, Sc, Y, and a lanthanoid. Arranged in contact.

  In the method of manufacturing the field effect transistor according to the tenth embodiment, the first gate insulating layer is contacted with the second solution to perform wet etching, and the second gate insulating layer is And wet etching by contacting with the first solution.

  By using the above solution for each gate insulating layer, each gate insulating layer can be suitably wet-etched. Since it is not necessary to use a conventional dry etching process, no highly dangerous gas is used, and there are no problems such as environmental impact and the price of the equipment used.

In addition, since the relative permittivity of the first oxide is about 6 to 20, which is higher than that of the SiO ₂ film, the use of the first oxide for the gate insulating layer can reduce the field effect transistor. Voltage drive (low power consumption) is possible.

  That is, by performing wet etching on each gate insulating layer using the above solution, a high-performance (low power consumption, high reliability) field effect transistor can be realized at low cost, high safety, and low environmental load. It can be produced.

<Modification of the tenth embodiment>
The modification of the tenth embodiment shows an example of a field effect transistor having a layer structure different from that of the tenth embodiment. Note that in the modification of the tenth embodiment, a description of the same components as those of the already described embodiments may be omitted.

  FIG. 20 is a cross-sectional view illustrating a field effect transistor according to a variation of the tenth embodiment. Each field effect transistor shown in FIG. 20 is a typical example of a semiconductor device according to the present invention.

  A field effect transistor 110E shown in FIG. 20A is a bottom-gate / top-contact field effect transistor. In the field effect transistor 110E, a gate electrode 12 is formed on an insulating substrate 11, a first gate insulating layer 13a is formed so as to cover the gate electrode 12, and a first gate insulating layer 13a is further formed on the first gate insulating layer 13a. Two gate insulating layers 13b are formed.

  Further, an active layer 16 is formed on the second gate insulating layer 13 b, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 with a predetermined interval to be a channel region of the active layer 16. Yes. Then, a first passivation layer 17a is formed on the second gate insulating layer 13b so as to cover the source electrode 14, the drain electrode 15, and the active layer 16.

  A field effect transistor 110F illustrated in FIG. 20B is a top-gate / bottom-contact field effect transistor. In the field effect transistor 110F, the source electrode 14 and the drain electrode 15 are formed on the insulating substrate 11, and the active layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a first gate insulating layer 13a is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second gate insulating layer 13b is further formed on the first gate insulating layer 13a. A gate electrode 12 is formed on the second gate insulating layer 13b. Then, a first passivation layer 17a is formed on the second gate insulating layer 13b so as to cover the gate electrode 12.

  A field effect transistor 110G shown in FIG. 20C is a top gate / top contact field effect transistor. In the field effect transistor 110 </ b> G, an active layer 16 is formed on an insulating substrate 11, and a source electrode 14 and a drain electrode 15 are formed on the active layer 16 at a predetermined interval to become a channel region of the active layer 16. Is formed. Further, a first gate insulating layer 13a is formed so as to cover the source electrode 14, the drain electrode 15, and the active layer 16, and a second gate insulating layer 13b is further formed on the first gate insulating layer 13a. A gate electrode 12 is formed on the second gate insulating layer 13b. Then, a first passivation layer 17a is formed on the second gate insulating layer 13b so as to cover the gate electrode 12.

  As described above, the layer structure of the field effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 17 and 20 can be appropriately selected depending on the purpose. Also in the field effect transistors 110E, 110F, and 110G shown in FIG. 20, the first gate insulating layer 13a and the second gate insulating layer 13b can be manufactured by the same manufacturing method as the field effect transistor 110D. Therefore, the field effect transistors 110E, 110F, and 110G have the same effect as the field effect transistor 110D.

  Note that, contrary to FIGS. 20A to 20C, the second gate insulating layer 13b may be disposed in the active layer 16 rather than the first gate insulating layer 13a. Further, the second gate insulating layer 13b may be disposed so as to cover the upper surface and the side surface of the first gate insulating layer 13a, or the first gate insulating layer 13b may be covered with the first gate insulating layer 13b. The gate insulating layer 13a may be disposed. Further, the passivation layer may be only the second passivation layer 17 b or may have a two-layer structure of the first passivation layer 17 a and the second passivation layer 17 b as in the field effect transistor 110.

<Eleventh embodiment>
The eleventh embodiment shows an example of an organic electroluminescence (organic EL) display element. In the eleventh embodiment, the description of the same components as those of the already described embodiments may be omitted.

  21 and 22 are cross-sectional views illustrating the structure and manufacturing method of the organic EL display element according to the eleventh embodiment.

  An organic EL display element 150 shown in FIG. 21A is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a bottom contact / top gate field effect transistor.

  An organic EL display element 150A shown in FIG. 21B is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a top contact / top gate type field effect transistor.

  The organic EL display elements 150 and 150A include a substrate 321, a first gate electrode 322 and a second gate electrode 323, a gate insulating layer 351, a first source electrode 325 and a second source electrode 326, 1 drain electrode 327 and 2nd drain electrode 328, 1st active layer 329 and 2nd active layer 330, 1st passivation layer 41a and 2nd passivation layer 41b, interlayer insulation film 43, An organic EL layer 352 and a cathode 45 are included.

  The first drain electrode 327 and the second gate electrode 323 are connected through a through hole formed in the gate insulating layer 351. The second drain electrode 328 functions as an anode in the organic EL element 350.

  In the case of FIGS. 21A and 21B, a capacitor is formed between the second gate electrode 323 and the second drain electrode 328, but the location where the capacitor is formed is not limited. Therefore, a capacitor having a necessary capacity can be designed and formed at a necessary position.

  A substrate 321, a first gate electrode 322 and a second gate electrode 323, a gate insulating layer 351, a first source electrode 325 and a second source electrode 326, a first drain electrode 327 and a second drain electrode 328, For the first active layer 329, the second active layer 330, the first passivation layer 41a, and the second passivation layer 41b, the materials and processes described in the description of the field effect transistor according to the ninth embodiment Etc. can be formed.

  Note that the first passivation layer 41a and the second passivation layer 41b correspond to the first passivation layer 17a and the second passivation layer 17b of the field effect transistor 110 and the like. Similarly to the ninth embodiment, the arrangement of the first passivation layer 41a and the second passivation layer 41b in the passivation layer is not particularly limited and can be appropriately selected according to the purpose. . The second passivation layer 41b may be disposed so as to cover the upper surface and the side surface of the first passivation layer 41a, or the first passivation layer may be covered so as to cover the upper surface and the side surface of the second passivation layer 41b. 41a may be arranged.

  There is no restriction | limiting in particular as a material of the interlayer insulation film 43 (planarization film | membrane), According to the objective, it can select suitably, For example, an organic material, an inorganic material, an organic inorganic composite material etc. are mentioned.

  Examples of the organic material include polyimide, acrylic resin, fluorine resin, non-fluorine resin, olefin resin, silicone resin, and other photosensitive resins.

  Examples of the inorganic material include SOG (spin on glass) materials such as Aquamica manufactured by AZ Electronic Materials.

  As an organic inorganic composite material, the organic inorganic composite compound etc. which consist of a silane compound currently disclosed by the patent document (Unexamined-Japanese-Patent No. 2007-158146) are mentioned, for example.

  The interlayer insulating film 43 preferably has a barrier property against moisture, oxygen, and hydrogen in the atmosphere.

  There is no restriction | limiting in particular as a formation process of the interlayer insulation film 43, According to the objective, it can select suitably, For example, it is desired by spin coating, inkjet printing, slit coating, nozzle printing, gravure printing, dip coating methods, etc. A method of directly forming the film shape, and a method of patterning by a photolithography method if a photosensitive material is used.

  It is also effective to stabilize the characteristics of the field-effect transistor constituting the display element by performing a heat treatment as a post-process after the formation of the interlayer insulating film 43.

  There is no restriction | limiting in particular as a preparation method of the organic EL layer 352 and the cathode 45, According to the objective, it can select suitably, For example, vacuum film-forming methods, such as a vacuum evaporation method and a sputtering method, an inkjet, a nozzle coat, etc. Examples include a solution process.

  This makes it possible to manufacture so-called “bottom emission” organic EL display elements 150 and 150A that extract light emitted from the substrate 321 side. In this case, the substrate 321, the gate insulating layer 351, and the second drain electrode (anode) 38 are required to be transparent.

  An organic EL display element 150B shown in FIG. 22A is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a bottom contact / bottom gate type field effect transistor.

  An organic EL display element 150C shown in FIG. 22B is a display element in which an organic EL element 350 and a drive circuit 320 are combined, and includes a top contact / bottom gate type field effect transistor.

  Unlike the organic EL display elements 150 and 150A, the organic EL display elements 150B and 150C include a first passivation layer 42a and a second passivation layer 42b in addition to the first passivation layer 41a and the second passivation layer 41b. Have. About the 1st passivation layer 42a and the 2nd passivation layer 42b, it can form by the material, the process, etc. as described in the description of the field effect transistor which concerns on 9th Embodiment.

  Note that the first passivation layer 42 a and the second passivation layer 42 b correspond to the first passivation layer 17 a and the second passivation layer 17 b of the field effect transistor 110 and the like. Similarly to the ninth embodiment, the arrangement of the first passivation layer 42a and the second passivation layer 42b in the passivation layer is not particularly limited and can be appropriately selected according to the purpose. . The second passivation layer 42b may be disposed so as to cover the upper surface and the side surface of the first passivation layer 42a, or the first passivation layer may be covered so as to cover the upper surface and the side surface of the second passivation layer 42b. 42a may be arranged.

21 and 22, the configuration in which the organic EL element 350 is disposed beside the drive circuit 320 has been described. However, the organic EL element 350 may be disposed above the drive circuit 320. Also in this case, so-called “bottom emission” in which light emission is extracted from the substrate 321 side, and the drive circuit 320 is required to be transparent. The source electrode, the drain electrode, and the anode have conductive conductivity such as ITO, In ₂ O ₃ , SnO ₂ , ZnO, ZnO added with Ga, ZnO added with Al, SnO ₂ added with Sb, or the like. It is preferable to use a simple oxide.

<Twelfth embodiment>
In the twelfth embodiment, an example of an image display device and system using the field effect transistor according to the first embodiment is shown. Note that in the twelfth embodiment, a description of the same components as those of the above-described embodiments may be omitted.

  FIG. 23 shows a schematic configuration of a television apparatus 500 as a system according to the twelfth embodiment. Note that the connection lines in FIG. 23 represent typical signals and information flows, and do not represent the entire connection relationship of each block.

  A television apparatus 500 according to the twelfth embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541 A hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500 and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code readable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a preset channel broadcast from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 and separates audio information and video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and a signal including display information in response to an instruction from the operation device 532 or the IR light receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like. The operating device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main controller 501 of various information input by the user. The drive IF 541 is a bi-directional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk and a drive device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and notifies the main controller 501 of it. The communication control device 552 controls communication with the Internet. Various information can be acquired via the Internet.

  As shown in FIG. 24 as an example, the image display device 524 includes a display 700 and a display control device 780. As shown in FIG. 25 as an example, the display 700 includes a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

  Further, as shown in FIG. 26 as an example, the display 710 includes n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at equal intervals along the line. The display element 702 can be specified by the scan line and the data line.

  As shown in FIG. 27 as an example, each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

  As an example, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714, as shown in FIG.

The organic EL element 750 can be disposed beside a field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same substrate. However, it is not limited to this, For example, the organic EL element 750 may be arrange | positioned on a field effect transistor. In this case, since the gate electrode needs to be transparent, the gate electrode was added with ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, Ga added ZnO, Al. A transparent oxide having conductivity such as SnO ₂ to which ZnO or Sb is added is used.

In the organic EL element 750, Al is used for the cathode 712. Note that an Mg—Ag alloy, an Al—Li alloy, ITO, or the like may be used. ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, an Ag—Nd alloy, or the like may be used.

  The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. A cathode 712 is connected to the electron transport layer 742, and an anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  As shown in FIG. 27, the drive circuit 720 includes two field effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 810 is turned on, the organic EL element 750 is driven by the field effect transistor 820.

  As an example, the display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG.

  The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line driving circuit 784 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 782. The data line driving circuit 786 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 782.

  As is clear from the above description, in the television apparatus 500 according to the present embodiment, the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525 constitute an image data creation apparatus. ing.

  In the above description, the light control element is an organic EL element. However, the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element may be used.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 30, the current supply line in the display element 703 is not necessary.

  In this case, as shown in FIG. 31 as an example, the drive circuit 730 is composed of only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can do. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 31 denote counter electrodes (common electrodes) of the capacitor 760 and the liquid crystal element 770, respectively.

  In the above embodiment, the case where the system is a television apparatus has been described. However, the present invention is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 524 are connected may be used.

  In addition, an image display device 524 is provided as a display means in a portable information device such as a mobile phone, a portable music playback device, a portable video playback device, an electronic BOOK, a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 524 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

[Example 1]
In Example 1, the bottom gate / bottom contact type field effect transistor shown in FIG. 1 was fabricated.

(Formation of gate electrode)
First, the gate electrode 12 was formed on the substrate 11. Specifically, a Mo film as a conductive film was formed on a glass substrate 11 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 12 was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern was not formed was removed by RIE (Reactive Ion Etching). Thereafter, the gate electrode 12 was formed by removing the resist pattern.

(Formation of gate insulating layer)
Next, the gate insulating layer 13 was formed. First, a coating liquid for forming a gate insulating layer was prepared. Specifically, lanthanum toluene solution of ethyl 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL of cyclohexylbenzene and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, a coating solution for forming a gate insulating layer was dropped onto the substrate 11 and the gate electrode 12 and spin-coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the formed gate insulating layer 13 was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, a stripping solution (Tokyo Ohka stripping solution 104) The gate insulating layer 13 was formed by removing the resist pattern by immersing in the substrate for 2 minutes. In this step, part of the strontium lanthanum zirconium oxide was removed, so that part of the gate electrode 12 was exposed and a voltage could be applied to the gate electrode 12.

(Formation of source electrode and drain electrode)
Next, the source electrode 14 and the drain electrode 15 were formed. Specifically, a Mo film, which is a conductive film, is formed on the gate insulating layer 13 by DC sputtering so that the average film thickness is about 100 nm. Thereafter, a photoresist is applied on the Mo film and prebaked. A resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 to be formed was formed by exposure with an exposure apparatus and development. Further, the Mo film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the resist pattern was also removed to form a source electrode 14 and a drain electrode 15 made of a Mo film.

(Formation of active layer)
Next, the active layer 16 was formed. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the active layer 16 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the active layer 16 was formed by removing the resist pattern. As a result, the active layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

(Formation of passivation layer)
Next, a passivation layer 17 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 17 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 17 was formed by removing the resist pattern.

  Thus, a bottom gate / bottom contact field effect transistor was completed.

[Example 2]
In “(Formation of gate insulating layer)” in Example 1, a field effect transistor was fabricated in exactly the same manner as in Example 1 except that the strontium lanthanum zirconium oxide etchant was an aqueous solution having a oxalic acid concentration of 5%. Produced.

[Example 3]
A field effect transistor was fabricated in exactly the same manner as in Example 1, except that in the “(Formation of gate insulating layer)” of Example 1, the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a nitric acid concentration of 20%. did.

[Example 4]
A field effect transistor was fabricated in exactly the same manner as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was changed to an aqueous solution having a phosphoric acid concentration of 50% in “(Formation of gate insulating layer)” in Example 1. did.

[Example 5]
In “(Formation of gate insulating layer)” of Example 1, the electric field was applied in the same manner as in Example 1 except that the etching solution for strontium lanthanum zirconium oxide was 5% acetic acid and the immersion time in the etching solution was 6 minutes. An effect transistor was fabricated.

[Example 6]
A field effect transistor was fabricated in exactly the same manner as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was changed to 10% sulfuric acid in “(Formation of gate insulating layer)” in Example 1.

[Example 7]
In “(Formation of gate insulating layer)” of Example 1, the same method as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was a mixed aqueous solution of 20% nitric acid, 60% phosphoric acid, and 20% water. A field effect transistor was fabricated.

[Example 8]
In Example 1, “(Formation of gate insulating layer)”, except that the etching solution of strontium lanthanum zirconium oxide was a mixed aqueous solution of 5% nitric acid, 80% phosphoric acid, 10% acetic acid, and 5% water, A field effect transistor was fabricated in exactly the same manner.

[Example 9]
In the “(formation of gate insulating layer)” of Example 1, the field effect type was the same as in Example 1 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution having a hydrogen peroxide concentration of 5%. A transistor was manufactured.

[Example 10]
In Example 10, a top-gate self-aligned field effect transistor shown in FIG. 5 was produced.

(Formation of active layer)
First, the active layer 122 was formed on the substrate 121. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed on a glass substrate 121 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the active layer 122 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the active layer 122 was formed by removing the resist pattern.

(Formation of gate insulating layer and gate electrode)
Next, the gate insulating layer 123 was formed. The same gate insulating layer forming coating solution as in Example 1 was dropped onto the substrate 121 and the active layer 122 and spin coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was.

  Next, a Mo / Al / Mo laminated film as a conductive film was formed by DC sputtering so that the average film thickness was about 300 nm (50 nm / 200 nm / 50 nm). Thereafter, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 124 was formed by pre-baking, exposure with an exposure apparatus, and development. Next, by immersing in a mixed aqueous solution of 5% nitric acid, 80% phosphoric acid, 10% acetic acid and 5% water for 30 seconds, a Mo / Al / Mo laminated film in a region where no resist pattern is formed, and strontium lanthanum zirconium The oxide was removed. Thereafter, the resist pattern was also removed to form the gate insulating layer 123 and the gate electrode 124.

  Next, an interlayer insulating film 127 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the interlayer insulating film 127 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the interlayer insulating film 127 was formed by removing the resist pattern.

(Formation of source electrode and drain electrode)
Next, the source electrode 125 and the drain electrode 126 were formed. Specifically, a Mo / Al / Mo laminated film which is a conductive film is formed on the interlayer insulating film 127 by DC sputtering so that the average film thickness is about 300 nm (50 nm / 200 nm / 50 nm). Photoresist was applied, and a resist pattern similar to the pattern of the source electrode 125 and the drain electrode 126 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo / Al / Mo laminated film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the resist pattern was also removed to form a source electrode 125 and a drain electrode 126 made of a Mo / Al / Mo laminated film.

(Formation of passivation layer)
Next, a passivation layer 128 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 128 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 128 was formed by removing the resist pattern.

  Thus, a top gate self-aligned field effect transistor 120 was completed.

(Transistor characteristics evaluation)
The transistor characteristics were evaluated for the field effect transistors manufactured in Examples 1 to 10. The transistor characteristics are as follows: the voltage between the gate electrode 12 and the source electrode 14 (Vgs) and the current between the source electrode 14 and the drain electrode 15 (Ids) when the voltage between the source electrode 14 and the drain electrode 15 (Vds) = + 10 V. The relationship (Vgs-Ids) was measured.

  Further, the field effect mobility in the saturation region was calculated from the evaluation result of the transistor characteristics (Vgs−Ids). Further, the S value was calculated as an index of the sharpness of the rise of Ids with respect to the Vgs application. Further, the ratio (on / off ratio) of Ids between the on state (for example, Vgs = + 10 V) and the off state (for example, Vgs = −10 V) of the transistor was calculated. Further, the threshold voltage (Vth) was calculated as the voltage value of the rise of Ids with respect to the Vgs application.

As a result of transistor characteristics, high transistor mobility, high on / off ratio, low S value, and Vth near 0 V are expressed as excellent transistor characteristics. Specifically, the transistor characteristics are excellent in that the mobility is 3 cm ² / Vs or more, the on / off ratio is 1.0 × 10 ⁸ or more, the S value is 0.7 or less, and Vth is within ± 5 V. It expresses.

  At the same time, the capacitance of the gate insulating layer was measured to calculate the relative dielectric constant. When the relative dielectric constant of the gate insulating layer is higher than 6, it is expressed as low power consumption.

  Table 1 shows the evaluation results of the transistor characteristics of the field effect transistors manufactured in Examples 1 to 10. It can be seen that all the field effect transistors manufactured in Examples 1 to 10 exhibit excellent transistor characteristics. The relative dielectric constant of the gate insulating layer was about 13 in all of Examples 1 to 10, and it was a field effect transistor with low power consumption.

  As described above, it was found that a high-performance field effect transistor can be manufactured by a low-cost process in which the first oxide is used as a gate insulating layer and the first oxide is patterned by wet etching.

［実施例１１］
実施例１１では、図１に示すボトムゲート／ボトムコンタクト型の電界効果型トランジスタを作製した。

[Example 11]
In Example 11, the bottom gate / bottom contact type field effect transistor shown in FIG. 1 was produced.

(Formation of gate electrode)
First, the gate electrode 12 was formed on the glass substrate 11 by the same method as in Example 1.

(Formation of gate insulating layer)
Next, the gate insulating layer 13 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the gate insulating layer 13 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the gate insulating layer 13 was formed by removing the resist pattern.

(Formation of source electrode and drain electrode)
Next, the source electrode 14 and the drain electrode 15 were formed by the same method as in Example 1.

(Formation of active layer)
Next, the active layer 16 was formed by the same method as in Example 1.

(Formation of passivation layer)
Next, a passivation layer 17 was formed. First, a passivation layer forming coating solution was prepared. Specifically, lanthanum toluene solution of ethyl 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL of cyclohexylbenzene and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a passivation layer forming coating solution.

Next, the passivation layer forming coating solution was dropped onto the substrate 11, the gate electrode 12, the gate insulating layer 13, the source electrode 14, the drain electrode 15 and the active layer 16, and spin coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the passivation layer 17 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. A passivation layer 17 was formed by removing the resist pattern by dipping for 2 minutes. By removing a part of the strontium lanthanum zirconium oxide in this step, a part of the gate electrode 12, the source electrode 14, and the drain electrode 15 are exposed, and a voltage can be applied to each electrode.

[Example 12]
A field effect transistor was produced in the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was changed to an aqueous solution having a concentration of oxalic acid of 5% in “(Formation of passivation layer)”. .

[Example 13]
A field effect transistor was fabricated in exactly the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was changed to an aqueous solution having a nitric acid concentration of 20% in “(Formation of Passivation Layer)”.

[Example 14]
A field effect transistor was fabricated in exactly the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was changed to an aqueous solution having a phosphoric acid concentration of 50% in “(Formation of Passivation Layer)”.

[Example 15]
In Example 11 “(Formation of Passivation Layer)”, a field effect type was produced in the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was 5% acetic acid and the immersion time in the etching solution was 6 minutes. A transistor was manufactured.

[Example 16]
A field effect transistor was fabricated in exactly the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was changed to 10% sulfuric acid in “(Formation of Passivation Layer)” in Example 11.

[Example 17]
In Example 11 “(Formation of Passivation Layer)”, the field effect was obtained in exactly the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was a mixed aqueous solution of 20% nitric acid, 60% phosphoric acid and 20% water. Type transistor was fabricated.

[Example 18]
Exactly the same as Example 11 except that the etching solution of strontium lanthanum zirconium oxide was a mixed aqueous solution of 5% nitric acid, 80% phosphoric acid, 10% acetic acid and 5% water in Example 11 “(Formation of Passivation Layer)”. A field effect transistor was fabricated by this method.

[Example 19]
In Example 11 “(Formation of Passivation Layer)”, a field effect transistor was fabricated in exactly the same manner as in Example 11 except that the etching solution of strontium lanthanum zirconium oxide was an aqueous solution containing 5% hydrogen peroxide. Produced.

(Transistor characteristics evaluation)
For the field effect transistors manufactured in Examples 11 to 19, the mobility, on / off ratio, S value, and threshold voltage (Vth) were calculated in the same manner as in Examples 1 to 10. In addition, a BTS (Bias Temperature Stress) test was performed for 100 hours in the atmosphere (temperature: 50 ° C., relative humidity: 50%) for the field effect transistors manufactured in Examples 11 to 19.

The stress conditions were the following four conditions.
(1) Vgs = + 10V and Vds = 0V
(2) Vgs = + 10V and Vds = + 10V
(3) Vgs = −10V and Vds = 0V
(4) Vgs = −10V and Vds = + 10V
Every time the BTS test passed, the relationship between Vgs and Ids (Vgs−Ids) when Vds = + 10 V was measured, and the amount of change in threshold voltage (ΔVth) at a stress time of 100 hours was evaluated. When the amount of change in threshold voltage (ΔVth) during stress time of 100 hours is 3 V or less, it is expressed as high reliability.

  Table 2 shows the evaluation results of the transistor characteristics of the field effect transistors manufactured in Examples 11 to 19. It can be seen that all of the field effect transistors manufactured in Examples 11 to 19 have excellent transistor characteristics. In addition, it can be seen that the change amount of the threshold voltage (ΔVth) is 1 V or less in any result, indicating high reliability.

  As described above, it has been found that a high-performance field effect transistor can be manufactured by a low-cost process using the first oxide as a passivation layer and patterning the first oxide by wet etching.

［実施例２０］
実施例２０では、図６に示す有機ＥＬ表示素子２００を作製した。まず、基板２１上に第１のゲート電極２２及び第２のゲート電極３２を形成した。具体的には、無アルカリガラスよりなる基板２１上に、ＤＣスパッタ法によりＭｏ膜を厚さが約１００ｎｍとなるよう成膜した。この後、フォトレジストを塗布し、プリベーク、露光装置による露光、現像により、形成されるパターンと同様のレジストパターンを形成した。更に、ＲＩＥにより、レジストパターンの形成されていない領域のＭｏ膜を除去し、この後、レジストパターンも除去することにより、第１のゲート電極２２及び第２のゲート電極３２を形成した。

[Example 20]
In Example 20, the organic EL display element 200 shown in FIG. 6 was produced. First, the first gate electrode 22 and the second gate electrode 32 were formed on the substrate 21. Specifically, a Mo film was formed on the substrate 21 made of alkali-free glass by DC sputtering so as to have a thickness of about 100 nm. Thereafter, a photoresist was applied, and a resist pattern similar to the pattern to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed, thereby forming the first gate electrode 22 and the second gate electrode 32.

  Next, the gate insulating layer 23 was formed over the substrate 21, the first gate electrode 22, and the second gate electrode 32. First, 1 L of a gate insulating layer forming coating solution having the same composition as in Example 1 was prepared.

Next, a coating liquid for forming a gate insulating layer was applied onto the substrate 21, the first gate electrode 22, and the second gate electrode 32 by a slit coating method. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was.

  Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the gate insulating layer 23 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. The gate insulating layer 23 having a through hole was formed on the second gate electrode 32 by removing the resist pattern by dipping for 2 minutes.

  Next, a first source electrode 24, a second source electrode 34, a first drain electrode 25, and a second drain electrode 35 were formed. Specifically, an ITO film, which is a transparent conductive film, was formed on the gate insulating layer 23 by DC sputtering so as to have a thickness of about 100 nm. Thereafter, a photoresist was applied on the ITO film, and a resist pattern similar to the pattern to be formed was formed by pre-baking, exposure by an exposure apparatus, and development.

  Further, by removing the ITO film in the region where the resist pattern is not formed by RIE, and then removing the resist pattern, the first source electrode 24, the second source electrode 34, the second source electrode made of the ITO film are removed. One drain electrode 25 and a second drain electrode 35 were formed. As a result, the first drain electrode 25 and the second gate electrode 32 are connected through a through hole formed in the gate insulating layer 23.

  Next, the first active layer 26 and the second active layer 36 were formed. Specifically, an Mg—In based oxide film is formed to a thickness of about 100 nm by DC sputtering, and then a photoresist is applied on the Mg—In based oxide film, A resist pattern similar to the pattern to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the RIE removes the Mg—In-based oxide film in the region where the resist pattern is not formed, and then removes the resist pattern, whereby the first active layer 26 and the second active layer 36 are formed. Formed.

  As a result, the first active layer 26 is formed between the second source electrode 34 and the second drain electrode 35 so that a channel is formed between the first source electrode 24 and the first drain electrode 25. The second active layer 36 was formed so that a channel was formed therebetween.

  Next, a first passivation layer 27 and a second passivation layer 37 were formed. First, a passivation layer forming coating solution was prepared. Specifically, lanthanum toluene solution of ethyl 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL of cyclohexylbenzene and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a passivation layer forming coating solution.

Next, the passivation layer forming coating solution is applied to the substrate 21, the first gate electrode 22, the second gate electrode 32, the gate insulating layer 23, the first source electrode 24, the first drain electrode 25, and the second The solution was dropped onto the source electrode 34, the second drain electrode 35, the first active layer 26, and the second active layer 36, and spin-coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) is applied, and a resist pattern similar to the pattern of the first passivation layer 27 and the second passivation layer 37 formed by pre-baking, exposure with an exposure apparatus, and development is applied. Formed.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. The first passivation layer 27 and the second passivation layer 37 were formed by immersing for 2 minutes to remove the resist pattern. Through the above steps, a driver circuit 210 having a two-transistor one-capacitor structure was manufactured.

  Next, an interlayer insulating film 220 (flattening film) was formed over the drive circuit 210. Specifically, a positive type photosensitive organic material (Sumiresin Excel CRC series, manufactured by Sumitomo Bakelite Co., Ltd.) was applied by spin coating, and a desired pattern was obtained by pre-baking, exposure with an exposure apparatus, and development. Thereafter, post-baking at 320 ° C. for 30 minutes was performed to form an interlayer insulating film 220 having a through hole 220 x on the second drain electrode 35. The average film thickness of the interlayer insulating film 220 thus formed was about 3 μm.

  Next, a lower electrode 231 to be a pixel electrode was formed. Specifically, an Ag—Pd—Cu thin film and an ITO thin film were sequentially formed by DC sputtering so that the average film thickness was 100 nm. Then, a photoresist was apply | coated on the Ag-Pd-Cu thin film and the ITO thin film, and the desired pattern was obtained by prebaking, exposure by an exposure apparatus, and image development. Further, the ITO thin film and the Ag—Pd—Cu thin film in the region where the resist pattern was not formed were sequentially removed by RIE. Thereafter, the lower electrode 231 was formed by removing the resist pattern.

  Next, the partition wall 240 was formed. Specifically, a positive photosensitive polyimide resin (DL-1000, manufactured by Toray Industries, Inc.) was applied by spin coating, and a desired pattern was obtained by prebaking, exposure using an exposure apparatus, and development. Then, the partition wall 240 was formed by post-baking at 230 ° C. for 30 minutes.

  Next, an organic EL layer 232 was formed on the lower electrode 231 by an inkjet apparatus using a polymer organic light emitting material.

  Next, the upper electrode 233 was formed. Specifically, the upper electrode 233 was formed on the organic EL layer 232 and the partition 240 by vacuum-depositing MgAg.

  Next, the sealing layer 250 was formed. Specifically, the sealing layer 250 was formed on the upper electrode 233 by forming a SiN film by plasma CVD so that the average film thickness was about 2 μm.

  Next, bonding with the opposing insulating substrate 270 was performed. Specifically, an adhesive layer 260 was formed on the sealing layer 250, and a counter insulating substrate 270 made of an alkali-free glass substrate was bonded thereto.

  The organic EL display element 200 manufactured by these steps exhibited low power consumption and high reliability.

  As described above, it was found that a high-performance organic EL display element can be manufactured by a low-cost process using the first oxide as a gate insulating layer and a passivation layer and patterning the first oxide by wet etching. .

[Example 21]
In Example 21, the organic EL display element 200A shown in FIG. 7 was produced. Specifically, the organic layer is formed in the same manner as in Example 21 except that the first passivation layer 27 and the second passivation layer 37 (FIG. 6) in Example 21 are changed to an integrated passivation layer 27A. An EL display element 200A was produced.

  The manufactured organic EL display element 200A exhibited low power consumption and highly reliable characteristics.

  As described above, it was found that a high-performance organic EL display element can be manufactured by a low-cost process using the first oxide as a gate insulating layer and a passivation layer and patterning the first oxide by wet etching. .

[Example 22]
In Example 22, the field effect transistor 50 (MOS-FET) shown in FIG. 8 was produced. First, a coating liquid for forming a gate insulating layer for forming the gate insulating layer 53 on a substrate 51 (8 inches) made of p-type Si was prepared. Specifically, to 4.0 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, a gate insulating layer forming coating solution was dropped onto the substrate 51 and spin-coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (film thickness: 10 nm) that is a paraelectric and amorphous. It was.

  Further, after forming a polycrystalline silicon film by the CVD method, the polycrystalline silicon film was patterned by a photolithography process, and the gate electrode 52 was obtained. Then, using the gate electrode 52 as a mask, it is immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds, and the strontium lanthanum zirconium oxide in the region where the gate electrode 52 is not formed is etched, whereby the gate insulating layer 53 was formed.

  Next, after depositing SiON by the CVD method, the entire surface was dry etched to form a gate sidewall insulating film 54. Next, phosphorus ions were implanted into the substrate 51 using the gate electrode 52 and the gate sidewall insulating film 54 as a self-alignment mask, and a source region 55 and a drain region 56 were formed by ion diffusion.

Next, SiO ₂ was deposited by a CVD method, and an interlayer insulating film 57 having through holes opened by a photolithography process was formed. Finally, an Al layer was deposited by sputtering, a through hole was filled, and patterning was performed by a photolithography process, so that a source electrode 58 and a drain electrode 59 were formed.

  Finally, a passivation layer 111 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 111 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 111 was formed by removing the resist pattern. Through the above steps, a field effect transistor 50 was manufactured.

  The field effect transistor 50 produced in this example showed excellent transistor characteristics. The relative dielectric constant of the gate insulating layer 53 was 13.3, and it was a field effect transistor with low power consumption.

  As described above, it was found that a high-performance field effect transistor can be manufactured by a low-cost process in which the first oxide is used as a gate insulating layer and the first oxide is patterned by wet etching.

[Example 23]
In Example 23, the volatile semiconductor memory element 60 shown in FIG. 9 was produced. First, the gate electrode 62 and the second capacitor electrode 69 were formed on the substrate 61 made of alkali-free glass. Specifically, a Mo film was formed on the substrate 61 so as to have a thickness of about 100 nm by DC sputtering. Thereafter, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 62 and the second capacitor electrode 69 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed, thereby forming the gate electrode 62 and the second capacitor electrode 69.

  Next, the gate insulating layer 63 was formed. First, a coating liquid for forming a gate insulating layer was prepared. Specifically, lanthanum toluene solution of ethyl 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL of cyclohexylbenzene and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, a coating solution for forming a gate insulating layer was dropped onto the substrate 61, the gate electrode 62, and the second capacitor electrode 69, and spin-coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the gate insulating layer 63 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. The gate insulating layer 63 was formed by immersing for 2 minutes to remove the resist pattern.

Next, a capacitor dielectric layer 68 was formed. The above-described coating liquid for forming a gate insulating layer was dropped onto the substrate 61, the gate electrode 62, the second capacitor electrode 69, and the gate insulating layer 63, and spin-coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (film thickness 30 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the capacitor dielectric layer 68 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. The capacitor dielectric layer 68 was formed by immersing for 2 minutes to remove the resist pattern.

  Next, the source electrode 64 and the drain electrode 65 were formed. In this embodiment, the drain electrode 65 forms a capacitor together with the capacitor dielectric layer 68 and the second capacitor electrode 69.

  Specifically, an ITO film, which is a transparent conductive film, was formed on the gate insulating layer 63 and the capacitor dielectric layer 68 by DC sputtering so as to have a thickness of about 100 nm. Thereafter, a photoresist was applied on the ITO film, and a resist pattern similar to the pattern of the source electrode 64 and the drain electrode 65 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Further, the ITO film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed, thereby forming the source electrode 64 and the drain electrode 65 made of the ITO film.

  Next, the active layer 66 was formed. Specifically, an Mg—In-based oxide film was formed to have a thickness of about 100 nm by DC sputtering. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the active layer 66 to be formed was formed by pre-baking, exposure using an exposure apparatus, and development. Furthermore, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by RIE, and then the resist pattern was also removed, thereby forming the active layer 66. Thereby, the active layer 66 was formed so that a channel was formed between the source electrode 64 and the drain electrode 65.

  Finally, a passivation layer 112 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 112 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 112 was formed by removing the resist pattern. Through these steps, the volatile semiconductor memory element 60 was produced.

  The volatile semiconductor memory device 60 manufactured by these steps exhibited low power consumption characteristics.

  As described above, a high-performance volatile semiconductor memory device can be manufactured by a low-cost process using the first oxide as a gate insulating layer and a capacitor dielectric layer and patterning the first oxide by wet etching. all right.

[Example 24]
In Example 24, the volatile semiconductor memory element 70 shown in FIG. 10 was produced. First, a coating solution for forming a gate insulating layer for forming the gate insulating layer 73 was prepared on a substrate 71 (8 inches) made of p-type Si. Specifically, to 4.0 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, a gate insulating layer forming coating solution was dropped onto the substrate 71 and spin coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (film thickness: 10 nm) that is a paraelectric and amorphous. It was.

  Next, after a polycrystalline silicon film was formed by a CVD method, the polycrystalline silicon film was patterned by a photolithography process, and a gate electrode 72 was obtained. Then, using the gate electrode 72 as a mask, the substrate is immersed in 0.1 mol / L hydrochloric acid (wako 083-0111) for 5 seconds, and the strontium lanthanum zirconium oxide in the region where the gate electrode 72 is not formed is etched. 73 was formed.

  Next, after depositing SiON by the CVD method, the gate sidewall insulating film 74 was formed by dry etching the entire surface. Next, using the gate electrode 72 and the gate sidewall insulating film 74 as a self-alignment mask, phosphorus ions were implanted into the substrate 71 and ion diffusion was performed, thereby forming a source region 75 and a drain region 76.

Next, SiO ₂ was deposited by a CVD method, and a first interlayer insulating film 77 having through holes opened by a photolithography process was formed. A polycrystalline silicon film was deposited by a CVD method, a through hole was buried, and a bit line electrode 78 was formed by a photolithography process.

Next, SiO ₂ was deposited by a CVD method, and a second interlayer insulating film 79 having a through hole opened on the drain region 76 was formed by a photolithography process. Next, a polycrystalline silicon film was formed by a CVD method, and a second capacitor electrode 80 was formed by a photolithography process.

Next, a capacitor dielectric layer 81 was formed. A coating liquid for forming a gate insulating layer was dropped onto the second interlayer insulating film 79 and the second capacitor electrode 80 and spin-coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (film thickness 30 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the capacitor dielectric layer 81 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. The capacitor dielectric layer 81 was formed by removing the resist pattern by dipping for 2 minutes.

  Next, a polycrystalline silicon film was formed by a CVD method, and a first capacitor electrode 82 was formed by a photolithography process. Finally, a passivation layer 113 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 113 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 113 was formed by removing the resist pattern. Through these steps, the volatile semiconductor memory element 70 was produced.

  The volatile semiconductor memory device 70 manufactured by these processes exhibited low power consumption characteristics.

  As described above, a high-performance volatile semiconductor memory device can be manufactured by a low-cost process using the first oxide as a gate insulating layer and a capacitor dielectric layer and patterning the first oxide by wet etching. all right.

[Example 25]
In Example 25, the nonvolatile semiconductor memory element 90 shown in FIG. 11 was produced. First, the gate electrode 92 was formed on the substrate 91 made of alkali-free glass. Specifically, a Mo film was formed on the substrate 91 by DC sputtering so as to have a thickness of about 30 nm. Thereafter, a photoresist was applied, and a resist pattern similar to the pattern of the gate electrode 92 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the gate electrode 92 was formed by removing the resist pattern.

  Next, a first gate insulating layer 93 was formed. First, a coating liquid for forming a gate insulating layer was prepared. Specifically, lanthanum toluene solution of ethyl 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.95 mL of cyclohexylbenzene and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, a gate insulating layer forming coating solution was dropped onto the substrate 91 and the gate electrode 92, and spin coating was performed under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (thickness: 135 nm) that is a paraelectric and amorphous. It was. Thereafter, a photoresist (Tokyo Ohka TSMR8800-BE) was applied, and a resist pattern similar to the pattern of the first gate insulating layer 93 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development.

  Next, after immersing in 0.1 mol / L hydrochloric acid (wako 083-01115) for 30 seconds to etch the strontium lanthanum zirconium oxide in the region where the resist pattern is not formed, the stripping solution (Tokyo Ohka stripping solution 104) is used. A first gate insulating layer 93 was formed by removing the resist pattern by dipping for 2 minutes.

  Next, a floating gate electrode 94 was formed. Specifically, a Mo film was formed on the first gate insulating layer 93 by DC sputtering so as to have a thickness of about 15 nm. Thereafter, a photoresist was applied, and a resist pattern similar to the pattern of the floating gate electrode 94 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Furthermore, the Mo film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed, thereby forming the floating gate electrode 94.

Next, a second gate insulating layer 95 was formed. Specifically, a SiO ₂ film having a thickness of 50 nm was formed on the first gate insulating layer 93 and the floating gate electrode 94 by a CVD method. Thereafter, a photoresist was applied, and a resist pattern similar to the pattern of the second gate insulating layer 95 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the second gate insulating layer 95 was formed by removing the SiO ₂ film in the region where the resist pattern was not formed by RIE, and thereafter removing the resist pattern.

  Next, the source electrode 96 and the drain electrode 97 were formed. Specifically, an ITO film, which is a transparent conductive film, was formed on the second gate insulating layer 95 by DC sputtering so as to have a thickness of about 100 nm. Thereafter, a photoresist was applied on the ITO film, and a resist pattern similar to the pattern of the source electrode 96 and the drain electrode 97 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Further, the ITO film in the region where the resist pattern is not formed is removed by RIE, and then the resist pattern is also removed, thereby forming the source electrode 96 and the drain electrode 97 made of the ITO film.

  Next, an active layer 98 was formed. Specifically, an Mg—In-based oxide film was formed to have a thickness of about 100 nm by DC sputtering. Thereafter, a photoresist was applied onto the Mg—In-based oxide film, and a resist pattern similar to the pattern of the active layer 98 to be formed was formed by pre-baking, exposure using an exposure apparatus, and development. Furthermore, the active layer 98 was formed by removing the Mg—In-based oxide film in the region where the resist pattern was not formed by RIE, and then removing the resist pattern.

  Thus, the active layer 98 was formed so that a channel was formed between the source electrode 96 and the drain electrode 97.

  Finally, a passivation layer 114 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 114 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 114 was formed by removing the resist pattern. The nonvolatile semiconductor memory element 90 was manufactured through the above steps.

  The nonvolatile semiconductor memory element 90 manufactured by these processes exhibited low power consumption characteristics.

  As described above, it is found that a high-performance nonvolatile semiconductor memory element can be manufactured by a low-cost process in which the first oxide is used as the first gate insulating layer and the first oxide is patterned by wet etching. It was.

[Example 26]
In Example 26, the nonvolatile semiconductor memory element 100 shown in FIG. 12 was produced. First, a surface of the substrate 101 made of p-type Si is thermally oxidized to form a 5 nm thick SiO ₂ film that will eventually become the second gate insulating layer 104, and then the floating gate electrode is finally formed by a CVD method. A polycrystalline silicon film 105 was formed.

  Next, a gate insulating layer forming coating solution for forming the first gate insulating layer 102 was prepared. Specifically, to 4.0 mL of cyclohexylbenzene, 1.95 mL of a lanthanum toluene solution of 2-ethylhexanoate (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and a strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL, 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0 0.09 mL was mixed to obtain a coating solution for forming a gate insulating layer.

Next, a gate insulating layer forming coating solution was dropped onto the substrate 101 and spin coated under predetermined conditions. Subsequently, after drying at 120 ° C. for 1 hour in the air, firing was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to obtain strontium lanthanum zirconium oxide (film thickness: 10 nm) that is a paraelectric and amorphous. It was.

Next, after a polycrystalline silicon film was formed by a CVD method, the polycrystalline silicon film was patterned by a photolithography process to obtain a gate electrode 103. Then, using the gate electrode 103 as a mask, the substrate is immersed in 0.1 mol / L hydrochloric acid (wako 083-01115) for 5 seconds, and the strontium lanthanum zirconium oxide in the region where the gate electrode 103 is not formed is etched. A gate insulating layer 102 was formed. Furthermore, the floating gate electrode 105 and the second gate insulating layer 104 (tunnel insulating layer) were formed by sequentially etching the polycrystalline silicon film and the SiO ₂ film below the first gate insulating layer 102 by dry etching. .

  Next, after depositing SiON by a CVD method, the entire surface was dry etched to form a gate sidewall insulating film 106. Next, using the gate electrode 103 and the gate sidewall insulating film 106 as a self-alignment mask, phosphorus ions were implanted into the substrate 101 and ion diffusion was performed, whereby a source region 107 and a drain region 108 were formed.

  Finally, a passivation layer 115 was formed. Specifically, the SiON film was formed by plasma CVD so that the average film thickness was 300 nm. Thereafter, a photoresist was applied on the SiON film, and a resist pattern similar to the pattern of the passivation layer 115 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Furthermore, the SiON film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the passivation layer 115 was formed by removing the resist pattern. The nonvolatile semiconductor memory element 100 was manufactured through the above steps.

  The non-volatile semiconductor memory device 100 manufactured through these steps exhibited low power consumption characteristics.

  As described above, it is found that a high-performance nonvolatile semiconductor memory element can be manufactured by a low-cost process in which the first oxide is used as the first gate insulating layer and the first oxide is patterned by wet etching. It was.

[Example 27]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
To 1 mL of toluene, 0.14 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content) 3% -8%, Alfa 36657, manufactured by Alfa Aesar) 0.37 mL was mixed to obtain a first passivation layer forming coating solution. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 3.

-Preparation of second passivation layer forming coating solution-
To 1.2 mL of cyclohexylbenzene, 2.17 mL of 2-ethylhexanoic acid lanthanum toluene solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and 2-ethylhexanoic acid strontium toluene solution (Sr content 2%) , Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) (0.63 mL) was mixed to obtain a second passivation layer-forming coating solution. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 3.

次に、図１６（ｂ）のような、ボトムコンタクト／トップゲート型の電界効果型トランジスタを作製した。

Next, a bottom contact / top gate type field effect transistor as shown in FIG.

-Formation of source and drain electrodes-
First, the source electrode 14 and the drain electrode 15 were formed on the substrate 11 made of glass. Specifically, an Al (aluminum) alloy film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Al alloy film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Further, the Al alloy film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a source electrode 14 and a drain electrode 15 made of an Al alloy film.

-Formation of active layer-
Next, the active layer 16 was formed. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the active layer 16 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by etching. Thereafter, the active layer 16 was formed by removing the resist pattern. As a result, the active layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

-Formation of gate insulation layer-
Next, the gate insulating layer 13 was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16. Specifically, an Al ₂ O ₃ film was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16 by RF sputtering so that the average film thickness was about 300 nm.

-Formation of gate electrode-
Next, the gate electrode 12 was formed on the gate insulating layer 13. Specifically, a Mo (molybdenum) film was formed on the gate insulating layer 13 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mo film, and a resist pattern similar to the pattern of the gate electrode 12 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a gate electrode 12 made of a Mo film.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds, 0 rpm for 5 seconds) The rotation was stopped so that Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer-forming coating solution was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, rotating at 3,000 rpm for 20 seconds, the rotation was stopped to reach 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), pre-baked, exposed by an exposure apparatus, and developed. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in 0.36 wt% hydrochloric acid (Wako 083-01115) for 20 seconds, and the first oxide film in a region where the resist pattern is not formed is removed by etching. Then, the second passivation layer 17b was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in 2.5 wt% hydrofluoric acid for 15 seconds, and the second oxide film in a region where no resist pattern is formed is removed by etching. 1 passivation layer 17a was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 28]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
To 1 mL of toluene, 0.13 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and magnesium 2-ethylhexanoate toluene solution (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) 0.32 mL and 2-ethylhexanoic acid barium toluene solution (Ba content 8%, Wako 021-09471, manufactured by Wako Chemical Co., Ltd.) 0.40 mL were mixed to form a first passivation. A layer forming coating solution was obtained. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 3.

-Preparation of second passivation layer forming coating solution-
Scandium (III) tris (2,2,6,6-tetramethyl-3,5-hebutanedionate) hydrate (SIGMA-ALDRICH 517607, manufactured by SIGMA-ALDRICH) 0.54 g in 1.2 mL of cyclohexylbenzene And 2-ethylhexanoic acid magnesium toluene solution (Mg content 3%, Strem 12-1260, made by Strem Chemicals) 0.12 mL, 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (Ca content 3% -8%) , Alfa36657, manufactured by Alfa Aesar) and 0.08 mL were mixed to obtain a second passivation layer forming coating solution. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 3.

  Next, similarly to Example 27, a bottom contact / top gate type field effect transistor was fabricated. However, the stacking order of the first passivation layer 17a and the second passivation layer 17b was reversed from that in Example 27.

-Formation of source and drain electrodes-
First, the source electrode 14 and the drain electrode 15 were formed on the substrate 11 made of glass. Specifically, an Al (aluminum) alloy film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Al alloy film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 to be formed was formed by pre-baking, exposure by an exposure apparatus, and development. Further, the Al alloy film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a source electrode 14 and a drain electrode 15 made of an Al alloy film.

-Formation of active layer-
Next, the active layer 16 was formed. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the active layer 16 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by etching. Thereafter, the active layer 16 was formed by removing the resist pattern. As a result, the active layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

-Formation of gate insulation layer-
Next, the gate insulating layer 13 was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16. Specifically, an Al ₂ O ₃ film was formed on the substrate 11, the source electrode 14, the drain electrode 15, and the active layer 16 by RF sputtering so that the average film thickness was about 300 nm.

-Formation of gate electrode-
Next, the gate electrode 12 was formed on the gate insulating layer 13. Specifically, a Mo (molybdenum) film was formed on the gate insulating layer 13 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mo film, and a resist pattern similar to the pattern of the gate electrode 12 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a gate electrode 12 made of a Mo film.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (after rotating at 500 rpm for 5 seconds, at 3,000 rpm). The rotation was stopped for 20 seconds and 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer-forming coating solution was dropped onto the second passivation layer 170b and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm for 5 seconds). So that the rotation stopped. Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

  Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the first passivation layer 170a (the first oxide film), and is formed by pre-baking, exposure using an exposure apparatus, and development. A resist pattern similar to the pattern of the first passivation layer 17a was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in a mixed solution of 19 wt% ammonium fluoride and 18 wt% ammonium hydrogen fluoride for 15 seconds, and the second region in the region where the resist pattern is not formed is etched. The oxide film was removed to form a first passivation layer 17a.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in 5 wt% oxalic acid heated to 30 ° C. for 4 minutes, and the first oxide film in a region where no resist pattern is formed is removed by etching. Two passivation layers 17b were formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 29]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.), aluminum di (s-butoxide) acetoacetate chelate (Al content 8) .4%, Alfa 89349, manufactured by Alfa Aesar) and 0.12 mL of strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 2.02 mL, A passivation layer-forming coating solution was obtained. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 3.

-Preparation of second passivation layer forming coating solution-
1.2 mL of cyclohexylbenzene, 0.19 g of samarium acetylacetonate trihydrate (Strem 93-6226, manufactured by Strem Chemicals), gadolinium 2-ethylhexanoate toluene solution (Gd content 25%, Strem 64-3500, Strem (Chemicals) 0.27mL and 2-ethylhexanoic acid barium toluene solution (Ba content 8%, Wako 021-09471, manufactured by Wako Chemical Co., Ltd.) 0.49mL are mixed to form a second passivation layer forming coating solution. Got. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 3.

  Next, a bottom contact / top gate type field effect transistor as shown in FIG. The source electrode 14, drain electrode 15, active layer 16, gate insulating layer 13, and gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds, 0 rpm for 5 seconds) The rotation was stopped so that Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer-forming coating solution was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, rotating at 3,000 rpm for 20 seconds, the rotation was stopped to reach 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), pre-baked, exposed by an exposure apparatus, and developed. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in a mixed solution of 57.9 wt% phosphoric acid and 21.1 wt% nitric acid for 30 seconds, and the first oxide in the region where the resist pattern is not formed is etched. The film was removed to form a second passivation layer 17b.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in 4 wt% TMAH (tetramethylammonium hydroxide) for 1 minute, and the second oxide film in a region where no resist pattern is formed is removed by etching. A first passivation layer 17a was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 30]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
To 1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and (4,4,5,5-tetramethyl-1, 0.08 g of 3,2-dioxaborolan-2-yl) benzene (Wako 325-59912, manufactured by Wako Chemical Co., Ltd.) and magnesium 2-ethylhexanoate toluene solution (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) ) 0.37 mL was mixed to obtain a first passivation layer forming coating solution. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 3.

-Preparation of second passivation layer forming coating solution-
To 1.2 mL of cyclohexylbenzene, 0.57 mL of neodymium 2-ethylhexanoate 2-ethylhexanoic acid solution (Nd content 12%, Strem 60-2400, manufactured by Strem Chemicals) and europium 2-ethylhexanoate (Strem 93-6611) 0.28 g of Strem Chemicals) and 0.12 mL of magnesium 2-ethylhexanoate toluene solution (Mg content 3%, Strem 12-1260, Strem Chemicals) are mixed to form a second passivation layer forming coating solution Got. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 3.

  Next, a bottom contact / top gate type field effect transistor was fabricated in the same manner as in Example 28 (the order of stacking the first passivation layer 17a and the second passivation layer 17b is opposite to that in Example 27).

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (after rotating at 500 rpm for 5 seconds, at 3,000 rpm). The rotation was stopped for 20 seconds and 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer-forming coating solution was dropped onto the second passivation layer 170b and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm for 5 seconds). So that the rotation stopped. Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the first passivation layer 170a (the first oxide film), and is formed by pre-baking, exposure using an exposure apparatus, and development. A resist pattern similar to the pattern of the first passivation layer 17a was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in a mixed solution of 14 wt% ammonium fluoride and 12 wt% ammonium hydrogen fluoride for 15 seconds, and the second region in the region where the resist pattern is not formed is etched. The oxide film was removed to form a first passivation layer 17a.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in a 6 wt% hydrogen peroxide solution for 2 minutes, and the first oxide film in the region where the resist pattern is not formed is removed by etching, whereby the second passivation layer is obtained. Layer 17b was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 31]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
To 1 mL of toluene, 0.17 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako) 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.47 mL and 2-ethylhexanoic acid barium toluene solution (Ba content 8%, Wako 021-09471, manufactured by Wako Chemical Co., Ltd.) 0.21 mL were mixed. A passivation layer-forming coating solution was obtained. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 4.

-Preparation of second passivation layer forming coating solution-
To 1.2 mL of cyclohexylbenzene, scandium (III) tris (2,2,6,6-tetramethyl-3,5-hebutanedionate) hydrate (SIGMA-ALDRICH 517607, manufactured by SIGMA-ALDRICH) 0.16 g 2-ethylhexanoic acid lanthanum toluene solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) 1.46 mL, 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (Ca content 3%- 8%, Alfa36657, Alfa Aesar 0.03mL, 2-ethylhexanoate strontium toluene solution (Sr content 2%, Wako 195-09561, Wako Chemical Co., Ltd.) 0.34mL, 2-ethylhexanoic acid oxidation Zirconium mineral spirit dissolution The liquid (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0.07 mL was mixed to obtain a second passivation layer forming coating liquid. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 4.

次に、図１６（ｂ）のような、ボトムコンタクト／トップゲート型の電界効果型トランジスタを作製した。ソース電極１４、ドレイン電極１５、活性層１６、ゲート絶縁層１３、及びゲート電極１２は、実施例２７と同様の方法で形成した。

Next, a bottom contact / top gate type field effect transistor as shown in FIG. The source electrode 14, drain electrode 15, active layer 16, gate insulating layer 13, and gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds, 0 rpm for 5 seconds) The rotation was stopped so that Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer-forming coating solution was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, rotating at 3,000 rpm for 20 seconds, the rotation was stopped to reach 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), pre-baked, exposed by an exposure apparatus, and developed. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in 0.36 wt% hydrochloric acid for 20 seconds, and the first oxide film in the region where the resist pattern is not formed is removed by etching, whereby the second passivation layer is formed. 17b was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in a mixed solution of 14 wt% ammonium fluoride and 3.2 wt% ammonium hydrogen fluoride for 1 minute, and is etched to form the first passivation layer 170a in the region where the resist pattern is not formed. The oxide film of 2 was removed, and a first passivation layer 17a was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 32]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
1 mL of toluene, 0.15 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.), calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content) 3% -8%, Alfa 36657, manufactured by Alfa Aesar) 0.31 mL was mixed to obtain a first passivation layer forming coating solution. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 4.

-Preparation of second passivation layer forming coating solution-
1.2 mL of cyclohexylbenzene, 0.13 g of dysprosium acetylacetonate trihydrate (Strem 66-2002, manufactured by Strem Chemicals), ytterbium acetylacetonate trihydrate (Strem 70-2202, manufactured by Strem Chemicals) 27 g, 2-ethylhexanoic acid magnesium toluene solution (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) 0.12 mL, 2-ethylhexanoic acid hafnium 2-ethylhexanoic acid solution (Gelest AKH332, manufactured by Gelest) 0.10 mL was mixed to obtain a second passivation layer forming coating solution. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 4.

  Next, a bottom contact / top gate type field effect transistor as shown in FIG. The source electrode 14, drain electrode 15, active layer 16, gate insulating layer 13, and gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds, 0 rpm for 5 seconds) The rotation was stopped so that Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer-forming coating solution was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, rotating at 3,000 rpm for 20 seconds, the rotation was stopped to reach 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), pre-baked, exposed by an exposure apparatus, and developed. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in a mixed solution of 55 wt% phosphoric acid, 30 wt% acetic acid, and 5 wt% nitric acid for 30 seconds, and the first oxidation is performed on the region where the resist pattern is not formed by etching. The material film was removed to form a second passivation layer 17b.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in 6 wt% TMAH (tetramethylammonium hydroxide) for 1 minute, and the second oxide film in a region where no resist pattern is formed is removed by etching. A first passivation layer 17a was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 33]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
1 mL of toluene, 0.09 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.), aluminum di (s-butoxide) acetoacetate chelate (Al content 8) .4%, Alfa 89349, manufactured by Alfa Aesar) 0.18 mL and 2-ethylhexanoic acid barium toluene solution (Ba content 8%, Wako 021-09471, manufactured by Wako Chemical Co., Ltd.) 0.69 mL were mixed. A passivation layer-forming coating solution was obtained. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 4.

-Preparation of second passivation layer forming coating solution-
1.2 mL of cyclohexylbenzene, 0.51 g of yttrium 2-ethylhexanoate (Strem 39-2400, manufactured by Strem Chemicals), magnesium toluene solution of 2-ethylhexanoate (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) ) 0.06 mL and 0.07 mL of 2-ethylhexanoic acid hafnium 2-ethylhexanoic acid solution (Gelest AKH332, manufactured by Gelest) were mixed to obtain a second passivation layer forming coating solution. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 4.

  Next, a bottom contact / top gate type field effect transistor was fabricated in the same manner as in Example 28 (the order of stacking the first passivation layer 17a and the second passivation layer 17b is opposite to that in Example 27).

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer forming coating solution was dropped onto the gate insulating layer 13 and the gate electrode 12 and spin-coated under predetermined conditions (after rotating at 500 rpm for 5 seconds, at 3,000 rpm). The rotation was stopped for 20 seconds and 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer-forming coating solution was dropped onto the second passivation layer 170b and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds and 0 rpm for 5 seconds). So that the rotation stopped. Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the first passivation layer 170a (the first oxide film), and is formed by pre-baking, exposure using an exposure apparatus, and development. A resist pattern similar to the pattern of the first passivation layer 17a was formed.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in 5 wt% hydrofluoric acid for 15 seconds, and the second oxide film in the region where the resist pattern is not formed is removed by etching. A passivation layer 17a was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in a mixed solution of 80 wt% phosphoric acid, 10 wt% acetic acid, and 5 wt% nitric acid for 30 seconds, and the first oxidation is performed on the region where the resist pattern is not formed by etching. The material film was removed to form a second passivation layer 17b.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

[Example 34]
<Fabrication of field effect transistor>
-Production of first passivation layer forming coating solution-
1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.), aluminum di (s-butoxide) acetoacetate chelate (Al content 8) .4%, Alfa 89349, manufactured by Alfa Aesar) 0.10 mL, (4,4,5,5-tetramethyl-1,3,2-dioxaborolan-2-yl) benzene (Wako 325-59912, Wako Corporation) Chemical) 0.07g, 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (Ca content 3% -8%, Alfa36657, Alfa Aesar) 0.09mL, 2-ethylhexanoic acid strontium toluene solution (Sr Content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.19 mL Were mixed to obtain a first passivation layer-forming coating solution. The second oxide formed by the first passivation layer forming coating solution has the composition shown in Table 4.

-Preparation of second passivation layer forming coating solution-
1.2 mL of cyclohexylbenzene, 1.95 mL of lanthanum 2-ethylhexanoate toluene solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.), 2-ethylhexanoate strontium toluene solution (Sr content 2%) , Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) 0.09 mL As a result, a second passivation layer forming coating solution was obtained. The first oxide formed by the second passivation layer forming coating solution has the composition shown in Table 4.

  Next, a bottom contact / top gate type field effect transistor as shown in FIG. The source electrode 14, drain electrode 15, active layer 16, gate insulating layer 13, and gate electrode 12 were formed in the same manner as in Example 27.

-Formation of the first passivation layer 170a-
Next, 0.4 mL of the first passivation layer forming coating solution was dropped onto the gate insulating layer and the gate electrode 12 and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds, and 0 rpm for 5 seconds. The rotation was stopped so that Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the second oxide film as the first passivation layer 170a. The average film thickness of the first passivation layer 170a was about 25 nm.

-Formation of the second passivation layer 170b-
Next, 0.6 mL of the second passivation layer-forming coating solution was dropped onto the first passivation layer 170a and spin-coated under predetermined conditions. (After rotating at 500 rpm for 5 seconds, rotating at 3,000 rpm for 20 seconds, the rotation was stopped to reach 0 rpm in 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form the first oxide film as the second passivation layer 170b. The average film thickness of the second passivation layer 170b was about 135 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied onto the second passivation layer 170b (the first oxide film), pre-baked, exposed by an exposure apparatus, and developed. A resist pattern similar to the pattern of the second passivation layer 17b was formed.

-Etching of the second passivation layer 170b-
Next, the second passivation layer 170b is immersed in 0.36 wt% hydrochloric acid (Wako083-01115 manufactured by Wako Pure Chemical Industries) for 20 seconds, and the first oxide film in a region where no resist pattern is formed by etching. Was removed to form a second passivation layer 17b.

-Etching of the first passivation layer 170a-
Next, the first passivation layer 170a is immersed in a mixed solution of 14 wt% ammonium fluoride and 12 wt% ammonium hydrogen fluoride for 15 seconds, and is etched to form the second passivation layer in the region where the resist pattern is not formed. The oxide film was removed to form a first passivation layer 17a.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.
<Evaluation of transistor characteristics of field effect transistor>
The transistor characteristics of the field effect transistors produced in Examples 27 to 34 were evaluated. The transistor characteristics of Examples 27 to 34 are as follows: the voltage (Vgs) between the gate electrode 12 and the source electrode 14 and the voltage between the drain electrode 15 and the source electrode 14 when the voltage (Vds) between the drain electrode 15 and the source electrode 14 is + 10V. The relationship (Vgs-Ids) with the current (Ids) was measured.

  Further, the field effect mobility in the saturation region was calculated from the evaluation result of the transistor characteristics (Vgs−Ids). Further, the ratio (on / off ratio, on / off ratio) of Ids between the on state (for example, Vgs = + 10 V) and the off state (for example, Vgs = −10 V) of the transistor was calculated. Further, the S value was calculated as an index of the sharpness of the rise of Ids with respect to the Vgs application. Further, the threshold voltage (Vth) was calculated as the voltage value of the rise of Ids with respect to the Vgs application.

Table 5 shows the mobility, on / off ratio, S value, and Vth calculated from the transistor characteristics of the field effect transistors manufactured in Examples 27 to 34. In the following, excellent transistor characteristics are expressed in the results of transistor characteristics that the mobility is high, the on / off ratio is high, the S value is low, and Vth is around 0V. Specifically, the transistor characteristics are excellent in that the mobility is 3 cm ² / Vs or more, the on / off ratio is 1.0 × 10 ⁸ or more, the S value is 0.7 or less, and Vth is within ± 5 V. It expresses.

  According to Table 5, the field effect transistors manufactured in Examples 27 to 34 have high mobility, high on / off ratio, low S value, Vth of around 0 V, and excellent transistor characteristics. Recognize.

＜電界効果型トランジスタのトランジスタ信頼性評価＞
実施例２７〜３４で作製した電界効果型トランジスタに対し、大気中（温度５０℃、相対湿度５０％）でＢＴＳ試験を１００時間実施した。

<Evaluation of transistor reliability of field effect transistor>
A BTS test was performed for 100 hours in the atmosphere (temperature: 50 ° C., relative humidity: 50%) for the field effect transistors manufactured in Examples 27 to 34.

The stress conditions were the following four conditions.
(1) Vgs = + 10V and Vds = 0V
(2) Vgs = + 10V and Vds = + 10V
(3) Vgs = −10V and Vds = 0V
(4) Vgs = −10V and Vds = + 10V
Further, every time the BTS test elapses, the relationship between Vgs and Ids (Vgs−Ids) when Vds = + 10 V was measured.

  FIG. 32 shows the results of Vgs-Ids of the BTS test in which the stress conditions are Vgs = + 10 V and Vds = 0 V in the field effect transistor manufactured in Example 34, and the field effect manufactured in Example 34. FIG. 33 shows the change amount (ΔVth) of the threshold voltage with respect to the stress time under the stress conditions Vgs = + 10 V and Vds = 0 V of the type transistor.

  Table 6 shows the value of ΔVth at a stress time of 100 hours in the BTS test of the field effect transistors manufactured in Examples 27 to 34. Here, ΔVth indicates the amount of change in Vth from the stress time of 0 hour to a certain stress time.

  32 and 33 and Table 6, it can be seen that the field-effect transistor manufactured in Example 34 has a small ΔVth shift and exhibits excellent reliability with respect to the BTS test. From Table 6, it can be seen that the field effect transistors fabricated in Examples 27 to 33 have a small ΔVth shift and show excellent reliability for the BTS test.

以上、好ましい実施の形態等について詳説したが、上述した実施の形態等に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態等に種々の変形及び置換を加えることができる。

The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

10, 10A, 10B, 10C, 20, 30 Field effect transistor 11, 21, 51, 61, 71, 91 Substrate 12 Gate electrode 13 Gate insulating layer 14 Source electrode 15 Drain electrode 16 Active layer 17 Passivation layer 17a, 41a, 41b 1st passivation layer 17b, 41b, 42b 2nd passivation layer 22 1st gate electrode 23 Gate insulating layer 24 1st source electrode 25 1st drain electrode 26 1st active layer 27 1st passivation layer 32 Second gate electrode 34 Second source electrode 35 Second drain electrode 36 Second active layer 37 Second passivation layer 200 Organic EL display element 210 Drive circuit 220 Interlayer insulating film 230 Organic EL element 240 Partition 250 Sealing Stop layer 260 Adhesive layer 270 Sex board

JP 2011-151370 A JP 2015-111163 A

Claims (20)

A method of manufacturing a field effect transistor having a gate insulating layer, an active layer, and a passivation layer,
Including a first step of forming the gate insulating layer and a second step of forming the passivation layer, wherein at least one of the first step and the second step comprises:
Forming a first oxide containing an alkaline earth metal and at least one of Ga, Sc, Y, and a lanthanoid;
Etching the first oxide with a first solution containing at least one of hydrochloric acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide. Method for producing effect transistor. The passivation layer includes a first passivation layer and a second passivation layer;
The second step includes
Forming a first passivation layer containing a second oxide containing Si and an alkaline earth metal;
Forming a second passivation layer disposed in contact with the first passivation layer and containing the first oxide;
Etching the first passivation layer by bringing it into contact with a second solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium hydrogen fluoride, and organic alkali; and
The method for manufacturing a field effect transistor according to claim 1, further comprising: etching the second passivation layer by bringing the second passivation layer into contact with the first solution. The second step includes
Forming the first passivation layer on the second passivation layer;
Forming a mask on the first passivation layer;
Etching the first passivation layer after contacting the second solution after forming the mask;
Etching the second passivation layer by contacting the first solution after etching the first passivation layer;
The method for manufacturing a field effect transistor according to claim 2, further comprising: removing the mask. The second step includes
Forming the second passivation layer on the first passivation layer;
Forming a mask on the second passivation layer;
Etching the second passivation layer by contacting the first solution after forming the mask;
Etching by contacting the first passivation layer with the second solution after etching the second passivation layer;
The method for manufacturing a field effect transistor according to claim 2, further comprising: removing the mask. The gate insulating layer includes a first gate insulating layer and a second gate insulating layer;
The first step includes
Forming a first gate insulating layer containing a second oxide containing Si and an alkaline earth metal;
Forming a second gate insulating layer disposed in contact with the first gate insulating layer and containing the first oxide;
Etching the first gate insulating layer by contacting with a second solution containing at least one of hydrofluoric acid, ammonium fluoride, ammonium hydrogen fluoride, and organic alkali; and
The method of manufacturing a field effect transistor according to claim 1, further comprising: etching the second gate insulating layer by bringing the second gate insulating layer into contact with the first solution. The first step includes
Forming the first gate insulating layer on the second gate insulating layer;
Forming a mask on the first gate insulating layer;
Etching the first gate insulating layer by contacting the second solution after forming the mask; and
Etching the second gate insulating layer by contacting the first solution after etching the first gate insulating layer;
6. The method of manufacturing a field effect transistor according to claim 5, further comprising a step of removing the mask. The first step includes
Forming the second gate insulating layer on the first gate insulating layer;
Forming a mask on the second gate insulating layer;
Etching the second gate insulating layer by contacting the first solution after forming the mask; and
Etching the second gate insulating layer by contacting the first gate insulating layer with the second solution after etching the second gate insulating layer;
6. The method of manufacturing a field effect transistor according to claim 5, further comprising a step of removing the mask.   6. The method of manufacturing a field effect transistor according to claim 2, wherein the second oxide contains at least one of Al and B.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the first oxide is a paraelectric amorphous oxide.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the first oxide contains at least one of Al, Ti, Zr, Hf, Nb, and Ta.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the active layer is made of an oxide semiconductor.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the gate insulating layer, the active layer, and the passivation layer are formed on an insulating substrate. The active layer is a semiconductor substrate;
2. The method of manufacturing a field effect transistor according to claim 1, wherein the gate insulating layer and the passivation layer are formed on the semiconductor substrate. Each process in the manufacturing method of the field effect transistor according to claim 1,
Forming a first capacitor electrode connected to a drain electrode of the field effect transistor, a second capacitor electrode, and a capacitor dielectric layer provided between the first capacitor electrode and the second capacitor electrode; A process for producing a volatile semiconductor memory device. Forming the capacitor dielectric layer comprises:
Forming the first oxide;
The method of manufacturing a volatile semiconductor memory device according to claim 14, further comprising: etching the first oxide by bringing the first oxide into contact with the first solution. Each process in the manufacturing method of the field effect transistor according to claim 1,
Forming a second gate insulating layer and a floating gate electrode between the active layer and the gate insulating layer. A method for manufacturing a nonvolatile semiconductor memory element, comprising: A method for manufacturing a display element, comprising: forming a drive circuit including a field effect transistor; and forming a light control element whose light output is controlled according to a drive signal from the drive circuit,
The method of manufacturing a display element according to claim 1, wherein the step of forming the driving circuit includes each step in the method of manufacturing a field effect transistor according to claim 1.   The method for manufacturing a display element according to claim 17, wherein the light control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, or an electrowetting element. A method of manufacturing an image display apparatus, comprising: a display device in which a plurality of display elements are arranged in a matrix; and a display control device that individually controls each of the display elements, wherein the step of forming the display elements comprises: Item 19. A method for manufacturing an image display device, comprising each step in a method for manufacturing a display element according to Item 17 or 18. A method for manufacturing a system, comprising: an image display device; and an image data creation device that supplies image data to the image display device, wherein the step of forming the image display device comprises: A method for manufacturing a system, comprising each step in the manufacturing method.

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