JP2007266461A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of preventing metal residue and resist residue from being generated. <P>SOLUTION: The manufacturing method of the semiconductor device including a metal deposition step S28 of forming an electrode 21 by depositing a metal in an opening 18 of a resist pattern 19 includes: between the metal depositing step S28 and a lift-off step S30 of removing metals other than the metal constituting the electrode by lifting-off, a side wall removing step S29 of removing a side wall 19s of the opening 18 of the resist pattern 19. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for manufacturing a field effect transistor such as an IC built-in Hall sensor chip.

  For example, in a manufacturing process of a GaAs semiconductor device, a channel pattern, a source region, and a drain region are formed by forming a resist pattern on a GaAs wafer and passing through an alignment mark forming step, an ion implantation step, and an annealing step. Next, a gate electrode joined to the channel layer by a Schottky junction and a source electrode and a drain electrode joined to the source region and the drain region by ohmic junction are formed.

  In a conventional GaAs semiconductor device manufacturing process, the gate electrode is formed of titanium / tungsten (Ti / W) with a sputtering device, patterned after resist, and then subjected to reactive ion etching (RIE) and resist stripping. It is completed through. The source electrode and the drain electrode are completed by depositing a metal constituting the ohmic electrode by vapor deposition after image reverse patterning and removing the excess metal by a lift-off method.

  The above-mentioned “image reverse patterning” refers to patterning capable of forming a shape (reverse taper shape) in which the wall surface of the resist opening recedes as it goes downward. In addition, the “lift-off method” is a method in which a metal film is formed by vacuum deposition in a pattern region surrounded by a resist film formed on a semiconductor substrate by using the resist film as a mask, and this is formed in an organic solvent such as acetone. A method of removing the resist film and the metal film by immersing the film in the substrate. The reason why the shape of the side surface of the opening of the resist is an inversely tapered shape is to prevent the electrode portion and the resist portion from contacting each other. Since the electrode portion and the resist portion are not in contact, when the lift-off method is performed, the organic solvent or the like can easily come into contact with the resist and can be lifted off easily.

  However, in the above conventional method for manufacturing a semiconductor device, the surface of the GaAs wafer is damaged by a resist stripping step using an organic solvent at the end of each step. In addition, when lift-off is involved, there is a risk that a resist residue is generated due to damage to the resist during vapor deposition. Therefore, it is necessary to perform the peeling condition in a direction of promoting damage to the GaAs wafer. The condition is such that the GaAs surface is etched by several hundred angstroms, thereby losing the channel layer itself. Further, since it is necessary to remove the resist residue that cannot be removed by dry etching, damage to the channel layer or the like due to plasma occurs. Naturally, plasma damage occurs on the GaAs surface even in the reactive ion etching (RIE) process. Due to the damage, there has been a problem that the transistor characteristics of the completed semiconductor device are not stable, that is, there are variations on the wafer.

  Therefore, the present applicant has previously filed a patent application relating to a method of manufacturing a semiconductor device that solves the above-described problems, by the following Patent Document 1. A method of manufacturing a semiconductor device disclosed in Patent Document 1 will be outlined with reference to FIGS.

  This method of manufacturing a semiconductor manufacturing apparatus includes a process of manufacturing a GaAs field effect transistor (GaAs MESFET). The manufacturing process of this GaAs MESFET is roughly divided into a process of forming a drain region, a source region and a channel layer (ST10), a process of forming a gate electrode (ST20), and a process of forming a drain electrode and a source electrode (ST30). ).

  More specifically, in the gate electrode formation step (ST20) or the drain electrode and source electrode formation step (ST30), the inorganic insulating layer exposed through the first opening is dried until a predetermined thickness is reached. Etching step for etching (ST23 or ST32), step for forming a second opening on the first opening (ST25, ST26 or ST34, ST35), and then the inorganic material exposed through the first opening And an etching process (ST27 or ST36) for performing wet etching until the system insulating layer is removed.

According to the method of manufacturing a semiconductor device according to Patent Document 1, since the etching process and the like are included, there is an advantage that the channel layer, the drain region, and the source region are not damaged by the plasma, thereby causing the plasma damage. The transistor characteristics of the semiconductor device to be processed are not varied, and the operation is stabilized.
JP 2003-124234 A

According to the method for manufacturing a semiconductor device according to Patent Document 1, the first resist pattern is removed, and the second resist pattern having a second opening wider than the first opening at the same position as the first opening is formed. The upper part of the SiO ₂ film exposed through the second opening is also etched. After this step, a metal is deposited by a vapor deposition method or the like in a metal deposition step. Thereafter, the second resist pattern is removed by a lift-off method, and unnecessary metal deposited on the resist pattern is removed.

  However, a defective product may occur even in a semiconductor device manufactured by the above manufacturing method. When a defective product is observed with a microscope, it is often caused by metal residues, dust / scratches, patterning defects, resist residues, and the like. Of those causes, metal residues were often the cause.

  Here, the “metal residue” is a metal powder remaining when unnecessary metal is removed (lifted off) in the electrode forming step. If the metal residue adheres across the electrodes of the electrode pattern, the electrodes are short-circuited to cause an IC malfunction.

  In the manufacturing method in Patent Document 1, when the second resist pattern is formed and the electrode part is deposited by vapor deposition, the electrode part and the resist side wall may be in contact with each other. When such a case occurs, an organic solvent such as acetone does not enter between the electrode portion and the resist side wall during the lift-off process, so that the resist on the side portion of the electrode portion is difficult to remove and the resist residue tends to remain. there were. This problem is described in detail below.

  FIG. 7 shows a longitudinal sectional view of a main part of the second opening after the second resist pattern is formed and the electrode part is deposited by metal vapor deposition and before lift-off is performed. This main part longitudinal cross-sectional view is drawn based on the cross-sectional shape observation result by SEM (scanning electron microscope). In this observation, two cases of the case shown in FIG. 7A and the case shown in FIG. 7B were observed.

In FIG. 7, reference numeral 100 denotes an opening, reference numeral 101 denotes a semiconductor substrate, reference numeral 102 denotes an SiO ₂ film, reference numeral 103 denotes an electrode, reference numeral 104 denotes a resist, and reference numeral 105 denotes a metal. In FIG. 7A, the electrode 103 and the side wall of the resist 104 are not in contact with each other, as can be seen from the portion surrounded by the circle A. Therefore, lift-off is easily performed and no resist residue is generated. Further, the metal 105 deposited on the side wall of the resist 104 is not in contact with the electrode 103. This metal is removed after lift-off and thus no metal residues are produced.

  On the other hand, in FIG. 7B, the electrode 103 and the side wall of the resist 104 are in contact with each other, as can be seen from the portion surrounded by the circle B. Further, the metal 105 deposited on the side wall of the resist 104 is also in contact with the electrode 103. At this time, when the lift-off method is performed, the portion of the resist 104 that is in contact with the electrode 103 is less likely to be in contact with an organic solvent such as acetone and is not easily dissolved. As a result, a resist residue is produced, and a metal residue is produced at the same time.

  Further, the resist where the metal adheres on the side wall of the resist 104 is prevented from coming into contact with the organic solvent by the metal and does not dissolve. For this reason, the resist residue remains without dissolving the portion where the metal powder adheres on the side wall of the second resist pattern. At that time, unnecessary metal powder (metal residue) remains in a state of being connected to the electrode portion via the resist residue, and the metal residue is not removed in the subsequent resist residue removing step. Even if the resist is removed by ashing for removing the resist residue thereafter, the metal residue remains and is connected between the gate electrode, the drain electrode, and the source electrode due to the metal residue, causing a short circuit. It was.

  In view of the above-mentioned problems, the object of the present invention is to eliminate the contact portion between the electrode portion and the opening-side resist side wall portion by adding a simple process, and reliably prevent the generation of resist residues and metal residues formed thereon. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can eliminate the occurrence of a short circuit between electrodes due to metal residues.

  In order to achieve the above object, a semiconductor device manufacturing method according to the present invention is configured as follows.

  A first method for manufacturing a semiconductor device (corresponding to claim 1) is a method for manufacturing a semiconductor device including a step of forming an electrode by depositing a metal on a substrate through an opening formed in a resist pattern. It is characterized by having a step of removing the resist side wall portion in the opening in the resist pattern between the step of forming and the step of removing metal other than the metal portion forming the electrode by lift-off thereafter.

  According to the first method for manufacturing a semiconductor device, the resist sidewall in the opening in the resist pattern between the step of forming an electrode and the step of removing metal other than the metal portion that forms the electrode by lift-off thereafter. Since the resist side wall is in contact with the electrode formed in the electrode forming step, the resist side wall is removed by the step of removing the resist side wall in the opening in the resist pattern. And the contact between the electrode and the resist is removed. Thereby, in the step of removing other metal other than the metal portion forming the electrode by subsequent lift-off, the resist and the other metal other than the metal portion forming the electrode can be easily removed, and the resist residue It becomes difficult to occur. Further, even if metal adheres to the side wall portion of the resist, the metal adhering to the side wall portion is also removed in the step of removing the resist side wall portion in the opening in the resist pattern, so that the metal residue can be reduced. .

  The second method for manufacturing a semiconductor device (corresponding to claim 2) is characterized in that, in the above-described method, preferably, in the step of removing the resist side wall portion, the contact portion between the electrode and the resist side wall portion is eliminated. It is done.

  A third method for manufacturing a semiconductor device (corresponding to claim 3) is characterized in that, in the above method, the step of removing the resist sidewall is preferably an ashing step.

  According to a fourth method of manufacturing a semiconductor device (corresponding to claim 4), in the above method, preferably the electrode is at least one of a gate electrode, a drain electrode, and a source electrode of a GaAs semiconductor element. Characterized.

  According to a fifth method of manufacturing a semiconductor device (corresponding to claim 5), a drain region, a source region, a channel layer formed on a GaAs semiconductor substrate, a drain electrode joined to the drain region, and a source region are joined. A method of manufacturing a semiconductor device including a source electrode and a gate electrode joined to a channel layer, the step of forming an insulating layer on the drain region, the source region, and the channel layer, and forming the gate electrode on the insulating layer Including a step of simultaneously forming a drain electrode and a source electrode on the insulating layer, and a step of forming a gate electrode and a step of simultaneously forming a drain electrode and a source electrode, or both of them The step of forming a first resist pattern having a first opening at a position corresponding to the electrode formation location in the insulating layer; A step of dry-etching the insulating layer exposed through one opening until a predetermined film thickness is obtained, a step of removing the first resist pattern, and the same position as the first opening of the first resist pattern. Forming a second resist pattern having a second opening wider than the first opening, performing a wet etching process until the insulating layer exposed through the first opening is removed, and forming an electrode Including a step of forming a metal film, a side wall portion removing step of removing the resist side wall portion in the opening of the second resist pattern, and a step of removing metal other than the metal forming the gate electrode by lift-off. Characterized.

  A sixth method for manufacturing a semiconductor device (corresponding to claim 6) is characterized in that, in the above method, the side wall portion removing step is preferably an ashing step.

  The present invention has the following effects. In the electrode forming process, after depositing metal using the second resist pattern, the resist side wall part contacting the metal part forming the electrode is removed by a side wall part removing process such as ashing, and then the second is formed by lift-off. Since the resist pattern is removed, resist residues with metal residues can be eliminated. Furthermore, since a metal residue can be eliminated, a short circuit between electrodes can be eliminated.

  DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

  1 and 2 are flowcharts showing steps of manufacturing a GaAs field effect transistor (hereinafter referred to as “GaAs MESFET”) by the method of manufacturing a semiconductor device according to the embodiment of the present invention. 1 and 2 show the manufacturing process as a whole. In particular, FIG. 1 shows the first half of the manufacturing process, and FIG. 2 shows the second half of the manufacturing process. The manufacturing process of the GaAs MESFET is roughly divided into a drain region, source region and channel layer forming step S10, a gate electrode forming step S20, and a drain electrode and source electrode forming step S40.

The gate electrode forming step S20 further includes the following eleven steps S21 to S31.
S21: Inorganic insulating layer deposition step.
S22: First resist patterning step.
S23: A step of etching the inorganic insulating layer exposed through the first opening in the portion where the gate electrode is formed to a predetermined film thickness by dry etching.
S24: First resist stripping step.
S25: a second resist patterning process having a second opening having a wider opening width than the first opening at the same position as the first opening of the first resist pattern by image reverse patterning.
S26: Ashing process.
S27: A step of performing etching until the inorganic insulating layer having a predetermined thickness exposed through the first opening is removed by wet etching.
S28: depositing a metal for forming the gate electrode.
S29: Side wall portion removing step.
S30: Lift-off process.

The drain electrode and source electrode forming step S40 further includes 10 steps S41 to S50.
S41: First resist patterning step.
S42: A step of etching the inorganic insulating layer exposed through the first opening of the portion where the drain electrode and the source electrode are formed by dry etching to a predetermined film thickness.
S43: First resist stripping step.
S44: a second resist patterning step having a second opening having a wider opening width than the first opening at the same position as the first opening of the first resist pattern by image reverse patterning.
S45: Ashing process.
S46: A step of etching the remaining inorganic insulating layer having a predetermined thickness exposed through the first opening by wet etching.
S47: depositing a metal for forming the drain electrode and the source electrode.
S48: Side wall removal step.
S49: Lift-off process.

In the drain region, source region, and channel layer forming step S10, as in the prior art, first, in order to form a high impurity concentration active layer to be a drain region and a source region on a GaAs semiconductor substrate on which alignment marks are formed, An oxide film of several hundred angstroms is formed on the surface, and Si ⁺ ion implantation at a high dose of 160 keV and 2.0 × 10 ¹³ / cm ² is performed through an appropriate mask. Next, in order to form a channel layer in the GaAs semiconductor substrate, Si ⁺ is ion-implanted through an appropriate mask at 120 keV and 2.0 × 10 ¹² / cm ² . Thereafter, an SiO ₂ film is deposited on the GaAs semiconductor substrate, and the GaAs semiconductor substrate is placed in an annealing furnace and heated at 800 ° C. for about 10 minutes in a hydrogen (H ₂ ) atmosphere to perform cap annealing. Thereby, Si ions are activated, and a channel layer, a drain region, and a source region are formed.

  Next, the specific contents of the gate electrode formation step S20 will be described with reference to FIGS. 3 and 4 are partial longitudinal sectional views of the GaAs semiconductor substrate in each step of the gate electrode forming step S20. 3A to 3D and FIG. 4A to 4E are executed continuously.

In the inorganic insulating layer deposition step (S21), as shown in FIG. 3A, a film thickness of 3000 Å is formed on the GaAs semiconductor substrate 13 on which the channel layer 10, the drain region 11, and the source region 12 are formed by plasma CVD. The SiO ₂ film 14 is formed as an inorganic insulating layer.

In the first resist patterning step (S22), first, as shown in FIG. 3B, the first resist 15 is applied onto the SiO ₂ film 14 which is an inorganic insulating layer deposited on the GaAs semiconductor substrate 13 by a spin coater or the like. Apply uniformly. Next, a mask in which the portion where the gate electrode is formed passes light is brought into close contact with the resist 15 on the SiO ₂ film 14 which is an inorganic insulating layer on the GaAs semiconductor substrate 13, and the resist 15 reacts. Exposure with light of a wavelength. Thereafter, the exposed portion of the resist is melted by dipping in a developing solution, and the first opening 16 is formed. Then, the developer is washed with a rinse solution.

Thereafter, post-baking is performed in order to increase the adhesiveness between the first resist 15 and the SiO ₂ film 14 which is an inorganic insulating layer by removing the developing solution or the rinsing solution present in the first resist 15.

Next, FIG. 3 as (c), the by reactive ion etching (RIE), the SiO ₂ in the first opening 16 of the resist 15, of predetermined thickness, for example, 500 Å in the thickness of the SiO ₂ Etching is performed so as to leave the film 17 (step S23).

  Thereafter, as shown in FIG. 3D, the first resist 15 is removed (step S24).

  Thereafter, as shown in FIG. 4A, a second opening having a wider opening width than the first opening 16 is formed at the same position as the first opening 16 of the first resist pattern by image reverse patterning. A second resist pattern 19 having 18 is formed (step S25).

  In the step of forming the second resist pattern 19, first, a positive resist is applied to the entire surface of the wafer. Next, first exposure is performed using a mask in which a region wider than the first opening 16 is shielded from light on the first opening 16 where the gate electrode is formed by ultraviolet rays. Next, as image reversal processing, baking is performed at 110 ° C., and then, the entire surface of the wafer is subjected to second exposure with ultraviolet rays and developed to remove unexposed portions of the resist film during the first exposure. As a result, the second opening 18 having an undercut shape (reverse taper shape) is formed on the first opening 16 so that the opening width is wide and lift-off is possible.

Next, in order to remove the development residue, ashing is performed by generating oxygen (O ₂ ) plasma with a plasma ashing apparatus (step S26). Thereafter, as shown in FIG. 4B, the remaining 500 Å thick SiO ₂ film 17 is removed by wet etching using buffered hydrofluoric acid (BHF) (step S27). At that time, the upper part of the SiO ₂ film exposed through the second opening 18 is also etched.

As described above, the step S23 of etching the inorganic insulating layer exposed through the first opening 16 by dry etching until the film thickness reaches a predetermined thickness, and the second opening wider than the first opening width on the first opening 16. After the opening 18 is formed, the etching is performed by the wet etching until the inorganic insulating layer having a predetermined thickness exposed through the first opening 16 is completely removed. Does not cause damage. As a result, the transistor characteristics of the semiconductor device due to damage do not vary and become stable. In addition, since the inorganic insulating layer is one kind of the SiO ₂ film 14, the number of steps for depositing the inorganic insulating layer can be reduced.

In the step of depositing the metal for forming the gate electrode (step S28), as shown in FIG. 4C, the metal for forming the gate electrode is, for example, titanium, gold, titanium (Ti / Au / Ti) of 3000 angstroms. The film is formed by a vapor deposition method with a film thickness of Thereby, the gate electrode 21 and the metal 20 on the resist 19 are formed. Thereafter, in the side wall portion removing step (step S29), ashing is performed by generating oxygen (O ₂ ) plasma with a plasma ashing device in order to remove the resist side wall portion. Thereby, as shown in FIG. 4D, the side wall portion 19s of the resist 19 is scraped off. As a result, it is possible to reliably prevent a contact portion between the gate electrode 21 and the side wall portion 19 s of the resist 19.

  Thereafter, as shown in FIG. 4E, the resist 19 and the metal 20 deposited on the resist are removed by lift-off (step S30). At this time, since the gate electrode 21 and the side wall of the resist 19 are not in contact with each other, the resist can be dissolved by an organic solvent such as acetone for lift-off. As described above, since the lift-off process is performed in a state in which the side wall portion 19s of the resist 19 is removed, the resist can be removed without accompanying metal residues, so that the generation of metal residues can be prevented and the electrodes are short-circuited by metal residues. Can be prevented, and the yield can be improved.

  After the aforementioned gate electrode formation step S20, a drain electrode and source electrode formation step S40 is performed.

  Next, specific contents of the drain electrode and source electrode formation step S40 will be described with reference to FIGS. 5 and 6 are partial longitudinal sectional views of the GaAs semiconductor substrate in each step of the gate electrode forming step S20. (A) to (d) in FIG. 5 and (a) to (e) in FIG. 6 are executed continuously.

First, as shown in FIG. 5A, a first resist 22 is uniformly coated on the SiO ₂ film 14 which is an inorganic insulating layer deposited on the GaAs semiconductor substrate 13 by a spin coater or the like. Next, as shown in FIG. 5B, a mask on which the drain electrode and source electrode forming portions allow light to pass is used as a resist on the SiO ₂ film 14 which is an inorganic insulating layer on the GaAs semiconductor substrate 13. The resist 22 is exposed to light having a wavelength at which the resist 22 reacts, and then the exposed portion of the resist is melted by being immersed in a developing solution to form first openings 23 and 24 (step S41). Then, the developer is washed with a rinse solution.

Thereafter, post-baking is performed in order to increase the adhesiveness between the resist 22 and the SiO ₂ film 14 that is an inorganic insulating layer by removing the developing solution or the rinsing solution present in the resist 22.

Next, FIG. 5 as (c), the reactive ion etching by (RIE), the first SiO ₂ a predetermined thickness of the opening 23 of the resist 22, for example, 500 Å in the thickness of the SiO ₂ Etching is performed to leave the films 25 and 26 (step S42).

  Thereafter, as shown in FIG. 5D, the first resist is stripped (step S43).

  Next, as shown in FIG. 6A, by image reverse patterning, the second opening 27 having a wider opening width than the first opening is formed at the same position as the first openings 23 and 24 of the first resist pattern. , 28 is formed (step S44).

  In the step of forming the second resist pattern 29, first, a positive resist is applied to the entire surface of the wafer. Next, first exposure is performed using a mask in which a region wider than the first opening is shielded from light on the first openings 23 and 24 for forming the ohmic electrode by ultraviolet rays. Next, as image reversal processing, baking is performed at 110 ° C., and then, the entire surface of the wafer is subjected to second exposure with ultraviolet rays and developed to remove unexposed portions of the resist film during the first exposure. As a result, the second openings 27 and 28 having an undercut shape (reverse taper shape) are formed on the first opening so that the opening width is wide and lift-off is possible.

Next, in order to remove the development residue, oxygen (O ₂ ) plasma is generated by a plasma ashing apparatus and ashing is performed (step S45).

Thereafter, as shown in FIG. 6B, the remaining 500 Å thick SiO ₂ films 25 and 26 are removed by wet etching using buffered hydrofluoric acid (BHF) (step S46). At this time, the upper part of the SiO ₂ film exposed by the second openings 27 and 28 is also etched.

In this way, the step S42 of etching the SiO ₂ that is the inorganic insulating layer exposed through the first openings 23 and 24 by dry etching until the film has a predetermined thickness, and the first opening width on the first opening. After forming the wider second openings 27 and 28, etching is performed by wet etching until the inorganic insulating layer having a predetermined film thickness exposed through the first opening is removed. Does not cause damage to the drain and source regions. As a result, the transistor characteristics of the semiconductor device due to damage do not vary and become stable. Further, since the inorganic insulating layer is a kind of SiO ₂ film, the number of steps for depositing the inorganic insulating layer can be reduced.

Next, as shown in FIG. 6C, as a metal for forming the drain electrode and the source metal, for example, an AuGe / Ni / Au film 30 is formed by vapor deposition to a thickness of 3000 angstrom (step S47). Thereby, the drain electrode 31 and the source electrode 32 are formed, and the metal 30 is deposited on the resist. Thereafter, in the side wall portion removing step S48, ashing is performed by generating oxygen (O ₂ ) plasma by a plasma ashing apparatus in order to remove the resist side wall portion. As a result, as shown in FIG. 6D, the side wall 29 s of the resist 29 is scraped off, and the contact between the drain electrode 31 or the source electrode 32 and the side wall 29 s of the resist 29 can be prevented.

  Next, the resist 29 and the metal 30 deposited on the resist are removed by a lift-off technique (step S49) (step S49). At this time, since the drain electrode 31 or the source electrode 32 and the side wall of the resist 29 are not in contact with each other, the resist can be dissolved by an organic solvent such as acetone for lift-off as shown in FIG. As described above, since the lift-off process is performed in a state where the side walls of the resist are removed, the resist can be removed without accompanying metal residues, so that a short circuit between the electrodes can be prevented and the yield can be improved. .

In the present embodiment, the GaAs semiconductor device has been described, but the present invention can also be used in a method for manufacturing a semiconductor device such as a Si semiconductor device, a SiC semiconductor device, or an InP semiconductor device. In this embodiment, the SiO ₂ film is used as the inorganic insulating layer. However, SiN x can also be used as the inorganic insulating layer. In this embodiment, etching by reactive ion etching (RIE) of SiO _{2 in} the first opening of the resist is performed so as to leave a predetermined film thickness of 500 Å. However, the pattern may spread. In consideration of the influence of side etching and the accuracy of dry etching, a film thickness other than 500 angstroms is possible as long as the predetermined film thickness is in the range of 300 angstroms or more and 700 angstroms or less.

  The configurations, shapes, sizes, and arrangement relationships described in the embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective configurations are only examples. Only. Therefore, the present invention is not limited to the embodiments described below, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

  INDUSTRIAL APPLICABILITY The present invention is used as a method for manufacturing a semiconductor device such as an IC built-in Hall sensor chip by eliminating a metal residue and eliminating a short circuit between electrodes.

It is a flowchart which shows the first half of the process of manufacturing a GaAs field effect transistor with the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a flowchart which shows the latter half part of the process of manufacturing a GaAs field effect transistor with the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a principal part longitudinal cross-sectional view of the GaAs semiconductor substrate in each process of the first half of a gate electrode formation process. It is a principal part longitudinal cross-sectional view of the GaAs semiconductor substrate in each process of the latter half of a gate electrode formation process. It is a principal part longitudinal cross-sectional view of the GaAs semiconductor substrate in each process of the first half of a drain electrode and a source electrode formation process. It is a principal part longitudinal cross-sectional view of the GaAs semiconductor substrate in each process of the latter half of a drain electrode and a source electrode formation process. In a conventional method of manufacturing a semiconductor device, a partial longitudinal section for explaining a second opening after a second resist pattern is formed and an electrode portion is formed by metal deposition and before lift-off is performed. FIG.

Explanation of symbols

10 channel layer 11 drain region 12 source region 13 GaAs semiconductor substrate 14 SiO ₂ film 15 resist 16 first opening 17 SiO ₂ film 18 second opening S10 drain region, source region and channel layer forming step S20 gate electrode forming step S40 Drain electrode and source electrode formation process

Claims (6)

A method of manufacturing a semiconductor device, including a step of depositing metal on a substrate through an opening formed in a resist pattern to form an electrode,
A step of removing a resist side wall portion in the opening in the resist pattern between the step of forming the electrode and a step of removing metal other than the metal portion forming the electrode by lift-off thereafter. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the resist side wall portion eliminates a contact portion between the electrode and the resist side wall portion.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the resist side wall portion is an ashing step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the electrode is at least one of a gate electrode, a drain electrode, and a source electrode of a GaAs semiconductor element. A drain region, a source region, and a channel layer formed on a GaAs semiconductor substrate, a drain electrode joined to the drain region, a source electrode joined to the source region, and a gate electrode joined to the channel layer A method of manufacturing a semiconductor device comprising:
Forming an insulating layer on the drain region, the source region, and the channel layer; forming the gate electrode on the insulating layer; and simultaneously forming the drain electrode and the source electrode on the insulating layer. Including steps,
The step of forming the gate electrode, the step of simultaneously forming the drain electrode and the source electrode, and either or both of the steps are:
Forming a first resist pattern having a first opening at a position corresponding to an electrode formation location in the insulating layer;
Dry etching the insulating layer exposed through the first opening to a predetermined thickness;
Removing the first resist pattern;
Forming a second resist pattern having a second opening having a wider opening width than the first opening at the same location as the position of the first opening of the first resist pattern;
Wet etching until the insulating layer exposed through the first opening is removed;
Forming a metal film for forming the electrode;
A sidewall removing step of removing a resist sidewall in the opening of the second resist pattern;
Removing a metal other than the metal forming the gate electrode by lift-off;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor manufacturing apparatus according to claim 5, wherein the side wall portion removing step is an ashing step.

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