KR20020050918A - Method for Fabricating of Flash Memory Device - Google Patents
Method for Fabricating of Flash Memory Device Download PDFInfo
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- KR20020050918A KR20020050918A KR1020000080222A KR20000080222A KR20020050918A KR 20020050918 A KR20020050918 A KR 20020050918A KR 1020000080222 A KR1020000080222 A KR 1020000080222A KR 20000080222 A KR20000080222 A KR 20000080222A KR 20020050918 A KR20020050918 A KR 20020050918A
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- floating gate
- flash memory
- semiconductor substrate
- memory device
- active region
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001020 plasma etching Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 플로팅 게이트(Floating Gate)의 첨점을 제거하여 플로팅 게이트의 전하 손실에 의한 문턱전압의 변화를 방지하기 위한 플레쉬 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a flash memory device for preventing a change in threshold voltage due to the loss of charge of a floating gate by removing the peaks of the floating gate.
이하, 첨부된 도면을 참조하여 종래의 플레쉬 메모리 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional flash memory device will be described with reference to the accompanying drawings.
도 1은 종래 기술에 따른 플레쉬 메모리의 단면도이고, 도 2는 종래 플레쉬 메모리의 단면 사진이다.1 is a cross-sectional view of a flash memory according to the prior art, Figure 2 is a cross-sectional picture of a conventional flash memory.
종래 기술에 따른 플레쉬 메모리 소자의 제조방법은 도 1에 도시된 바와 같이, LOCOS(Local Oxidation of Silicon) 공정으로 반도체 기판(11)의 소정 영역에 필드 산화막(12)을 형성하여 필드 영역 및 활성 영역을 정의한다.In the method of manufacturing a flash memory device according to the related art, as shown in FIG. 1, a field oxide layer 12 is formed in a predetermined region of a semiconductor substrate 11 by a local oxide of silicon (LOCOS) process, thereby forming a field region and an active region. Define.
이때, 상기 활성 영역의 반도체 기판(11)과 필드 산화막(12)이 형성된 필드 영역간에 단차가 발생하게 된다.At this time, a step is generated between the semiconductor substrate 11 of the active region and the field region where the field oxide film 12 is formed.
그리고, 상기 반도체 기판(11)의 전면에 산화막(13)과 폴리 실리콘막을 차례로 증착한다.The oxide film 13 and the polysilicon film are sequentially deposited on the entire surface of the semiconductor substrate 11.
이어, 포토 및 식각 공정으로 상기 활성 영역의 반도체 기판(11) 및 그에 인접한 필드 영역상에 남도록 상기 폴리 실리콘막과 산화막(13)을 선택적으로 제거하여 상기 폴리 실리콘막으로 플로팅 게이트(14)를 형성한다.Subsequently, the polysilicon layer and the oxide layer 13 are selectively removed to remain on the semiconductor substrate 11 and the field region adjacent to the active region by a photo and etching process to form the floating gate 14 as the polysilicon layer. do.
이때, 상기 플로팅 게이트(14)가 활성 영역의 반도체 기판(11)뿐만 아니라 그에 인접한 필드 영역에 형성됨에 따라서 상기 플로팅 게이트(14)의 에지(Edge) 부분에 첨점이 형성되게 된다.At this time, as the floating gate 14 is formed not only in the semiconductor substrate 11 of the active region but also in the field region adjacent thereto, a point is formed at an edge portion of the floating gate 14.
즉, 도 2의 사진에 나타난 바와 같이 플로팅 게이트(14) 양끝 상부에 첨점이 발생되게 된다.That is, as shown in the photograph of FIG. 2, a peak is generated on both ends of the floating gate 14.
이러한, 첨점 부위에서는 전하 집중 현상이 발생되게 되므로 프로그램(program)된 전하가 빠져나가게 되는 원인이 된다.Since the charge concentration phenomenon occurs in the point region, the programmed charge is caused to escape.
도 3은 종래 플레쉬 메모리의 게이트 전압에 따른 드레인 전류를 나타낸 그래프로, 플로팅 게이트(14) 에치부에 첨점이 발생함에 따라서 문턱전압(Threshold Voltage)이 변화함을 나타낸다.FIG. 3 is a graph illustrating a drain current according to a gate voltage of a conventional flash memory, and shows that a threshold voltage changes as a peak is generated in an etched portion of the floating gate 14.
즉, 노멀(Normal)한 상태에서 플레쉬 메모리의 문턱 전압은 약 7.5V를 유지하는 반면에 플로팅 게이트(14) 에지부이 첨점 발생되면 프로그램된 전하가 상기 첨점 부위를 통해 빠져나가므로 문턱 전압이 약 6V로 낮아지게 된다.That is, in the normal state, the threshold voltage of the flash memory is maintained at about 7.5V, whereas if the edge of the floating gate 14 is pointed, the programmed charge is discharged through the pointed part, so the threshold voltage is about 6V. Will be lowered.
그러나, 상기와 같은 종래의 플레쉬 메모리 소자의 제조방법은 다음과 같은 문제점이 있다.However, the conventional method of manufacturing a flash memory device as described above has the following problems.
첫째, 플로팅 게이트 에지부의 첨점으로 인하여 문턱전압이 낮아지므로 소자의 특성이 저하된다.First, since the threshold voltage is lowered due to the peaks of the floating gate edge, the device characteristics are degraded.
둘째, 플로팅 게이트 에지부의 첨점으로 인하여 후속 공정을 진행하기가 어렵고 공정 난이도가 증가된다.Second, it is difficult to proceed with subsequent processes and the process difficulty is increased due to the sharpness of the floating gate edges.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 플로팅 게이트 에지부의 첨점을 제거하여 소자의 특성 및 공정의 용이성을 향상시키는데 적합한 플레쉬 메모리 소자의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a flash memory device suitable for improving the characteristics of the device and the ease of processing by eliminating the dots of the floating gate edge.
도 1은 종래 기술에 따른 플레쉬 메모리 소자의 단면도1 is a cross-sectional view of a flash memory device according to the prior art
도 2는 종래 플레쉬 메모리 소자의 단면 사진2 is a cross-sectional view of a conventional flash memory device
도 3은 종래 플레쉬 메모리 소자의 게이트 전압에 따른 드레인 전류를 나타낸 그래프3 is a graph illustrating drain current according to a gate voltage of a conventional flash memory device.
도 4a 내지 도 4c는 본 발명의 실시예에 따른 플레쉬 메모리 소자의 제조공정 단면도4A to 4C are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
41 : 반도체 기판 42 : 필드 산화막41 semiconductor substrate 42 field oxide film
43 : 산화막 44 : 플로팅 게이트43: oxide film 44: floating gate
45 : 웨이퍼 46 : 식각기45: wafer 46: etcher
상기와 같은 목적을 달성하기 위한 본 발명의 플레쉬 메모리 소자의 제조방법은 반도체 기판의 소정 영역에 소자 격리막을 형성하여 필드 영역 및 활성 영역을 정의하는 단계와, 상기 활성 영역의 반도체 기판 및 이에 인접한 소자 격리막상에 게이트 절연막과 플로팅 게이트를 적층하여 형성하는 단계와, 플라즈마 식각 공정으로 상기 소자 격리막상에 형성된 플로팅 게이트 에지부의 첨점을 제거하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a flash memory device of the present invention for achieving the above object is to form a device isolation layer in a predetermined region of the semiconductor substrate to define the field region and the active region, the semiconductor substrate of the active region and the device adjacent thereto And forming a gate insulating film and a floating gate on the isolation layer, and removing a dot of the floating gate edge formed on the device isolation layer by a plasma etching process.
이하, 첨부된 도면을 참조하여 본 발명의 플레쉬 메모리 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a flash memory device of the present invention will be described with reference to the accompanying drawings.
도 4a 내지 도 4c는 본 발명의 실시예에 따른 플레쉬 메모리 소자의 제조공정 단면도이다.4A to 4C are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.
본 발명에 따른 플레쉬 메모리 소자의 제조방법은 도 4a에 도시된 바와 같이, LOCOS(LOCal Oxidation of Silicon) 공정으로 반도체 기판(41)의 소정 영역에 필드 산화막(42)을 형성하여 필드 영역 및 활성 영역을 정의한다.In the method of manufacturing a flash memory device according to the present invention, as shown in FIG. 4A, a field oxide layer 42 is formed in a predetermined region of a semiconductor substrate 41 by a LOCOS (LOCal Oxidation of Silicon) process, thereby forming a field region and an active region. Define.
이때, 상기 활성 영역의 반도체 기판(41)과 필드 산화막(42)이 형성된 필드 영역간에 단차가 발생하게 된다.At this time, a step is generated between the semiconductor substrate 41 of the active region and the field region where the field oxide film 42 is formed.
그리고, 상기 반도체 기판(41)의 전면에 산화막(43)과 폴리 실리콘막을 차례로 증착한다.An oxide film 43 and a polysilicon film are sequentially deposited on the entire surface of the semiconductor substrate 41.
여기서, 상기 폴리 실리콘막으로는 도핑된 폴리 실리콘막(Doped Poly Si), 비정질 실리콘막(Amorphous Si), 임플렌테이션 실리콘막(Implantation Si) 중 어느 하나를 이용한다.The polysilicon layer may be any one of a doped polysilicon layer, an amorphous silicon layer, and an implantation silicon layer.
그리고, 상기 반도체 기판(41)의 전면에 포토레지스트(도시하지 않음)를 도포하고 노광 및 현상 공정으로 상기 활성 영역의 반도체 기판(41) 및 그에 인접한 필드 영역 상부의 상기 폴리 실리콘막이 노출되도록 상기 포토레지스트를 선택적으로 패터닝한다.Then, a photoresist (not shown) is coated on the entire surface of the semiconductor substrate 41, and the photoresist is exposed to expose the polysilicon film on the semiconductor substrate 41 in the active region and the field region adjacent thereto by an exposure and development process. Selectively pattern the resist.
이어, 상기 패터닝된 포토레지스트를 마스크로 이용한 플라즈마 식각(Plasma Etch) 공정으로 상기 폴리 실리콘막과 산화막(43)을 선택적으로 제거하여 상기 폴리 실리콘막으로 플로팅 게이트(44)를 형성한다.Subsequently, the polysilicon layer and the oxide layer 43 are selectively removed by a plasma etching process using the patterned photoresist as a mask to form a floating gate 44 with the polysilicon layer.
이때, 상기 플로팅 게이트(44)가 활성 영역의 반도체 기판(41)뿐만 아니라 그에 인접한 필드 영역에 형성됨에 따라서 상기 플로팅 게이트(44)의 에지(Edge) 부분에 첨점이 형성되게 된다.In this case, as the floating gate 44 is formed not only in the semiconductor substrate 41 of the active region but also in the adjacent field region, a point is formed at an edge portion of the floating gate 44.
그리고, 도 4b에 도시된 바와 같이 상기 공정을 마친 웨이퍼(45)를 상기 플라즈마 식각 공정을 실시한 장비와 동일한 식각기(46)에서 플라즈마 방전시킨다.As shown in FIG. 4B, the wafer 45 having the above-described process is plasma discharged in the same etching machine 46 as the equipment which has performed the plasma etching process.
이때, 상기 식각기(46)에 바이어스 전원(Bias Power)을 인가하지 않는다.In this case, a bias power is not applied to the etcher 46.
그리고, 상기 식각기(46)로는 TCP, ICP, ERC, RIE 등의 고밀도 플라즈마 소스를 사용하는 장비를 이용한다.As the etcher 46, equipment using a high density plasma source such as TCP, ICP, ERC, or RIE is used.
이어, 도 4c에 도시된 바와 같이 등방성 식각 공정을 실시하여 상기 플로팅 게이트(44) 에지부에 형성된 첨점을 제거한다.Subsequently, as shown in FIG. 4C, an isotropic etching process is performed to remove the dots formed at the edges of the floating gate 44.
이때, 상기 등방성 식각 공정은 상기 플로팅 게이트(44) 첨점 부분과 플로팅 게이트(44) 중앙 부분간에 발생된 단차의 20∼100%를 타겟(Target)으로 하여 진행한다.In this case, the isotropic etching process proceeds with a target of 20 to 100% of the step generated between the peak portion of the floating gate 44 and the center portion of the floating gate 44.
즉, 고밀도 플라즈마 소스를 이용하는 장비를 이용하여 플라즈마를 발생시킨후에 바이어스 전원을 인가하지 않으면, 라디컬(Radical)의 농도 분포에 의하여 등방성 식각 공정이 진행된다.That is, if a bias power is not applied after generating plasma using equipment using a high density plasma source, an isotropic etching process is performed by radical concentration distribution.
이때, 플로팅 게이트(44) 에지 첨점 부위의 라디컬 농도 분포가 주위보다 상대적으로 높아 보다 빨리 식각되므로 플로팅 게이트(44) 에지부의 첨점이 완화되게 된다.At this time, since the radical concentration distribution of the edge point of the floating gate 44 is relatively higher than that of the surroundings, the radical concentration distribution is etched faster, so that the peak point of the edge of the floating gate 44 is relaxed.
그리고, 세정(Cleaning) 공정을 실시하여 본 발명의 플레쉬 메모리 소자를 완성한다.Then, a cleaning process is performed to complete the flash memory device of the present invention.
상기와 같은 본 발명의 플레쉬 메모리 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the flash memory device of the present invention as described above has the following effects.
첫째, 플로팅 게이트 에지부의 첨점을 제거하여 전하의 손실을 방지할 수 있으므로 문턱 전압의 변화를 방지하여 소자의 신뢰성을 향상시킬 수 있다.First, since the loss of electric charge can be prevented by removing the tip of the floating gate edge, the reliability of the device can be improved by preventing the change of the threshold voltage.
둘째, 바이어스 전원을 인가하지 않은 상태에서 플로팅 게이트 에지부의 첨점을 제거하므로 하부 레이어에 대한 플라즈마 데미지를 줄이어 소자의 특성을 향상시킬 수 있다.Second, since the peaks of the floating gate edges are removed while the bias power is not applied, the characteristics of the device may be improved by reducing plasma damage to the lower layer.
셋째, 플로팅 게이트 에지부의 첨점을 제거하여 단차를 완화시킬 수 있으므로 후속 공정의 난이도 및 불량을 줄일 수 있다.Third, since the step difference can be alleviated by removing the cusps of the floating gate edge part, it is possible to reduce the difficulty and the defect of the subsequent process.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000080222A KR20020050918A (en) | 2000-12-22 | 2000-12-22 | Method for Fabricating of Flash Memory Device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020000080222A KR20020050918A (en) | 2000-12-22 | 2000-12-22 | Method for Fabricating of Flash Memory Device |
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| KR20020050918A true KR20020050918A (en) | 2002-06-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7842570B2 (en) | 2007-06-14 | 2010-11-30 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of manufacturing the same |
| US7968407B2 (en) | 2007-06-14 | 2011-06-28 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor memory devices |
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2000
- 2000-12-22 KR KR1020000080222A patent/KR20020050918A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7842570B2 (en) | 2007-06-14 | 2010-11-30 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of manufacturing the same |
| US7968407B2 (en) | 2007-06-14 | 2011-06-28 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor memory devices |
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