JPH04199517A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To independently set distances between a gate electrode and a source electrode or a drain electrode by forming a dummy gate comprising upper and lower layer parts and performing a predetermined amount of etching on a side of the lower layer part. CONSTITUTION:A dummy gate comprising an Ni layer 5 as an upper layer and an SiO2 film as a lower layer is formed. An etching mask 6 is formed on one of widthwise sides of the dummy gate and only the lower layer 4 is subjected to a predetermined amount of etching while ion implantation is performed with the upper layer 5 as a mask to form regions 7, 8 with highly concentrated impurities on semiconductor layers on both sides adjacent widthwise to the dummy gate. Further a gate electrode 9 with a shape of the lower layer 4 transferred is formed, and a source electrode 10 and a drain electrode 11 are formed on the respective highly concentrated impurity regions 7, 8. Thus distances between the gate and the drain and between the gate and the source can be independently set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applicable to field effect transistors (hereinafter also referred to as FETs), such as GaAs MESFETs.
Regarding the manufacturing method.

[Prior Art] GaAs MESFET is a promising semiconductor device as a device that can operate at high frequencies, but in order to improve its performance, shortening of the gate length is required. ing. However, it is difficult to make the gate electrode have a short gate length and precisely align the patterns of the gate electrode with the short gate length and the source and drain electrodes.

As a conventional manufacturing method for this, for example, a self-line method is used. In this method, a gate electrode is first formed, and high impurity concentration regions in the source and drain electrode portions are formed by ion implantation using the gate electrode as a mask. In this method, in order to prevent the area under the gate electrode from overlapping with the high impurity concentration region, side walls are provided on both side walls of the gate electrode, or the gate electrode is made of a two-layer metal film, and ion implantation is performed. It is known that after forming a high impurity concentration region, both side walls of the lower metal film of the two layers are selectively etched by a required amount.

[Problems to be Solved by the Invention] In the case of power amplification FETs, etc., in order to improve the source-drain breakdown voltage, it is possible to increase the gate-drain distance without unnecessarily increasing the gate-source distance and increasing the source resistance. You may want to increase the distance between them. However, in the conventional manufacturing method, the distance between the gate and the drain and the distance between the gate and the source become equal, and it is not possible to set the two independently.

One possible solution to this problem is to implant ions from diagonally above the source region side of the gate electrode to make the gate-drain distance longer than the gate-source distance. In this case, the arrangement of each FET on the same substrate is limited. In particular, in the case of a power FET with a comb-shaped structure, the source electrode and drain electrode are arranged alternately with respect to multiple gate electrodes, so the above-mentioned ion implantation method from above in an oblique direction should not be adopted. I can't.

Therefore, the present invention makes it possible to independently set the gate-drain and gate-source distances, shorten the gate length to less than the line width that can be created by photolithography, and furthermore provide process freedom. An object of the present invention is to provide a method for manufacturing a field effect transistor with high performance.

[Means for Solving the Problems] In order to solve the above problems, the present invention includes (a) forming a dummy gate portion having a predetermined width consisting of an upper layer portion and a lower layer portion on a semiconductor layer having a predetermined impurity concentration; The first step,
(b) a second step of forming an etching mask on one side of the dummy gate portion in the width direction and selectively etching only the lower layer portion by a predetermined amount; (c) performing ion implantation using the upper layer portion as a mask; (d) a fourth step of forming a gate electrode having the shape of the lower layer portion transferred thereto; (d) a fourth step of forming a gate electrode having the shape of the lower layer portion transferred thereto; , (e) a fifth step of forming a source electrode and a drain electrode on each of the high impurity concentration regions.

Desirably, the upper layer part of the dummy gate part is made of an insulator, and the lower layer part is made of metal.

A resist layer is used as an etching mask in the second step, and after selectively etching the lower layer, the etching mask is removed. After that, or in advance, both sides of the lower layer are etched by the same predetermined amount.

The third step of performing ion implantation may be performed before the second step. Activation annealing is performed after ion implantation. During annealing, an insulating film such as SiN is formed as a cap layer. Alternatively, such a cap layer is formed on the semiconductor layer before the first step.

As a method of transferring the shape of the lower layer of the dummy gate to the gate electrode, a resist layer with an opening in a region corresponding to the lower layer is provided, a conductive layer that will become the gate electrode is formed on the entire surface, and finally the resist layer is Transfer is performed by removing.

[Operation] The distance between the gate electrode and the source or drain electrode can be set independently depending on the amount of etching on the side surface of the lower layer of the dummy gate. Furthermore, by forming a gate electrode by transferring the shape of this lower layer, the gate length can be made shorter than the line width that can be created by photolithography. Furthermore, by using a dummy gate, the degree of freedom in the process (eg, etching solution, etc.) is increased, and the gate electrode is not exposed during annealing after ion implantation.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the manufacturing process of an embodiment of the present invention.

In the following description, each item symbol (a) to (f) corresponds to each item (a) to (f) in FIG. 1, respectively.

Q) Semi-insulating GaAs with a resistivity of 107 Ω and above the level of cracking
29 Si on substrate 1 at 80 keV, 6X1, 0'
After ion implantation under 2an-2 conditions, a SiNx film 3 is deposited as a first insulating film to a thickness of approximately 1500 nm on the substrate surface by plasma CVD.

5iNy and the film 3 as a cap layer, heat treatment is performed at 820° C. and 101n in an N 2 atmosphere in an electric furnace to form an active layer 2 that will become a channel layer. Next, a 5i02 film 4 was deposited at 200 OA by sputtering as a second insulating film.
Ni layer 5 having a predetermined width of about 1 μm is formed thereon by vapor deposition and a normal lift-off method.

The width of this N1 layer 5 corresponds to the distance between the drain and source of the FET to be manufactured.

(b) The S'i02 film 4 is etched by reactive ion etching using CF4 gas. In the etching, the amount of side etching of the 5i02 film 4 under the Ni layer 5 was 0.
Repeat until the thickness is 1 μm. As a result, a dummy gate section is formed in which the Ni layer 5 is the upper layer and the Si 02 film 4 is the lower layer. At this time, the amount of side etching of the 5i02 film 4 described above corresponds to the gate-source distance.

(c) One side surface of the dummy gate portion in the width direction, that is, the source side surface is covered with a resist mask 6 using a normal photolithography technique. Side etching is performed only on the drain side of the 5i02 film 4 by reactive ion etching using CF4 gas. The side etch amount is
In addition to the above side etching amount of 0.1 μm, the total amount is 0.3
Repeat until it reaches μm. This total amount of side etching corresponds to the gate-drain distance. In this reactive ion etching, the first insulating film, SiNx
The film 3 and the second insulating film S i 02 film 4 are approximately 1
:10, the SiNx film 3 is not entirely etched and the surface of the GaAs substrate is not exposed.

(d) After removing the resist mask 6, using the dummy gate as a mask, apply 29Si at 200keV, 3x1, 0''
After ion implantation under am-2 conditions, the N i N 5 is removed with a FeCl3 solution, and then heat treatment is performed in the electric furnace described above to form n1 high impurity concentration regions 7. on both sides adjacent to the width direction of the dummy gate portion. form 8.

(e) After coating the entire surface with the resist, the resist is etched using the 02 plasma etching method until the surface of the 5i02 film 4 is exposed. After this, the 5i02 film 4 was etched by reactive ion etching using CF4 gas.
Then, the SiNx film 3 is etched to form an opening corresponding to the lower layer portion of the dummy gate portion in the resist. Next, T i /Al is deposited, and a gate electrode 9 is formed on the active layer 2 by a lift-off method.

(f) Using ordinary photolithography technology, areas other than the ohmic area are covered with resist, and SiN is etched by reactive ion etching using CF4 gas.
The X film 3 is selectively removed. Next, a source electrode 10 and a drain electrode 11 each made of an AuGe/Ni/Au film are formed on the n+ high impurity concentration region 7.8 by vapor deposition and a lift-off method.

As described above, according to the manufacturing method of this embodiment, the distance between the gel electrode 9 and the source electrode 10 and the distance between the gate electrode 9 and the drain electrode 11 can be set independently. In addition, it is possible to set the inter-gate withstand voltage and the gate-drain withstand voltage to desired values, and avoid unnecessary increases in source resistance. Furthermore, by forming the gate electrode 9 by transferring the shape of the lower layer of the dummy gate part, it is possible to shorten the gate length compared to the line width that can be created by photolithography. Furthermore, since the dummy gate portion is used, the degree of freedom in the process is increased, and the gate electrode is not exposed to annealing after ion implantation, increasing the selectivity of the metal for the gate electrode.

Next, another method of transferring the shape of the lower layer of the dummy gate section will be explained.

FIG. 2 shows a first example of another transfer method.

On the 5iNX film 3, the 5i
After leaving the 02 film 4 (FIG. 2Q)), a thin metal film 12 is formed on the entire surface (FIG. 2(b)).

Selectively etching and lifting off the SiO2 film 4,
An opening corresponding to the shape of the 5i02 film 4 is formed in the metal film 12 (FIG. 2(c)). Using the metal film 12 as a mask, the 5iNy film 3 is etched to open by reactive ion etching (Fig. 2, (e)), T i /A.
A gate electrode 9 is formed on the active layer 2 by depositing a gate metal such as f() and etching and lifting off the SiNx film 3 (FIGS. 12(f) and (g)).

FIG. 3 shows a second example of another transfer method.

In this method, the 5f02 film 4, which is the lower layer of the dummy gate part, is formed directly on the active layer 2 of the GaAs substrate (FIG. 3(a)). Next, apply a thin resist or 5i0 to the entire surface.
3(b)),
The S i 02 film 4 is etched and lifted off, and an opening corresponding to the shape of the 5i 02 film 4 is formed in the thin resist or insulating film 13 .

Thereafter, a gate electrode is formed on the active layer 2 in the same manner as in the steps (e) to (g) in FIG.

[Effects of the Invention] As explained above, according to the present invention, the distance between the gate and the drain and the distance between the gate and the source can be independently controlled by the amount of etching on the side surface of the lower layer of the dummy gate section consisting of the upper layer and the lower layer. Furthermore, by forming the gate electrode by transferring the shape of the lower layer, the gate length can be shortened to a line width that can be created by photolithography. Further, by using the dummy gate portion, the degree of freedom in the process is increased, and the gate electrode is not exposed to annealing treatment after ion implantation, so that the selectivity of the metal for the gate electrode can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a process diagram for explaining one embodiment of the method for manufacturing a field effect transistor according to the present invention, and FIGS. 2 and 3 are diagrams for explaining another method of transferring the lower layer of the dummy gate part. It is a process diagram. a semi-insulating GaAs substrate, 2: active layer, 4: 5i02 film that will be the lower layer of the dummy gate section, 5: Ni layer that will be the upper layer of the dummy gate section, 6: resist mask (etching mask), 7.8 :01 High impurity concentration region, 9: Gate electrode, 10: Source electrode, 11 Nidrain electrode.

Claims (1)

[Scope of Claims] (a) a first step of forming a dummy gate portion having a predetermined width, consisting of an upper layer portion and a lower layer portion, on a semiconductor layer having a predetermined impurity concentration; (b) width of the dummy gate portion; a second step of forming an etching mask on one side in the direction and selectively etching only the lower layer portion by a predetermined amount; (c) performing ion implantation using the upper layer portion as a mask to improve the width direction of the dummy gate portion; a third step of forming high impurity concentration regions in the semiconductor layer on both sides adjacent to the semiconductor layer; (d) a fourth step of forming a gate electrode having the shape of the lower layer portion transferred; (e) each of the high impurity concentrations. A method for manufacturing a field effect transistor, comprising a fifth step of forming a source electrode and a drain electrode on the region.