JPH06204254A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a self-alignment type field-effect transistor having a high- gate-drain breakdown strength. CONSTITUTION:A recess 20 is formed and thereafter, N-type layers 7 are formed by an ion implantation 30, a high-melting point metal film, such as a tungsten film, is selectively made to deposit on an N-type layer 4 to form a gate electrode 5, an insulating film 6 is formed on the sidewalls of the electrode 5 and N<-> layers 7 and N<+> layers 8 are respectively formed on the sides of the layer 4 and outwards of the layers 7 by the oblique ion implantation 30. Thereby, a field-effect transistor having a high gate-drain breakdown strength can be stably obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor formed in a self-aligned manner.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a conventional method for manufacturing a field effect transistor of a compound semiconductor which is formed in a self-aligned manner. In the figure, 1 is a GaAs substrate and 4 is an impurity concentration of about 1.5.times.10. An n layer (impurity concentration layer to be a channel layer) having a thickness of ¹⁷ cm ^-3 and a thickness of about 0.15 μm, 5 is a gate electrode,
Reference numeral 15 is a photoresist, 16 is a resist, 8 is an n + layer (high impurity concentration layer) having an impurity concentration of about 2 × 10 ¹⁷ cm ^-3 and a film thickness of about 0.4 μm, and 9 is a source / drain electrode.

A conventional manufacturing method will be described below. First, as shown in FIG. 5A, an n layer 4 is formed on the surface of a GaAs substrate 1 by an ion implantation method, a refractory metal such as WSi5 is deposited by a sputtering method, and a photoresist 15 is formed by a transfer technique. Patterning is performed, anisotropic etching of the WSi 5 is performed by the RIE method or the like using the photoresist 15 as a mask, and the resist 15 is removed to form the gate electrode 5.

Next, as shown in FIG. 5B, the resist 16 is patterned by a transfer technique so that the source-gate region is opened, and the gate electrode 5 and the resist 1 are patterned.
Ion implantation is performed by using 6 as a mask to form an n + layer 8 which becomes a source region in a self-aligned manner with respect to the gate electrode 5.

Next, as shown in FIG. 5C, a source electrode and a drain electrode 9 are formed on the n + layer 8 and the n layer 4, respectively, by vapor deposition and lift-off.

[0006]

The conventional field effect transistor has been manufactured as described above.
Since the n layer 4 having a high impurity concentration exists between the drains,
It was not possible to obtain a field effect transistor having a high gate / drain breakdown voltage.

Further, in order to improve the characteristics of the field effect transistor, it is necessary to shorten the gate length.
It is necessary to make the layer thinner and to have a higher concentration, which causes a problem that the breakdown voltage of the gate / drain becomes lower.

The present invention has been made to solve the above problems, and provides a method for manufacturing a field effect transistor having a higher gate / drain breakdown voltage and capable of being formed in a self-aligned manner. It is an object.

[0009]

In the method of manufacturing a field effect transistor according to the present invention, a step of forming an impurity concentration layer (n layer) to be a channel layer only in a region immediately below a gate electrode after forming a recess. And, after forming a gate electrode thereon, a low impurity concentration layer (n-layer) beside the n layer in a self-aligned manner with respect to the n layer, and a high impurity concentration layer (n + layer) outside thereof. And a step of forming.

Further, according to the present invention, after forming the n + layer, a step of patterning a resist by a transfer technique so as to open only the gate / source region, and using the resist as a mask, only the region between the gate and the source is subjected to ion implantation. High impurity concentration layer (n + layer) with higher concentration than the drain side by implantation
And a step of forming.

Further, according to the present invention, after forming the n + layer, a step of patterning a resist having a desired opening only in a region between the gate and the drain by a transfer technique, and using the resist as a mask, the recess is formed. And a step of forming a shallow second recess.

Further, according to the present invention, after the step of forming the gate electrode in the above-mentioned first invention, a resist having a desired opening portion is formed only in a region between the gate and the drain by a transfer technique, and the resist is used as a mask. A step of forming a second recess shallower than the above recess, a step of depositing an insulating film on the entire surface after removing the resist, and leaving an insulating film only on the side wall of the gate electrode by anisotropic etching; Patterning is performed so that only the region between the gate and drain is opened, and the high impurity concentration layer (n +
Layer) and after removing the resist, the resist is patterned by a transfer technique so that only the gate-source region is opened, and the side portion of the n layer is formed by oblique ion implantation using the resist as a mask. And on the outside,
And a step of forming at most an impurity concentration layer (n ++ layer) having a higher concentration than the n + layer.

[0013]

According to the present invention, in any of the above methods, the insulating film formed on the side portion of the gate electrode is used as a mask,
By performing the oblique ion implantation, the n − layer is formed next to the n layer in a self-aligned manner, so that a field effect transistor having a high gate / drain breakdown voltage can be stably obtained.

[0014]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a method of manufacturing a field effect transistor according to a first embodiment of the present invention in the order of steps. In the figure, 1 is a GaAs substrate, 2 is a film thickness of about 0.
1 μm insulating film, 3 is resist, 4 is impurity concentration about 1.
An impurity concentration layer (n layer) 5 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.15 μm, which is a gate metal, 6 is SiO 2,
2 Insulating film, 7 has an impurity concentration of about 1.2 to 1.5 × 10 ¹⁷ cm
^-3 , low impurity concentration layer (n-layer) with a film thickness of about 0.4 cm, 8
Is a high impurity concentration layer (n + layer) having an impurity concentration of about 2 × 10 ¹⁷ cm ^-3 and a film thickness of about 0.4 μm, 9 is a source / drain electrode,
20 is a recess having a depth of about 0.4 μm and a width of about 0.7 μm, 3
0 is ion implantation. In addition, the gate electrode 5 and the source,
The distance between the drain electrodes 9 is about 1.5 μm.

Next, the manufacturing method of this embodiment will be described. First, as shown in FIG. 1A, an insulating film 2 having a thickness of about 0.1 μm is deposited on the entire surface of a GaAs substrate 1 by plasma CVD, and then a resist 3 having a desired opening is patterned by a transfer technique. Then, the insulating film 2 and the GaAs substrate 1 are etched by anisotropic etching such as RIE using the resist 3 having the opening as a mask to form a recess 20 having a depth of about 0.4 μm and a width of about 0.7 μm. Form. Then, after that, the ion implantation energy in the recess 20 is 50 KeV, and the dose amount is about 1 ×.
10 ¹³ is implanted with at cm ^-2, an impurity concentration of about 1.5 ×
An n layer 4 having a thickness of 10 ¹⁷ cm ⁻³ and a thickness of about 0.15 μm is formed.

Next, as shown in FIG. 1B, after removing the resist 3, a refractory metal 5 such as tungsten (W) is selectively deposited only on the n layer 4 by a CVD method or the like. After forming the gate electrode 5, the insulating film 2 is removed, then the insulating film 6 is deposited on the entire surface by the CVD method or the like, and the entire surface is etched by the RIE method or the like to form the insulating film only on the side wall of the gate electrode. Leave 6

Next, as shown in FIG. 1C, with the gate electrode 5 and the insulating film 6 as a mask, oblique ion implantation 30 is performed in the direction of the arrow in the figure, and ion implantation energy is 350 Ke.
V and a dose amount of 7 × 10 ¹² cm ⁻² are used to form an n − layer 7 beside the n layer 4 and, in the figure, n
-In the direction in which the interface between the layer 7 and the n + layer 8 is formed, the ion implantation energy is 350 KeV and the dose is 1.2 × 10 ¹³ cm.
By performing ion implantation with ^-2 , an n + layer 8 is formed next to the n- layer 7. Next, as shown in FIG. 1D, the source and drain electrodes 9 are formed on the n + layers 8 on both sides of the gate electrode 5 by vapor deposition, lift-off method or the like.

In the method for manufacturing the field effect transistor of the first embodiment as described above, after forming the recess, the n layer 4 is formed only in the region immediately below the gate electrode, and the gate electrode 5 is formed thereon. , Beside the n-layer, in a self-aligned manner with respect to the n-layer 4, by the oblique ion implantation, a low concentration n- layer 7
Thus, a field effect transistor having a high gate / drain breakdown voltage can be stably obtained.

Example 2. FIG. 2 shows a method of manufacturing a field effect transistor according to a second embodiment of the present invention. In the figure, 4, 5, 6, 7, and 8 are the same as those in the above-mentioned Embodiment 1, 10 is a resist, and 11 is a resist. Is an impurity concentration of about 5 × 10 ¹⁷
cm ^-3 n + layer (high impurity concentration layer), 40 is resist 1
Ion implantation is performed by using 0 as a mask.

In the second embodiment, as shown in FIG. 1 (c), after oblique ion implantation 30 for forming the n- layer 7 and ion implantation for forming the n + layer 8, As shown in FIG. 2, the resist 10 is patterned by a transfer technique so as to open only the region between the gate and the source,
Using the resist 10 as a mask, the ion implantation 40 is performed with 350 KeV and a dose amount of 2.8 × 10 ¹³ cm ⁻² .
By forming the n + layer 11 having a higher concentration than the n + layer 8 on the drain side only in the gate-source region, the resistance between the gate and source can be reduced. Therefore, this makes it possible to obtain a field effect transistor having a high gate-drain breakdown voltage and a low source resistance.

Example 3. FIG. 3 shows a method for manufacturing a field effect transistor according to a third embodiment of the present invention. In the figure, 4, 5, 6, 7 and 8 are the same as those in the above-mentioned embodiment 1, 19 is a resist, Is a second recess formed with the resist 19 as a mask following the first recess 20 and having a shallow depth, that is, a depth of about 0.2 μm and a width of about 0.8 μm.

In the third embodiment, as shown in FIG. 3, a resist 19 having an opening having a desired size between the gate and the drain is patterned by a transfer technique,
The GaAs substrate 1 is etched by using the resist 19 as a mask and is shallower than the first recess 20 and has a depth of about 0.2 μm.
The second recess 17 having a width of m and a width of 0.8 μm is formed.

In the third embodiment, the second recess 1
By forming 7 between the gate and the drain, a field effect transistor having a high breakdown voltage between the gate and the drain can be obtained.

Example 4. FIG. 4 shows a method of manufacturing a field effect transistor according to a fourth embodiment of the present invention. In the figure, 4, 7, 8 and 11 are the same as those of the first and second embodiments, and 12, 12, 13 are Each is a resist, 1
Reference numeral 8 denotes a second recess having a depth of about 0.2 μm and a width of about 0.8 μm formed on the side portion of the gate electrode 5 using the resist 12 as a mask.

In the fourth embodiment, first, as shown in FIG. 4A, after forming the gate electrode 5, the resist 1 is formed by a transfer technique so that the gate-drain region is opened.
After patterning 2, the GaAs substrate 1 is etched to have a shallow depth, a depth of about 0.2 μm, and a width of 0.8 μm.
A second recess 18 is formed.

Next, as shown in FIG. 4B, the resist 1
After removing 2, the insulating film is deposited on the entire surface by plasma CVD, and anisotropic etching such as RIE is performed.
The insulating film 6 is left only on the side wall of the gate electrode 5.

Next, as shown in FIG. 4C, a resist 1 is formed by a transfer technique so that the gate and drain regions are opened.
3 is patterned, and the n − layer 7 is formed on the side of the n layer 4 on the drain side by oblique ion implantation using the resist 13 as a mask.
, An n + layer 8 is formed on the outer side of the resist, and the resist 13 is removed.

Next, as shown in FIG. 4D, a resist 14 is formed by a transfer technique so that the gate and source regions are opened.
Patterning is performed, and by oblique ion implantation using the resist 14 as a mask, n is formed on the side portion of the n layer 4 and outside thereof.
+ Layer 11 is formed.

In the fourth embodiment as described above, the second recess 18 is provided between the gate and the drain, and the n- layer 7 is formed.
As a result, the field effect transistor having a high breakdown voltage between the gate and the drain can be obtained.

[0030]

As described above, according to the method of manufacturing the field effect transistor of the present invention, after forming the recess, the n layer is formed only in the region immediately below the gate electrode, and the gate electrode is formed thereon. After the formation, a low concentration n- layer is formed beside the n layer in a self-aligned manner with respect to the n layer, and an n + layer is further formed on the side of the n layer, which deteriorates the transistor characteristics. In this way, it is possible to stably obtain a field effect transistor having a high gate / drain breakdown voltage.

After the n + layer is formed, the resist is patterned by the transfer technique so that only the gate / source regions are opened to form the high-concentration n + layer only on the source side. There is an effect that a field effect transistor having a high gate / drain breakdown voltage can be stably obtained without deteriorating.

After forming the n + layer, patterning of a resist having a desired opening only in the region between the gate and the drain is performed by a transfer technique to form a second recess following the first recess on the drain side. Therefore, there is an effect that a field effect transistor having a high gate / drain breakdown voltage can be stably obtained without deteriorating the transistor characteristics.

After forming the gate electrode, patterning of a resist having a desired opening only in the region between the gate and the drain is performed by a transfer technique, and a second recess shallower than the above recess is formed using the resist as a mask. After the resist is removed, an insulating film is deposited on the entire surface, and the insulating film is left only on the side wall of the gate electrode by anisotropic etching. A transfer technique is used to open only the gate-drain region. Patterning the resist on the surface of the n-layer and the n + layer on the side of the n-layer by oblique ion implantation using the resist as a mask, and after removing the resist, a gate-source region is formed by a transfer technique. Pattern the resist so that it opens only,
By oblique ion implantation using the resist as a mask, the n + layer on the drain side is formed on the side of the n layer on the source side and outside thereof.
And a step of forming an n + layer having a higher concentration than the layer,
Again, there is an effect that it is possible to stably obtain a field effect transistor having a high gate / drain breakdown voltage and a low source resistance without deteriorating the transistor characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a method of manufacturing a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a method for manufacturing a field effect transistor according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a method of manufacturing a field effect transistor according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional field effect transistor.

[Explanation of symbols]

 1 GaAs substrate 2 Insulating film 3 Photoresist 4 Impurity concentration layer (n layer) to be a channel layer 5 Gate electrode 6 Insulating film 7 Low impurity concentration layer (n- layer) 8 High impurity concentration layer (n + layer) 9 Source and drain Electrode 10 Photoresist 11 High-concentration n + layer 12 Photoresist 13 Photoresist 14 Photoresist 15 Photoresist 16 Photoresist 17 Second recess 18 Second recess 19 Photoresist 20 Recess 30 Ion implantation 40 Ion implantation

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[Procedure amendment]

[Submission date] October 15, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

Next, as shown in FIG. 5B, the resist 16 is patterned by a transfer technique so that the source-gate region is opened, and the gate electrode 5 and the resist 1 are patterned.
After performing ion implantation using 6 as a mask , annealing is performed,
An n + layer 8 serving as a source region is formed in a self-aligned manner with respect to the gate electrode 5.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a method of manufacturing a field effect transistor according to a first embodiment of the present invention in the order of steps. In the figure, 1 is a GaAs substrate, 2 is a film thickness of about 0.
1 μm insulating film, 3 is resist, 4 is impurity concentration about 1.
An impurity concentration layer (n layer) 5 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.15 μm, which is a gate metal, 6 is SiO 2,
2 Insulating film, 7 has an impurity concentration of about 1.2 to 1.5 × 10 ¹⁷ cm
^-3 , low impurity concentration layer (n-layer) with a film thickness of about 0.4 μm , 8
Is a high impurity concentration layer (n + layer) having an impurity concentration of about 2 × 10 ¹⁷ cm ^-3 and a film thickness of about 0.4 μm, 9 is a source / drain electrode,
20 is a recess having a depth of about 0.4 μm and a width of about 0.7 μm, 3
0 is ion implantation. In addition, the gate electrode 5 and the source,
The distance between the drain electrodes 9 is about 1.5 μm.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

Next, as shown in FIG. 1C, with the gate electrode 5 and the insulating film 6 as a mask, oblique ion implantation 30 is performed in the direction of the arrow in the figure, and ion implantation energy is 350 Ke.
V and a dose amount of 7 × 10 ¹² cm ⁻² are used to form an n − layer 7 beside the n layer 4 and, in the figure, n
-In the direction in which the interface between the layer 7 and the n + layer 8 is formed, the ion implantation energy is 350 KeV and the dose is 1.2 × 10 ¹³ cm.
Ion implantation is performed with ^-2 and annealing is performed to form an n + layer 8 beside the n- layer 7. Next, FIG.
As shown in (d), the source and drain electrodes 9 are formed on the n + layers 8 on both sides of the gate electrode 5 by vapor deposition, lift-off method or the like.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

Example 4. Figure 4 shows a method for manufacturing a field effect transistor according to the fourth embodiment of the present invention. In the figure, 4,7,8,11 have the same meanings as those in Examples 1 and 2, 12 and 13, 14 Each is a resist, 1
Reference numeral 8 denotes a second recess having a depth of about 0.2 μm and a width of about 0.8 μm formed on the side portion of the gate electrode 5 using the resist 12 as a mask.

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (4)

[Claims] 1. An insulating film is deposited on the entire surface of a semi-insulating GaAs substrate, a resist having a desired opening is patterned, and the insulating film and the GaAs substrate are etched by anisotropic etching using the resist as a mask. A step of forming a recess, a step of forming an impurity concentration layer to be a channel layer by ion implantation using the resist as a mask, and a step of selectively removing refractory metal such as tungsten by CVD method after removing the resist. And the step of forming the gate electrode, and after removing the insulating film, the insulating film is deposited on the entire surface, and then the insulating film is etched back by anisotropic etching to form only the side wall of the gate electrode. The step of leaving the insulating film, and the ion implantation performed obliquely with the gate electrode and the insulating film on the side wall of the gate electrode as a mask, Method of manufacturing a field effect transistor, characterized in that the low impurity concentration layer on both sides of the doped layer, and forming a high impurity concentration layer on both outside. 2. The method for manufacturing a field effect transistor according to claim 1, wherein after the high impurity concentration layer is formed, patterning of a resist is performed by a transfer technique so as to open only a gate / source region, and the resist. Forming a high impurity concentration layer having a higher concentration than the high impurity concentration layer in the gate-drain region by ion implantation only in the gate-source region with the mask as
A method of manufacturing a field effect transistor, further comprising: 3. The method for manufacturing a field effect transistor according to claim 1, wherein after forming the high impurity concentration layer, patterning a resist having a desired opening only in a gate-drain region by a transfer technique. And a step of forming a second recess, which is shallower than the above-mentioned recess, using the resist as a mask, and a method of manufacturing a field effect transistor. 4. The method of manufacturing a field effect transistor according to claim 1, wherein after the step of forming the gate electrode according to claim 1, a resist having a desired opening is formed only in a gate-drain region by a transfer technique. Patterning, and using the resist as a mask to form a second recess shallower than the above-mentioned recess, and after removing the resist, an insulating film is deposited on the entire surface and anisotropic etching is applied to the side wall of the gate electrode. Only the step of leaving the insulating film and the transfer technique are used to pattern the resist so that only the region between the gate and the drain is opened, and the resist is used as a mask to perform oblique ion implantation to form a low impurity concentration layer on the drain side. A step of forming a high-concentration layer on the outside of the high-concentration layer, and removing the resist, and then using a transfer technique The resist is patterned so that only the inter-regions are opened, and by oblique ion implantation using the resist as a mask, a high impurity concentration higher than that of the high impurity concentration layer on the drain side is provided on the side of the impurity concentration and outside thereof. A method of manufacturing a field effect transistor, comprising the step of forming a layer.