JPS62204576A - Manufacture of vertical type transistor - Google Patents
Manufacture of vertical type transistorInfo
- Publication number
- JPS62204576A JPS62204576A JP4759586A JP4759586A JPS62204576A JP S62204576 A JPS62204576 A JP S62204576A JP 4759586 A JP4759586 A JP 4759586A JP 4759586 A JP4759586 A JP 4759586A JP S62204576 A JPS62204576 A JP S62204576A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- electrode
- gaas
- layer
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 5
- 150000004678 hydrides Chemical class 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910001258 titanium gold Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000003779 heat-resistant material Substances 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8122—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超高速、高周波の縦型トランジスタの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing ultra-high speed, high frequency vertical transistors.
従来の超高速、高周波の縦型トランジスタとしては、第
2図に示す二うに、単結晶11中に埋め込まnたベース
電極3によって縦方向の電流全制御するパーミアブルベ
ーストランジスタ(PBT)が知らnておジ、それは素
子の微細化に工っで電子10がエミッタ電極8からコレ
クメ電極9までを無衝突あるいは数回の散乱で走行し、
電子の走行速度とし定常状態に比べ数倍大きい値が期待
さnる。このためPBTnGaAs MESFETkし
のぐ高周波、高速デバイスとして研死開発が行なわnて
いる。As a conventional ultra-high-speed, high-frequency vertical transistor, a permable base transistor (PBT) is known, as shown in FIG. Well, that is because the electrons 10 travel from the emitter electrode 8 to the correct electrode 9 without colliding or scattering several times due to the miniaturization of the element.
The traveling speed of electrons is expected to be several times larger than in the steady state. For this reason, efforts are being made to develop it as a high-frequency, high-speed device that surpasses PBTnGaAs MESFETs.
このデバイスの動作原理はエミッタ電極8から注入さn
*電子10がコレクメ電極9に流n込む量全ベース電極
3に電圧を加え、ベース電極付近のポテンシャルを変化
させ、ベース電極3量全通過する電子の−i1’に制御
するものである。この構造において、ベースを他3.に
上部の層は動作には必−;−
要すく、ベースコレクタ間の容償?低減し、高周波、高
速性をさらに向上させる構造として第3図に示す工うな
ベース電憚3上部に半纏体層のない、縦型トランジスタ
が考えらn試作さnている。The operating principle of this device is that n is injected from the emitter electrode 8.
*The amount of electrons 10 flowing into the correct electrode 9 is applied to all the base electrodes 3, the potential near the base electrode is changed, and the amount of electrons 10 flowing into the base electrode 9 is controlled to -i1'. In this structure, the base is connected to the other 3. The upper layer is necessary for operation. In short, is there a compensation between the base and collector? As a structure to further improve high frequency and high speed performance, a vertical transistor without a semi-coupled layer on the top of the base electric current 3 as shown in FIG. 3 has been considered and prototyped.
この第3図に示す構造の縦型トランジスタ全夷造する方
法としては、第4図(a3〜(e)の工程による方法が
知られている。まず、第4図(a)に示すように、第1
の半纏体層1上にエピタキシャル面長した第2の半纏体
層2をもつ基板にレジスト5奮バターニングし、次に、
第4[N(b)に示す工うに、レジスト5をマスクにド
ライエツチングにエフ第2の半纏体層2の一部全垂直に
加工し1次いで%第4図(c)に示す工うに、レジスト
’6除去する。そして、第4図(d)に示す=うに、コ
レクタ電極9、ペースII極3′(Il−セルファライ
ンで形成し、その後、第4図(e)に示すように、裏面
にエミッタ電極8全形成するものである。As a method for manufacturing the entire vertical transistor having the structure shown in FIG. 3, a method using the steps shown in FIG. 4 (a3 to (e)) is known. First, as shown in FIG. 4(a), , 1st
The substrate having the second semi-coherent layer 2 with an epitaxial surface length on the semi-coherent layer 1 is patterned with resist 5 times, and then,
4. In the process shown in FIG. 4(b), a part of the second semi-integrated body layer 2 is etched completely vertically by dry etching using the resist 5 as a mask. Then, in the process shown in FIG. 4(c), Remove resist '6. Then, as shown in FIG. 4(d), the collector electrode 9 and the pace II electrode 3' (Il-Self-line) are formed, and then, as shown in FIG. 4(e), the emitter electrode 8 is completely formed on the back surface. It is something that forms.
また、もう1つの方法としては第5図(a)〜(f)に
示す工うな方法がある。まず、第5図(a)に示すLう
に、第2の半24体層を形成した第1の半纏体層の表面
にレジスト5のマスクを形成し、このレジスト5勿マス
クとして、第5図(b)に示す工うに、ドライエツチン
グし、第2の半纏体層2を垂直に加工する。次に、第5
1A (c)に示す工うに、異方性ウェットエツチング
に:す、ドライエツチングにより生じたダメージ層6t
−除去する。次いで第5図(d)に示すように、レジス
ト5を除去する。その後、第5図(e)に示すように、
コレクタ′祇働9、ベース電極10を斜め蒸着にニジ形
放し、次いで、第5図げ)に示す工うに、エミッタ電像
8を形成するものである。Another method is the method shown in FIGS. 5(a) to 5(f). First, as shown in FIG. 5(a), a mask of resist 5 is formed on the surface of the first half-body layer on which the second half-24 body layer is formed, and this resist 5 is used as a mask as shown in FIG. As shown in (b), dry etching is performed to vertically process the second semi-integrated layer 2. Next, the fifth
1A (c) shows the damaged layer 6t caused by anisotropic wet etching: dry etching.
-Remove. Next, as shown in FIG. 5(d), the resist 5 is removed. After that, as shown in FIG. 5(e),
The collector electrode 9 and the base electrode 10 are diagonally deposited in a rainbow shape, and then an emitter electric image 8 is formed as shown in FIG.
縦型トランジスタでは、縦方向に流れる電流を制御する
ためベース電極10のエッヂはこの製作方法において堀
り込んだ溝の端に接触させる心安があり、溝を垂直に加
工するか、ベース電極全科め蒸着して形成しなけ扛ばな
らない。溝を垂直にエツチングするには、異方性の高い
条件でドライエツチングを行うため、エツチング面にダ
メージ層6が形成さA、ベース1億10付近の結晶性が
劣化してしまい、良好な特性に得らnない。またダメー
ジ層6をウェットエツチングで除去すると垂直性が悪く
なり、斜め族N7Ft使用しなけnばならなくなり、ベ
ース電億幅及び厚さの制御性が恋くな9%特性が大きく
ばらついてしまう。In a vertical transistor, in order to control the current flowing in the vertical direction, the edge of the base electrode 10 can be safely brought into contact with the edge of the groove dug in this manufacturing method. It must be formed by vapor deposition. In order to vertically etch the grooves, dry etching is performed under highly anisotropic conditions, which results in the formation of a damaged layer 6 on the etched surface. I don't get it. Furthermore, if the damaged layer 6 is removed by wet etching, the perpendicularity deteriorates, making it necessary to use diagonal group N7Ft, which makes it difficult to control the base current width and thickness, and causes large variations in the 9% characteristics.
本発明の目的は、縦型トランジスタの製造方法において
、ベース電極10の形成に伴なう結晶の劣化をなくシ、
1億寸法の制御性を向上させ、高性能な縦型トランジス
タを量産性工く形成する製造方法を提供することにある
〇
〔問題点7!r:解決するための手段〕本発明の縦型ト
ラ/ンスタの製造方法は、半導体層上に耐熱性金属、絶
縁膜を積層し、エツチングにより一部全前記半導体層ま
で開口し、前記絶縁膜をマスクとして前記開口部にのみ
半導体層を成長させ、電流制御用電極と能動層を形成す
ることにより構放される。An object of the present invention is to eliminate deterioration of crystals accompanying the formation of a base electrode 10 in a method for manufacturing a vertical transistor;
The purpose is to provide a manufacturing method that improves the controllability of 100 million dimensions and allows mass production of high-performance vertical transistors.〇 [Problem 7! r: Means for Solving] In the method for manufacturing a vertical transistor/transistor of the present invention, a heat-resistant metal and an insulating film are laminated on a semiconductor layer, a part of the semiconductor layer is opened through etching, and the insulating film is A semiconductor layer is grown only in the opening using the mask as a mask, and a current control electrode and an active layer are formed, and the semiconductor layer is left open.
本発明の縦型トランジスタの製造方法は、上述したとお
り、半纏体層上に耐熱性金属及び絶縁膜を積層し、エツ
チングにより一部を前記半纏体層に至るまで開口し、そ
の後に前記絶縁膜tマスクにして前記開口部のみに半導
体層?底置させ、上記耐熱性金属を電流制御用電極とし
、成長させ九半導体#は能動層とするものである。As described above, the method for manufacturing a vertical transistor of the present invention includes laminating a heat-resistant metal and an insulating film on a semi-integrated layer, etching to open a portion of the film up to the semi-integrated layer, and then forming the insulating film. Is there a semiconductor layer only in the opening using a t mask? The heat-resistant metal is placed at the bottom and used as a current control electrode, and the grown semiconductor #9 is used as an active layer.
この工つな製造方法では、まずエツチングは反応性エツ
チングによジマスクに準じて正確に形成でき、また第2
の半導体層上には耐熱性金属層が形成さnているのでエ
ツチング条件の選択が容易となり半導体層にダメージ金
与えることは少なくなり、その後のわずかのウェットエ
ツチングにエフダメージ層を除去できる。従って電流制
御用電極の寸法、開口部寸法を精度よ<、シかも半導体
層にダメージ金与えない開口が形成できる。In this easy manufacturing method, first, the etching can be formed accurately according to the di-mask by reactive etching, and the second
Since a heat-resistant metal layer is formed on the semiconductor layer, the etching conditions can be easily selected and damage to the semiconductor layer is reduced, and the ef-damaged layer can be removed with a little wet etching thereafter. Therefore, if the dimensions of the current control electrode and the dimensions of the opening are kept accurate, it is possible to form an opening that does not cause damage to the semiconductor layer.
一方、開口部への半導体層の成長は耐熱性金属上に絶縁
膜がある九め、従来のLうに耐熱性金属のみでは、その
上層に質のよくない結晶がしばしば成長したのに対して
、本発明方法では選択性が十分あるため、良好な半導体
層が形成できる。On the other hand, the growth of a semiconductor layer in an opening requires an insulating film on a heat-resistant metal, whereas in the conventional case where only a heat-resistant metal is used, poor quality crystals often grow on the upper layer. Since the method of the present invention has sufficient selectivity, a good semiconductor layer can be formed.
次に、本発明の実施例について図面全参照して説明する
。第1図(a)〜(f)は本発明の一実施例を説明する
ために工程順に示した主要工程の素子の断面図である。Next, embodiments of the present invention will be described with reference to all the drawings. FIGS. 1(a) to 1(f) are cross-sectional views of an element in main steps shown in the order of steps to explain an embodiment of the present invention.
まず、第1図(a)に示す工うに、第1の半纏体層1で
あるn GaAs基板上にハイドライドVPE(Va
por Phase lli;pitaxy)に工り
5 X 1016cm″の第2の半導体層2のn−Ga
As k 200OA成長したウェーハを準備し、その
上面に、スパッタにより耐熱性金槁3で、後にベースt
!a−形収するタングステン(W)を30OA、ひきつ
yきCVDChemicatVapor Depos
ition )に=り絶縁膜4としてS i02全30
0OA積層する。次に第19(b)に示すように、X線
露光技術によりレジスト5を形成したのち、第1図(C
)に示すように、レジスト5をマスクとして5反応性イ
オンエツチングに工り3000A間隔W/SiO,のグ
レーティング全形成する。その後、81図(d)に示す
ように%露出してダメージ金堂けたGaAafi面をウ
ェットエッチフグにLジ300Aエツチングした後、第
1図(e)に示すように、基板温度650°Cのハイド
ライドVPEに! り 5 X 10”cm−” tD
n −GaAs k 4000ASiO,iマスクに
選択成長する。5i02を選択成長用マスクとして用い
るので選択性は十分有ジ、良質なn−GaAs層を成長
することができる。First, in the process shown in FIG. 1(a), a hydride VPE (Va
por Phase lli; pitaxy)
5 x 1016 cm" of n-Ga second semiconductor layer 2
A 200OA grown wafer is prepared, and the top surface is coated with heat-resistant Gold 3 by sputtering, and later with base T.
! A-type tungsten (W) of 30OA is applied to CVD Chemical Vapor Depos.
S i02 total 30 as insulating film 4
0OA stacking. Next, as shown in FIG. 19(b), a resist 5 is formed by X-ray exposure technology, and then as shown in FIG.
), using the resist 5 as a mask, 5 reactive ion etching is performed to completely form a grating with a spacing of 3000 A, W/SiO. Thereafter, as shown in Figure 1(d), the exposed and damaged GaAafi surface was etched with a 300A L diode using a wet etch, and then etched with hydride at a substrate temperature of 650°C as shown in Figure 1(e). To VPE! 5 x 10"cm-"tD
Selective growth is performed on an n-GaAs k 4000ASiO,i mask. Since 5i02 is used as a mask for selective growth, the selectivity is sufficient and a high quality n-GaAs layer can be grown.
次に、第1図(f)に示すように、コレクタ電極部にオ
ーミック電極全形成し、さらにその上部にTiAuを3
μm形成する。そしてコレクタ電極全マスクにして5i
Ot’r除去し、プロトンのイオン注入にエフ、コレク
タを極面下の動作層以外全絶縁分離する0また。エミッ
タ電極は裏面に形成する。このようにして製作され之縦
型トランジスタは、ベース電極の寸法は精度:く制御さ
れ、また!極付近にエツチングによるダメージもないた
め、丁ぐれt特性をもっ之縦型トランジスタが量産性:
く製作できる。Next, as shown in FIG. 1(f), an ohmic electrode is completely formed on the collector electrode part, and 3 layers of TiAu are added on top of the ohmic electrode.
μm is formed. And the entire collector electrode mask is 5i
After removing Ot'r and implanting protons, the collector is completely insulated and isolated except for the active layer below the polar surface. An emitter electrode is formed on the back surface. In the vertical transistor manufactured in this way, the dimensions of the base electrode can be precisely controlled, and! Since there is no damage caused by etching near the poles, vertical transistors with uneven T characteristics are suitable for mass production:
It can be manufactured easily.
以上説明し之工うに1本発明によれば縦型トランジスタ
の製造方法において、ベース’4極の寸法が精度=く制
御でき最適設計ができ、また成極付近に結晶の劣化がな
い定め、すぐれた特注金示す縦型トランジスタが量産性
工く製造できる0As explained above, according to the present invention, in the manufacturing method of a vertical transistor, the dimensions of the base quadrupole can be controlled with high accuracy, an optimal design can be made, and there is no deterioration of the crystal near the polarization. Custom-made vertical transistors can be easily manufactured in mass production.
第11a(a)〜(f)は本発明の一実施例を説明する
之めに工程順に示し定素子の断面図、第2図、第3図に
何れも従来の縦型FFJTの構造並びに原理説明用の模
式的断面図、第41SiJ(a)〜(e)、第5図(a
)〜(f)は何れも従来の縦型FETの製造方法全説明
する几めに工程110に示し友素子の断面図である。
1・・・・・・第1の半導体層、2・・・・・・第2の
半導体層、3・・・・・・耐熱性金属(ベースを極)、
4・・・・・・絶縁膜、5・・・・・・レジスト、6・
・・・・・ドライエツチングによるダメージ層、7・・
・・・・第3の半導体層、8・・・・・・エミッタ電極
、9・・・・・・コレクタ電極、10・・・・・・電子
。
11・・・・・・単結晶。
躬 / 図
第 7回
第 4 図
倍4図
肩左 図
第タ 口11a(a) to 11(f) are cross-sectional views of constant elements shown in the order of steps to explain one embodiment of the present invention, and FIGS. 2 and 3 each show the structure and principle of a conventional vertical FFJT. Schematic cross-sectional views for explanation, No. 41 SiJ (a) to (e), and Fig. 5 (a)
) to (f) are all cross-sectional views of a companion element shown in step 110 for the purpose of fully explaining the conventional manufacturing method of a vertical FET. 1...First semiconductor layer, 2...Second semiconductor layer, 3...Heat-resistant metal (base as pole),
4... Insulating film, 5... Resist, 6...
...Damage layer due to dry etching, 7...
...Third semiconductor layer, 8...Emitter electrode, 9...Collector electrode, 10...Electron. 11...Single crystal. Tsumugi / Figure No. 7 No. 4 Figure Double Figure 4 Shoulder Left Figure No. T Mouth
Claims (1)
により一部を前記半導体層まで開口し、前記絶縁膜をマ
スクとして前記開口部にのみ選択的に半導体層を成長さ
せ、電流制御用電極と能動層を形成することを特徴とす
る縦型トランジスタの製造方法。A heat-resistant metal and an insulating film are laminated on the semiconductor layer, a part is opened to the semiconductor layer by etching, and the semiconductor layer is selectively grown only in the opening using the insulating film as a mask, and a current control electrode is formed. A method for manufacturing a vertical transistor, comprising forming an active layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4759586A JPS62204576A (en) | 1986-03-04 | 1986-03-04 | Manufacture of vertical type transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4759586A JPS62204576A (en) | 1986-03-04 | 1986-03-04 | Manufacture of vertical type transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62204576A true JPS62204576A (en) | 1987-09-09 |
Family
ID=12779597
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4759586A Pending JPS62204576A (en) | 1986-03-04 | 1986-03-04 | Manufacture of vertical type transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62204576A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01120075A (en) * | 1987-11-02 | 1989-05-12 | Agency Of Ind Science & Technol | Semiconductor device |
JPH01222485A (en) * | 1988-03-02 | 1989-09-05 | Agency Of Ind Science & Technol | Permeable base transistor and manufacture thereof |
US5010034A (en) * | 1989-03-07 | 1991-04-23 | National Semiconductor Corporation | CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron |
WO1996012302A1 (en) * | 1994-10-17 | 1996-04-25 | Forschungszentrum Jülich GmbH | Permeable base transistor and process for the preparation thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53147472A (en) * | 1977-05-27 | 1978-12-22 | Mitsubishi Electric Corp | Production of semiconductor device |
JPS58138077A (en) * | 1982-02-10 | 1983-08-16 | Fujitsu Ltd | Semiconductor device and its manufacture |
JPS6038885A (en) * | 1983-08-11 | 1985-02-28 | Nippon Telegr & Teleph Corp <Ntt> | Vertical type field effect transistor and manufacture thereof |
JPS60251671A (en) * | 1984-05-29 | 1985-12-12 | Fujitsu Ltd | Field-effect type transistor and manufacture thereof |
-
1986
- 1986-03-04 JP JP4759586A patent/JPS62204576A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53147472A (en) * | 1977-05-27 | 1978-12-22 | Mitsubishi Electric Corp | Production of semiconductor device |
JPS58138077A (en) * | 1982-02-10 | 1983-08-16 | Fujitsu Ltd | Semiconductor device and its manufacture |
JPS6038885A (en) * | 1983-08-11 | 1985-02-28 | Nippon Telegr & Teleph Corp <Ntt> | Vertical type field effect transistor and manufacture thereof |
JPS60251671A (en) * | 1984-05-29 | 1985-12-12 | Fujitsu Ltd | Field-effect type transistor and manufacture thereof |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01120075A (en) * | 1987-11-02 | 1989-05-12 | Agency Of Ind Science & Technol | Semiconductor device |
JPH01222485A (en) * | 1988-03-02 | 1989-09-05 | Agency Of Ind Science & Technol | Permeable base transistor and manufacture thereof |
US5010034A (en) * | 1989-03-07 | 1991-04-23 | National Semiconductor Corporation | CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron |
WO1996012302A1 (en) * | 1994-10-17 | 1996-04-25 | Forschungszentrum Jülich GmbH | Permeable base transistor and process for the preparation thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS63263770A (en) | Gaas mesfet and manufacture of the same | |
JPS6351550B2 (en) | ||
JPS62204576A (en) | Manufacture of vertical type transistor | |
JP3109590B2 (en) | Method for manufacturing semiconductor device | |
JPS6237890B2 (en) | ||
JPS6323669B2 (en) | ||
JP2504785B2 (en) | Semiconductor integrated circuit and manufacturing method thereof | |
JP2776053B2 (en) | Method for manufacturing semiconductor device | |
JPS6323366A (en) | Manufacture of field-effect transistor | |
JPH06310523A (en) | Heterojunction bipolar transistor and its manufacture | |
JPH02234474A (en) | Manufacture of electronic device | |
JPS6151980A (en) | Manufacture of semiconductor device | |
JPS6239834B2 (en) | ||
JPH01117366A (en) | Manufacture of semiconductor device | |
JPS59191333A (en) | Manufacture of semiconductor device | |
JPS62171162A (en) | Manufacture of field-effect transistor | |
JPH01251659A (en) | Manufacture of hetero junction bipolar transistor | |
JP4072248B2 (en) | Manufacturing method of semiconductor device | |
JPS63152175A (en) | Manufacture of semiconductor device | |
JPH06204259A (en) | Manufacture of compound semiconductor device | |
JPH0442940A (en) | Manufacture of semiconductor device | |
JPH0797634B2 (en) | Field effect transistor and manufacturing method thereof | |
JPS6294981A (en) | Formation of electrode for semiconductor device | |
JPS60234373A (en) | Manufacture of semiconductor device | |
JPH07118483B2 (en) | Method for manufacturing compound semiconductor device |