JPH02234474A - Manufacture of electronic device - Google Patents

Abstract

PURPOSE:To facilitate a fine processing by a method wherein an undercut formed by isotropic etching is utilized. CONSTITUTION:A first layer 12 is formed on a forming surface 10. After a resist layer 14 is formed on the first layer 12, the resist layer 14 is patterned into a required pattern to form an aperture. If the first layer 12 is subjected to isotropic etching with the patterned resist layer 14 as a mask, the part of the insulating layer 12 under the resist layer 14 is etched and an undercut of a distance (d) from the aperture of the resist layer 14 is formed. The distance (d) is equal to the width of the fine line of a formed quantum interference ring. Therefore, plasma etching conditions and the thickness of the insulating layer 12 are so determined as to have the undercut distance (d) about 100-200Angstrom . With this constitution, a fine processing can be realized.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method of manufacturing electronic devices, particularly a method of manufacturing fine wire patterns and quantum interference rings, which enables microfabrication on the order of 10 to 100 people, which was previously impossible. The aim is to provide a manufacturing method, which includes a step of forming a first layer on a surface to be formed, a step of forming a resist layer on the first layer, and a patterning of the resist layer into a predetermined shape. and forming an opening using the patterned resist layer as a mask.
isotropically etching the first layer to remove an area slightly larger than the predetermined shape that extends below the resist layer, and etching the opening using the patterned resist layer as a mask. I'ftVI the second layer having the predetermined shape on the surface to be formed; removing the resist layer; and forming a gap between the second layer having the predetermined shape and the layer with the predetermined shape. depositing a thin line with a third layer on the surface to be formed, and forming a thin line with the third layer. It grows into a tree. [Field of Industrial Application] The present invention relates to a method for manufacturing electronic devices, and in particular to a method for manufacturing fine wire patterns and quantum interference rings. [Conventional technology] In recent years, as demands for higher speeds in semiconductor devices have become more severe, star interference devices that utilize quantum interference effects have begun to attract attention. In order to function as a quantum interference device, its dimensions must be smaller than the distance (coherence distance) at which electronic waves can interfere. This is because when an electron wave propagates a distance longer than this coherent ff[[Lφ, the coherence of the electron wave is lost due to inelastic scattering of electrons. Normally, the coherence length Lφ of metals and semiconductors used as propagation paths for electron waves in single-child interference devices has a strong temperature dependence, so they are operated at temperatures below the liquid helium temperature. In general, the coherence length, ILφ, is short, for example, in aluminum, it is about 0.78 to 1.47 μm at 4.5”K. In addition, in quantum interference devices, there is no elastic scattering source in the electron wave propagation path, and the electron It is desirable that the electron waves propagate ballistically, since the phase of the electron waves changes when subjected to bony collapse.According to experiments, the cross-sectional dimension of the electron wave propagation path is on the order of 100 people. It is known that when this happens, elastic scattering becomes negligible and interference effects become noticeable.

In this way, in order to manufacture a good quantum interference device, a mesoscopic scale manufacturing technology on the order of 10 to 100 people is required, which is even more elaborate than the past.

However, with the current RFL, III processing technology, 10
It is impossible to produce ~100 fine wires.

By using high-resolution electron beam exposure technology, which is the mainstream of current microfabrication technology, several hundred thin lines of less than 0.1 μm have been obtained. However, 10~
Mesoscopic scale fine processing technology on the order of 100 people has not been established. In addition, even in the X-ray exposure method, the mask used for X-ray exposure must be made using other methods such as electron beam exposure technology, and microfabrication of 0.1 to 0.2 μm or more is currently difficult. be.

Furthermore, in the focused ion beam exposure method, since the proximity effect is reduced, it is theoretically possible to perform ffi R old processing with a pattern resolution of about 0.05 to 0.01 μm, and this is expected in the future, but the current It is difficult at a technical level.

Furthermore, in optical exposure using near ultraviolet light, the pattern resolution is approximately 0.5 μm, and even if a short wavelength i-line stepper or excimer laser light source is used, the pattern resolution is approximately 0.1 μm.
It is not possible to achieve even the resolution of . [The problem that the invention aims to solve] Even if we use the current state-of-the-art microfabrication technology,
．． It was only possible to perform microfabrication of about 1 μm, and it was impossible for mesoscopic scale la, 4I machining to be performed by 10 to 100 people. The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a method for manufacturing an electronic device that enables microfabrication on the order of 10 to 100 people, which was previously impossible. [Means for Solving the Problems J The above purpose includes a step of forming a first layer on a surface to be formed;
forming a resist layer on the first layer; patterning the resist layer into a predetermined shape to provide an opening; and using the patterned resist layer as a mask, forming the first layer, etc. directional etching to remove the first layer in an area slightly larger than the predetermined shape that has penetrated below the resist layer; depositing the second layer in the predetermined shape;
removing the resist layer; and removing the second resist layer of the predetermined shape.
and a step of forming a thin line formed by the third layer by forming a thin line formed by the third layer by 111M on the surface to be formed in the gap between the layer and the third layer according to the predetermined shape. This is achieved by a method of manufacturing an electronic device characterized by the following. Therefore, it is achieved. [Operation] According to the present invention, undercuts are utilized by isotropic etching to perform y1 fine processing on the order of 10 to 100 people, exceeding the resolution limit. [Example] 1L Erligai] The method for manufacturing an electronic device according to the first example of the present invention is described in the first example.
As shown in the figure. Same figure (a1), (b1),..., (J1)
, (k) , ..., (0) is a plan view, (a2) of the same figure,
(b2),...(j2) are the same as (a1), (b1),
..., (j1) is a sectional view. In this example, a single-child interference device having a quantum interference ring made of thin metal wires will be explained as an example. A semiconductor substrate 10 made of silicon, GaAs, etc. is used as the substrate for forming the device. It is preferable not to use a narrow gap substrate. It is desirable that the resistance value of the semiconductor substrate 10 is not too low.
For example, the doping concentration is 10′7~10” cm→
It is desirable to use an n-type semiconductor substrate 10 of approximately Next, an insulating layer 12 is formed on the semiconductor substrate 10. In this embodiment, SfiN< is used as the insulation WJ12, but SfiN< is used as the insulation WJ12.
i 02 ,. It may be an insulator such as Aj N etc. Although the formed insulating layer 12 is not required to have a strict thickness, it is desirable that the insulating layer 12 has a thickness that can be appropriately etched by plasma etching, which will be described later. In this example, 300 people
The number of participants will be approximately 1,000. Next, a resist layer 14 is coated on the insulation 112. In this example, a positive type resist called AZ (manufactured by Shigley Co., Ltd. m!+) is used. The thickness is preferably 500 to 1 μm. After coating, baking is performed at approximately 100° C. to harden the resist layer 14. This improves the sharpness of the pattern in the subsequent phosphorography process and improves the resistance in the dry etching process. Next, the resist layer 14 is patterned into a predetermined shape using a lithography technique. Determine the patterning shape so that the outer shape follows the thin line to be formed. For example, when forming a quantum interference ring with an outer diameter of 0.5 to 1.0 μm and a thin line width of approximately 100 to 200 mm as in this embodiment, the resist 1 and layer 14 are formed of a positive resist. So,
A circular opening of 0.5 to 1.0 μm should be provided (Fig. 1 (aIHa2)). Note that the resist layer 14
If it is a negative resist, it is sufficient to form an inverted pattern. The patterning of the resist layer 14 is performed by electron beam exposure, x
Either IS light or optical exposure phosphorography technology may be used. Since the outer diameter of the quantum interference ring is about 0.5 to 1.0 μm, which is the coherence length MLφ, it is desirable that the lithography pattern accuracy is about 0.1 to 0.2 μm. Next, the insulating layer 12 is dry-etched using the resist layer 14 as a mask. Plasma etching using plasma is performed as dry etching. Generally, in plasma etching, isotropic etching is performed when the plasma gas pressure is increased to about 10 to 100 Pa.
Anisotropic etching occurs when the plasma gas pressure is lowered. In addition, when the energy of plasma ions reaching the substrate is low, isotropic etching is performed, and when it is high, anisotropic etching (generally reactive ion beam etching (RI)
BE) is performed. In this example, isotropic etching is performed with high plasma gas pressure and low ion energy. When etched isotropically, as shown in FIG. 1 (b1) and (b2),
The insulating layer 12 is etched to below the resist layer 14,
Underforce y I by a distance d from the opening of the resist layer 14
'It will be done. This distance ld is the width of the thin wire of the quantum interference ring formed in this example. Therefore, the plasma etching conditions and the thickness of the insulating layer 12 are determined so that the undercut distance, ld, is about 100 to 2008. In this embodiment, the insulating layer 12 is S i s Na
It has been experimentally revealed that when using the insulating layer 12, the following relationship exists between the thickness t of the insulating layer 12 and the undercut distance iNffid. CF was introduced into a cylindrical plasma chamber at a pressure of 0.7 Torr. When plasma is generated by exciting gas with R'F power of 200 W, the thickness t of the insulating layer 12 and the undercut distance ud are as shown in the following table.

Thickness t [μm] Distance d [μm] 0.05 0.0 0.15 0.1 0.23 0.2 0134 0. '3 0.48 0.4 Furthermore, when N F s gas is used, the inside of the plasma chamber is reduced to 0.48 0.4. Make it OITorr, 50W
When excited with RFt power of 3000 Si,N. 5
It has been found that in order to side-etch only 00 people, it is sufficient to etch for 2 minutes. Based on these experimental results, the type of plasma gas, gas pressure, RF power, etching time, and thickness of the insulating layer 12 are determined so as to obtain the desired line width. Next, an insulating layer 16 is deposited by resistance heating or electron beam. Then, Fig. 1 [cI
As shown in HC2), an insulating layer 16 is formed on the semiconductor substrate 10 under the opening of the resist layer 14 and on the resist layer 14. As a result, a gap of the distance d is formed between the insulating layer 12 and the insulating layer 16 on the semiconductor substrate 10.

In this process, it is desirable to use a point-like vapor deposition source. This is to prevent the deposit from wrapping around the undercut area as much as possible. It is desirable that the insulating layer 16 has a thickness that can withstand subsequent steps and is thinner than the first formed insulating layer 12.

Insulation N! 16 is SiO, S i O2- S i-s N4, S
Materials such as iON and AJIN are preferable. Note that in electron beam evaporation, a reactive gas such as oxygen or nitrogen may be introduced to assist the formation of an insulator during evaporation. Furthermore, in resistance heating evaporation, it is possible to form an insulating layer using SiO as an evaporation source. Although spatter deposition is also possible, there is a risk that the deposit may wrap around the undercanted area. Next, the insulation/
1 16 is removed by the riff 1 off method (see Figure 1(d)
i) [d2)). Then, the insulating layer 12 and the insulating layer 16
As a result, a pattern with a narrow ring-shaped opening having a width d is formed on the semiconductor substrate 10.

Next, the semiconductor substrate that has gone through the manufacturing process up to this point is placed on the cathode in an electrolytic solution, and the metal for coating is placed on the anode and plated. Then, the ring-shaped opening is plated with a metal layer 18, and a ring 18 with a diameter of about 0.5 to 1 μm is formed with a line width of about 100 to 200 thin metal wires (
Figure 1 (eIHe2)). As the electrolytic solution for plating, for example, Temperex (manufactured by Tanaka Kikinzoku) is used. Examples of metals for plating include Au, Cu, AJ, Sn. It is possible to use a metal layer such as Nj, a high melting point metal.

It is desirable to keep the plating current density to about 4mA/cn+2 or less. Note that later on in this plating process, it is necessary to remove by etching the metal that has adhered to unnecessary parts, so it is desirable to use a metal that has strong adhesion to the semiconductor substrate 10 and is easily removed by etching.

Following the formation of the thin metal wire ring 18 of the quantum interference ring, thin metal wires for sources and drains are formed in the same manner. First, patterned resists 1 to 20 are formed so as to have an outer edge passing through the center of the ring 18 (see FIG.
f1)(f2)). Next, the insulating layers 12 and 16 are isotropically etched by plasma etching. Then, the insulating layer l2, 16 is undercut by a distance id to below the resist layer 20 (
Figure 1 (gl) (g2)).

Next, the insulating layer 22 is deposited by resistance heating or electron beam, and the insulating layer 22 is formed on the semiconductor substrate 10 under the opening of the resist layer 20 and on the resist layer 20, as shown in FIG. It is formed. As a result, a gap of distance Ud is formed between the insulating layers 12 and 16 on the semiconductor substrate 10 and the insulating layer 22. Next, the resist layer 2 is
After removing the insulating layer 22 on the 0, the gap is plated with metal using a plating method. Then, the line width is about 100-200
A rectangular ring 24 is formed by human thin metal wire (first
Figures (i1) (i2)). Next, when the insulating layers 12, 16, and 22 are removed by plasma etching or wet etching, an annular ring 18 and a rectangular ring 24 made of thin metal wires are connected to each other on the semiconductor substrate 10 as shown in FIG. 1 (jlHj2). It is made in. Next, as shown in FIG. 1(k), a mask layer 26 is formed to cover the entire annular ring 18 and the connection portion between the rectangular ring 24 and the annular ring 18 (FIG. 1(k)). The mask layer 26 may be a resist layer, a SiO2 layer, or a double layer of resist and SiO2. In addition, Figure 1 (
k) The following is only a plan view, and the annular ring 18 and the rectangular ring 24 are simply shown by one solid line. Next, using the mask layer 26 as a mask, the unexposed metal wires are removed by ion milling or plasma etching. Then, as shown in FIG. 1(1), the annular ring 18
and a thin metal wire 24s for the source and a thin metal wire 2 for the drain.
4d is formed on the semiconductor substrate 10.

For ion milling, place A in the milling chamber.
After introducing r and keeping the gas pressure at about 2 to 4 x 10' Torr and discharging it, milling is carried out by accelerating Ar at about 500 mm. Milling speed varies depending on the material. For example, for Au, approximately 550A/lIlin. About 400 people/min for GaAs. Approximately 100 people/min with sio2,
In resist, it is about 100 people/l10. The thickness of the mask layer 26 is determined in consideration of these milling speeds. Next, in this state, ion implantation is performed to make the surface layer of the semiconductor substrate 10 electrically inactive. This is semiconductor substrate 1
This is to reduce the conductivity of the 0 surface layer and relatively increase the conductivity of the thin metal wire. If the semiconductor substrate 10 is a GaAs substrate, ions of H, B, He, O, Ar, etc. may be implanted. When the semiconductor substrate 10 is a silicon substrate, O.
Ne, Ar, or the like may be ion-implanted. Ion energy is lower for lighter ions and higher for heavier ions.
It is desirable to set it to about 0 keV to IMeV. The dose ranges from lQl5 to lQl7/cl2, and the lighter the ion, the larger the amount used.
Next, approximately 50~I
OOOA thick gate insulation II! 28 (FIG. 1(1)) Next, a resist layer 30 for forming a gate electrode is formed. That is, as shown in FIG. 1(n), the mask layer 30 is opened only in a region narrower than the gate insulator 828.
form. Next, a gate electrode metal is deposited using the resist layer 30 as a mask, and the gate electrode f! 3 2 a and 32 b are formed (Fig. 1 (0)). This completes the quantum interference device. The operating principle of the quantum interference ring manufactured in this way will be explained using Fig. 2. As shown in Figure 2(a), when an electron wave is input from point A of the quantum interference ring,
At point B, the electron wave branches into an electron wave passing through path C and an electron wave passing through path D. When both electron waves merge at point E, the electron wave is generated according to the phase shift due to the difference (distance, size, scattering source) between path C and path D, and is output from point F. When a magnetic flux B directed from the front to the back of the paper is applied to this quantum interference ring as shown in Figure 2(b), the phase difference changes periodically depending on the strength of the applied magnetic field, and both ends of the ring exhibits an AB effect in which the resistance of the resistor oscillates periodically. For phase modulation, an electric field E may be applied instead of a magnetic field, and in the quantum interference ring according to this embodiment, ffif! 32a and 32b apply an electric field to the annular ring 18 for phase modulation. In this way, according to this example, it is possible to manufacture a crown interference ring using ultra-fine wire, which was impossible with conventional lamination lithography technology. The method for manufacturing an electronic device according to the second embodiment of the present invention is described in a third embodiment.
It is shown in the figure. Same figure (a1), (b1),..., (g1)
, (h) is a plan view, (a2), (b2),...
(f2) is the same figure as (a1), (b1), ..., (fl)
(g2) is a perspective view of (g1), and (g3) and (g4) are cross-sectional views showing the structure of the semiconductor layer W4 in (g1) and (g2). In this embodiment, a quantum interference device having a quantum interference ring made of semiconductor thin wires will be explained as an example.

Corresponding components are given the same reference numerals, and manufacturing steps similar to those in the first embodiment will be briefly described. As a substrate for forming a device, a GaAs substrate, an In
A semi-insulating semiconductor substrate 10 such as a P substrate is used. It is desirable that the substrate be a crystalline substrate on which a semiconductor layer can be grown epitaxially.

Next, an insulating layer 12 is formed on the semiconductor substrate 10, and then a resist 14J14 is coated on the insulating rWJ12. Next, the resist layer 14 is patterned into a predetermined shape using phosphorography technology (Fig. 3 (a1) (a2)).
). This patterning shape is different from the first embodiment in that it partially has a semicircle that is half of the quantum interference ring. Next, the insulating layer 12 is dry-etched using the resist layer 14 as a mask, and then, for example, Si.
N. 3 (bl) (b2)
).

For dry etching, high plasma gas pressure is used.
Perform plasma etching with low ion energy. As a result, the insulating layer 12 is isotropically etched, and the insulating layer 12 is etched to below the resist layer 14, as shown in FIGS. It will be cut. In the first example, this distance d was the width of the metal thin wire of the quantum interference ring, but since the semiconductor thin wire is formed in this example, the depletion occurs from both sides of the semiconductor thin wire toward the inside. will be converted into Therefore, the distance Md is set to a width that can ensure the effective width of the semiconductor thin line, taking these depletion layers into consideration. In other words, the distance 1d minus the depletion layer is approximately 100 to 20
Adjust the undercut distance Md so that there are 0 people. Furthermore, when depositing the insulating layer 16 using an electron beam, a reactive gas such as nitrogen may be introduced to assist the formation of the insulating layer 16 during the deposition process. Next, resist layer 1
The insulating layer 16 formed on 4 is removed by a lift-off method (FIG. 3 (cIHc2)). Then, a thin line-shaped opening pattern with a width d is formed on the semiconductor substrate 10 by the insulating layer 12 and the insulating layer 16. In the first actual fiber example, the openings were plated with metal at this stage to form thin metal wires, but in this example, a quantum interference ring was created by forming another opening pattern on top of this opening pattern. Mm. That is, among the aperture patterns manufactured so far, it covers a semicircular part that is a part of the quantum interference ring and exposes the other part, and includes a semicircular shape for manufacturing the remaining semicircular part of the quantum interference ring. Form a resist layer 20 patterned into a shape (Fig. 3 [61) (d2)]. Next, the insulation NJ12 and 16 are removed by plasma etching. Isotropic etching followed by deposition of an insulating layer 22 (
Figure 3 (e1) (e2)). Then, the insulating layers 12, 1
6 is undercut by a distance d below the resist layer 20, and unnecessary portions are etched away, and a gap of a distance Md is formed between the insulating layers 12, 16 on the semiconductor substrate 10 and the insulating layer 22. ．． Next, the insulating layer 2 on the resist layer 20 is removed by a lift-off method.
2 (Figure 3 (flHf2)). Then, a pattern of circular openings made of thin lines forms on the semiconductor substrate 10.
It is formed on top. Next, a semiconductor material is epitaxially grown on the semiconductor substrate 10 having a thin line-shaped opening. In this example, GaAs
Since the substrate 10 is used, MOCVD method, atomic layer epitaxy (A
When a semiconductor is grown epitaxially by a method such as LE, a semiconductor layer grows epitaxially on the exposed semiconductor substrate 10, but does not grow epitaxially on the insulating layers 12, 16, and 22. A thin line is formed. The plane of the quantum interference ring made of semiconductor thin wires is shown in Figure 3 (g1
), the same figure (Ω2) is its perspective view, and the same figure (g
3) Semiconductor layer! A specific example of R construction is shown below. Figure 3 {93)
A specific example of the semiconductor layer arrangement shown in is explained below. This semiconductor layer structure is basically a heterostructure containing a modulation dove layer or a quantum well layer using a Group 1V compound, and two-dimensional electron gas or two-dimensional hole gas is formed at the hetero interface. It is. In this example, a case will be explained in which a two-dimensional electron gas is formed using AJI GaAs/GaAs materials.
First, as shown in FIG. 3 (g3), an i-GaAs buffer layer 40 not doped with impurities and an i-GaAs active layer 42 in which a two-dimensional electron channel is formed are formed on a semiconductor substrate 10 by MOCVD or ALE. ,i-ANG
aAs spacer layer 44, n-Aj Ga supplying electrons
An n+GaAs contact layer 48 for contacting an As electron supply NJ46 and a source or drain electrode is sequentially formed. The thickness and impurity concentration of each layer can be manufactured to the same values as normal HEMTs. Then, active layer 4
A two-dimensional electron gas is formed in the second electron supply layer 461111. The A1 composition ratio X of the n-Aj GaAs electron supply layer 46 is preferably about 0.2 to 0.3. The extent to which two-dimensional electron gas is supplied from the electron supply layer 46 is basically set to a degradation mode. Note that the impurity doping area of the electron supply layer 46 is, of course, n''
Adjustment is made so that the two-dimensional electron gas is not depleted even if the GaAs contact layers 1 to 48 are removed or the gate metal layer described later is formed. Furthermore, the semiconductor layer lf4 is not limited to the one shown in FIG. 3 (Q3), and various other structures are possible. For example, a 4i structure as shown in the same figure (g4) may be used.

That is, in this structure, the i-GaAs active layer 42 is
- i-AN GaA between the GaAs buffer layer 40
This is a double heterostructure in which an n-AjGaAs electron supply layer 52 is provided with an s spacer layer 50 interposed therebetween. This makes it possible to confine the two-dimensional electron gas more strongly than in the single heterostructure shown in Figure 3 (g3). As another example of semiconductor layering, the spacer layer 44 and electron supply layer 46 shown in FIG. 3 (q2) may be provided only below the active layer 42. As shown in the plan view of Figure 3 (g1) and the perspective view of Figure 3 (g2), in an actual quantum interference ring, a semiconductor layer is formed only in the ring part and the thin source wire and thin drain wire extending from it. It will be done. , No semiconductor layer is grown except for the 4I line part because there is an insulating layer. Further, the contact layer 48 is formed only on a part of the contact portions of the thin source wire and the thin drain wire. Therefore, the surface of the electron supply layer 46 is exposed in the pond area. Note that in order to prevent oxidation, the electron supply layer 4
An n-GaAs layer (not shown) may be provided between the electron supply layer 6 and the contact layer 48, and the contact layer 48 may be removed to prevent the surface of the electron supply layer 46 from being exposed. Next, the insulating layers 12, 16, and 22 are removed by plasma etching or wet etching, and a Schottky gate electrode is added to each part of the branch path of the quantum interference ring.
A and 32b are formed to complete the R-type device (FIG. 3(h)).

In this way, according to this embodiment. A quantum interference ring with 141 semiconductor layers can be manufactured.

115 Disaster 1 The method for manufacturing an electronic device according to the third embodiment of the present invention is described in the fourth embodiment.
It is shown in the figure. Figures (a) to ff) are plan views. Although the second embodiment described above was a circular quantum interference ring, this embodiment manufactures a rectangular quantum interference ring. The basic manufacturing process is the same as that of the second embodiment except that the shape of the quantum interference ring is different, so a detailed explanation will be omitted and the pattern shape will be mainly explained.

First, a resist layer 14 having a rectangular opening as shown in FIG. 4(a) is formed on the insulating layer 12.

Next, after isotropically etching the insulating layer 12 using the resist layer 14 as a mask, the insulating layer 16 is deposited, and the unnecessary insulating layer 16 deposited on the resist layer 14 is removed by a lift-off method, as shown in FIG. f-1i1z as shown in [b)
41 rectangular aperture rings are formed. Next, a resist 1 layer 20 having a rectangular opening as shown in FIG. 4(C) is formed on the insulating layers 12 and 16. This will cover approximately half of the already formed rectangular shaped ring, leaving half of the pond exposed.

Next, using the resist layer 20 as a mask, the insulating layers 12 and 16 are
After isotropically etching, an insulating layer 22 is deposited, and the unnecessary anti-green layer 22 deposited on the resist layer 20 is removed by a lift-off method, resulting in an ultrafine vortex opening pattern as shown in FIG. 4(d). is formed.

Next, a semiconductor layer having a structure similar to that of the second embodiment is formed in this opening pattern (FIG. t1(e)).

Next, the insulating layers 12, 16, and 22 are etched away, and Schottky gate voltages are applied to each branch of the rectangular quantum interference ring. ! 3 2 a and 32 b are formed to complete the quantum interference device (FIG. 4(f)).

As described above, according to this embodiment, since the opening pattern has a rectangular shape, highly accurate pattern formation is possible, and
Pattern alignment is relatively easy. Although this embodiment has been described using a semiconductor quantum interference ring as an example, it is possible to manufacture a rectangular quantum interference ring using thin metal wires using a manufacturing method similar to that of the first embodiment. 1±Nirijufu The method for manufacturing an electronic device according to the fourth embodiment of the present invention is described in the fifth embodiment.
As shown in the figure. The same figure (b1), ..., (f1), [g),
(h) is a plan view, and (b2), ..., (f2) are cross-sectional views of (b1), ..., (f1) in the same figure. In the first to third embodiments described above, metal or semiconductor was formed in the thin line-shaped opening formed by the method of the present invention.
In this example, a semiconductor layer capable of forming a two-dimensional electron gas is formed in advance on a semiconductor substrate, a thin wire is formed on the semiconductor layer by the method of the present invention, and the m-line is used as a mask to form a semiconductor layer. By etching away the portion, a quantum interference ring of the semiconductor layer is formed.

A method of manufacturing an electronic device according to the present embodiment ρj will be described with reference to FIG. The same reference numerals are given to the same top components as in the first to third embodiments, and the explanation thereof will be omitted. First, MOCVD method, atomic layer epitaxy (ALE) is applied on the semiconductor substrate 10.
A semiconductor multilayer structure 60 similar to a HEMT in which a two-dimensional electron gas is formed is formed by epitaxially growing a semiconductor material by a method or the like (FIG. 5fa)). In this example, G
Since the aAs substrate 10 is used, an AJGaAs crystal is grown. That is, MOCV is formed on the semiconductor substrate 10.
i-G without doping impurities by D method or ALE method
an aAs buffer N62, an i-GaAs active layer 163 in which a two-dimensional electron channel is formed, an L-AJGaAs sublayer 64, and an n-AjGaAs electron supply layer 6 that supplies electrons.
5. n” for source or drain electrode contact
A GaAs contact layer 66 is sequentially formed. The thickness and impurity concentration of each layer should be the same as in a normal HEMT. Then, a two-dimensional electron gas is formed on the electron supply layer 65 side of the active layer 63. Note that the semiconductor multilayer structure 60 may be a double heterostructure as shown in FIG. 3 (g4).

Next, on the semiconductor multilayer structure 60, a thin metal wire 70 having a shape similar to that of the second embodiment, which partially has a semicircle that is half of the quantum interference ring, is formed (FIG. 5 (b1) fb2).
.

Next, a thin metal wire 72 having a shape similar to that of the second embodiment, including a semicircular shape for manufacturing the remaining semicircular portion of the quantum interference ring, is formed (FIG. 5(c1) fc2).

Subsequently, when the insulating layers 12 and 16 are removed, the structure shown in FIG. 5 (d1
) As shown in (d2), thin metal wires 70 and 72 having shapes as shown are formed on the semiconductor multilayer structure 60. Next, using the thin metal wires 70 and 72 as a mask, only the contact layer 66, which is the uppermost layer of the semiconductor multilayer structure 60, is selectively etched away (FIG. 5(e1)le2). ca
j2 When reactive ion etching is performed using F2 gas, only the contact layer 66 under the thin metal wires 70 and 72 is left, and the remaining regions are etched. Tact layer 66 is removed.

Next, when the thin metal wires 70 and 72 are removed, the electron supply layer 6
A thin line of a contact layer 66 is formed on the surface of the contact layer 5 (see FIG. 5).
f1)(f2)). When using Au or an AU alloy as the metal, use Technistrip gold as the removal liquid. When using Ti, use hydrofluoric acid < HF as the removal solution.
) is used. Next, only the portion required as a quantum interference ring is covered with a resist M (not shown), and CC. When unnecessary portions are removed by reactive ion etching using Q2F2 gas, a contact layer 66 having a shape as shown in FIG. 5(h) is formed.

Electron gas is formed in the active layer 63 only under the contact layer 66, forming a quantum interference ring.

That is, if a gate metal is provided, the contact layer 66
In a certain region, the two-dimensional electron gas becomes depletion mode, and the contact layer 66 is removed and the electron supply layer 6
It is known that the two-dimensional electron gas becomes an enhancement mode in the region where 5 is exposed. If the potential of the gate metal is set to zero, electron gas exists in the region where the contact layer 66 is present, and no electron gas exists in the region where the contact layer 66 is removed. In this embodiment, a quantum interference ring is realized by utilizing this property and leaving the contact layer 66 only in the region where electrons are to be conducted.

Finally, as shown in FIG. 5(h), the Schottky gate voltage w! is applied to each part of the branch path of the quantum interference ring. 7 4
A, 74b are formed, and source t&76 and drain electrode 78, which are ohmic electric rectangles, are formed in the thin wire portion to complete a single-child interference ring. In this way, according to this example, a quantum interference ring made of semiconductor layers can be manufactured. The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways. For example, in the above embodiment, a quantum interference ring was manufactured, but the invention is not limited to quantum interference rings, but can also be applied to the manufacture of ultra-fine wires, which were previously impossible, and devices using ultra-fine wires. Further, in the above embodiment, an undercut is used when isotropically etching the insulating layer, but any material layer may be used as long as a good undercut is produced by isotropic etching.

[Effects of the Invention] As described above, according to the present invention, since an undercut is utilized by isotropic etching, In 4m processing on the order of 10 to IOOA, which was previously impossible, becomes possible. This makes it possible to manufacture practical quantum interference devices using metals and semiconductors.

[Brief explanation of drawings]

FIG. 1 is a process diagram of a method for manufacturing an electronic device according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of the operating principle of a quantum interference ring, and FIG. FIG. 4 is a process diagram of a method for manufacturing an electronic device according to a third embodiment of the present invention. FIG. 5 is a process diagram of a method for manufacturing an electronic device according to a fourth embodiment of the present invention. This is a diagram. In the figure, 10...Semiconductor substrates 12, 16, 22...Insulating layers 14, 20...Resist layer 18...Metal layer 24...Rectangular rings 26, 30...Mask layer 28... - Gate insulating films 32a, 32b...gate electrode 40...buffer layer 42...active layer 44, 50...substrate layer 46, 52...electron supply layer 48...contact layer 0...・Semiconductor multilayer 'TJ structure 2...Buffer layer 3...Active layer 4...Spacer layer 5...Electron supply layer 6...Contact layer 0, 72...Gold 1iL thin wire 4a, 74b. . . . Gate electrode 6 . . Source electrode 8 . . . Train electrode (o1) (a2) (b1) [- (b2) F1 (c1) Manufacturing of the electronic equipment according to the first embodiment of the present invention Process diagram of the method Figure 1 (d1) (d2) (k) (e1) (e2) (Ql (m) First implementation of the present invention θ1) Electronic table 1 of 1,500,000 milligrams of manufactured sheep! Figure 1 Figure (h2) (h1) Process diagram of the electronic dragon infection of the first implementation Ij of the present invention A process diagram of the manufacturing method of electronic ogimen as a practical example (
n) (b) (C) Schematic diagram of the method of making a child according to the first implementation of the present invention. Figure 1. Illustration of the operating principle of the quantum interference ring. Figure 2 (d2). (d1) (e2) (e1) Second (b) of the present invention (d) Third real ratio A series electron positioning lie Anrofa) (b1) (b2) 70.72・・Fine Metal Wire The Fourth Invention of the Fourth Eida 91] Process diagram of the manufacturing method for electronic devices Figure 5 Figure 5 A two-step diagram of the manufacturing method for electronics and equipment of the fourth embodiment of the present invention gJ

Claims (1)

[Claims] 1. A step of forming a first layer on a surface to be formed;
forming a resist layer on the layer; patterning the resist layer into a predetermined shape to provide an opening; isotropically etching the first layer using the patterned resist layer as a mask; removing the first layer in an area slightly larger than the predetermined shape that has penetrated below the resist layer; and forming the predetermined shape on the formation surface of the opening using the patterned resist layer as a mask. a step of depositing a second layer; a step of removing the resist layer; and a step of depositing a third layer on the formed surface in a gap between the second layer having the predetermined shape and the layer with the predetermined shape. A method for manufacturing an electronic device, comprising the step of depositing the third layer to form a thin line. 2. A quantum interference ring is formed by the thin wire of the third layer formed by the method according to claim 1, and a gate is provided on each part of the quantum interference ring divided by the input and output ends of the quantum interference ring. A method of manufacturing an electronic device, the method comprising forming an electrode. 3. Forming a conductive layer for conducting charge on the substrate, and forming a thin wire on the conductive layer by the method according to claim 1,
A method for manufacturing an electronic device, characterized in that the thin wire of the conductive layer is formed by etching away at least a portion of the conductive layer using the thin wire as a mask.