CN114023641A - Manufacturing method and application of enhanced HEMT ohmic contact structure - Google Patents

Manufacturing method and application of enhanced HEMT ohmic contact structure Download PDF

Info

Publication number
CN114023641A
CN114023641A CN202111305214.6A CN202111305214A CN114023641A CN 114023641 A CN114023641 A CN 114023641A CN 202111305214 A CN202111305214 A CN 202111305214A CN 114023641 A CN114023641 A CN 114023641A
Authority
CN
China
Prior art keywords
mask layer
layer
ohmic contact
etching
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111305214.6A
Other languages
Chinese (zh)
Inventor
杜仲凯
张炳良
刘雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Nengwu Electronic Technology Co ltd
Original Assignee
Suzhou Nengwu Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Nengwu Electronic Technology Co ltd filed Critical Suzhou Nengwu Electronic Technology Co ltd
Priority to CN202111305214.6A priority Critical patent/CN114023641A/en
Publication of CN114023641A publication Critical patent/CN114023641A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

The invention discloses a manufacturing method and application of an enhanced HEMT ohmic contact structure. In one embodiment, the manufacturing method comprises the following steps: sequentially arranging a bottom layer photoresist, a metal layer and a top layer photoresist on an epitaxial structure of the HEMT device to form a composite mask with a sandwich structure; selectively exposing and developing the top photoresist, etching and removing the metal layer below the developing region, then removing the top photoresist and the bottom photoresist below the developing region, etching and removing the p-GaN below the developing region to expose the ohmic contact region, and finally depositing source and drain metals on the ohmic contact region to form an ohmic contact structure. The invention can effectively be compatible with the oxygen-introduction self-stopping etching GaN process, accurately control the GaN etching depth of the ohmic contact region, reduce secondary etching damage, has no secondary photoetching deviation influence, can obviously improve the ohmic contact performance of the enhanced HEMT device, simplifies the process and reduces the cost.

Description

Manufacturing method and application of enhanced HEMT ohmic contact structure
Technical Field
The invention belongs to the technical field of semiconductor devices, relates to a manufacturing method of an enhanced HEMT device, and particularly relates to a manufacturing method of an enhanced HEMT ohmic contact structure, a manufacturing method of the enhanced HEMT device and the enhanced HEMT device.
Background
In today's society, power conversion and control is not always possible with power electronics. With the obvious environmental problems, the awareness of resource protection of people is gradually improved, and the loss is reduced and the efficiency is improved in the energy conversion process. In order to realize the efficient energy conversion, the demand on the core device, i.e. the power device, of the power conversion in the power electronic system is higher and higher.
At present, the performance of power electronic devices prepared from Si-based materials reaches the theoretical limit of the materials. In order to further improve the performance and reliability of the device. The development of new materials is imperative. Compared with Si materials, the GaN materials have the excellent characteristics of large forbidden band width, high breakdown field strength, large electronic saturation velocity and the like, so that the GaN HEMT device can meet the requirements of high frequency, high power and high efficiency.
And the ohmic contact metal is one of the key processes for preparing the enhanced p-GaN HEMT device. The method for manufacturing the ohmic contact metal of the p-GaN HEMT device mainly comprises a double-layer photoresist photoetching stripping process, a dielectric film secondary photoetching stripping process and the like.
For the double-layer photoresist photoetching stripping process, the p-GaN etching process is difficult to control due to the small etching selection ratio of the p-GaN to the AlGaN. Although the oxygen-introduced self-stop etching GaN process can solve the problem that the etching selection ratio of p-GaN and AlGaN is small, and further can accurately control the etching depth of the p-GaN, the etching speed of the photoresist is very high after oxygen is introduced, the etching selection ratio of the p-GaN and the double-layer photoresist is small, the double-layer photoresist cannot protect the p-GaN in a non-ohmic contact region, and the etching depth of the p-GaN in the ohmic contact region cannot be accurately monitored, so that the p-GaN under the ohmic contact region is not etched completely or is over-etched, the contact resistance of a device is increased, a two-dimensional electron gas channel is cut off, and the saturation current of the device is reduced. Although the dielectric film secondary photoetching stripping process can be compatible with the oxygen-filling self-stop GaN etching process, the ohmic contact performance of a device can be influenced by the secondary photoetching alignment deviation of a photoetching machine, the secondary photoetching process is complex, the process cost is high, secondary etching damage is easily introduced, the operation is complicated, and the realization is difficult.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of an enhanced HEMT ohmic contact structure, a manufacturing method of an enhanced HEMT device and the enhanced HEMT device, so as to overcome the defects of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
one aspect of the invention provides a method for manufacturing an enhanced HEMT ohmic contact structure, which comprises the following steps:
providing an epitaxial structure for forming an enhancement type HEMT device, wherein the epitaxial structure comprises a channel layer, a barrier layer and a P-type layer which are sequentially stacked;
sequentially arranging a first mask layer, a second mask layer and a third mask layer on the P-type layer, wherein for the selected etchant, the etching selection ratio of the second mask layer to the P-type layer is greater than that of either the first mask layer or the third mask layer to the P-type layer;
removing a region corresponding to an ohmic contact region in the third mask layer;
taking the remaining area of the third mask layer as a mask, etching the second mask layer, and removing the area corresponding to the ohmic contact area in the second mask layer;
completely etching and removing the third mask layer, and etching and removing a region corresponding to an ohmic contact region in the first mask layer;
taking the remaining areas of the first mask layer and the second mask layer as masks, etching the P-type layer by adopting the selected etchant, and removing the area, corresponding to the ohmic contact area, in the P-type layer to expose the ohmic contact area;
and manufacturing a source electrode and a drain electrode on the ohmic contact region, and enabling the source electrode and the drain electrode to form ohmic contact with the barrier layer.
In some embodiments, the material of the first mask layer and the third mask layer includes photoresist, the material of the second mask layer includes any one or a combination of metal, metal oxide and nonmetal oxide, and the selected etchant includes dry etching reagent containing oxygen.
Another aspect of the invention provides an enhancement mode HEMT ohmic contact structure made by any of the methods described above.
In another aspect, the invention also provides the use of the aforementioned manufacturing method.
Compared with the prior art, the invention has the beneficial effects that:
(1) by adopting the composite mask with the sandwich structure, for example, more than one metal layer is inserted between the double-layer photoresist masks, the method can be compatible with the oxygen-introduction self-stop etching GaN process, accurately monitor the p-GaN etching depth of the ohmic contact area, and effectively solve the problem that the p-GaN of the non-ohmic contact area can not obtain good protection because the oxygen-introduction self-stop etching GaN process etches the double-layer photoresist masks too fast;
(2) the method can realize ohmic contact self-alignment etching and photoetching by directly growing the ohmic contact metal in the etching area through one-time photoetching, reduce ohmic contact resistance of a device, improve saturation current of the device, simplify process difficulty, reduce process cost and effectively overcome the defects caused by the fact that secondary alignment photoetching etching is needed in the conventional dielectric film secondary photoetching stripping process, the ohmic contact metal cannot grow in situ in the ohmic etching area and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic epitaxial structure of an enhanced HMET device in an exemplary embodiment of the invention;
FIG. 2 is a schematic illustration of forming a composite mask on the epitaxial structure shown in FIG. 1;
FIG. 3 is a schematic illustration of the composite mask of FIG. 2 after portions of the second mask layer and the third mask layer have been removed;
FIG. 4 is a schematic illustration of a composite mask used to etch away local regions of the P-type layer;
fig. 5 is a schematic diagram of an ohmic contact structure for an enhanced HMET device in an exemplary embodiment of the invention;
fig. 6 is a schematic diagram of an enhanced HMET device in accordance with an exemplary embodiment of the invention;
fig. 7 is a schematic diagram of another enhanced HMET device in an exemplary embodiment of the invention.
Detailed Description
In view of the defects of the prior art, the inventor of the present invention has made extensive research and practice to propose the technical solution of the present invention. The technical scheme of the invention is more clearly and completely described in detail below.
Some embodiments of the present invention provide a method for manufacturing an enhancement mode HEMT ohmic contact structure, comprising:
providing an epitaxial structure for forming an enhancement type HEMT device, wherein the epitaxial structure comprises a channel layer, a barrier layer and a P-type layer which are sequentially stacked;
sequentially arranging a first mask layer, a second mask layer and a third mask layer on the P-type layer, wherein for the selected etchant, the etching selection ratio of the second mask layer to the P-type layer is greater than that of either the first mask layer or the third mask layer to the P-type layer;
removing a region corresponding to an ohmic contact region in the third mask layer;
taking the remaining area of the third mask layer as a mask, etching the second mask layer, and removing the area corresponding to the ohmic contact area in the second mask layer;
completely etching and removing the third mask layer, and etching and removing a region corresponding to an ohmic contact region in the first mask layer;
taking the remaining areas of the first mask layer and the second mask layer as masks, etching the P-type layer by adopting the selected etchant, and removing the area, corresponding to the ohmic contact area, in the P-type layer to expose the ohmic contact area;
and manufacturing a source electrode and a drain electrode on the ohmic contact region, and enabling the source electrode and the drain electrode to form ohmic contact with the barrier layer.
In some embodiments, the material of the first mask layer and the third mask layer includes a photoresist, such as LOR10A photoresist, AZ5214 photoresist or other photoresists, but is not limited thereto.
In some embodiments, the material of the second mask layer includes any one or a combination of metals (e.g., Cr, etc.), metal oxides (e.g., aluminum oxide, etc.), and non-metal oxides (e.g., silicon nitride, silicon dioxide, etc.), but is not limited thereto.
In some embodiments, the selected etchant includes a dry etching reagent containing oxygen, such as an inductively coupled plasma, which may contain an oxygen plasma or the like, to achieve an oxygen-on self-stop etching GaN process.
In some specific embodiments, the first mask layer is formed of a non-photosensitive photoresist, the third mask layer is formed of a photosensitive photoresist, and the second mask layer is a metal layer. The third mask layer can be used for transferring the pattern of the ohmic contact area to the second mask layer, and the second mask layer can prevent the influence of paste caused by the reaction of oxygen and photoresist when the GaN is etched by adopting oxygen self-stopping, improve the etching selection ratio of the etching mask layer and the GaN and protect the first mask layer.
In some embodiments, the epitaxial structure may be formed from a III-V compound. For example, the material of the channel layer includes GaN, the material of the barrier layer includes AlGaN, and the material of the P-type layer includes GaN, but is not limited thereto.
In some embodiments, the manufacturing method specifically includes:
exposing and developing the third mask layer by using a photoetching machine, and removing a region corresponding to an ohmic contact region in the third mask layer;
taking the remaining area of the third mask layer as a mask, and etching and removing the area corresponding to the ohmic contact area in the second mask layer by adopting a metal dry etching machine;
etching and removing the remaining area of the third mask layer and the area corresponding to the ohmic contact area in the first mask layer by using a plasma photoresist remover;
and etching and removing the region corresponding to the ohmic contact region in the P-type layer by adopting an inductively coupled plasma dry method.
In some embodiments, the manufacturing method specifically includes: and stripping after depositing source metal and drain metal on the exposed ohmic contact region, and annealing to realize ohmic contact between the formed source and drain and the barrier layer.
In a more specific embodiment, a method for fabricating an ohmic contact structure for an enhancement mode p-GaN HEMT device comprises: the method is characterized in that a metal layer (namely the second mask layer) is inserted between top and bottom photoresist layers (namely the first mask layer and the third mask layer), selective exposure and development are carried out on the top photoresist layer, then the metal layer below a development area is etched by using metal dry etching equipment, then the top photoresist layer and the bottom photoresist below the development area are removed completely by using a plasma photoresist remover, then p-GaN below the development area is etched to remove the ohmic contact area, and finally source and metal leakage are deposited on the ohmic contact area to form an ohmic contact structure, so that the manufacturing of the p-GaN HEMT in-situ growth ohmic contact metal is realized. The method can be effectively compatible with the process of etching the GaN by oxygen self-stopping, accurately control the GaN etching depth of the ohmic contact area, reduce secondary etching damage, has no secondary photoetching deviation influence, can obviously improve the ohmic contact performance, simplifies the process and reduces the cost.
Some embodiments of the invention also provide an ohmic contact structure of the enhancement mode HEMT device formed by any one of the methods.
Some embodiments of the present invention also provide a composite mask structure disposed on an epitaxial structure for forming an enhancement mode HEMT device, the epitaxial structure including a channel layer, a barrier layer, and a P-type layer stacked in this order; further, the composite mask structure comprises a first mask layer, a second mask layer and a third mask layer which are sequentially stacked on the P-type layer; and for the selected etchant, the etching selection ratio of the second mask layer to the P-type layer is greater than that of any one of the first mask layer and the third mask layer to the P-type layer.
In some embodiments, the material of the first mask layer and the third mask layer includes, but is not limited to, photoresist. The material of the second mask layer includes, but is not limited to, any one or a combination of metals, metal oxides, and non-metal oxides. The selected etchant includes, but is not limited to, an oxygen-containing dry etching reagent.
Some embodiments of the present invention further provide a method for manufacturing an enhancement mode HEMT device, including:
adopting any one of the methods to manufacture and form an ohmic contact structure of the enhancement type HEMT device;
and manufacturing a grid electrode on the P type layer.
The manufacturing method provided by the embodiment of the invention is simple and easy to implement, does not need a complex secondary photoetching process and the like, has high controllability and low cost, can effectively improve the yield of products and ensure the performance of the products, and for example, the manufactured enhanced HEMT device has the characteristics of low ohmic contact resistance, high saturation current and the like.
The technical solution of the present invention is further described in detail with reference to the following embodiments and the accompanying drawings, wherein the embodiments are implemented on the premise of the technical solution of the present invention, and detailed embodiments and specific operation procedures are provided, but the scope of the present invention is not limited to the following embodiments.
In summary, the method for manufacturing the ohmic contact structure of the enhancement-mode p-GaN HEMT device provided in this embodiment includes the following steps: spin-coating a non-photosensitive bottom layer photoresist (first mask layer) on a wafer; growing a metal layer (a second mask layer); spin coating a photosensitive top layer photoresist (third mask layer); exposing and developing the area corresponding to the top layer photoresist and the ohmic contact area by a photoetching machine; etching the area of the metal layer corresponding to the ohmic contact area by a metal dry etching machine; removing all areas of the top photoresist and the bottom photoresist corresponding to the ohmic contact area by using a plasma photoresist remover; dry etching the region of p-GaN and the like corresponding to the ohmic contact region; growing an ohmic contact metal on the exposed ohmic contact region; organically cleaning and stripping off the metal distributed in the non-ohmic contact area; and performing rapid annealing to form an ohmic contact structure.
Specifically, the manufacturing method comprises the following steps:
(1) an epitaxial structure (hereinafter, also referred to as a "wafer") of a Si-based p-GaN HEMT device is obtained, which includes an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, an A1GaN barrier layer 5, and a p-GaN layer 6 sequentially formed on a Si substrate 1, as shown in fig. 1. Wherein the thickness of the nucleation layer is about 1 μm, the thickness of the buffer layer is about 3-5 μm, the thickness of the channel layer is about 100-300nm, the thickness of the barrier layer is about 15-30nm, and the thickness of the p-GaN layer is about 50-150 nm.
(2) Cleaning the wafer, then spin-coating a bottom layer of LOR10A photoresist (non-photosensitive photoresist) on the wafer to form a first mask layer 9, then growing a metal Cr layer, i.e. a second mask layer 10, on the first mask layer, and then spin-coating a top layer of AZ5214 photoresist (photosensitive photoresist) on the second mask layer to form a third mask layer 11, i.e. forming a composite mask with a sandwich structure on the wafer, as shown in fig. 2.
More specifically, the wafer can be respectively ultrasonically cleaned by acetone, isopropanol and deionized water, then the wafer is placed into an HMDS surface pretreatment machine for surface hexamethyldisilazane coating, a spin coater is utilized to spin-coat bottom layer LOR10A photoresist on the wafer, the rotating speed is 4000rpm, the time is 30s, then soft drying is carried out, the temperature of a hot plate is set to be 140 ℃, and the time is 120 s. A metallic Cr layer with a thickness of 100nm was subsequently evaporated with a PVD electron beam evaporation stage. And putting the wafer into an HMDS surface pretreatment machine again for hexamethyldisilazane coating, carrying out top-layer AZ5214 photoresist spin coating on the wafer by using a spin coater at the rotating speed of 4000rpm for 30s, and then carrying out soft baking, wherein the temperature of a hot plate is set to be 95 ℃ and the time is 90 s.
(3) And putting the wafer with the surface covered with the composite mask into a photoetching machine, exposing the areas of the third mask layer corresponding to the ohmic contact areas (the source electrode area and the drain electrode area), putting the exposed sample into a developing solution for development, repeatedly washing with ultrapure water and drying with nitrogen, thereby removing the areas of the third mask layer corresponding to the ohmic contact areas.
(4) And (3) taking the remaining third mask layer as a mask, and completely etching the region of the metal Cr layer corresponding to the ohmic contact region by using a metal dry etching machine, wherein the etching depth can be 100nm, as shown in fig. 3.
(5) And completely removing the third mask layer on the surface of the wafer by using a plasma photoresist remover, and completely removing the area of the first mask layer corresponding to the ohmic contact area, as shown in fig. 4.
(6) And etching the region of the p-GaN layer corresponding to the ohmic contact region by using an inductively coupled plasma dry etching machine to expose the ohmic contact region. In the process, an etching atmosphere containing oxygen plasma is adopted, and an oxygen-introducing self-stopping etching GaN process is preferably adopted, so that the p-GaN etching depth is more accurately controlled.
(7) And depositing source electrode metal and drain electrode metal on the ohmic contact area by using a metal deposition technology such as electron beam evaporation or sputtering, stripping the metal from the wafer, and annealing by using a rapid annealing furnace after the metal is completely stripped to realize ohmic contact so as to obtain an ohmic contact structure shown in figure 5.
Specifically, the wafer with the ohmic contact region exposed can be placed in an electron beam evaporation table, and four layers of metals of Ti/Al/Ni/Au are sequentially evaporated in the source region and the drain region. And stripping after metal evaporation is finished, putting the stripped sample into a rapid annealing furnace, and performing rapid annealing at the nitrogen atmosphere temperature of 875 ℃ for 30s to form ohmic contact.
Further, the p-GaN layer may be processed in a manner known in the art, followed by fabrication of the gate, thereby forming an enhancement mode HEMT device. As shown in fig. 6, the gate source and drain regions of the p-GaN layer may be removed by dry etching or the like, and then the gate electrode 12 may be formed on the remaining p-GaN layer. Alternatively, as shown in fig. 7, the gate source and drain regions of the p-GaN layer may be converted into the high resistance GaN layer 13 by means of H ion implantation, H plasma treatment, or the like, and the gate electrode 12 may be formed on the gate region of the p-GaN layer.
Compared with the Si-based p-GaN HEMT device manufactured by adopting the double-layer photoresist photoetching stripping process and the dielectric film secondary photoetching stripping process, the ohmic contact saturation current of the Si-based p-GaN HEMT device is greatly improved, and the contact resistance is obviously reduced.
It should be understood that the technical solution of the present invention is not limited to the above-mentioned specific embodiments, and all technical modifications made according to the technical solution of the present invention fall within the protection scope of the present invention without departing from the spirit of the present invention and the protection scope of the claims.

Claims (10)

1. A manufacturing method of an enhanced HEMT ohmic contact structure is characterized by comprising the following steps:
providing an epitaxial structure for forming an enhancement type HEMT device, wherein the epitaxial structure comprises a channel layer, a barrier layer and a P-type layer which are sequentially stacked;
sequentially arranging a first mask layer, a second mask layer and a third mask layer on the P-type layer, wherein for the selected etchant, the etching selection ratio of the second mask layer to the P-type layer is greater than that of either the first mask layer or the third mask layer to the P-type layer;
removing a region corresponding to an ohmic contact region in the third mask layer;
taking the remaining area of the third mask layer as a mask, etching the second mask layer, and removing the area corresponding to the ohmic contact area in the second mask layer;
completely etching and removing the third mask layer, and etching and removing a region corresponding to an ohmic contact region in the first mask layer;
taking the remaining areas of the first mask layer and the second mask layer as masks, etching the P-type layer by adopting the selected etchant, and removing the area, corresponding to the ohmic contact area, in the P-type layer to expose the ohmic contact area;
and manufacturing a source electrode and a drain electrode on the ohmic contact region, and enabling the source electrode and the drain electrode to form ohmic contact with the barrier layer.
2. The method of manufacturing according to claim 1, wherein: the first mask layer and the third mask layer are made of photoresist, and the second mask layer is made of any one or combination of metal, metal oxide and nonmetal oxide; and/or the selected etchant comprises a dry etching reagent containing oxygen.
3. The method of manufacturing according to claim 2, wherein: the first mask layer and the third mask layer are respectively formed by non-photosensitive photoresist and photosensitive photoresist, and the second mask layer is a metal layer.
4. The method of manufacturing according to claim 1, wherein: the material of the channel layer comprises GaN; and/or the barrier layer is made of A1 GaN; and/or the material of the P-type layer comprises GaN.
5. The manufacturing method according to claim 3, characterized by specifically comprising:
exposing and developing the third mask layer by using a photoetching machine, and removing a region corresponding to an ohmic contact region in the third mask layer;
taking the remaining area of the third mask layer as a mask, and etching and removing the area corresponding to the ohmic contact area in the second mask layer by adopting a metal dry etching machine;
etching and removing the remaining area of the third mask layer and the area corresponding to the ohmic contact area in the first mask layer by using a plasma photoresist remover;
and etching and removing the region corresponding to the ohmic contact region in the P-type layer by adopting an inductively coupled plasma dry method.
6. The manufacturing method according to claim 1, characterized by specifically comprising: and stripping after depositing source metal and drain metal on the exposed ohmic contact region, and annealing to realize ohmic contact between the formed source and drain and the barrier layer.
7. An ohmic contact structure for an enhancement mode HEMT device formed by the method of any one of claims 1-6.
8. A composite mask structure provided on an epitaxial structure for forming an enhancement mode HEMT device, the epitaxial structure including a channel layer, a barrier layer, and a P-type layer stacked in this order, characterized in that: the composite mask structure comprises a first mask layer, a second mask layer and a third mask layer which are sequentially stacked on the P-type layer; and for the selected etchant, the etching selection ratio of the second mask layer to the P-type layer is greater than that of any one of the first mask layer and the third mask layer to the P-type layer.
9. The composite mask structure of claim 8, wherein: the first mask layer and the third mask layer are made of photoresist, and the second mask layer is made of any one or combination of metal, metal oxide and nonmetal oxide; and/or the selected etchant comprises a dry etching reagent containing oxygen.
10. A manufacturing method of an enhancement type HEMT device is characterized by comprising the following steps:
forming an ohmic contact structure of the enhancement mode HEMT device by adopting the method of any one of claims 1-6;
and manufacturing a grid electrode on the P type layer.
CN202111305214.6A 2021-11-05 2021-11-05 Manufacturing method and application of enhanced HEMT ohmic contact structure Pending CN114023641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111305214.6A CN114023641A (en) 2021-11-05 2021-11-05 Manufacturing method and application of enhanced HEMT ohmic contact structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111305214.6A CN114023641A (en) 2021-11-05 2021-11-05 Manufacturing method and application of enhanced HEMT ohmic contact structure

Publications (1)

Publication Number Publication Date
CN114023641A true CN114023641A (en) 2022-02-08

Family

ID=80061272

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111305214.6A Pending CN114023641A (en) 2021-11-05 2021-11-05 Manufacturing method and application of enhanced HEMT ohmic contact structure

Country Status (1)

Country Link
CN (1) CN114023641A (en)

Similar Documents

Publication Publication Date Title
CN107393959A (en) GaN hyperfrequencies device and preparation method based on sag
CN108133961A (en) A kind of GaN_HEMT device preparation methods based on aluminum nitride barrier layers
CN110600549B (en) Enhanced AlGaN/GaN MOS-HEMT device structure and preparation method thereof
CN107293482B (en) Method for manufacturing gate electrode of gallium nitride high electron mobility transistor
CN112614835B (en) Enhanced and depletion HEMT integrated device and preparation method thereof
CN114023641A (en) Manufacturing method and application of enhanced HEMT ohmic contact structure
CN113451129B (en) High electron mobility transistor and preparation method thereof
CN112542384B (en) Manufacturing method of gallium nitride enhanced device
CN114334649A (en) Transfer and heterogeneous integration method of flip GaN HEMT device array and device array thereof
WO2020192303A1 (en) Semiconductor device and manufacturing method
CN109346405B (en) Preparation method of GaN-based SBD flip chip
CN113594037A (en) GaN MISHEMT device and manufacturing method thereof
CN113257901A (en) Radio frequency HEMT device with grid air cavity structure and preparation method thereof
CN102306626B (en) Semiconductor heterojunction field effect transistor grid structure preparation method
CN112820774A (en) GaN device and preparation method thereof
CN112018177A (en) Full-vertical Si-based GaN UMOSFET power device and preparation method thereof
JP2005243719A (en) Field effect transistor and its manufacturing method
CN115498034B (en) GaN HEMT device and preparation method thereof
CN114171387A (en) Enhanced HEMT based on P-type gate and preparation method thereof
US20220254632A1 (en) Preparation Method of GaN Field Effect Transistor Based on Diamond Substrate
CN109378271B (en) Preparation method of patterned metal film layer, thin film transistor and display substrate
CN110634946B (en) Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof
CN113540230A (en) Semiconductor device and method for manufacturing the same
CN109545851A (en) Enhanced GaN base power device and preparation method thereof
JPH02192172A (en) Superconducting transistor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination