CN114171387A - Enhanced HEMT based on P-type gate and preparation method thereof - Google Patents

Enhanced HEMT based on P-type gate and preparation method thereof Download PDF

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CN114171387A
CN114171387A CN202111487381.7A CN202111487381A CN114171387A CN 114171387 A CN114171387 A CN 114171387A CN 202111487381 A CN202111487381 A CN 202111487381A CN 114171387 A CN114171387 A CN 114171387A
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layer
cap layer
gate
gan
epitaxial structure
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杜仲凯
张炳良
刘雷
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Suzhou Nengwu Electronic Technology Co ltd
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Suzhou Nengwu Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses an enhanced HEMT based on a P-type gate and a preparation method thereof. The preparation method comprises the steps of manufacturing the HEMT device main body and the source, the drain and the grid matched with the HEMT device main body; wherein the step of fabricating the device body comprises: providing an epitaxial structure comprising a channel layer, a barrier layer, and a cap layer, the cap layer formed of HR-GaN; and implanting acceptor ions into the gate lower region of the cap layer and activating to convert the gate lower region of the cap layer into a P-type layer. The method can effectively reduce the interface state density, avoid etching damage and enhance the thermal stability so as to ensure the performance of the device, has higher controllability and lower cost, and can also obviously improve the yield of enhanced HEMT products.

Description

Enhanced HEMT based on P-type gate and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, relates to a preparation method of an HEMT device, and particularly relates to an enhanced HEMT based on a P-type gate and a preparation method thereof.
Background
Hemt (high Electron Mobility transistor) has been widely used in various fields such as power electronic systems. Compared with the traditional Si-based HEMT device, the GaN HEMT device has obvious advantages and can meet the application requirements of high frequency, high power and high efficiency.
Currently, HEMT devices are generally classified as enhancement mode (V) depending on whether the threshold voltage is greater than zero or notth> 0) and depletion mode (V)th< 0) two. Most of conventional HEMT devices are depletion mode devices, in practical circuit application, the depletion mode devices need to introduce a negative pressure source to turn off the devices, potential safety hazards exist, and complexity and cost of circuits are increased. And thus in practical applications there is a greater tendency to use enhancement mode HEMT devices. There are currently four schemes for implementing an enhanced HEMT, including: a Cascode structure, an F ion treatment, a concave grid structure and a P-type grid structure. Compared with the other three schemes, the HEMT device based on the P-type gate has stable threshold value and excellent performance, and is expected by the industry. The conventional HEMT device based on the P-type gate is mainly prepared by dry etching, selective epitaxy, H plasma treatment and the like, but the methods have defects. For example, for a dry etching method, the etching selectivity of P-GaN and AlGaN is small, the P-GaN etching process is difficult to control, the repeatability is poor, and in addition, damage and a high-concentration interface state are generated in the etching process, so that a severe current collapse phenomenon is caused, and the performance of a device is reduced. For the selective area epitaxy mode, the performance of the device is influenced by various factors such as the shape of a mask, materials, growth temperature, gas pressure in a reaction cavity and the like, and the selective epitaxy interface has high state density and complex process and is difficult to realize. The device formed by the H plasma processing method has poor thermal stability, and H ions can diffuse under thermal stress, so that the threshold voltage of the device can shift. In summary, the conventional preparation method of the HEMT device based on the P-type gate all causes the problems of high damage, high interface state, poor thermal stability and the like.
Disclosure of Invention
The invention mainly aims to provide an enhancement type HEMT based on a P-type grid and a preparation method thereof, so as to overcome the defects of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
one aspect of the invention provides a preparation method of an enhanced HEMT based on a P-type grid, which comprises the steps of manufacturing a HEMT device main body and manufacturing a source electrode, a drain electrode and a grid electrode which are matched with the device main body.
Wherein the step of fabricating the device body comprises:
s1, providing an epitaxial structure, wherein the epitaxial structure comprises a channel layer, a barrier layer and a cap layer which are sequentially stacked, and the cap layer is made of high-resistance materials or intrinsic semiconductor materials;
and S2, injecting acceptor ions into the area under the gate of the cap layer and activating the area to convert the area under the gate of the cap layer into a P-type layer, wherein the P-type layer is used for depleting two-dimensional electron gas below the gate.
Preferably, in step S1, the cap layer is formed of a high-resistance material.
Another aspect of the invention provides a P-gate based enhancement mode HEMT made by any of the methods described above.
Compared with the prior art, the enhanced HEMT preparation method provided by the invention has the advantages that the high-resistance GaN (HR-GaN) cap layer or the intrinsic GaN cap layer is grown in situ, Mg is injected into the selected area under the gate of the cap layer for activation to realize P-GaN, the interface state density can be effectively reduced, various defects caused by etching damage are avoided, the thermal stability is enhanced, the controllability of the process is higher, the cost is lower, and the product yield can be obviously improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic view of an epitaxial structure of a P-gate based enhancement mode HMET in an exemplary embodiment of the invention;
FIG. 2 is a schematic view of the epitaxial structure of FIG. 1 after implantation of ions in selected regions to form P-GaN;
FIG. 3 is a schematic diagram of the epitaxial structure of FIG. 2 after source and drain formation;
fig. 4 is a schematic structural view of an enhancement mode HMET formed after a gate is formed on the epitaxial structure shown in fig. 3.
Detailed Description
In view of the defects of the prior art, the inventor of the present invention has made extensive research and practice to propose the technical solution of the present invention. The technical solution of the present invention will be further described in detail with reference to the following detailed description and the accompanying drawings, wherein the following examples are implemented on the premise of the technical solution of the present invention, and the detailed description and the specific operation procedures are given, but the scope of the present invention is not limited to the following examples.
Some embodiments of the invention provide a preparation method of an enhanced HEMT based on a P-type grid, which comprises the steps of manufacturing a HEMT device main body and manufacturing a source electrode, a drain electrode and a grid electrode which are matched with the device main body; wherein the step of fabricating the device body comprises:
s1, providing an epitaxial structure, wherein the epitaxial structure comprises a channel layer, a barrier layer and a cap layer which are sequentially stacked, and the cap layer is made of high-resistance materials or intrinsic semiconductor materials;
and S2, injecting acceptor ions into the area under the gate of the cap layer and activating the area to convert the area under the gate of the cap layer into a P-type layer, wherein the P-type layer is used for depleting two-dimensional electron gas below the gate.
In some embodiments, step S1 further includes: and sequentially growing and forming a nucleating layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the substrate so as to form the epitaxial structure. Including but not limited to sapphire substrates, SiC substrates, GaN substrates, and the like.
In some embodiments, step S2 further includes: and performing active region isolation processing on the epitaxial structure, and then performing operation of injecting acceptor ions into the sub-gate region of the cap layer and activating.
Further, step S2 may specifically include: and implanting Mg ions into the subgrid region of the cap layer, and activating at a high temperature of 1200-1600 ℃.
In some embodiments, the step of fabricating an epitaxial structure further comprises: after step S2 is completed, the regions of the cap layer corresponding to the source and the drain are removed to expose the source region and the drain region of the barrier layer, and then the source and the drain are fabricated on the source region and the drain region of the barrier layer.
In some embodiments, the step of fabricating an epitaxial structure further comprises: after step S2 is completed, a gate is fabricated on the P-type layer.
In some embodiments, the epitaxial structure may be formed from a III-V compound. For example, the channel layer may include GaN, the barrier layer may include AlGaN, and the cap layer may include high-resistance GaN or intrinsic GaN (HR-GaN), but not limited thereto. Preferably, the cap layer is formed of high-resistance GaN.
In some embodiments, the cap layer has a thickness of 50-100 nm.
The source, drain and gate electrodes may be formed by methods well known in the art, such as metal sputtering, evaporation, etc., and preferably, the source and drain electrodes form ohmic contacts with the epitaxial structure.
Some embodiments of the invention provide a P-gate based enhancement mode HEMT made by any of the methods described above.
In a preferred embodiment of the present invention, a method for manufacturing an enhancement mode HEMT (HEMT device for short) based on a P-type gate includes the following steps:
(1) and (3) obtaining a substrate, cleaning the substrate, and then sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the substrate to form the epitaxial structure shown in the figure 1. Wherein the cap layer is formed by high-resistance GaN and has a thickness of 50-100 nm.
(2) An isolation pattern is photo-etched on the epitaxial structure shown in fig. 1 by spin-coating photoresist, and isolation of the active region is achieved by using ion implantation or etching technology. The operation of this step is well known to those skilled in the art and will not be described in detail here.
(3) And injecting Mg ions into the cap layer by utilizing the selective region of the ion implanter, and activating at the high temperature of 1200-1600 ℃ to change the GaN in the area under the gate of the cap layer into P-type GaN so as to form a device structure shown in figure 2, thereby consuming the two-dimensional electron gas below.
(4) Ohmic regions are etched on the device structure shown in fig. 2 and metal is deposited to make ohmic contacts. Specifically, after the step (3) is completed, a photoresist is coated on the surface of the device structure shown in fig. 2 in a spinning mode, a source electrode and a drain electrode are photoetched, then a source region and a drain region of the cap layer are etched by using an etching technology, the source region and the drain region of the barrier layer are exposed, then metal is deposited on the source region and the drain region of the barrier layer by using a metal deposition technology such as electron beam evaporation or sputtering, and ohmic contact is achieved after annealing, so that the device structure shown in fig. 3 is obtained.
(5) A gate region is etched on the device structure shown in fig. 3 and a gate metal is deposited. Specifically, after the step (4) is completed, spin-coating a photoresist on the device structure shown in fig. 3 again, performing photolithography to form a gate pattern, and depositing a gate metal in the gate pattern region by using a metal deposition technique such as electron beam evaporation or sputtering, thereby finally forming the HEMT device shown in fig. 4. The HEMT device comprises a substrate, a nucleating layer, a buffer layer, a channel layer and a barrier layer from bottom to top, wherein a source electrode and a drain electrode are arranged above the barrier layer, P-GaN is distributed between the source electrode and the drain electrode, and a grid electrode is arranged on the P-GaN.
Further, in an embodiment of the present invention, a HEMT device is prepared by a method comprising:
the method comprises the following steps: MOCVD growth HEMT epitaxial structure (hereinafter also referred to as wafer)
And after the Si substrate is obtained, respectively ultrasonically cleaning the Si substrate by using acetone, isopropanol and deionized water. Then the film is put into MOCVD equipment to grow a nucleation layer with the thickness of 100nm, an AlGaN stress control layer with the thickness of 2 microns, a high-resistance GaN layer with the thickness of 300nm, a GaN channel layer with the thickness of 300nm, an AlGaN barrier layer with the thickness of 20nm and a high-resistance GaN layer with the thickness of 50nm in sequence.
Step two: mesa etch isolation
Firstly, spin coating and spin coating are carried out on a wafer by a spin coater, wherein the time is 30s at the rotating speed of 3000 rpm. Subsequently, soft baking was carried out, and the hot plate was set to a temperature of 90 ℃ for 100 seconds. And carrying out active area isolation exposure on the wafer after soft baking. And finally, placing the exposed wafer into a developing solution for developing, repeatedly washing with ultrapure water and drying with nitrogen.
And carrying out mesa etching isolation on the wafer after the photoetching and developing is finished by utilizing an ICP etching device, wherein the etching depth is 500nm, ultrasonically cleaning the wafer for 3min by using an acetone solution after the etching is finished to remove a mask, then ultrasonically cleaning the wafer for 5min by using an isopropanol solution, repeatedly washing the wafer by using ultrapure water, and finally drying the wafer by using nitrogen.
Step three: ion implantation for realizing P-GaN under grid
Spin coating and spin coating are carried out on the wafer by a spin coater, and the time is 30s at the rotating speed of 3000 rpm. Subsequently, soft baking was carried out, and the hot plate was set to a temperature of 90 ℃ for 100 seconds. And exposing the gate region of the wafer subjected to soft baking. And finally, placing the exposed wafer into a developing solution for developing, repeatedly washing with ultrapure water and drying with nitrogen. And utilizing an ion implanter to implant Mg ions into the area under the gate of the cap layer, wherein the implantation depth is 50 nm. Then at about 1200-1600 ℃ in N2And activating under the atmosphere to form the P-GaN.
Step four: ohmic contact preparation
Spin coating and spin coating are carried out on the wafer by a spin coater, and the time is 30s at the rotating speed of 3000 rpm. Subsequently, soft baking was carried out, and the hot plate was set to a temperature of 90 ℃ for 100 seconds. And exposing the soft baked wafer in an ohmic area. And finally, placing the exposed wafer into a developing solution for developing, repeatedly washing with ultrapure water and drying with nitrogen.
Etching the source electrode area and the drain electrode area of the cap layer by utilizing ICP etching equipment, putting the etched wafer into an electron beam evaporation table, and sequentially evaporating Ti/Al/Ni/Au four-layer metal on the source electrode area and the drain electrode area of the barrier layer which is not covered by the photoresist. And stripping after metal evaporation is finished, putting the stripped wafer into a rapid annealing furnace, and performing rapid annealing under the conditions of nitrogen atmosphere, 850 ℃ and 30s to form ohmic contact.
Step four: gate preparation
Spin coating and spin coating are carried out on the wafer by a spin coater, and the time is 30s at the rotating speed of 3000 rpm. Subsequently, soft baking was carried out, and the hot plate was set to a temperature of 90 ℃ for 100 seconds. And exposing the grid region of the wafer subjected to soft baking. And finally, placing the exposed wafer into a developing solution for developing, repeatedly washing with ultrapure water and drying with nitrogen. Putting the photoetched sample into an electron beam evaporation table, sequentially evaporating Ni/Au two layers of metals in a gate region (namely the surface of p-GaN) of a cap layer which is not covered by photoresist, and then stripping to form gate contact, thereby finally obtaining the HEMT device, wherein the structure of the HEMT device can be seen in figure 4.
Compared with the scheme of forming the enhanced HEMT by adopting selective area epitaxy P-GaN, the GaN/AlGaN/GaN structure is formed by epitaxy in the epitaxy process of the HEMT device main body in the embodiment, so that the interface state density can be obviously reduced, and the stability of the device can be effectively improved.
Compared with the scheme of forming the enhancement type HEMT by adopting dry etching, the cap layer in the embodiment can be used as a passivation layer formed by primary epitaxy of a barrier layer and the like, and can also avoid damage caused by etching, so that the saturation current of the device is improved, and the on-resistance is reduced.
Compared with the mode of realizing an enhanced HEMT device by adopting H passivation and F ion implantation, the mode of firstly forming the high-resistance GaN cap layer, then carrying out Mg ion implantation and then activating at high temperature is adopted in the embodiment to realize P-GaN under the gate, so that the defects of poor thermal stability and the like of the device caused by diffusion of H ions and F ions can be avoided, and the stability of the device in high-temperature work is improved.
It should be understood that the technical solution of the present invention is not limited to the above-mentioned specific embodiments, and all technical modifications made according to the technical solution of the present invention fall within the protection scope of the present invention without departing from the spirit of the present invention and the protection scope of the claims.

Claims (10)

1. A preparation method of an enhanced HEMT based on a P-type grid comprises the steps of manufacturing a HEMT device main body and manufacturing a source electrode, a drain electrode and a grid electrode which are matched with the device main body;
the method is characterized in that the step of manufacturing the device main body comprises the following steps:
s1, providing an epitaxial structure, wherein the epitaxial structure comprises a channel layer, a barrier layer and a cap layer which are sequentially stacked, and the cap layer is made of high-resistance materials or intrinsic semiconductor materials;
and S2, injecting acceptor ions into the area under the gate of the cap layer and activating the area to convert the area under the gate of the cap layer into a P-type layer, wherein the P-type layer is used for depleting two-dimensional electron gas below the gate.
2. The method according to claim 1, wherein step S1 further includes: and sequentially growing and forming a nucleating layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the substrate so as to form the epitaxial structure.
3. The method according to claim 1, wherein step S2 further includes: and performing active region isolation processing on the epitaxial structure, and then performing operation of injecting acceptor ions into the sub-gate region of the cap layer and activating.
4. The preparation method according to claim 1 or 3, wherein the step S2 specifically comprises: and implanting Mg ions into the subgrid area of the cap layer, and activating at the high temperature of 1200-1600 ℃.
5. The method of claim 1, wherein the step of fabricating an epitaxial structure further comprises: after step S2 is completed, the regions of the cap layer corresponding to the source and the drain are removed to expose the source region and the drain region of the barrier layer, and then the source and the drain are fabricated on the source region and the drain region of the barrier layer.
6. The method of claim 1, wherein the step of fabricating an epitaxial structure further comprises: after step S2 is completed, a gate is fabricated on the P-type layer.
7. The method according to claim 1, wherein the channel layer, the barrier layer and the cap layer are made of III-V compounds.
8. The method according to claim 7, wherein the cap layer is made of high-resistance GaN or intrinsic GaN; and/or the material of the channel layer comprises GaN; and/or the barrier layer is made of A1 GaN.
9. The method for preparing a semiconductor device according to claim 1, wherein the cap layer has a thickness of 50 to 100 nm.
10. An enhancement mode HEMT based on P type grid, its characterized in that: it is prepared by the method of any one of claims 1 to 9.
CN202111487381.7A 2021-12-07 2021-12-07 Enhanced HEMT based on P-type gate and preparation method thereof Pending CN114171387A (en)

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CN202111487381.7A CN114171387A (en) 2021-12-07 2021-12-07 Enhanced HEMT based on P-type gate and preparation method thereof

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